MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER * LCD drive control circuit DESCRIPTION The 3822 group is the 8-bit microcomputer based on the 740 family core technology. The 3822 group has the LCD drive control circuit an 8-channel AD converter, and a Serial I/O as additional functions. The various microcomputers in the 3822 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3822 group, refer to the section on group expansion. * * FEATURES * Basic machine-language instructions ....................................... 71 * The minimum instruction execution time ............................ 0.5 s * APPLICATIONS Camera, household appliances, consumer electronics, etc. SEG8 SEG9 SEG10 SEG11 P34 /SEG12 P35 /SEG13 P36/SEG14 P37/SEG15 P00/SEG16 P01/SEG17 P02/SEG18 P03 /SEG19 P04/SEG20 P05/SEG21 P06/SEG22 P07/SEG23 P10 /SEG24 P11/SEG25 P12/SEG26 P13/SEG27 P14/SEG28 P15/SEG29 P16/SEG30 P17/SEG31 PIN CONFIGURATION (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 * * * SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M38223M4-XXXFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 * * * * VL2 VL1 P67 /AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62 /AN2 P61/AN1 P60/AN0 P57 /ADT P56 / TOUT P55 /CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46 /SCLK P45/ TXD P44/RXD P43 /INT1 P42/INT0 * (at 8MHz oscillation frequency) Memory size ROM .................................................................. 4 K to 32 K bytes RAM ................................................................. 192 to 1024 bytes Programmable input/output ports ............................................. 49 Software pull-up/pull-down resistors (Ports P0-P7 except Port P40) Interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) Timers ........................................................... 8-bit 3, 16-bit 2 Serial I/O1 ..................... 8-bit 1 (UART or Clock-synchronized) Serial I/O2 ........................................................ 8-bit 8 channels Bias ................................................................................... 1/2, 1/3 Duty ............................................................................ 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ......................................................................... 32 2 Clock generating circuit Clock (XIN-XOUT) .................................. Internal feedback resistor Sub-clock (XCIN-XCOUT) .......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode .................................................... 4.0 to 5.5 V (at 8MHz oscillation frequency and high-speed selected) In middle-speed mode ................................................ 2.5 to 5.5 V (at 8MHz oscillation frequency and middle-speed selected) In low-speed mode ...................................................... 2.5 to 5.5 V (Extended operating temperature version: 3.0 V to 5.5 V) Power dissipation In high-speed mode ........................................................... 32 mW (at 8 MHz oscillation frequency) In low-speed mode .............................................................. 45 W (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range ................................... - 20 to 85C (Extended operating temperature version: -40 to 85C) Package type : 80P6N-A 80-pin plastic-molded QFP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70 /XCOUT P71 /XCIN RESET P40 P41 / MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG10 SEG11 P34/SEG12 P35 /SEG13 P36/SEG14 P37/SEG15 P00/SEG16 P01 /SEG17 P02/SEG18 P03/SEG19 P04/SEG20 P05/SEG21 P06 /SEG22 P07/SEG23 P10/SEG24 P11/SEG25 P12/SEG26 P13 /SEG27 P14/SEG28 P15/SEG29 PIN CONFIGURATION (TOP VIEW) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M38223M4-XXXGP M38223M4-XXXHP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P67/AN7 P66 /AN6 P65/AN5 P64/AN4 P63 /AN3 P62/AN2 P61/AN1 P60 /AN0 P57/ADT P56/ TOUT P55 /CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46 /SCLK P45/ TXD P44/RXD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM 3 COM 2 COM 1 COM 0 VL3 VL2 VL1 Package type : 80P6S-A/80P6D-A 80-pin plastic-molded QFP 2 P16/SEG30 P17/SEG31 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/ P42/INT0 P43/INT1 XCIN 1 2 3 4 5 6 7 8 I/O port P6 26 27 I/O port P7 72 73 VREF AVSS (0 V) TOUT PS PCL S Y X A P5(8) I/O port P5 I/O port P4 17 18 19 20 21 22 23 24 P4(8) ROM SI/O(8) Input port P3 I/O port P2 31 32 33 34 35 36 37 38 55 56 57 58 LCD display RAM (16 bytes) RAM P2(8) Real time port function P3(8) Timer X(16) Timer Y(16) Timer 1(8) Timer 2(8) Timer 3(8) 30 71 Data bus (0 V) VSS (5 V) VCC CNTR0 ,CNTR1 RTP0 ,RTP 1 CPU 25 Reset input RESET 9 10 11 12 13 14 15 16 PCH A-D converter(8) P6(8) XCOUT Subclock output P7(2) XCOUT XCIN Subclock input Clock generating circuit 29 28 ADT Clock output XOUT INT2 ,INT3 Clock input XIN INT0,INT1 FUNCTIONAL BLOCK DIAGRAM (Package : 80P6S-A) I/O port P0 47 48 49 50 51 52 53 54 39 40 41 42 43 44 45 46 I/O port P1 P0(8) Key-on wake up P1(8) LCD drive control circuit 59 70 69 68 67 66 65 64 63 62 61 60 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 COM0 COM1 COM2 COM3 77 76 75 74 VL1 VL2 VL3 80 79 78 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 3 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin Function Function except a port function VCC, VSS Power source * Apply voltage of 2.5 V to 5.5 V to VCC, and 0 V to VSS. VREF Analog reference voltage * Reference voltage input pin for A-D converter. AVSS Analog power source * GND input pin for A-D converter. * Connect to VSS. RESET Reset input *Reset input pin for active "L" XIN Clock input XOUT Clock output * Input and output pins for the main clock generating circuit. * Feedback resistor is built in between XIN pin and XOUT pin. * Connect a ceramic resonator or a quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency. * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * This clock is used as the oscillating source of system clock. VL1 - VL3 LCD power source * Input 0 VL1 VL2 VL3 VCC voltage * Input 0 - VL3 voltage to LCD COM0 - COM3 Common output * LCD common output pins * COM2 and COM3 are not used at 1/2 duty ratio. * COM3 is not used at 1/3 duty ratio. SEG0 - SEG11 Segment output * LCD segment output pins P00/SEG16 - P07/SEG23 I/O port P0 I/O port P1 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each port to be individually programmed as either input or output. * Pull-down control is enabled. * LCD segment pins P10/SEG24 - P17/SEG31 * * * * P20 - P27 I/O port P2 * * * * 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * Key input (key-on wake up) interrupt input pins P30/SEG12 - P37/SEG15 Input port P3 * 4-bit Input port * CMOS compatible input level * Pull-down control is enabled. * LCD segment pins P40 Input port P4 * 1-bit input pin * CMOS compatible input level P41/ I/O port P4 * * * * P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY 4 Name 7-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * clock output pin * Interrupt input pins * Serial I/O1 function pins MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin Name Function Function except a port function P50/INT2, P51/INT3 I/O port P5 P52/RTP0, P53/RTP1 * * * * 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * Interrupt input pins * Real time port function pins * Timer function pins P54/CNTR0, P55/CNTR1 * Timer output pin P56/TOUT * A-D trigger input pin P57/ADT P60/AN0P67/AN7 I/O port P6 * * * * 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * A-D conversion input pins P70/XCOUT, P71/XCIN I/O port P7 * * * * * Sub-clock generating circuit I/O pins (Connect a resonator. External clock cannot be used.) 2-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. 5 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M3822 3 M 4 - XXX FP Package type FP : 80P6N-A package GP : 80P6S-A package HP : 80P6D-A package FS : 80D0 package ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character - : Standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 6 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (3) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP 80P6S-A ........................... 0.65 mm-pitch plastic molded QFP 80P6D-A ............................. 0.5 mm-pitch plastic molded QFP 80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version) Mitsubishi plans to expand the 3822 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions (2) ROM/PROM size .......................................... 8 K to 16 K bytes RAM size ....................................................... 384 to 512 bytes Memory Expansion Plan ROM size (bytes) 32K 28K 24K 20K Mass product 16K M38223M4/E4 12K Mass product 8K M38223M2 4K 192 256 384 512 640 768 896 1024 RAM size (bytes) As of May 1996 Currently supported products are listed below. Product M38223M4-XXXFP M38223E4-XXXFP M38223E4FP M38223M4-XXXGP M38223E4-XXXGP M38223E4GP M38223M4-XXXHP M38223E4-XXXHP M38223E4HP M38223E4FS M38222M2-XXXFP M38222M2-XXXGP M38222M2-XXXHP (P) ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package 80P6N-A 16384 (16254) 512 80P6S-A 80P6D-A 8192 (8062) 384 80D0 80P6N-A 80P6S-A 80P6D-A Remarks Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version 7 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) (2) ROM size ................................................................ 16 K bytes RAM size .................................................................. 512 bytes (3) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP Mitsubishi plans to expand the 3822 group (extended operating temperature version) as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions Memory Expansion Plan ROM size (bytes) 32K 28K 24K 20K Under development 16K M38223M4D 12K Mass product 8K M38222M2D 4K 192 256 384 512 640 768 896 1024 RAM size (bytes) Products under development: the development schedule and specification may be revised without notice. As of May 1996 Currently supported products are listed below. 8 Product ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package M38223M4DXXXFP M38222M2DXXXGP 16384(16254) 8192(8062) 512 384 80P6N-A 80P6S-A Remarks Mask ROM version Mask ROM version MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3822 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User's Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. CPU Mode Register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit. b7 b0 CPU mode register (CPUM (CM) : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns "1" when read) (Do not write "0" to this bit) Port XC switch bit 0 : I/O port 1 : XCIN , XCOUT Main clock ( X IN -XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN )/2 (high-speed mode) 1 : f(XIN )/8 (middle-speed mode) Internal system clock selection bit 0 : XIN -XOUT selected (middle-/high-speed mode) 1 : XCIN -XCOUT selected (low-speed mode) Fig. 1 Structure of CPU mode register 9 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. The interrupt vector area contains reset and interrupt vectors. RAM area 000016 RAM size (bytes) Address XXXX16 192 00FF 16 004016 256 013F 16 005016 384 01BF16 512 023F 16 640 02BF16 768 033F 16 896 03BF16 1024 043F 16 SFR area LCD display RAM area Zero page 010016 RAM XXXX16 Reserved area 044016 Not used ROM area ROM size (bytes) Address YYYY16 Address ZZZZ 16 4096 F000 16 F080 16 8192 E00016 E080 16 12288 D00016 D08016 16384 C00016 C08016 20480 B00016 B080 16 24576 A00016 A080 16 28672 900016 908016 32768 800016 808016 YYYY16 Reserved ROM area (128 bytes) ZZZZ 16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 Reserved ROM area FFFF 16 Fig. 2 Memory map diagram 10 Special page MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 002016 Timer X (low) (TXL) 002116 Timer X (high) (TXH) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (TYH) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 002416 Timer 1 (T1) 000616 Port P3 (P3) 000716 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 002A16 output control register (CKOUT) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 002C16 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 002E16 001016 003016 001116 003116 001216 003216 001316 003316 001416 003416 A-D control register (ADCON) 001516 003516 A-D conversion register (AD) 003616 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16 002B16 002D16 002F 16 003716 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F 16 Interrupt control register 2(ICON2) Fig.3 Memory map of special function register (SFR) 11 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers (ports P2, P41-P47, and P5-P7) The 3822 group has 49 programmable I/O pins arranged in seven I/O ports (ports P0-P2 and P41-P47 and P5-P7). The I/O ports P2, P41-P47, and P5-P7 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Direction Registers (ports P0 and P1) Ports P0 and P1 have direction registers which determine the input /output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When "0" is written to the bit 0 of a direction register, that port becomes an input port. When "1" is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used. Ports P3 and P40 These ports are only for input. Pull-up/Pull-down Control By setting the PULL register A (address 0016 16) or the PULL register B (address 001716), ports except for port P40 can control either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. 12 b7 b0 PULL register A (PULLA : address 0016 16) P00 -P07 pull-down P10 -P17 pull-down P20 -P27 pull-up P30 -P37 pull-down P70 , P71 pull-up Not used (return "0" when read) b7 b0 PULL register B (PULLB : address 0017 16) P41 -P43 pull-up P44 -P47 pull-up P50 -P53 pull-up P54 -P57 pull-up P60 , P63 pull-up P64 -P67 pull-up Not used (return "0" when read) 0 : Disable 1 : Enable Note : The contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Fig. 4 Structure of PULL register A and PULL register B MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Pin Name Input/Output P00/SEG16- P07/SEG23 Port P0 Input/output, individual ports P10/SEG24- P17/SEG31 Port P1 Input/output, individual ports P20 - P27 Port P2 Input/output, individual bits P34/SEG12- P37/SEG15 Port P3 Input I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level Non-Port Function LCD segment output LCD segment output Key input(Key-on wake up) interrupt input LCD segment output Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register PULL register A Interrupt control register 2 PULL register A Segment output enable register clock output P41/ External interrupt input Port P4 P44/RXD P45/TXD P46/SCLK1 P47/SRDY Serial I/O function I/O P50/INT2, P51/INT3 Input/output, individual bits P52/RTP0, P53/RTP1 P54/CNTR0 CMOS compatible input level CMOS 3-state output External interrupt input Real time port function oputput Timer I/O Port P5 P55/CNTR1 Timer I/O P56/TOUT Timer output P57/ADT A-D trigger input P60/AN0- P67/AN7 P70/XCOUT P71/XCIN COM0-COM3 SEG0-SEG11 (1) (2) (3) (4) P40 P42/INT0, P43/INT1 Diagram No. Port P6 A-D conversion input Port P7 Sub-clock generating circuit I/O LCD common output Common Segment output LCD segment output PULL register B output control register PULL register B Interrupt edge selection register PULL register B Serial I/O control register Serial I/O status register UART control register PULL register B Interrupt edge selection register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A-D control register PULL register A CPU mode register LCD mode register Segment output enable register (5) (2) (6) (7) (8) (9) (2) (10) (11) (12) (13) (12) (14) (15) (16) (17) (18) Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. 13 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1)Ports P0, P1 (2)Ports P2, P42 , P43, P50 , P51 VL2/VL3 Pull-up control VL1/VSS Segment output enable bit (Note) Direction register Direction register Data bus Data bus Port latch Port latch Key input (Key-on wake up) interrupt input INT0 -INT3 interrupt input Pull-down control Segment output enable bit Note : Bit 0 of direction register (3)Ports P34 -P37 (4)Port P40 VL2/VL3 Data bus VL1/VSS Pull-down control Segment output enable bit (6)Port P44 (5)Port P41 Pull-up control Pull-up control Serial I/O enable bit Reception enable bit Direction register Data bus Port latch output control bit Fig. 5 Port block diagram (1) 14 Direction register Data bus Port latch Serial I/O input MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (8)Port P46 (7)Port P45 Pull-up control P45/TXD P-channel output disable bit Serial I/O enable bit Transmission enable bit Direction register Data bus Serial I/O clock-synchronized selection bit Serial I/O enable bit Pull-up control Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Port latch Serial I/O clock output Serial I/O output Serial I/O clock input (9) Port P47 (10)Ports P52 , P53 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Pull-up control Pull-up control Direction register Port latch Data bus Port latch Real time port control bit Date for real time port Serial I/O ready output (11) Port P54 (12) Ports P5 5 , P57 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Timer X operating mode bit (Pulse output mode selection) Timer output CNTR0 interrupt input CNTR1 interrupt input A-D trigger interrupt input Fig. 6 Port block diagram (2) 15 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (14) Port P6 (13) Port P56 Pull-up control Pull-up control Direction register Direction register Data bus Data bus Port latch Port latch TOUT output control bit Timer output A-D conversion input Analog input pin selection bit (15) Port P7 0 (16) Port P7 1 Port selection/Pull-up control Port selection/Pull-up control Port XC switch bit Direction register Data bus Port XC switch bit Direction register Port latch Data bus Port latch Oscillation circuit Sub-clock generating circuit input Port P7 1 Port XC switch bit (17) COM0-COM3 (18) SEG 0-SEG11 VL2/VL3 VL3 VL2 VL1 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VSS Fig. 7 Port block diagram (3) 16 VL1/VSS The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupt Operation Interrupts occur by seventeen sources: eight external, eight internal, and one software. When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. Notes on Use When the active edge of an external interrupt (INT0-INT3, CNTR0, or CNTR 1 ) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to "0". (4) Enable the external interrupt which is selected. Table 1. Interrupt vector addresses and priority Interrupt Source Priority Vector Addresses (Note 1) High Low FFFD16 FFFC16 Reset (Note 2) 1 INT0 2 FFFB16 FFFA16 INT1 3 FFF916 FFF816 Serial I/O reception 4 FFF716 FFF616 Serial I/O transmission 5 FFF516 FFF416 Timer X Timer Y Timer 2 Timer 3 6 7 8 9 FFF316 FFF116 FFEF16 FFED16 FFF216 FFF016 FFEE16 FFEC16 CNTR0 10 FFEB16 FFEA16 CNTR1 11 FFE916 FFE816 Timer 1 12 FFE716 FFE616 INT2 13 FFE516 FFE416 INT3 14 FFE316 FFE216 Key input (Key-on wake up) 15 FFE116 FFE016 At falling of ADT input ADT 16 FFDF16 FFDE16 At completion of A-D conversion A-D conversion BRK instruction Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At falling of conjunction of input level for port P2 (at input mode) 17 FFDD16 FFDC16 At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when an "L" level is applied) Valid when ADT interrupt is selected External interrupt (valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority. 17 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Interrupt request BRK instruction Reset Fig. 8 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A 16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit Not used (return "0" when read) b7 b0 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C 16 ) b7 b0 INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D 16 ) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E 16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 0 b0 Interrupt control register 2 (ICON2 : address 003F 16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 9 Structure of interrupt-related registers 18 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER An example of using a key input interrupt is shown in Figure 10, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20-P23. Key Input Interrupt (Key-on Wake Up) A Key input interrupt request is generated by applying "L" level to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0". Port PXx "L" level output PULL register A Bit 2 = "1" Port P27 direction register = "1" Key input interrupt request Port P27 latch P27 output Port P26 direction register = "1" Port P26 latch P26 output Port P25 direction register = "1" Port P25 latch P25 output Port P24 direction register = "1" Port P24 latch P24 output P23 input P22 input P21 input P20 input Port P23 direction register = "0" Port P23 latch Port P2 Input reading circuit Port P22 direction register = "0" Port P22 latch Port P21 direction register = "0" Port P21 latch Port P20 direction register = "0" Port P20 latch P-channel transistor for pull-up CMOS output buffer Fig. 10 Connection example when using key input interrupt and port P2 block diagram 19 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. The 3822 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches "00 16", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". Real time port control bit "1" Data bus Q D P60 P60 data for real time port Latch P60 direction register "0" P60 latch Real time port control bit "1" Q D P61 P61 data for real time port Real time port control bit "0" Latch P61 direction register "0" P61 latch Timer X mode register write signal "1" f(XIN )/16 (f(XCIN )/16 in low-speed mode ) P54 /CNTR0 Timer X stop control bit Timer X operating mode bit "00","01","11" CNTR0 active edge switch bit "0" "10" "1" Pulse width measurement mode CNTR0 active edge switch bit "0" Timer X write control bit Timer X (low) latch (8) Timer X (high) latch (8) Timer X (low) (8) Timer X (high) (8) CNTR0 interrupt request Pulse output mode QS Timer Y operating mode bit "00","01","10" T "1" Q P54 direction register Pulse width HL continuously measurement mode P54 latch Rising edge detection Period measurement mode Falling edge detection P55 /CNTR1 f(XIN )/16 (f(XCIN )/16 in low-speed mode ) Timer Y stop control bit Timer Y (low) latch (8) "00","01","11" Timer Y (high) latch (8) Timer Y (low) (8) Timer Y (high) (8) "10" Timer Y operating mode bit "1" f(X IN )/16 (f(XCIN )/16 in low-speed mode ) Timer 1 count source selection bit "0" Timer 1 latch (8) XCIN CNTR1 interrupt request "11" Pulse output mode CNTR1 active edge switch bit "0" Timer X interrupt request Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 1 (8) "1" Timer 2 (8) "1" Timer 2 write control bit Timer Y interrupt request Timer 1 interrupt request Timer 2 interrupt request f(XIN)/16 (f(XCIN )/16 in low-speed mode) TOUT output active edge switch bit "0" P56/TOUT TOUT output control bit QS T "1" Q P56 latch P56 direction register TOUT output control bit f(XIN )/16(f(XCIN )/16 in low-speed mode ) Internal clock = XCIN /2. Fig. 11 Timer block diagram 20 "0" Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit Timer 3 interrupt request MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Pulse output mode Each time the timer underflows, a signal output from the CNTR 0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode. Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode. Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR0 active edge switch bit is "0", the timer counts while the input signal of CNTR0 pin is at "H". If it is "1", the timer counts while the input signal of CNTR0 pin is at "L". When using a timer in this mode, set the corresponding port P5 4 direction register to input mode. Timer X Write Control If the timer X write control bit is "0", when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is "1", when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Note on CNTR0 Interrupt Active Edge Selection CNTR0 interrupt active edge depends on the CNTR 0 active edge switch bit. Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from "0" to "1", data are output without the timer X.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. b7 b0 Timer X mode register (TXM : address 0027 16) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from "H" output in pulse output mode Measure "H" pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from "L" output in pulse output mode Measure "L" pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Fig. 12 Structure of timer X mode register 21 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Period measurement mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down/Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Pulse width HL continuously measurement mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Note on CNTR1 Interrupt Active Edge Selection CNTR1 interrupt active edge depends on the CNTR 1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 22 b7 b0 Timer Y mode register (TYM : address 0028 16) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop Fig. 13 Structure of timer Y mode register MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. Timer 2 Write Control If the timer 2 write control bit is "0", when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is "1", when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. Timer 2 Output Control When the timer 2 (T OUT) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the output mode. Note on Timer 1 to Timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. b7 b0 Timer 123 mode register (T123M : address 0029 16) TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT output control bit 0 : T OUT output disabled 1 : T OUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode) 1 : f(XCIN ) Not used (return "0" when read) Note : Internal clock is f(XCIN)/2 in the low-speed mode. Fig. 14 Structure of timer 123 mode register 23 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Clock Synchronous Serial I/O Mode Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816). Data bus Serial I/O control register Address 0018 16 Receive buffer Receive shift register P44/RXD Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Shift clock Clock control circuit P46 /SCLK1 f(XIN ) Serial I/O synchronization clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit Baud rate generator P47/SRDY1 F/F 1/4 Address 001C 16 1/4 Clock control circuit Falling-edge detector Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Serial I/O transmit interrupt request (TI) Shift clock P45 /TXD Transmit shift register Transmit buffer register (TB) Transmit buffer empty flag (TBE) Address 0019 16 Serial I/O status register Address 0018 16 Data bus Fig. 15 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output T XD D0 D1 D2 D3 D4 D5 D6 D7 Serial input R XD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal S RDY1 Write signal to receive/transmit buffer register (address 0018 16) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the T XD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 16 Operation of clock synchronous serial I/O function 24 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous Serial I/O1 (UART) Mode ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O1 mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- Data bus Address 0018 16 Serial I/O control register Address 001A16 Receive buffer register(RB) OE Character length selection bit P44 /RXD ST detector 7 bits Receive buffer full flag (RBF) Serial I/O receive interrupt request (RI) Receive shift register 1/16 8 bits PE FE UART control register Address 001B16 SP detector Clock control circuit Serial I/O synchronization clock selection bit P46 /SCLK1 f(XIN ) Frequency division ratio 1/(n+1) Baud rate generator Address 001C 16 BRG count source selection bit 1/4 ST/SP/PA generator Transmit shift register shift completion flag (TSC) 1/16 P45 /TXD Transmit shift register Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer register Address 0018 16 Transmit buffer empty flag (TBE) Serial I/O status register Address 0019 16 Data bus Fig. 17 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer register write signal TBE=0 TSC=0 TBE=1 Serial output T XD TBE=0 TSC=1 TBE=1 ST D0 D1 SP ST D0 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer register read signal Generated RBF=0 RBF=1 Serial input R XD ST D0 D1 D1 SP ST D0 D1 SP at 2nd bit in 2-stop-bit mode RBF=1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 18 Operation of UART serial I/O function 25 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O Control Register (SIO1CON) 001A16 The serial I/O control register contains eight control bits for the serial I/O function. UART Control Register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin. Serial I/O Status Register (SIO1STS) 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". Transmit Buffer/Receive Buffer Register (TB/ RB) 001816 The transmit buffer register and the receive buffer are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is "0". Baud Rate Generator (BRG) 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 26 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O status register (SIOSTS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty b0 b0 Serial I/O control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN ) 1: f(XIN )/4 Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Serial I/O1 synchronization clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronized serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronized serial I/O is selected. External clock input divided by 16 when UART is selected. Overrun error flag (OE) 0: No error 1: Overrun error SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as S RDY1 output pin Parity error flag (PE) 0: No error 1: Parity error Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Framing error flag (FE) 0: No error 1: Framing error Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Not used (returns "1" when read) Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full b7 b7 UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44 -P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44 -P47 operate as serial I/O pins) Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45 /TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read) Fig. 19 Structure of serial I/O control registers 27 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The functional blocks of the A-D converter are described below. A-D Conversion Register (AD) 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. A-D Control Register (ADCON) 003416 Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500 kHz during A-D conversion. The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to "1", this bit enables A-D conversion even by a falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger. b7 b0 A-D control register (ADCON : address 0034 16) Analog input pin selection bits 0 0 0 : P60 /AN0 0 0 1 : P61 /AN1 0 1 0 : P62 /AN2 0 1 1 : P63 /AN3 1 0 0 : P64 /AN4 1 0 1 : P65 /AN5 1 1 0 : P66 /AN6 1 1 1 : P67 /AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : OFF 1 : ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input falling Not used (returns "0" when read) Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages. Channel Selector The channel selector selects one of the input ports P6 7/AN 7 to P60/AN0. Fig. 20 Structure of A-D control register Data bus b0 b7 A-D control register P57/ADT 3 ADT/A-D interrupt request A-D control circuit P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 Channel selector P60/AN0 Comparator A-D conversion register 8 Resistor ladder P66/AN6 P67/AN7 AVSS Fig. 21 A-D converter block diagram 28 VREF MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. LCD DRIVE CONTROL CIRCUIT The 3822 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. LCD display RAM Segment output enable register LCD mode register Selector Timing controller Common driver Segment driver Bias control circuit A maximum of 32 segment output pins and 4 common output pins can be used. Up to 128 pixels can be controlled for LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register, * * * * * * * * b7 Table 2. Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 64 dots or 8 segment LCD 8 digits 96 dots or 8 segment LCD 12 digits 128 dots or 8 segment LCD 16 digits b0 Segment output enable register (SEG : address 0038 16) Segment output enable bit 0 0 : Input ports P3 4 -P37 1 : Segment output SEG 12-SEG15 Segment output enable bit 1 0 : I/O ports P0 0, P01 1 : Segment output SEG 16,SEG17 Segment output enable bit 2 0 : I/O ports P0 2-P07 1 : Segment output SEG 18-SEG23 Segment output enable bit 3 0 : I/O ports P1 0,P11 1 : Segment output SEG 24,SEG25 Segment output enable bit 4 0 : I/O port P1 2 1 : Segment output SEG 26 Segment output enable bit 5 0 : I/O ports P1 3-P17 1 : Segment output SEG 27-SEG31 Not used (return "0" when read) (Do not write "1" to this bit) b7 b0 LCD mode register (LM : address 0039 16) Duty ratio selection bits 0 0 : Not available 0 1 : 2 (use COM 0,COM 1) 1 0 : 3 (use COM 0-COM 2) 1 1 : 4 (use COM 0-COM 3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Not used (returns "0" when read) (Do not write "1" to this bit) LCD circuit divider division ratio selection bits 0 0 : CLOCK input 0 1 : 2 division of CLOCK input 1 0 : 4 division of CLOCK input 1 1 : 8 division of CLOCK input LCDCK count source selection bit (Note) 0 : f(XCIN )/32 1 : f(XIN )/8192 Note : LCDCK is a clock for a LCD timing controller. Fig. 22 Structure of segment output enable register and LCD mode register 29 30 Fig. 23 Block diagram of LCD controller/driver SEG2 SEG3 P34/SEG12 Bias control bit VSS VL1 VL2 VL3 Bias control LCD display RAM P16/SEG30 P17/SEG31 Segment Segment driver driver Segment Segment Segment Segment driver driver driver driver SEG1 Selector Selector Selector Selector Selector Selector SEG0 Address 004F 16 Address 0041 16 Address 0040 16 Data bus Common driver Common driver Common driver COM0 COM1 COM2 COM3 Common driver 2 Timing controller 2 LCD circuit divider division ratio selection bits Duty ratio selection bits LCD enable bit LCDCK LCD divider "0" f(XCIN )/32 LCDCK count source selection bit "1" f(XIN )/8192 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1-VL3), apply the voltage shown in Table 3 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 3. Bias control and applied voltage to VL1-VL3 Bias value 1/3 bias 1/2 bias VL3=VLCD VL2=VL1=1/2 VLCD Common Pin and Duty Ratio Control The common pins (COM0-COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD Note 1 : VLCD is the maximum value of supplied voltage for the LCD panel. Table 4. Duty ratio control and common pins used Duty ratio Duty ratio selection bit 2 Bit 1 0 Bit 0 1 3 4 1 1 0 1 Common pins used COM0, COM1 (Note 1) COM0-COM2 (Note 2) COM0-COM3 Notes 1 : COM2 and COM3 are open 2 : COM3 is open Contrast control VL3 Contrast control VL3 R1 VL2 R4 VL2 R2 VL1 VL1 R5 R3 1/3 bias R1 = R2 = R3 1/2 bias R4 = R5 Fig. 24 Example of circuit at each bias 31 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Display RAM LCD Drive Timing Address 004016 to 004F16 is the designated RAM for the LCD display. When "1" are written to these addresses, the corresponding segments of the LCD display panel are turned on. The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK)= (frequency of count source for LCDCK) (divider division ratio for LCD) Frame frequency= f(LCDCK) duty ratio Bit 7 6 5 4 3 2 1 0 Address 004016 004116 004216 004316 004416 SEG5 SEG7 SEG9 SEG4 SEG6 SEG8 004516 004616 004716 004816 SEG11 SEG13 SEG10 SEG12 SEG15 SEG17 SEG19 SEG14 SEG16 SEG18 SEG21 SEG23 SEG25 SEG20 SEG22 SEG24 SEG27 SEG29 SEG31 SEG26 SEG28 SEG30 004916 004A16 004B16 004C16 004D16 004E16 004F16 Fig. 25 LCD display RAM map 32 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 SEG1 SEG0 SEG3 SEG2 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 VL3 VSS SEG0 OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2=VL1 VSS COM0 COM1 COM2 VL3 VSS SEG0 ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2=VL1 VSS COM0 COM1 VL3 VSS SEG0 ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 26 LCD drive waveform (1/2 bias) 33 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 VL3 SEG0 VSS OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2 VL1 VSS COM0 COM1 COM2 VL3 SEG0 VSS ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2 VL1 VSS COM0 COM1 VL3 SEG0 VSS ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 27 LCD drive waveform (1/3 bias) 34 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK OUTPUT FUNCTION The internal system clock can be output from port P41 by setting the output control register. Set bit 1 of the port P4 direction register to when outputting clock. b7 b0 output control register (CKOUT : address 002A 16) output control bit 0 : Port function 1 : clock output Not used (return "0" when read) Fig. 28 Structure of output control register 35 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.5 V and 5.5 V, and the oscillation should be stable), reset is released. In order to give the XIN clock time to stabilize, internal operation does not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are connected together and 512 cycles of f(XIN)/16) are complete. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.5 V for V CC of 2.5 V (Extended operating temperature version: the reset input voltage is less than 0.6V for VCC of 3.0V). Address 0016 ( 2 ) Port P1 direction register (0003 16) * * * 0016 ( 3 ) Port P2 direction register (000516) * * * 0016 ( 4 ) Port P4 direction register (000916) * * * 0016 ( 5 ) Port P5 direction register (000B16) * * * 0016 ( 6 ) Port P6 direction register (000D 16) * * * 0016 ( 7 ) Port P7 direction register (000F16 ) * * * 0016 ( 8 ) PULL register A (001616) * * * 0 0 0 0 1 0 1 1 ( 9 ) PULL register B (001716) * * * RESET VCC Power source voltage (Note) 0V Reset input voltage 0V 0.2VCC Note. Reset release voltage : VCC = 2.5V (Extended operating temperature version : 3.0V) RESET VCC Power source voltage detection circuit Fig. 29 Example of reset circuit 0016 (10) Serial I/O status register (001916) * * * 1 0 0 0 0 0 0 0 (11) Serial I/O control register (001A16) * * * Power on Register contents ( 1 ) Port P0 direction register (000116) * * * 0016 (12) UART control register (001B16) * * * 1 1 1 0 0 0 0 0 (13) Timer X (low) (002016 ) * * * FF16 (14) Timer X (high) (002116 ) * * * FF16 (15) Timer Y (low) (002216 ) * * * FF16 (16) Timer Y (high) (002316 ) * * * FF16 (17) Timer 1 (002416 ) * * * FF16 (18) Timer 2 (002516 ) * * * 0116 (19) Timer 3 (002616 ) * * * FF16 (20) Timer X mode register (002716 ) * * * 0016 (21) Timer Y mode register (002816 ) * * * 0016 (22) Timer 123 mode register (002916 ) * * * 0016 (23) output control register (002A16) * * * 0016 (24) A-D control register (003416 ) * * * 0 0 0 0 1 0 0 0 (25) Segment output enable register (003816 ) * * * 0016 (26) LCD mode register (003916 ) * * * 0016 (27) Interrupt edge selection register (003A16) * * * 0016 (28) CPU mode register (003B16) * * * 0 1 0 0 1 0 0 0 (29) Interrupt request register 1 (003C16) * * * 0016 (30) Interrupt request register 2 (003D16) * * * 0016 (31) Interrupt control register 1 (003E16) * * * 0016 (32) Interrupt control register 2 (003F16) * * * 0016 (33) Processor status register (34) Program counter (PS) 1 (PCH) Contents of address FFFD 16 (PCL ) Contents of address FFFC 16 Note : Undefined The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. Fig. 30 Internal state of microcomputer after reset 36 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN RESET Internal reset Reset address from vector table Address ? Data ? ? ? FFFC FFFD ADL ADH, ADL ADH SYNC XIN : about 8200 clock cycles Notes 1 : f(XIN ) and f() are in the relationship : f(XIN ) = 8 * f() Notes 2 : A question mark (?) indicates an undefined status that depends on the previous status. Fig. 31 Reset sequence 37 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT Oscillation Control The 3822 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the X OUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and X CIN and X COUT pins function as I/O ports. The pull-up resistor of XCIN and X COUT pins must be made invalid to use the sub-clock. Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116". Either X IN or X CIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to "0". Set the timer 1 and timer 2 interrupt enable bits to disabled ("0") before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Frequency Control Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected. Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. High-speed mode The internal clock is half the frequency of XIN. Low-speed mode * The internal clock is half the frequency of XCIN. * A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency on condition that f(XIN)>3f(XCIN). XCIN XCOUT Rf XIN Rd CCOUT CCIN XOUT CIN Fig. 32 Ceramic resonator circuit XCIN Rf CCIN XCOUT XIN CCOUT XOUT Open Rd External oscillation circuit VCC VSS Fig. 33 External clock input circuit 38 COUT MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCOUT XCIN "1" "0" Port XC switch bit XIN XOUT Timer 1 count source selection bit Internal system clock selection bit (Note) Low-speed mode "1" 1/2 "0" Middle-/High-speed mode Timer 2 count source selection bit "1" Timer 1 1/2 1/4 "0" "0" Timer 2 "1" Main clock division ratio selection bit Middle-speed mode Timing (Internal system clock) High-speed mode or Low-speed mode Main clock stop bit Q S S R STP instruction WIT instruction Q R Q S R STP instruction Reset Interrupt disable flag I Interrupt request Note : When using the low-speed mode, set the port X C switch bit to "1" . Fig. 34 Clock generating circuit block diagram 39 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset " "0 CM " "1 M6 C " "1 " "0 CM7 =0(8 MHz selected) CM6 =0(High-speed) CM5 =0(8 MHz oscillating) CM4 =0(32 kHz stopped) C "0 M4 " CM "1 " 6 "1 " "0 " Middle-speed mode (f() =1 MHz) CM6 "1" "0" CM6 "1" "0" High-speed mode (f() =4 MHz) CM7 =0(8 MHz selected) CM6 =0(High-speed) CM5 =0(8 MHz oscillating) CM4 =1(32 kHz oscillating) CM7 "1" CM 7 "1" "0" "0" CM7 =0(8 MHz selected) CM6 =1(Middle-speed) CM5 =0(8 MHz oscillating) CM4 =1(32 kHz oscillating) "0" CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) " CM5 "1" 5 CM " "1 M6 C " "1 Low-speed mode (f() =16 kHz) CM7 =1(32 kHz selected) CM6 =1(Middle-speed) CM5 =1(8 MHz stopped) CM4 =1(32 kHz oscillating) Low-speed mode (f() =16 kHz) "0 0" " "1 " CM7 =1(32 kHz selected) CM6 =0(High-speed) CM5 =0(8 MHz oscillating) CM4 =1(32 kHz oscillating) C "0 M5 " CM 6 "1 " "0 " CM6 "1" "0" Low-speed mode (f() =16 kHz) CM 5 "1" CM4 "1" 4 High-speed mode (f() =4 MHz) "0" "0" "0" CM7 =0(8 MHz selected) CM6 =1(Middle-speed) CM5 =0(8 MHz oscillating) CM4 =0(32 kHz stopped) CM 4 "1" CM6 "1" Middle-speed mode (f() =1 MHz) Low-speed mode (f() =16 kHz) "0" CM7 =1(32 kHz selected) CM6 =0(High-speed) CM5 =1(8 MHz stopped) CM4 =1(32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B 16) CM4 : Port Xc switch bit 0: I/O port 1: XCIN , XCOUT CM5 : Main clock (XIN -XOUT ) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN )/2 (high-speed mode) 1: f(XIN )/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN -XOUT selected (middle-/high-speed mode) 1: XCIN -XCOUT selected (low-speed mode) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : Timer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle-/highspeed mode. 7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. indicates the internal clock. Fig. 35 State transitions of internal clock 40 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register Serial I/O The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1". Serial I/O continues to output the final bit from the TXD pin after transmission is completed. Interrupt A-D Converter The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. 41 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Package Name of Programming Adapter 80P6N-A PCA4738F-80A 80P6S-A PCA4738G-80 80P6D-A PCA4738H-80 80D0 PCA4738L-80A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 36 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 36 Programming and testing of One Time PROM version 42 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI VI VI Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P34-P37, P40-P47, P50-P57, P60-P67, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN VO Output voltage P00-P07, P10-P17 VO Output voltage P34-P37 Output voltage P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 Output voltage SEG0-SEG11 Output voltage XOUT Power dissipation Operating temperature Storage temperature VI VO VO VO Pd Topr Tstg Conditions Ratings -0.3 to 7.0 Unit V -0.3 to VCC +0.3 V -0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VL3 +0.3 -0.3 to VL3 +0.3 V V V V V V V -0.3 to VCC +0.3 V -0.3 to VL3 +0.3 -0.3 to VCC +0.3 300 -20 to 85 (Note 1) -40 to 125 (Note 2) V V mW C C All voltages are based on VSS. Output transistors are cut off. At output port At segment output At segment output Ta = 25 C Notes 1 : Extended operating temperature version : -40 to 85C 2 : Extended operating temperature version : -65 to 150C RECOMMENDED OPERATING CONDITIONS (VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5V, Ta = -20 to 85C) Symbol VCC Parameter Power source voltage High-speed mode f(XIN)=8 MHz Middle-speed mode Ta = -20 to 85C f(XIN)=8 MHz Ta = -40 to -20C Low-speed mode VSS VREF AVSS VIA VIH VIH VIH VIH VIL VIL VIL VIL Ta = -20 to 85C Ta = -40 to -20C Power source voltage A-D conversion reference input voltage Analog power source voltage Analog input voltage AN0-AM7 "H" input voltage P00-P07, P10-P17, P34-P37, P40, P41, P45, P47, P52, P53, P56, P60-P67, P70, P71 (CM4=0) "H" input voltage P20-P27, P42-P44, P46, P50, P51, P54, P55, P57 "H" input voltage RESET "H" input voltage XIN "L" input voltage P00-P07, P10-P17, P34-P37, P40, P41, P45, P47, P52, P53, P56, P60-P67, P70, P71 (CM4=0) "L" input voltage P20-P27, P42-P44, P46, P50, P51, P54, P55, P57 "L" input voltage RESET "L" input voltage XIN Min. 4.0 2.5 3.0 2.5 3.0 Limits Typ. 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 Unit V AVSS VCC V V V V 0.7 VCC VCC V 0.8 VCC 0.8 VCC 0.8 VCC VCC VCC VCC V V V 0 0.3 VCC V 0 0 0 0.2 VCC V 0.2 VCC 0.2 VCC V 2 VCC 0 V 43 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RECOMMENDED OPERATING CONDITIONS (VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) Parameter "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "H" peak output current "H" peak output current "L" peak output current "L" peak output current "H" average output current "H" average output current IOL(avg) IOL(avg) "L" average output current "L" average output current f(CNTR0) f(CNTR1) Input frequency for timers X and Y (duty cycle 50 %) f(XIN) f(XCIN) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17 (Note 2) P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 2) P00-P07, P10-P17 (Note 2) P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 2) P00-P07, P10-P17 (Note 3) P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 3) P00-P07, P10-P17 (Note 3) P20-P27, P40-P47, P50-P57, P60-P67, P70, P71 (Note 3) 4.0 V VCC 5.5 V 2.5 V VCC 4.0 V High-speed mode (4.0 V VCC 5.5 V) Main clock input oscillation High-speed mode (2.5 V VCC 4.0 V) frequency (Note 4) Middle-speed mode Sub-clock input oscillation frequency (Note 4, 5) Min. Limits Typ. Max. -40 -40 40 40 -20 -20 20 20 -2 Unit mA mA mA mA mA mA mA mA mA -5 mA 5 mA 10 mA -1.0 mA -2.5 mA 2.5 mA 5.0 mA 4.0 MHz (2XVCC)-4 MHz 8.0 (4XVCC)-8 8.0 32.768 50 MHz MHz MHz kHz Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current is an average value measured over 100 ms. 4 : When the oscillation frequency has a duty cycle of 50%. 5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 44 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol VOH VOH VOL VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH Parameter "H" output voltage P00-P07, P10-P17 "H" output voltage P20-P27, P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) "L" output voltage P00-P07, P10-P17 "L" output voltage P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 1) Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0-INT3, P20-P27 RXD, SCLK RESET P00-P07, P10-P17, P30-P37 Test conditions IOH = -2.5 mA IOH = -0.6 mA VCC = 2.5 V IOH = -5 mA IOH = -1.25 mA IOH = -1.25 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V RESET: VCC=2.5 V to 5.5 V VI = VCC Pull-downs "off" VCC= 5.0 V, Ta = -20 to 85C VI = VCC Ta = -40 to -20C Pull-downs "on" VCC= 3.0 V, VI = VCC Pull-downs "on" IIH "H" input current P20-P27, P40-P47, P50-P57, P60-P67, P70, P71 IIH IIH "H" input current "H" input current RESET XIN IIL "L" input current P00-P07, P10-P17, P34-P37, P40 IIL "L" input current P20-P27, P41-P47, P50-P57, P60-P67, P70-P77 Ta = -20 to 85C Min. VCC-2.0 Limits Typ. Unit V VCC-1.0 V VCC-2.0 VCC-0.5 V V VCC-1.0 V 2.0 0.5 V V 1.0 V 2.0 0.5 V 1.0 V 0.5 0.5 0.5 30 6.0 70 140 70 170 25 45 25 55 VI = VCC VI = VCC A A A 5.0 A 5.0 A A -5.0 A -5.0 A 4.0 VI = VCC V V V V 5.0 Ta = -40 to -20C VI = VSS Pull-ups "off" VCC= 5.0 V, VI = VSS Pull-ups "on" VCC= 3.0 V, VI = VSS Pull-ups "on" VI = VSS VI = VSS Max. -30 -70 -140 A -6 -25 -45 A A -5.0 "L" input current RESET -4.0 A "L" input current XIN Note 1 : When "1" is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. IIL IIL 45 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol VRAM ICC Parameter RAM hold voltage Power source current Test conditions When clock is stopped * High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors "off" A-D converter in operating * High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" A-D converter stopped * Low-speed mode, VCC = 5 V, Ta 55C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" * Low-speed mode, VCC = 5 V, Ta = 25C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" * Low-speed mode, VCC = 3 V, Ta 55C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" * Low-speed mode, VCC = 3 V, Ta = 25C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" All oscillation stopped (in STP state) Output transistors "off" 46 Ta = 25 C Ta = 85 C Min. 2.0 Limits Typ. Max. 5.5 Unit V 6.4 13 mA 1.6 3.2 mA 25 36 A 7.0 14.0 A 15 22 A 4.5 9.0 A 0.1 1.0 10 A MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, 4 MHz f(XIN) 8 MHz, middle-/high-speed mode, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol Parameter Test conditions - - Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 5 V tCONV Conversion time f(XIN) = 8 MHz RLADDER VREF IIA Ladder resistor Reference input current Analog port input current VREF = 5 V Min. Limits Typ. Max. 8 2 12.5 (Note) Unit Bits LSB s 12 35 100 k 50 150 200 A 5.0 A Note : When an internal trigger is used in middle-speed mode, it is 14 s. 47 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns 2 125 45 40 200 80 80 80 80 800 370 370 220 100 Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART). TIMING REQUIREMENTS 2(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Note : When f(XIN) = 2 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is "0" (UART). 48 Min. 2 125 45 40 500 230 230 230 230 2000 950 950 400 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol twH(SCLK) twL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Limits Parameter Min. Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Typ. Max. tc(SCLK)/2-30 tc(SCLK)/2-30 140 -30 30 30 30 30 10 10 Unit ns ns ns ns ns ns ns ns Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2 : XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol twH(SCLK) twL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Min. tc(SCLK)/2-50 tc(SCLK)/2-50 Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Typ. Max. 350 -30 20 20 50 50 50 50 Unit ns ns ns ns ns ns ns ns Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2 : XOUT and XCOUT pins are excluded. Measurement output pin 1 k 100 pF Measurement output pin 100 pF CMOS output N-channel open-drain output (Note) Note : When bit 4 of the UART control register (address 001B 16) is "1". (N-channel open-drain output mode) Fig. 37 Circuit for measuring output switching characteristics (1) 49 MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAM tc(CNTR) twH(CNTR) CNTR 0,CNTR1 twL(CNTR) 0.8VCC 0.2VCC twH(INT) INT0-INT3 twL(INT) 0.8VCC 0.2VCC tw(RESET) RESET 0.8VCC 0.2VCC tc(XIN) twL(XIN ) twH(XIN) XIN 0.8VCC 0.2VCC tc(SCLK) tf tr twL(SCLK) SCLK 0.8VCC 0.2VCC tsu(RXD-SCLK ) RX D 50 th(SCLK -RXD) 0.8VCC 0.2VCC td(SCLK -TXD) TXD twH(SCLK ) tv(SCLK-TXD) MITSUBISHI MICROCOMPUTERS 3822 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials * * * * * * (c) 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jan. 1998. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 3822 GROUP DATA SHEET Revision Description First Edition Rev. date 980120 (1/1)