M38223E4FS - Mitsubishi Electric Semiconductor

SEG

/ADT

RDY

CLK

/INT

/CNTR

/RTP

/INT

/CNTR

/AN

/φ

OUT

RESET

COUT

CIN

M38223M4-XXXFP

SEG

REF

COM

/AN

OUT

SEG

/SEG

3822 Group

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6N-A

80-pin plastic-molded QFP

DESCRIPTION

The 3822 group is the 8-bit microcomputer based on the 740 fam-

ily core technology.

The 3822 group has the LCD drive control circuit an 8-channel A-

D converter, and a Serial I/O as additional functions.

The various microcomputers in the 3822 group include variations

of internal memory size and packaging. For details, refer to the

section on part numbering.

For details on availability of microcomputers in the 3822 group, re-

fer to the section on group expansion.

FEATURES

•Basic machine-language instructions....................................... 71

•The minimum instruction execution time ............................ 0.5 µs

(at 8MHz oscillation frequency)

•Memory size

ROM .................................................................. 4 K to 32 K bytes

RAM ................................................................. 192 to 1024 bytes

•Programmable input/output ports ............................................. 49

•Software pull-up/pull-down resistors (Ports P0-P7 except Port P40)

•Interrupts .................................................. 17 sources, 16 vectors

(includes key input interrupt)

•Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2

•Serial I/O1 .....................8-bit ✕ 1 (UART or Clock-synchronized)

•Serial I/O2 ........................................................ 8-bit ✕ 8 channels

•LCD drive control circuit

Bias ................................................................................... 1/2, 1/3

Duty ............................................................................1/2, 1/3, 1/4

Common output .......................................................................... 4

Segment output......................................................................... 32

•2 Clock generating circuit

Clock (XIN-XOUT).................................. Internal feedback resistor

Sub-clock (XCIN-XCOUT)..........Without internal feedback resistor

(connect to external ceramic resonator or quartz-crystal oscillator)

•Power source voltage

In high-speed mode ....................................................4.0 to 5.5 V

(at 8MHz oscillation frequency and high-speed selected)

In middle-speed mode ................................................2.5 to 5.5 V

(at 8MHz oscillation frequency and middle-speed selected)

In low-speed mode......................................................2.5 to 5.5 V

(Extended operating temperature version: 3.0 V to 5.5 V)

•Power dissipation

In high-speed mode ...........................................................32 mW

(at 8 MHz oscillation frequency)

In low-speed mode..............................................................45 µW

(at 32 kHz oscillation frequency, at 3 V power source voltage)

•Operating temperature range ...................................– 20 to 8 5°C

(Extended operating temperature version: –40 to 85°C)

APPLICATIONS

Camera, household appliances, consumer electronics, etc.

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6S-A/80P6D-A

80-pin plastic-molded QFP

M38223M4-XXXGP

M38223M4-XXXHP

/φ

OUT

RESET

COUT

CIN

SEG

REF

COM

/ADT

RDY

CLK

/INT

/CNTR

/RTP

/INT

/CNTR

/AN

OUT

SEG

/SEG

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

FUNCTIONAL BLOCK DIAGRAM (Package : 80P6S-A)

ADT

CNTR

,CNTR

OUT

CPU A

ROM

P7(2)

SI/O(8)

COM

CIN

COUT

φLCD

drive control

circuit

RAM

LCD display

RAM

(16 bytes)

Timer X(16)

Timer Y(16)

Timer 1(8) Timer 2(8)

Timer 3(8)

Data bus

Clock generating

circuit

Clock

input

Clock

output

OUT

COUT

Sub-

clock

output

CIN

Sub-

clock

input

Reset input (5 V)

RESET

Key-on wake up

Real time port function

INT

,INT

A-D converter(8)

RTP

,RTP

29 25 71 30

(0 V)

SEG

47 54

I/O port P0

P0(8)

39 46

I/O port P1

P1(8)

31 38

I/O port P2

P2(8)

Input port P3

P3(8)

17 24

I/O port P4

P4(8)

916

I/O port P5

P5(8)

INT

,INT

REF

(0 V)

I/O port P6

P6(8)

I/O port P7

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Function

• Apply voltage of 2.5 V to 5.5 V to VCC, and 0 V to VSS.

• Reference voltage input pin for A-D converter.

• GND input pin for A-D converter.

• Connect to VSS.

•Reset input pin for active “L”

• Input and output pins for the main clock generating circuit.

• Feedback resistor is built in between XIN pin and XOUT pin.

• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set

the oscillation frequency.

• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• This clock is used as the oscillating source of system clock.

• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage

• Input 0 – VL3 voltage to LCD

• LCD common output pins

• COM2 and COM3 are not used at 1/2 duty ratio.

• COM3 is not used at 1/3 duty ratio.

• LCD segment output pins

• 8-bit I/O port

• CMOS compatible input level

• CMOS 3-state output structure

• I/O direction register allows each port to be individually

programmed as either input or output.

• Pull-down control is enabled.

• 8-bit I/O port

• CMOS compatible input level

• CMOS 3-state output structure

• I/O direction register allows each pin to be individually

programmed as either input or output.

• Pull-up control is enabled.

• 4-bit Input port

• CMOS compatible input level

• Pull-down control is enabled.

• 1-bit input pin

• CMOS compatible input level

• 7-bit I/O port

• CMOS compatible input level

• CMOS 3-state output structure

• I/O direction register allows each pin to be individually

programmed as either input or output.

• Pull-up control is enabled.

• LCD segment pins

• Key input (key-on wake up) interrupt

input pins

• LCD segment pins

•φ clock output pin

• Interrupt input pins

• Serial I/O1 function pins

VCC, VSS

VREF

AVSS

RESET

XIN

XOUT

VL1 – VL3

COM

– COM

SEG

– SEG

P00/

SEG

–

P07/

SEG

/SEG

–

P17/

SEG

P20

–

P27

P30/

SEG

–

P37/

SEG

P40

P41/ φ

P42/INT0,

P43/INT1

P44/RXD,

P45/TXD,

P46/SCLK,

P47/SRDY

Name

Power source

Analog reference

voltage

Analog power

source

Reset input

Clock input

Clock output

LCD power source

Common output

Segment output

I/O port P0

I/O port P1

I/O port P2

Input port P3

Input port P4

I/O port P4

Function except a port function

PIN DESCRIPTION

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Function

• 8-bit I/O port

• CMOS compatible input level

• CMOS 3-state output structure

• I/O direction register allows each pin to be individually

programmed as either input or output.

• Pull-up control is enabled.

• 8-bit I/O port

• CMOS compatible input level

• CMOS 3-state output structure

• I/O direction register allows each pin to be individually

programmed as either input or output.

• Pull-up control is enabled.

• 2-bit I/O port

• CMOS compatible input level

• CMOS 3-state output structure

• I/O direction register allows each pin to be individually

programmed as either input or output.

• Pull-up control is enabled.

P50/INT2,

P51/INT3

P52/RTP0,

P53/RTP1

P54/CNTR0,

P55/CNTR1

P56/TOUT

P57/ADT

P60/AN0-

P67/AN7

P70/XCOUT,

P71/XCIN

PIN DESCRIPTION

Name

I/O port P5

I/O port P6

I/O port P7

Function except a port function

• Interrupt input pins

• Real time port function pins

• Timer function pins

• Timer output pin

• A-D trigger input pin

• A-D conversion input pins

• Sub-clock generating circuit I/O pins

(Connect a resonator. External clock

cannot be used.)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

PART NUMBERING

M3822 3 M 4 - XXX

Product

ROM/PROM size

: 4096 bytes

: 8192 bytes

: 12288 bytes

: 16384 bytes

: 20480 bytes

: 24576 bytes

: 28672 bytes

: 32768 bytes

The first 128 bytes and the last 2 bytes of ROM

are reserved areas ; they cannot be used.

Memory type

E : Mask ROM version

: EPROM or One Time PROM version

RAM size

: 192 bytes

: 256 bytes

: 384 bytes

: 512 bytes

: 640 bytes

: 768 bytes

: 896 bytes

: 1024 bytes

Package type

ROM number

Omitted in some types.

Normally, using hyphen

When electrical characteristic, or division of quality

identification code using alphanumeric character

– : Standard

D : Extended operating temperature version

: 80P6N-A package

: 80P6S-A package

: 80P6D-A package

: 80D0 package

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Remarks

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

EPROM version

Mask ROM version

Product

M38223M4-XXXFP

M38223E4-XXXFP

M38223E4FP

M38223M4-XXXGP

M38223E4-XXXGP

M38223E4GP

M38223M4-XXXHP

M38223E4-XXXHP

M38223E4HP

M38223E4FS

M38222M2-XXXFP

M38222M2-XXXGP

M38222M2-XXXHP

GROUP EXPANSION

Mitsubishi plans to expand the 3822 group as follows:

(1) Support for mask ROM, One Time PROM, and EPROM

versions

(2) ROM/PROM size.......................................... 8 K to 16 K bytes

RAM size....................................................... 384 to 512 bytes

(3) Packages

80P6N-A............................. 0.8 mm-pitch plastic molded QFP

80P6S-A........................... 0.65 mm-pitch plastic molded QFP

80P6D-A............................. 0.5 mm-pitch plastic molded QFP

80D0................ 0.8 mm-pitch ceramic LCC (EPROM version)

Memory Expansion Plan

Currently supported products are listed below. As of May 1996

RAM size (bytes)

512

384

Package

80P6N-A

80P6S-A

80P6D-A

80D0

80P6N-A

80P6S-A

80P6D-A

16384

(16254)

(P) ROM size (bytes)

ROM size for User in ( )

8192

(8062)

M38223M4/E4

Mass product

ROM size (bytes)

32K

28K

24K

20K

16K

12K

192 256 384 512 640 768 896 1024

RAM size (bytes)

M38223M2

Mass product

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

GROUP EXPANSION

(EXTENDED OPERATING TEMPERATURE VERSION)

Mitsubishi plans to expand the 3822 group (extended operating

temperature version) as follows:

(1) Support for mask ROM, One Time PROM, and EPROM

versions

(2) ROM size ................................................................16 K bytes

RAM size.................................................................. 512 bytes

(3) Packages

80P6N-A............................. 0.8 mm-pitch plastic molded QFP

Memory Expansion Plan

Currently supported products are listed below.

RAM size (bytes)

512

384

16384(16254)

8192(8062)

Remarks

Mask ROM version

As of May 1996

Package

80P6N-A

80P6S-A

Product

M38223M4DXXXFP

M38222M2DXXXGP

ROM size (bytes)

ROM size for User in ( )

Products under development: the development schedule and specification may be revised without notice.

M38223M4D

Under development

ROM size (bytes)

32K

28K

24K

20K

16K

12K

192 256 384 512 640 768 896 1024

RAM size (bytes)

M38222M2D

Mass product

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The 3822 group uses the standard 740 family instruction set. Refer

to the table of 740 family addressing modes and machine instruc-

tions or the SERIES 740 <Software> User’s Manual for details on

the instruction set.

Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used.

The STP, WIT, MUL, and DIV instruction can be used.

CPU Mode Register

The CPU mode register is allocated at address 003B16.

The CPU mode register contains the stack page selection bit and

the internal system clock selection bit.

Fig. 1 Structure of CPU mode register

Not available

Processor mode bits

b1 b0

0 0 : Single-chip mode

0 1 :

1 0 :

1 1 :

Stack page selection bit

0 : RAM in the zero page is used as stack area

1 : RAM in page 1 is used as stack area

Not used (returns “1” when read)

(Do not write “0” to this bit)

Port X

switch bit

0 : I/O port

1 : X

CIN

, X

COUT

Main clock ( X

–X

OUT

) stop bit

0 : Oscillating

1 : Stopped

Main clock division ratio selection bit

0 : f(X

)/2 (high-speed mode)

1 : f(X

)/8 (middle-speed mode)

Internal system clock selection bit

0 : X

-X

OUT

selected (middle-/high-speed mode)

1 : X

CIN

-X

COUT

selected (low-speed mode)

CPU mode register

(CPUM (CM) : address 003B

)

b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

MEMORY

Special Function Register (SFR) Area

The Special Function Register area in the zero page contains con-

trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine

calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the

zero page area. The internal RAM and the special function regis-

ters (SFR) are allocated to this area.

The zero page addressing mode can be used to specify memory

and register addresses in the zero page area. Access to this area

with only 2 bytes is possible in the zero page addressing mode.

Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the

special page area. The special page addressing mode can be

used to specify memory addresses in the special page area. Ac-

cess to this area with only 2 bytes is possible in the special page

addressing mode.

Fig. 2 Memory map diagram

192

256

384

512

640

768

896

1024

00FF

013F

01BF

023F

02BF

033F

03BF

043F

RAM area

RAM size

(bytes) Address

XXXX

4096

8192

12288

16384

20480

24576

28672

32768

F000

E000

D000

C000

B000

A000

9000

8000

F080

E080

D080

C080

B080

A080

9080

8080

ROM area

ROM size

(bytes) Address

YYYY

Address

ZZZZ

0100

0000

0040

0440

FF00

FFDC

FFFE

FFFF

XXXX

YYYY

ZZZZ

RAM

ROM

0050

Reserved area

SFR area

Not used

Interrupt vector area

Reserved ROM area

(128 bytes)

Zero page

Special page

LCD display RAM area

Reserved ROM area

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig.3 Memory map of special function register (SFR)

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Interrupt control register 2(ICON2)

Timer 3 (T3)

Timer X mode register (TXM)

Interrupt edge selection register

(INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1(IREQ1)

Interrupt request register 2(IREQ2)

Interrupt control register 1(ICON1)

Timer X (low) (TXL)

Timer Y (low) (TYL)

Timer 1 (T1)

Timer 2 (T2)

Timer X (high) (TXH)

Timer Y (high) (TYH)

PULL register A (PULLA)

PULL register B (PULLB)

Timer Y mode register (TYM)

Timer 123 mode register (T123M)

φ output control register (CKOUT)

Segment output enable register (SEG)

LCD mode register (LM)

A-D control register (ADCON)

A-D conversion register (AD)

Transmit/Receive buffer register(TB/RB)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

I/O PORTS

Direction Registers (ports P2, P41–P47, and

P5–P7)

The 3822 group has 49 programmable I/O pins arranged in seven

I/O ports (ports P0–P2 and P41–P47 and P5–P7). The I/O ports

P2, P41–P47, and P5–P7 have direction registers which determine

the input/output direction of each individual pin. Each bit in a direc-

tion register corresponds to one pin, each pin can be set to be in-

put port or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

If data is read from a pin set to output, the value of the port output

latch is read, not the value of the pin itself. Pins set to input are

floating. If a pin set to input is written to, only the port output latch

is written to and the pin remains floating.

Direction Registers (ports P0 and P1)

Ports P0 and P1 have direction registers which determine the in-

put /output direction of each individual port.

Each port in a direction register corresponds to one port, each

port can be set to be input or output.

When “0” is written to the bit 0 of a direction register, that port be-

comes an input port. When “1” is written to that port, that port be-

comes an output port.

Bits 1 to 7 of ports P0 and P1 direction registers are not used.

Ports P3 and P40

These ports are only for input.

Pull-up/Pull-down Control

By setting the PULL register A (address 001616) or the PULL reg-

ister B (address 001716), ports except for port P40 can control ei-

ther pull-down or pull-up (pins that are shared with the segment

output pins for LCD are pull-down; all other pins are pull-up) with a

program.

However, the contents of PULL register A and PULL register B do

not affect ports programmed as the output ports.

Fig. 4 Structure of PULL register A and PULL register B

–P0

pull-down

–P1

pull-down

–P2

pull-up

–P3

pull-down

, P7

pull-up

Not used (return “0” when read)

PULL register A

(PULLA : address 0016

)

b7 b0

–P4

pull-up

–P4

pull-up

–P5

pull-up

–P5

pull-up

, P6

pull-up

–P6

pull-up

Not used (return “0” when read)

0 : Disable

1 : Enable

PULL register B

(PULLB : address 0017

)

b7 b0

Note : The contents of PULL register A and PULL register B

do not affect ports programmed as the output ports.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

Input/Output

Input/output,

individual ports

Input/output,

individual ports

Input/output,

individual bits

Input

Input/output,

individual bits

output

Related SFRs

PULL register A

Segment output

enable register

PULL register A

Segment output

enable register

PULL register A

Interrupt control

PULL register A

Segment output

enable register

PULL register B

φ output control

PULL register B

Interrupt edge selection

PULL register B

Serial I/O control register

Serial I/O status register

UART control register

PULL register B

Interrupt edge selection

PULL register B

Timer X mode register

PULL register B

Timer X mode register

PULL register B

Timer Y mode register

PULL register B

Timer 123 mode register

PULL register B

A-D control register

PULL register A

CPU mode register

LCD mode register

Segment output

enable register

P00/SEG16–

P07/SEG23

P10/SEG24–

P17/SEG31

P20 – P27

P34/SEG12–

P37/SEG15

P40

P41/ φ

P42/INT0,

P43/INT1

P44/RXD

P45/TXD

P46/SCLK1

P47/SRDY

P50/INT2,

P51/INT3

P52/RTP0,

P53/RTP1

P54/CNTR0

P55/CNTR1

P56/TOUT

P57/ADT

P60/AN0–

P67/AN7

P70/XCOUT

P71/XCIN

COM

-COM

SEG

-SEG

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Port P7

Common

Segment

I/O Format

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS compatible

input level

CMOS 3-state output

LCD common output

LCD segment output

Non-Port Function

LCD segment output

Key input(Key-on

wake up) interrupt

input

LCD segment output

φ clock output

External interrupt input

Serial I/O function I/O

External interrupt input

Real time port function

oputput

Timer I/O

Timer output

A-D trigger input

A-D conversion input

Sub-clock

generating circuit I/O

Diagram No.

(1)

(2)

(3)

(4)

(5)

(2)

(6)

(7)

(8)

(9)

(2)

(10)

(11)

(12)

(13)

(12)

(14)

(15)

(16)

(17)

(18)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 5 Port block diagram (1)

(1)Ports P0, P1

Segment output enable bitV

(Note)

Data bus

Direction

Port latch

Pull-down control

Segment output enable bit

Note : Bit 0 of direction register

(2)Ports P2, P4

, P4

, P5

Data bus

Pull-up control

Key input (Key-on wake up) interrupt input

INT

–INT

interrupt input

Direction

Port latch

(3)Ports P3

–P3

Pull-down control

Segment output enable bit

(4)Port P4

Data bus

(5)Port P4

φ output control bit

Pull-up control

Data bus Port latch

Direction

(6)Port P4

Pull-up control

Reception enable bit

Serial I/O enable bit

Serial I/O input

Data bus

Direction

Port latch

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 6 Port block diagram (2)

Pull-up control

Direction

Data bus Port latch

(7)Port P4

Serial I/O output

D P-channel output disable bit

Serial I/O enable bit

Transmission enable bit Serial I/O mode selection bit

Serial I/O enable bit

(8)Port P4

Serial I/O clock input

Pull-up control

Data bus

Serial I/O clock output

Serial I/O clock-synchronized

selection bit

Direction

Port latch

Serial I/O ready output

(9) Port P4

Serial I/O mode selection bit

Serial I/O enable bit

RDY

output enable bit

Data bus

Pull-up control

Direction

Port latch

(10)Ports P5

Real time port control bit

Pull-up control

Data bus Port latch

Direction

Date for real time port

Timer X operating mode bit

(Pulse output mode selection)

CNTR

interrupt input

Timer output

Pull-up control

(11) Port P5

Direction

Port latch

Data bus

(12) Ports P5

, P5

CNTR

interrupt input

A-D trigger interrupt input

Pull-up control

Data bus Port latch

Direction

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Data bus

Pull-up control

Timer output

OUT

output control bit

(13) Port P5

Direction

Port latch

(15) Port P7

Data bus

Port selection/Pull-up control

Port X

switch bit

Oscillation circuit

Port P7

Port X

switch bit

Direction

Port latch

(16) Port P7

Data bus

Port selection/Pull-up control

Port X

switch bit

Sub-clock generating circuit input

Direction

Port latch

(17) COM

–COM

The gate input signal of each

transistor is controlled by the

LCD duty ratio and the bias

value.

(18) SEG

–SEG

The voltage applied to the sources of

P-channel and N-channel transistors

is the controlled voltage by the bias

value.

Analog input pin selection bit

(14) Port P6

Data bus

Pull-up control

Direction

Port latch

A-D conversion input

Fig. 7 Port block diagram (3)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

INTERRUPTS

Interrupts occur by seventeen sources: eight external, eight inter-

nal, and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the corre-

sponding interrupt request and enable bits are “1” and the inter-

rupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

flag disables all interrupts except the BRK instruction interrupt.

Interrupt Operation

When an interrupt is received, the contents of the program counter

and processor status register are automatically stored into the

stack. The interrupt disable flag is set to inhibit other interrupts

from interfering.The corresponding interrupt request bit is cleared

and the interrupt jump destination address is read from the vector

table into the program counter.

Notes on Use

When the active edge of an external interrupt (INT0–INT3, CNTR0,

or CNTR1) is changed, the corresponding interrupt request bit

may also be set. Therefore, please take following sequence;

(1) Disable the external interrupt which is selected.

(2) Change the active edge selection.

(3) Clear the interrupt request bit which is selected to “0”.

(4) Enable the external interrupt which is selected.

Notes 1 : Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Interrupt Request

Generating Conditions

At reset

At detection of either rising or

falling edge of INT0 input

At detection of either rising or

falling edge of INT1 input

At completion of serial I/O data

reception

At completion of serial I/O

transmit shift or when transmission

buffer is empty

At timer X underflow

At timer Y underflow

At timer 2 underflow

At timer 3 underflow

At detection of either rising or

falling edge of CNTR0 input

At detection of either rising or

falling edge of CNTR1 input

At timer 1 underflow

At detection of either rising or

falling edge of INT2 input

At detection of either rising or

falling edge of INT3 input

At falling of conjunction of input

level for port P2 (at input mode)

At falling of ADT input

At completion of A-D conversion

At BRK instruction execution

Remarks

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O1 is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(valid when an “L” level is applied)

Valid when ADT interrupt is

selected External interrupt

(valid at falling)

Valid when A-D interrupt is

selected

Non-maskable software interrupt

Interrupt Source

Reset (Note 2)

INT0

INT1

Serial I/O

reception

Serial I/O

transmission

Timer X

T imer Y

Timer 2

Timer 3

CNTR0

CNTR1

Timer 1

INT2

INT3

Key input

(Key-on wake up)

ADT

A-D conversion

BRK instruction

Low

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

High

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

Table 1. Interrupt vector addresses and priority

Priority

Vector Addresses (Note 1)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

b7 b0 Interrupt edge selection register

INT

interrupt edge selection bit

INT

interrupt edge selection bit

INT

interrupt edge selection bit

INT

interrupt edge selection bit

Not used (return “0” when read)

(INTEDGE : address 003A

)

Interrupt request register 1

INT

interrupt request bit

INT

interrupt request bit

Serial I/O receive interrupt request bit

Serial I/O transmit interrupt request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

Interrupt control register 1

INT

interrupt enable bit

INT

interrupt enable bit

Serial I/O receive interrupt enable bit

Serial I/O transmit interrupt enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

0 : No interrupt request issued

1 : Interrupt request issued

(IREQ1 : address 003C

)

(ICON1 : address 003E

)

Interrupt request register 2

CNTR

interrupt request bit

CNTR

interrupt request bit

Timer

interrupt request bit

INT

interrupt request bit

INT

interrupt request bit

Key input interrupt request bit

ADT/AD conversion interrupt request bit

Not used (returns “0” when read)

(IREQ2 : address 003D

)

Interrupt control register 2

CNTR

interrupt enable bit

CNTR

interrupt enable bit

Timer 1 interrupt enable bit

INT

interrupt enable bit

INT

interrupt enable bit

Key input interrupt enable bit

ADT/AD conversion interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

0 : Interrupts disabled

1 : Interrupts enabled

(ICON2 : address 003F

)

0 : Falling edge active

1 : Rising edge active

b7 b0

Fig. 8 Interrupt control

Fig. 9 Structure of interrupt-related registers

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset Interrupt request

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Key Input Interrupt (Key-on Wake Up)

A Key input interrupt request is generated by applying “L” level to

any pin of port P2 that have been set to input mode. In other

words, it is generated when AND of input level goes from “1” to “0”.

An example of using a key input interrupt is shown in Figure 10,

where an interrupt request is generated by pressing one of the

keys consisted as an active-low key matrix which inputs to ports

P20–P23.

Fig. 10 Connection example when using key input interrupt and port P2 block diagram

 

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "1"

Port P2

latch

Port P2

direction register = "1"

Port P2

latch

Port P2

direction register = "1"

Port P2

latch

Port P2

direction register = "1"

input

output

PULL register A

Bit 2 = "1"

Port P2

Input reading circuit

Port PXx

"L" level output

  P-channel transistor for pull-up

 CMOS output buffer

Key input interrupt request

✽✽

✽

✽✽

✽

✽✽

✽

✽✽

✽

✽✽

✽

✽✽

✽

✽✽

✽

✽✽

✽

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

TIMERS

The 3822 group has five timers: timer X, timer Y, timer 1, timer 2,

and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,

timer 2, and timer 3 are 8-bit timers.

All timers are down count timers. When the timer reaches “0016”,

an underflow occurs at the next count pulse and the correspond-

ing timer latch is reloaded into the timer and the count is contin-

ued. When a timer underflows, the interrupt request bit corre-

sponding to that timer is set to “1”.

Read and write operation on 16-bit timer must be performed for

both high and low-order bytes. When reading a 16-bit timer, read

the high-order byte first. When writing to a 16-bit timer, write the

low-order byte first. The 16-bit timer cannot perform the correct op-

eration when reading during the write operation, or when writing

during the read operation.

Fig. 11 Timer block diagram

CNTR

active

edge switch bit

Timer 1 count source

selection bit

Real time port

control bit “0”

“1”

/CNTR

“0”

f(X

)/16

(f(X

CIN

)/16 in low-speed mode

✽

)

CNTR

active

edge switch bit

“10”

Timer Y stop

control bit

Falling edge detection Period

measurement mode

Timer Y

interrupt

request

Pulse width HL continuously measurement mode

Rising edge detection

“00”,“01”,“11”

Timer Y operating

mode bit

Timer X

interrupt

request

Timer X mode register

write signal

/CNTR

direction register

Pulse output mode

latch

Timer X stop

control bit

“0”

“1”

Timer X write

control bit

Q D

Latch

Q D

Latch

“1”

“0”

“1” “10”

Timer X operat-

ing mode bit

“00”,“01”,“11”

f(X

)/16

(f(X

CIN

)/16 in low-speed mode

✽

)

Pulse width

measurement

mode

CNTR

active

edge switch bit

Pulse output mode

“0”

direction register P5

latch

“1”

OUT

output

active edge

switch bit “0”

Timer 2 write

control bit

“0”

“1”

OUT

output

control bit

“1”

OUT

CIN

Timer 3 count

source selection bit

“0”

“1”

Timer 2

interrupt

request

Timer 3

interrupt

request

OUT

output control bit

Timer 2 count source

selection bit

Timer 1

interrupt

request

Data bus

f(X

)/16

(f(X

CIN

)/16 in low-speed mode

✽

)

f(X

)/16

(f(X

CIN

)/16 in low-speed mode✽)

f(X

)/16(f(X

CIN

)/16 in low-speed mode

✽

)

✽

Internal clock φ = X

CIN

/2.

CNTR

interrupt

request

CNTR

interrupt

request

Timer Y operating mode bit

“00”,“01”,“10”

“11”

direction register “0”

Real time port

control bit “1”

latch

direction register “0”

Real time port

control bit “1”

latch

data for real time port

Timer Y (low) (8) Timer Y (high) (8)

Timer 3 latch (8)

Timer 3 (8)

Timer 1 latch (8)

Timer 1 (8) Timer 2 latch (8)

Timer 2 (8)

Timer X (low) (8) Timer X (high) (8)

Timer X (low) latch (8) Timer X (high) latch (8)

Timer Y (low) latch (8) Timer Y (high) latch (8)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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3822 Group

Fig. 12 Structure of timer X mode register

Timer X

Timer X is a 16-bit timer that can be selected in one of four modes

and can be controlled the timer X write and the real time port by

setting the timer X mode register.

Timer mode

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

Pulse output mode

Each time the timer underflows, a signal output from the CNTR0

pin is inverted. Except for this, the operation in pulse output mode

is the same as in timer mode. When using a timer in this mode, set

the corresponding port P54 direction register to output mode.

Event counter mode

The timer counts signals input through the CNTR0 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the corre-

sponding port P54 direction register to input mode.

Pulse width measurement mode

The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If

CNTR0 active edge switch bit is “0”, the timer counts while the in-

put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while

the input signal of CNTR0 pin is at “L”. When using a timer in this

mode, set the corresponding port P54 direction register to input

mode.

Timer X Write Control

If the timer X write control bit is “0”, when the value is written in the

address of timer X, the value is loaded in the timer X and the latch

at the same time.

If the timer X write control bit is “1”, when the value is written in the

address of timer X, the value is loaded only in the latch. The value

in the latch is loaded in timer X after timer X underflows.

If the value is written in latch only, unexpected value may be set in

the high-order counter when the writing in high-order latch and the

underflow of timer X are performed at the same timing.

Note on CNTR0 Interrupt Active Edge Selec-

tion

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit.

Real T ime Port Control

While the real time port function is valid, data for the real time port

are output from ports P52 and P53 each time the timer X

underflows. (However, after rewriting a data for real time port, if the

real time port control bit is changed from “0” to “1”, data are output

without the timer X.) If the data for the real time port is changed

while the real time port function is valid, the changed data are out-

put at the next underflow of timer X.

Before using this function, set the corresponding port direction

registers to output mode.

Timer X mode register

(TXM : address 0027

)

Timer X write control bit

0 : Write value in latch and counter

1 : Write value in latch only

Real time port control bit

0 : Real time port function invalid

1 : Real time port function valid

data for real time port

Timer X operating mode bits

b5 b4

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

CNTR

active edge switch bit

0 : Count at rising edge in event counter mode

Start from “H” output in pulse output mode

Measure “H” pulse width in pulse width

measurement mode

Falling edge active for CNTR

interrupt

1 : Count at falling edge in event counter mode

Start from “L” output in pulse output mode

Measure “L” pulse width in pulse width

measurement mode

Rising edge active for CNTR

interrupt

Timer X stop control bit

0 : Count start

1 : Count stop

b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Timer Y

T imer Y is a 16-bit timer that can be selected in one of four modes.

Timer mode

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

Period measurement mode

CNTR1 interrupt request is generated at rising/falling edge of

CNTR1 pin input signal. Simultaneously, the value in timer Y latch

is reloaded in timer Y and timer Y continues counting down/Except

for the above-mentioned, the operation in period measurement

mode is the same as in timer mode.

The timer value just before the reloading at rising/falling of CNTR1

pin input signal is retained until the timer Y is read once after the

reload.

The rising/falling timing of CNTR1 pin input signal is found by

CNTR1 interrupt. When using a timer in this mode, set the corre-

sponding port P55 direction register to input mode.

Event counter mode

The timer counts signals input through the CNTR1 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the corre-

sponding port P55 direction register to input mode.

Pulse width HL continuously measurement mode

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode. When using a timer in this mode, set

the corresponding port P55 direction register to input mode.

Note on CNTR1 Interrupt Active Edge Selec-

tion

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit. However, in pulse width HL continuously measurement

mode, CNTR1 interrupt request is generated at both rising and

falling edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

Fig. 13 Structure of timer Y mode register

Timer Y mode register

(TYM : address 0028

)

b7 b0

Not used (return “0” when read)

Timer Y operating mode bits

b5 b4

0 0 : Timer mode

0 1 : Period measurement mode

1 0 : Event counter mode

1 1 : Pulse width HL continuously

measurement mode

CNTR

active edge switch bit

0 : Count at rising edge in event counter mode

Measure the falling edge to falling edge

period in period measurement mode

Falling edge active for CNTR

interrupt

1 : Count at falling edge in event counter mode

Measure the rising edge period in period

measurement mode

Rising edge active for CNTR

interrupt

Timer Y stop control bit

0 : Count start

1 : Count stop

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

OUT

output active edge switch bit

0 : Start at “H” output

1 : Start at “L” output

OUT

output control bit

0 : T

OUT

output disabled

1 : T

OUT

output enabled

Timer 2 write control bit

0 : Write data in latch and counter

1 : Write data in latch only

Timer 2 count source selection bit

0 : Timer 1 output

1 : f(X

)/16

(or f(X

CIN

)/16 in low-speed mode)

Timer 3 count source selection bit

0 : Timer 1 output

1 : f(X

)/16

(or f(X

CIN

)/16 in low-speed mode)

Timer 1 count source selection bit

0 : f(X

)/16

(or f(X

CIN

)/16 in low-speed mode)

1 : f(X

CIN

)

Not used (return “0” when read)

Timer 123 mode register

(T123M : address 0029

)

Note : Internal clock φ is f(X

CIN

)/2 in the low-speed mode.

b7 b0

Timer 1, T imer 2, T imer 3

Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for

each timer can be selected by timer 123 mode register. The timer

latch value is not affected by a change of the count source. How-

ever, because changing the count source may cause an inadvert-

ent count down of the timer. Therefore, rewrite the value of timer

whenever the count source is changed.

Timer 2 Write Control

If the timer 2 write control bit is “0”, when the value is written in the

address of timer 2, the value is loaded in the timer 2 and the latch

at the same time.

If the timer 2 write control bit is “1”, when the value is written in the

address of timer 2, the value is loaded only in the latch. The value

in the latch is loaded in timer 2 after timer 2 underflows.

Timer 2 Output Control

When the timer 2 (TOUT) is output enabled, an inversion signal

from pin TOUT is output each time timer 2 underflows.

In this case, set the port P56 shared with the port TOUT to the out-

put mode.

Note on Timer 1 to Timer 3

When the count source of timer 1 to 3 is changed, the timer count-

ing value may be changed large because a thin pulse is generated

in count input of timer . If timer 1 output is selected as the count

source of timer 2 or timer 3, when timer 1 is written, the counting

value of timer 2 or timer 3 may be changed large because a thin

pulse is generated in timer 1 output.

Therefore, set the value of timer in the order of timer 1, timer 2 and

timer 3 after the count source selection of timer 1 to 3.

Fig. 14 Structure of timer 123 mode register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

SERIAL I/O

Serial I/O can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer (baud rate generator) is

also provided for baud rate generation.

Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the

mode selection bit of the serial I/O control register to “1”.

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB (address 001816).

Fig. 15 Block diagram of clock synchronous serial I/O

Fig. 16 Operation of clock synchronous serial I/O function

CLK1

RDY1

f(X

)1/4

1/4

F/F

Serial I/O status register

Serial I/O control register

Receive buffer

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O synchronization

clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C

BRG count source selection bit

Clock control circuit

Falling-edge detector

Data busAddress 0018

Shift clock Transmit shift register shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Serial I/O transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 0019

Data bus

Address 001A

Transmit buffer register (TB)

Transmit shift register

RBF = 1

TSC = 1

TBE = 0 TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output T

Serial input R

Write signal to receive/transmit

buffer register (address 0018

)

Overrun error (OE)

detection

Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)

or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O control register.

2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is

output continuously from the T

D pin.

3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal S

RDY1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Asynchronous Serial I/O1 (UART) Mode

Clock asynchronous serial I/O1 mode (UART) can be selected by

clearing the serial I/O mode selection bit of the serial I/O control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer regis-

ter, but the two buffers have the same address in memory. Since

the shift register cannot be written to or read from directly, transmit

data is written to the transmit buffer register, and receive data is

read from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 17 Block diagram of UART serial I/O

Fig. 18 Operation of UART serial I/O function

f(X

)

1/4

PE FE

1/16

Data bus

Receive buffer register(RB)

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Serial I/O receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C

ST/SP/PA generator

Transmit buffer register

Data bus

Transmit shift register

Address 0018

Transmit shift register shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Address 0019

ST detector

SP detector UART control register

Address 001B

Character length selection bit

Address 001A

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O synchronization clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O control register

CLK1

Serial I/O status register

TSC=0

TBE=1

RBF=0

TBE=0 TBE=0

RBF=1 RBF=1

STD

SP D

ST SP

TBE=1 TSC=1

✽

STD

SP D

ST SP

Transmit buffer register

write signal

✽

Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bits

1 or 0 parity bit

1 or 2 stop bit (s)

1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt

source selection bit (TIC) of the serial I/O control register.

3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.

4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

Serial output T

Serial input R

Receive buffer register

read signal

Transmit or receive clock

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Serial I/O Control Register (SIO1CON) 001A16

The serial I/O control register contains eight control bits for the se-

rial I/O function.

UART Control Register (UARTCON) 001B16

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer. One bit in this register (bit 4) is

always valid and sets the output structure of the P45/TXD pin.

Serial I/O Status Register (SIO1STS) 001916

The read-only serial I/O status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the receive buffer full flag is set. A write to the serial I/O

status register clears all the error flags OE, PE, FE, and SE (bit 3

to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE

(bit 7 of the Serial I/O Control Register) also clears all the status

flags, including the error flags.

All bits of the serial I/O status register are initialized to “0” at reset,

but if the transmit enable bit (bit 4) of the serial I/O control register

has been set to “1”, the transmit shift completion flag (bit 2) and

the transmit buffer empty flag (bit 0) become “1”.

Transmit Buffer/Receive Buffer Register (TB/

RB) 001816

The transmit buffer register and the receive buffer are located at

the same address. The transmit buffer register is write-only and

the receive buffer register is read-only. If a character bit length is 7

bits, the MSB of data stored in the receive buffer register is “0”.

Baud Rate Generator (BRG) 001C16

The baud rate generator determines the baud rate for serial trans-

fer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate genera-

tor.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

BRG count source selection bit (CSS)

0: f(X

)

1: f(X

)/4

Serial I/O1 synchronization clock selection bit (SCS)

0: BRG output divided by 4 when clock synchronized serial

I/O is selected.

BRG output divided by 16 when UART is selected.

1: External clock input when clock synchronized serial I/O is

selected.

External clock input divided by 16 when UART is selected.

RDY1

output enable bit (SRDY)

0: P4

pin operates as ordinary I/O pin

1: P4

pin operates as S

RDY1

output pin

Transmit interrupt source selection bit (TIC)

0: Interrupt when transmit buffer has emptied

1: Interrupt when transmit shift operation is completed

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Serial I/O mode selection bit (SIOM)

0: Asynchronous serial I/O (UART)

1: Clock synchronous serial I/O

Serial I/O enable bit (SIOE)

0: Serial I/O disabled

(pins P4

–P4

operate as ordinary I/O pins)

1: Serial I/O enabled

(pins P4

–P4

operate as serial I/O pins)

Serial I/O control register

(SIO1CON : address 001A

)

b7 b0

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

Transmit shift register shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

Overrun error flag (OE)

0: No error

1: Overrun error

Parity error flag (PE)

0: No error

1: Parity error

Framing error flag (FE)

0: No error

1: Framing error

Summing error flag (SE)

0: (OE) U (PE) U (FE) =0

1: (OE) U (PE) U (FE) =1

Not used (returns “1” when read)

Serial I/O status register

(SIOSTS : address 0019

)

b7 b0

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

D P-channel output disable bit (POFF)

0: CMOS output (in output mode)

1: N-channel open-drain output (in output mode)

Not used (return “1” when read)

UART control register

(UARTCON : address 001B

)

b7 b0

Fig. 19 Structure of serial I/O control registers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

A-D CONVERTER

The functional blocks of the A-D converter are described below.

A-D Conversion Register (AD) 003516

The A-D conversion register is a read-only register that contains

the result of an A-D conversion. When reading this register during

an A-D conversion, the previous conversion result is read.

A-D Control Register (ADCON) 003416

The A-D control register controls the A-D conversion process. Bits

0 to 2 of this register select specific analog input pins. Bit 3 signals

the completion of an A-D conversion. The value of this bit remains

at “0” during an A-D conversion, then changes to “1” when the A-D

conversion is completed.

Writing “0” to this bit starts the A-D conversion. Bit 4 controls the

transistor which breaks the through current of the resistor ladder.

When bit 5, which is the AD external trigger valid bit, is set to “1”,

this bit enables A-D conversion even by a falling edge of an ADT

input. Set ports which share with ADT pins to input when using an

A-D external trigger.

Comparison Voltage Generator

The comparison voltage generator divides the voltage between

AVSS and VREF by 256, and outputs the divided voltages.

Channel Selector

The channel selector selects one of the input ports P67/AN7 to

P60/AN0.

Comparator and Control Circuit

The comparator and control circuit compares an analog input volt-

age with the comparison voltage and stores the result in the A-D

conversion register. When an A-D conversion is completed, the

control circuit sets the AD conversion completion bit and the AD

interrupt request bit to “1”.

Note that the comparator is constructed linked to a capacitor, so

set f(XIN) to at least 500 kHz during A-D conversion.

Fig. 20 Structure of A-D control register

Fig. 21 A-D converter block diagram

A-D control register

(ADCON : address 003416)

AD conversion completion bit

0 : Conversion in progress

1 : Conversion completed

Analog input pin selection bits

0 0 0 : P60/AN0

0 0 1 : P61/AN1

0 1 0 : P62/AN2

0 1 1 : P63/AN3

1 0 0 : P64/AN4

1 0 1 : P65/AN5

1 1 0 : P66/AN6

1 1 1 : P67/AN7

VREF input switch bit

0 : OFF

1 : ON

AD external trigger valid bit

0 : A-D external trigger invalid

1 : A-D external trigger valid

b7 b0

Interrupt source selection bit

0 : Interrupt request at A-D

conversion completed

1 : Interrupt request at ADT

input falling

Not used (returns “0” when read)

Comparator

A-D control circuit ADT/A-D interrupt request

REF

/AN

Data bus

A-D control register b7 b0

A-D conversion

Resistor ladder

Channel selector

/AN

/ADT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

LCD DRIVE CONTROL CIRCUIT

The 3822 group has the built-in Liquid Crystal Display (LCD) drive

control circuit consisting of the following.

•LCD display RAM

•Segment output enable register

•LCD mode register

•Selector

•Timing controller

•Common driver

•Segment driver

•Bias control circuit

A maximum of 32 segment output pins and 4 common output pins

can be used.

Up to 128 pixels can be controlled for LCD display. When the LCD

enable bit is set to “1” after data is set in the LCD mode register,

Fig. 22 Structure of segment output enable register and LCD mode register

the segment output enable register and the LCD display RAM, the

LCD drive control circuit starts reading the display data automati-

cally, performs the bias control and the duty ratio control, and dis-

plays the data on the LCD panel.

Table 2. Maximum number of display pixels at each

duty ratio

Duty ratio Maximum number of display pixel

64 dots

or 8 segment LCD 8 digits

96 dots

or 8 segment LCD 12 digits

128 dots

or 8 segment LCD 16 digits

Segment output enable bit 0

0 : Input ports P34–P37

1 : Segment output SEG12–SEG15

Segment output enable bit 1

0 : I/O ports P00, P01

1 : Segment output SEG16,SEG17

Segment output enable bit 2

0 : I/O ports P02–P07

1 : Segment output SEG18–SEG23

Segment output enable bit 3

0 : I/O ports P10,P11

1 : Segment output SEG24,SEG25

Segment output enable bit 4

0 : I/O port P12

1 : Segment output SEG26

Segment output enable bit 5

0 : I/O ports P13–P17

1 : Segment output SEG27–SEG31

Not used (return “0” when read)

(Do not write “1” to this bit)

Segment output enable register

(SEG : address 003816)

b7 b0 LCD mode register

(LM : address 003916)

Duty ratio selection bits

0 0 : Not available

0 1 : 2 (use COM0,COM1)

1 0 : 3 (use COM0–COM2)

1 1 : 4 (use COM0–COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

Not used (returns “0” when read)

(Do not write “1” to this bit)

LCD circuit divider division ratio selection bits

0 0 : CLOCK input

0 1 : 2 division of CLOCK input

1 0 : 4 division of CLOCK input

1 1 : 8 division of CLOCK input

LCDCK count source selection bit (Note)

0 : f(XCIN)/32

1 : f(XIN)/8192

Note : LCDCK is a clock for a LCD timing controller.

b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 23 Block diagram of LCD controller/driver

Data bus

Timing controller

LCD

divider f(XCIN)/32

f(XIN)/8192

Common

driver

Bias control

COM0COM1COM2COM3

VSS VL1 VL2 VL3

SEG3

SEG2

SEG1

SEG0

Address 004016 Address 004116

“1”

“0”

LCDCK

LCDCK count source

selection bit

LCD circuit

divider division

ratio selection bits

Bias control bit

LCD enable bit

Duty ratio selection bits

Selector Selector Selector Selector Selector

Selector

LCD display RAM

Address 004F16

P16/SEG30

P34/SEG12 P17/SEG31

Segment

driver Segment

driver Common

driver

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Bias Control and Applied Voltage to LCD

Power Input Pins

To the LCD power input pins (VL1–VL3), apply the voltage shown in

Table 3 according to the bias value.

Select a bias value by the bias control bit (bit 2 of the LCD mode

Common Pin and Duty Ratio Control

The common pins (COM0–COM3) to be used are determined by

duty ratio.

Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the

LCD mode register).

Fig. 24 Example of circuit at each bias

Table 3. Bias control and applied voltage to VL1–VL3

Bias value

1/3 bias

1/2 bias

Voltage value

VL3=VLCD

VL2=2/3 VLCD

VL1=1/3 VLCD

VL3=VLCD

VL2=VL1=1/2 VLCD

Note 1 :VLCD is the maximum value of supplied voltage for the

LCD panel.

Table 4. Duty ratio control and common pins used

Duty

ratio

Common pins used

Notes 1 : COM2 and COM3 are open

2 : COM3 is open

Bit 1

Bit 0

COM0, COM1 (Note 1)

COM0–COM2 (Note 2)

COM0–COM3

Duty ratio selection bit

VL3

VL2

VL1

R4 = R5

Contrast control

1/2 bias

VL3

VL2

VL1

Contrast control

R1 = R2 = R3

1/3 bias

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

LCD Display RAM

Address 004016 to 004F16 is the designated RAM for the LCD dis-

play. When “1” are written to these addresses, the corresponding

segments of the LCD display panel are turned on.

LCD Drive Timing

The LCDCK timing frequency (LCD drive timing) is generated in-

ternally and the frame frequency can be determined with the fol-

lowing equation;

(frequency of count source for LCDCK)

(divider division ratio for LCD)

f(LCDCK)=

f(LCDCK)

duty ratio

Frame frequency=

Fig. 25 LCD display RAM map

Bit

Address

0046

0047

0048

0049

004A

004B

004C

004D

004E

004F

SEG

0040

0041

0042

0043

0044

0045

SEG

76543210

COM

SEG

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 26 LCD drive waveform (1/2 bias)

Internal logic

LCDCK timing

1/4 duty Voltage level

VL3

VL2=VL1

VSS

VL3

VSS

COM0

COM1

COM2

COM3

SEG0

OFF ON OFF ON

COM3COM2COM1COM0COM3COM2COM1COM0

1/3 duty

VL3

VL2=VL1

VSS

VL3

VSS

OFFON ON OFF ON OFF

1/2 duty

COM0

COM1

COM2

SEG0

COM0

COM1

SEG0

VL3

VL2=VL1

VSS

VL3

VSS

OFFON OFFON OFFON OFFON

COM0COM2COM1COM0COM2COM1COM0COM2

COM1COM0COM1COM0COM1COM0COM1COM0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 27 LCD drive waveform (1/3 bias)

Internal logic

LCDCK timing

1/4 duty Voltage level

VL3

VSS

COM0

COM1

COM2

COM3

SEG0

OFF ON OFF ON

COM3COM2COM1COM0COM3COM2COM1COM0

1/3 duty

OFFON ON OFF ON OFF

1/2 duty

COM0

COM1

COM2

SEG0

COM0

COM1

SEG0

OFFON OFFON OFFON OFFON

VL3

VL2

VSS

VL1

VL3

VL2

VSS

VL1

VL3

VSS

VL3

VL2

VSS

VL1

VL3

VSS

COM0COM2COM1COM0COM2COM1COM0COM2

COM1COM0COM1COM0COM1COM0COM1COM0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

φ CLOCK OUTPUT FUNCTION

The internal system clock φ can be output from port P41 by setting

the φ output control register. Set bit 1 of the port P4 direction reg-

ister to when outputting φ clock.

Fig. 28 Structure of φ output control register

φ output control bit

0 : Port function

1 : φ clock output

φ output control register

(CKOUT : address 002A

)

b7 b0

Not used (return “0” when read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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3822 Group

RESET CIRCUIT

To reset the microcomputer, RESET pin should be held at an “L”

level for 2 µs or more. Then the RESET pin is returned to an “H”

level (the power source voltage should be between 2.5 V and

5.5 V, and the oscillation should be stable), reset is released. In or-

der to give the XIN clock time to stabilize, internal operation does

not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are

connected together and 512 cycles of f(XIN)/16) are complete. Af-

ter the reset is completed, the program starts from the address

contained in address FFFD16 (high-order byte) and address

FFFC16 (low-order byte).

Make sure that the reset input voltage is less than 0.5 V for VCC of

2.5 V (Extended operating temperature version: the reset input

voltage is less than 0.6V for VCC of 3.0V).

Fig. 30 Internal state of microcomputer after reset

Fig. 29 Example of reset circuit

(Note)

0.2V

Note. Reset release voltage : V

= 2.5V

(Extended operating temperature version : 3.0V)

Power on

RESET

Power source voltage

detection circuit

Reset input

voltage

Power source

voltage

(0001

)

• • •

Timer Y (low)

Port P0 direction register

Port P1 direction register

Port P2 direction register

PULL register B

Timer Y (high)

Serial I/O control register

UART control register

Timer X (high)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(0003

)

• • •

(0005

)

• • •

(0017

)

• • •

(001A

)

• • •

(001B

)

• • •

(0020

)

• • •

(0021

)

• • •

(0022

)

• • •

(0023

)

• • •

(0024

)

• • •

(0025

)

• • •

(0026

)

• • •

(0027

)

• • •

(0028

)

• • •

(0029

)

• • •

(002A

)

• • •

Address

Timer X (low)

Timer 1

Timer 2

Timer 3

Timer X mode register

Timer Y mode register

Timer 123 mode register

φ output control register

(000F

)

• • •

111000 00

Serial I/O status register (0019

)

• • •

100000 00

Port P4 direction register

Port P5 direction register

Port P6 direction register

(0009

)

• • •

(000B

)

• • •

(000D

)

• • •

(25)

(26)

(27)

(0034

)

• • •

(0038

)

• • •

(0039

)

• • •

A-D control register

Segment output enable register

LCD mode register

PULL register A (0016

)

• • •

000010 11

Note ✕ : Undefined

The contents of all other registers and RAM are undefined

after reset, so they must be initialized by software.

(28)

(29)

(30)

(31)

(32)

(33)

(34)

(003A

)

• • •

(003B

)

• • •

(003C

)

• • •

(003D

)

• • •

(003E

)

• • •

Interrupt edge selection register

CPU mode register

Interrupt request register 1

Interrupt request register 2

Interrupt control register 1

Interrupt control register 2

Processor status register

Program counter

1001000

Contents of address FFFC 16

(PS)

(PC

)

(PC

)

Contents of address FFFD 16

(003F

)

• • •

000010 0

( 1 )

( 2 )

( 3 )

( 4 )

( 5 )

( 6 )

( 7 )

( 8 )

( 9 )

1✕✕ ✕✕ ✕✕

Port P7 direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 31 Reset sequence

FFFC FFFD AD

, AD

????

: about 8200

clock cycles

Notes 1 : f(X

) and f(φ) are in the relationship

f(X

) = 8

•

f(φ)

Notes 2 : A question mark (?) indicates an undefined status that depends on the previous status.

Reset address from

vector table

RESET

Internal reset

Address

Data

SYNC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

OUT

External oscillation

circuit

Open

CIN

COUT

Rf Rd

CIN

COUT

CIN

COUT

OUT

CIN

COUT

Rf Rd

CLOCK GENERATING CIRCUIT

The 3822 group has two built-in oscillation circuits. An oscillation

circuit can be formed by connecting a resonator between XIN and

XOUT (XCIN and XCOUT). Use the circuit constants in accordance

with the resonator manufacturer's recommended values. No exter-

nal resistor is needed between XIN and XOUT since a feed-back re-

sistor exists on-chip. However, an external feed-back resistor is

needed between XCIN and XCOUT.

To supply a clock signal externally, input it to the XIN pin and make

the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit

cannot directly input clocks that are externally generated. Accord-

ingly, be sure to cause an external resonator to oscillate.

Immediately after poweron, only the XIN oscillation circuit starts

oscillating, and XCIN and XCOUT pins function as I/O ports. The

pull-up resistor of XCIN and XCOUT pins must be made invalid to

use the sub-clock.

Frequency Control

Middle-speed mode

The internal clock φ is the frequency of XIN divided by 8.

After reset, this mode is selected.

High-speed mode

The internal clock φ is half the frequency of XIN.

Low-speed mode

•The internal clock φ is half the frequency of XCIN.

•A low-power consumption operation can be realized by stopping

the main clock XIN in this mode. To stop the main clock, set bit 5

of the CPU mode register to “1”.

When the main clock XIN is restarted, set enough time for oscil-

lation to stabilize by programming.

Note: If you switch the mode between middle/high-speed and low-

speed, stabilize both XIN and X CIN oscillations. The suffi-

cient time is required for the sub-clock to stabilize, espe-

cially immediately after poweron and at returning from stop

mode. When switching the mode between middle/high-

speed and low-speed, set the frequency on condition that

f(XIN)>3f(XCIN).

Fig. 32 Ceramic resonator circuit

Fig. 33 External clock input circuit

Oscillation Control

Stop mode

If the STP instruction is executed, the internal clock φ stops at an

“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”

and timer 2 is set to “0116”.

Either XIN or XCIN divided by 16 is input to timer 1 as count

source, and the output of timer 1 is connected to timer 2.

The bits of the timer 123 mode register except bit 4 are cleared to

“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled

(“0”) before executing the STP instruction.

Oscillator restarts at reset or when an external interrupt is re-

ceived, but the internal clock φ is not supplied to the CPU until

timer 2 underflows. This allows time for the clock circuit oscillation

to stabilize.

Wait mode

If the WIT instruction is executed, the internal clock φ stops at an

“H” level. The states of XIN and X CIN are the same as the state be-

fore the executing the WIT instruction. The internal clock restarts

at reset or when an interrupt is received. Since the oscillator does

not stop, normal operation can be started immediately after the

clock is restarted.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Fig. 34 Clock generating circuit block diagram

WIT

instruction STP instruction

Timing φ

(Internal system clock)

STP instruction

Main clock stop bit

Timer 2

Timer 1

1/2 1/4

OUT

COUT

CIN

Interrupt request

Reset

Port X

switch bit

“1” “0”

Timer 1 count

source selection

bit

Timer 2 count

source selection

bit

Low-speed mode

Middle-/High-speed mode

Internal system clock selection bit

(Note)

Middle-speed mode

High-speed mode

or Low-speed mode

Note : When using the low-speed mode, set the port X

switch bit to “1” .

Main clock division ratio selection bit

“1”

“0”

“1”

“0” “1”

“0”

Interrupt disable flag I

1/2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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3822 Group

Fig. 35 State transitions of internal clock

Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)

2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait

mode is ended.

3 : Timer and LCD operate in the wait mode.

4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.

5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.

6 : Wait until oscillation stabilizes after oscillating the main clock X

before the switching from the low-speed mode to middle-/high-

speed mode.

7 : The example assumes that 8 MHz is being applied to the X

pin and 32 kHz to the X

CIN

pin. φ indicates the internal clock.

: Port Xc switch bit

0: I/O port

1: X

CIN

, X

COUT

: Main clock (X

–X

OUT

) stop bit

0: Oscillating

1: Stopped

: Main clock division ratio selection bit

0: f(X

)/2 (high-speed mode)

1: f(X

)/8 (middle-speed mode)

: Internal system clock selection bit

0: X

–X

OUT

selected

(middle-/high-speed mode)

1: X

CIN

–X

COUT

selected

(low-speed mode)

CPU mode register

(CPUM : address 003B

)

b7 b4

Reset

“0”“1”

“0”

“1”

=0(8 MHz selected)

=1(Middle-speed)

=0(8 MHz oscillating)

=0(32 kHz stopped)

Middle-speed mode (f(φ) =1 MHz)

=0(8 MHz selected)

=1(Middle-speed)

=0(8 MHz oscillating)

=1(32 kHz oscillating)

Middle-speed mode (f(φ) =1 MHz)

=0(8 MHz selected)

=0(High-speed)

=0(8 MHz oscillating)

=0(32 kHz stopped)

High-speed mode (f(φ) =4 MHz)

=0(8 MHz selected)

=0(High-speed)

=0(8 MHz oscillating)

=1(32 kHz oscillating)

High-speed mode (f(φ) =4 MHz)

=1(32 kHz selected)

=1(Middle-speed)

=0(8 MHz oscillating)

=1(32 kHz oscillating)

Low-speed mode (f(φ) =16 kHz)

=1(32 kHz selected)

=0(High-speed)

=0(8 MHz oscillating)

=1(32 kHz oscillating)

Low-speed mode (f(φ) =16 kHz)

=1(32 kHz selected)

=1(Middle-speed)

=1(8 MHz stopped)

=1(32 kHz oscillating)

Low-speed mode (f(φ) =16 kHz)

=1(32 kHz selected)

=0(High-speed)

=1(8 MHz stopped)

=1(32 kHz oscillating)

Low-speed mode (f(φ) =16 kHz)

“0”“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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3822 Group

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. Af-

ter a reset, initialize flags which affect program execution.

In particular, it is essential to initialize the index X mode (T) and

the decimal mode (D) flags because of their effect on calculations.

Interrupt

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt re-

quest register, execute at least one instruction before performing a

BBC or BBS instruction.

Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to

“1”, then execute an ADC or SBC instruction. Only the ADC and

SBC instructions yield proper decimal results. After executing an

ADC or SBC instruction, execute at least one instruction before

executing a SEC, CLC, or CLD instruction.

In decimal mode, the values of the negative (N), overflow (V), and

zero (Z) flags are invalid.

The carry flag can be used to indicate whether a carry or borrow

has occurred. Initialize the carry flag before each calculation.

Clear the carry flag before an ADC and set the flag before an

SBC.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n + 1).

Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Ports

The contents of the port direction registers cannot be read.

The following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction regis-

ter as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a

direction register

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the SRDY signal, set the transmit en-

able bit, the receive enable bit, and the SRDY output enable bit to

“1”.

Serial I/O continues to output the final bit from the TXD pin after

transmission is completed.

A-D Converter

The comparator uses internal capacitors whose charge will be lost

if the clock frequency is too low.

Make sure that f(XIN) is at least 500 kHz during an A-D conversion.

Do not execute the STP or WIT instruction during an A-D conver-

sion.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The frequency of the internal clock φ is half of the XIN frequency.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Programming with PROM

programmer

Screening (Caution)

(150°C for 40 hours)

Verification with

PROM programmer

Functional check in

target device

The screening temperature is far higher

than the storage temperature. Never

expose to 150 °C exceeding 100 hours.

Caution :

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc-

tion:

(1) Mask ROM Order Confirmation Form

(2) Mark Specification Form

(3) Data to be written to ROM, in EPROM form (three identical

copies)

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built-

in EPROM version can be read or programmed with a general-

purpose PROM programmer using a special programming

adapter. Set the address of PROM programmer in the user ROM

area.

The PROM of the blank One Time PROM version is not tested or

screened in the assembly process and following processes. To en-

sure proper operation after programming, the procedure shown in

Figure 36 is recommended to verify programming.

Fig. 36 Programming and testing of One Time PROM version

Package

80P6N-A

80P6S-A

80P6D-A

80D0

Name of Programming Adapter

PCA4738F-80A

PCA4738G-80

PCA4738H-80

PCA4738L-80A

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

High-speed mode f(XIN)=8 MHz

Middle-speed mode

f(XIN)=8 MHz

Low-speed mode

Power source voltage

A-D conversion reference input voltage

Analog power source voltage

Analog input voltage AN0–AM7

“H” input voltage P00–P07, P10–P17, P34–P37, P40, P41, P45, P47,

P52, P53, P56, P60–P67, P70, P71 (CM4=0)

“H” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57

“H” input voltage RESET

“H” input voltage XIN

“L” input voltage P00–P07, P10–P17, P34–P37, P40, P41, P45, P47,

P52, P53, P56, P60–P67, P70, P71 (CM4=0)

“L” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57

“L” input voltage RESET

“L” input voltage XIN

RECOMMENDED OPERATING CONDITIONS

Ta = –20 to 85°C

Ta = –40 to –20°C

Ta = –20 to 85°C

Ta = –40 to –20°C

ABSOLUTE MAXIMUM RATINGS

Power source voltage

Input voltage P00–P07, P10–P17, P2 0–P27,

P34–P37, P40–P47, P50–P57,

P60–P67, P70, P71

Input voltage VL1

Input voltage VL2

Input voltage VL3

Input voltage RESET, XIN

Output voltage P00–P07, P10–P17

Output voltage P34–P37

Output voltage P20–P27, P41–P47, P50–P57,

P60–P67, P70, P71

Output voltage SEG0–SEG11

Output voltage XOUT

Power dissipation

Operating temperature

Storage temperature

VCC

Topr

Tstg

Symbol Parameter Conditions Ratings

–0.3 to 7.0

–0.3 to VCC +0.3

–0.3 to VL2

VL1 to VL3

VL2 to VCC +0.3

–0.3 to VCC +0.3

–0.3 to VL3 +0.3

–0.3 to VCC +0.3

–0.3 to VL3 +0.3

–0.3 to VCC +0.3

300

–20 to 85 (Note 1)

–40 to 125 (Note 2)

°C

Unit

All voltages are based on VSS.

Output transistors are cut off.

At output port

At segment output

Ta = 25 °C

(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.

5.5

VCC

0.3 VCC

0.2 VCC

0.2 V

0.2 VCC

VCC

VSS

VREF

AVSS

VIA

VIH

VIL

Symbol Parameter Limits

Min.

Unit

4.0

2.5

3.0

2.5

3.0

AVSS

0.7 VCC

0.8 VCC

5.0

Typ. Max.

Notes 1 : Extended operating temperature version : –40 to 85°C

2 : Extended operating temperature version : –65 to 150°C

Power source voltage

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5V, Ta = –20 to 85°C)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

RECOMMENDED OPERATING CONDITIONS (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

MHz

–40

–20

–2

–5

–1.0

–2.5

2.5

5.0

8.0

(4XVCC)–8

8.0

“H” total peak output current

–P0

, P1

–P1

, P2

–P2

(Note 1)

“H” total peak output current P41–P47,P50–P57, P60–P67, P70, P71 (Note 1)

“L” total peak output current

–P0

, P1

–P1

, P2

–P2

(Note 1)

“L” total peak output current P41–P47,P50–P57, P60–P67, P70, P71 (Note 1)

“H” total average output current

–P0

, P1

–P1

, P2

–P2

(Note 1)

“H” total average output current P41–P47,P50–P57, P60–P67, P70, P71 (Note 1)

“L” total average output current

–P0

, P1

–P1

, P2

–P2

(Note 1)

“L” total average output current P41–P47,P50–P57, P60–P67, P70, P71 (Note 1)

“H” peak output current P00–P07, P10–P17 (Note 2)

“H” peak output current P20–P27, P41–P47, P50–P57, P60–P67, P70, P71

(Note 2)

“L” peak output current

–P0

, P1

–P1

(Note 2)

“L” peak output current P20–P27, P41–P47, P50–P57, P60–P67, P70, P71

(Note 2)

“H” average output current P00–P07, P10–P17 (Note 3)

“H” average output current P20–P27, P41–P47, P50–P57, P60–P67, P70, P71

(Note 3)

“L” average output current P00–P07, P10–P17 (Note 3)

“L” average output current P20–P27, P40–P47, P50–P57, P60–P67, P70, P71

(Note 3)

Input frequency

for timers X and Y

(duty cycle 50 %)

Main clock input oscillation

frequency (Note 4)

Sub-clock input oscillation frequency (Note 4, 5)

Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av-

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

2 : The peak output current is the peak current flowing in each port.

3 : The average output current is an average value measured over 100 ms.

4 : When the oscillation frequency has a duty cycle of 50%.

5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that

f(XCIN) < f(XIN)/3.

ΣIOH(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOL(avg)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(CNTR0)

f(CNTR1)

f(XIN)

f(XCIN)

Symbol Parameter Limits

Min. mA

MHz

kHz

Unit

Typ. Max.

4.0 V ≤ VCC ≤ 5.5 V

2.5 V ≤ VCC ≤ 4.0 V

32.768

High-speed mode (4.0 V ≤ VCC ≤ 5.5 V)

High-speed mode (2.5 V ≤ VCC ≤ 4.0 V)

Middle-speed mode

4.0

(2XVCC)–4

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

IOH = –2.5 mA

IOH = –0.6 mA

VCC = 2.5 V

IOH = –5 mA

IOH = –1.25 mA

VCC = 2.5 V

IOL = 5 mA

IOL = 1.25 mA

VCC = 2.5 V

IOL = 10 mA

IOL = 2.5 mA

VCC = 2.5 V

RESET: VCC=2.5 V to 5.5 V

VI = VCC

Pull-downs “off”

VCC= 5.0 V,

VI = VCC

Pull-downs “on”

VCC= 3.0 V,

VI = VCC

Pull-downs “on”

VI = VCC

VI = VSS

Pull-ups “off”

VCC= 5.0 V, VI = VSS

Pull-ups “on”

VCC= 3.0 V, VI = VSS

Pull-ups “on”

VI = VSS

= –20 to 85°C

= –40 to –20°C

= –20 to 85°C

= –40 to –20°C

2.0

0.5

1.0

2.0

0.5

1.0

5.0

140

170

5.0

–5.0

–140

–45

–5.0

VCC–2.0

VCC–1.0

VCC–2.0

VCC–0.5

VCC–1.0

6.0

–30

–6

VT+ – VT–

IIH

IIL

Note 1 : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the

value above mentioned.

“H” output voltage P0

–P0

, P1

–P1

“H” output voltage P2

–P2

, P4

–P4

,P5

–P5

–P6

, P7

(Note 1)

“L” output voltage P0

–P0

, P1

–P1

“L” output voltage P2

–P2

, P4

–P4

, P5

–P5

–P6

, P7

(Note 1)

Hysteresis

CNTR0, CNTR1, INT0–INT3, P20–P27

Hysteresis R

D, S

CLK

Hysteresis RESET

“H” input current P0

–P0

, P1

–P1

, P3

–P3

“H” input current P2

–P2

, P4

–P4

, P5

–P5

–P6

, P7

“H” input current RESET

“H” input current X

“L” input current P0

–P0

, P1

–P1

, P3

–P3

“L” input current P2

–P2

, P4

–P4

, P5

–P5

–P6

, P7

–P7

“L” input current RESET

“L” input current X

Symbol Parameter Limits

Min. V

µA

Unit

0.5

4.0

–70

–25

–4.0

Typ. Max.

Test conditions

VOH

VOL

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

ELECTRICAL CHARACTERISTICS (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

3.2

14.0

9.0

1.0

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz

f(XCIN) = 32.768 kHz

Output transistors “off”

A-D converter in operating

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = 32.768 kHz

Output transistors “off”

A-D converter stopped

• Low-speed mode, VCC = 5 V, Ta ≤ 55°C

f(XIN) = stopped

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 5 V, Ta = 25°C

f(XIN) = stopped

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

• Low-speed mode, VCC = 3 V, Ta ≤ 55°C

f(XIN) = stopped

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 3 V, Ta = 25°C

f(XIN) = stopped

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

All oscillation stopped

(in STP state)

Output transistors “off”

Symbol Parameter Limits

Min. Unit

Typ. Max.

Ta = 25 °C

Ta = 85 °C

Test conditions

ICC

µA

Power source current

6.4

1.6

7.0

4.5

0.1

VRAM RAM hold voltage

When clock is stopped

2.0 5.5 V

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

A-D CONVERTER CHARACTERISTICS

(

VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, middle-/high-speed mode, unless otherwise noted. Extended

operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

Symbol Parameter Limits

Min. Unit

Typ. Max.

Test conditions

–

tCONV

RLADDER

VREF

IIA

Resolution

Absolute accuracy (excluding quantization error)

Conversion time

Ladder resistor

Reference input current

Analog port input current

= V

REF

= 5 V

Bits

LSB

µs

kΩ

µA

f(X

) = 8 MHz

REF

= 5 V

12.5

(Note)

150

±2

100

200

5.0

Note : When an internal trigger is used in middle-speed mode, it is 14 µs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

tc(SCLK)

twH(SCLK)

twL(SCLK)

su(R

D–S

CLK

)

h(S

CLK

–R

125

500

230

2000

950

400

200

TIMING REQUIREMENTS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.

TIMING REQUIREMENTS 2(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.

125

200

800

370

220

100

Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

Reset input “L” pulse width

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O clock input cycle time (Note)

Serial I/O clock input “H” pulse width (Note)

Serial I/O clock input “L” pulse width (Note)

Serial I/O input set up time

Serial I/O input hold time

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

tc(SCLK)

twH(SCLK)

twL(SCLK)

su(R

D–S

CLK

)

h(S

CLK

–R

Symbol Parameter Limits

Min. µs

Unit

Typ. Max.

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

Reset input “L” pulse width

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O clock input cycle time (Note)

Serial I/O clock input “H” pulse width (Note)

Serial I/O clock input “L” pulse width (Note)

Serial I/O input set up time

Serial I/O input hold time

Symbol Parameter Limits

Min. µs

Unit

Typ. Max.

Note : When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

Measurement output pin

100 pF

CMOS output

Note : When bit 4 of the UART

control register (address 001B

) is “1”.

(N-channel open-drain output mode)

N-channel open-drain output (Note)

1 kΩ

100 pF

Measurement output pin

SWITCHING CHARACTERISTICS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.

Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2 : XOUT and XCOUT pins are excluded.

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time (Note 1)

Serial I/O output valid time (Note 1)

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

Symbol Parameter Limits

Min. ns

Unit

c(S

CLK

)

/2–30

c(S

CLK

)

/2–30

–30

Typ. Max.

twH(SCLK)

twL(SCLK)

d(S

CLK

–T

v(S

CLK

–T

tr(SCLK)

tf(SCLK)

tr(CMOS)

tf(CMOS)

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

Fig. 37 Circuit for measuring output switching characteristics (1)

SWITCHING CHARACTERISTICS 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.

Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2 : XOUT and XCOUT pins are excluded.

Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = –40 to –20°C and VCC = 2.5 to 5.5 V, Ta = –20 to 85°C)

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time (Note 1)

Serial I/O output valid time (Note 1)

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

Symbol Parameter Limits

Min. ns

Unit

c(S

CLK

)

/2–50

c(S

CLK

)

/2–50

–30

Max.

twH(SCLK)

twL(SCLK)

d(S

CLK

–T

v(S

CLK

–T

tr(SCLK)

tf(SCLK)

tr(CMOS)

tf(CMOS)

Typ.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3822 Group

TIMING DIAGRAM

w(RESET)

0.8V

0.2V

RESET

c(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

0.8V

0.2V

CNTR

,CNTR

wH(INT)

wL(INT)

0.8V

0.2V

INT

–INT

wH(X

)

wL(X

)

0.8V

0.2V

c(S

CLK

)

wL(S

CLK

)

wH(S

CLK

)

0.2V

0.8V

CLK

d(S

CLK

-T

v(S

CLK

-T

0.2V

0.8V

su(R

D-S

CLK

)

h(S

CLK

-R

New publication, effective Jan. 1998.

Specifications subject to change without notice.

Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any

intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples

contained in these materials.

• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi

Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor

product distributor for the latest product information before purchasing a product listed herein.

• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact

Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for

transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the

approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

Keep safety first in your circuit designs!

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of

substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

MITSUBISHI MICROCOMPUTERS

3822 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Rev. Rev.

No. date

1.0 First Edition 980120

REVISION DESCRIPTION LIST 3822 GROUP DATA SHEET

(1/1)

Revision Description