LMH6554LE-EVAL - National Semiconductor

LMH6554

October 29, 2009

2.8 GHz Ultra Linear Fully Differential Amplifier

General Description

The LMH6554 is a high performance fully differential amplifier

designed to provide the exceptional signal fidelity and wide

large-signal bandwidth necessary for driving 8 to 16 bit high

speed data acquisition systems. Using National’s proprietary

differential current mode input stage architecture, the

LMH6554 has unity gain, small-signal bandwidth of 2.8 GHz

and allows operation at gains greater than unity without sac-

rificing response flatness, bandwidth, harmonic distortion, or

output noise performance.

The device's low impedance differential output is designed to

drive ADC inputs and any intermediate filter stage. The

LMH6554 delivers 16-bit linearity up to 75 MHz when driving

2V peak-to-peak into loads as low as 200Ω.

The LMH6554 is fabricated in National Semiconductor’s ad-

vanced complementary BiCMOS process and is available in

a space saving, thermally enhanced 14 lead LLP package for

higher performance.

Features

■Small signal bandwidth 2.8 GHz

■2 VPP large signal bandwidth 1.8 GHz

■0.1 dB Gain flatness 830 MHz

■OIP3 @ 150 MHz 47 dBm

■HD2/HD3 @ 75 MHz -96 / -97 dBc

■Input noise voltage 0.9 nV/√Hz

■Input noise current 11 pA/√Hz

■Slew rate 6200 V/μs

■Power 260mW

■Typical supply current 52 mA

■Package 14 Lead LLP

Applications

■Differential ADC driver

■Single-ended to differential converter

■High speed differential signaling

■IF/RF and baseband gain blocks

■SAW filter buffer/driver

■Oscilloscope Probes

■Automotive Safety Applications

■Video over twisted pari

■Differential line driver

Typical Application

Single to Differential ADC Driver

30073201

LMH™ is a trademark of National Semiconductor Corporation.

LMH6554 2.8 GHz Ultra Linear Fully Differential Amplifier

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Tolerance (Note 5)

Human Body Model 2000V

Machine Model 250V

Charge Device Model 750V

Supply Voltage (VS = V+ - V−)5.5V

Common Mode Input Voltage ±1.25V

Maximum Input Current 30mA

Maximum Output Current (pins 12, 13) (Note 4)

Soldering Information

Infrared or Convection (30 sec) 260°C

Operating Ratings (Note 1)

Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Total Supply Voltage Temperature

Range 4.7V to 5.25V

Thermal Properties

Junction-to-Ambient Thermal

Resistance (θJA)60°C/W

Maximum Operating Junction

Temperature 150°C

+5V Electrical Characteristics (Note 2)

Unless otherwise specified, all limits are guaranteed for TA = +25°C, AV = +2, V+ = +2.5V, V− = −2.5V, RL = 200Ω, VCM = (V+

+V-)/2, RF = 200Ω, for single-ended in, differential out. Boldface Limits apply at the temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

AC Performance (Differential)

SSBW Small Signal −3 dB Bandwidth

(Note 8)

AV = 1, VOUT = 0.2 VPP 2800

MHz

AV = 2, VOUT = 0.2 VPP 2500

AV = 4, VOUT = 0.2 VPP 1600

LSBW Large Signal Bandwidth AV = 1, VOUT = 2 VPP 1800

MHz

AV = 2, VOUT = 2 VPP 1500

AV = 2, VOUT = 1.5 VPP 1900

0.1 dBBW 0.1 dB Bandwidth AV = 2, VOUT = 0.2 VPP, RF=250Ω 830 MHz

SR Slew Rate 4V Step 6200 V/μs

tr/tfRise/Fall Time 2V Step, 10–90% 290 ps

0.4V Step, 10–90% 150

Ts_0.1 0.1% Settling Time 2V Step, RL = 200Ω 4 ns

Overdrive Recovery Time VIN = 2V, AV = 5 V/V 6 ns

Distortion and Noise Response

HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz -102

dBc

VOUT = 2 VPP, f = 75 MHz -96

VOUT = 2 VPP, f = 125 MHz -87

VOUT = 2 VPP, f = 250 MHz −79

VOUT = 1.5 VPP, f = 250 MHz −81

HD3 3rd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz −110

dBc

VOUT = 2 VPP, f = 75 MHz −97

VOUT = 2 VPP, f = 125 MHz −87

VOUT = 2 VPP, f = 250 MHz −70

VOUT = 1.5 VPP, f = 250 MHz −75

OIP3 Output 3rd-Order Intercept f = 150 MHz, VOUT = 2VPP Composite 47 dBm

IMD3 Two-Tone Intermodulation f = 150 MHz, VOUT = 2VPP Composite −99 dBc

enInput Voltage Noise Density f = 10 MHz 0.9 nV/

in+ Input Noise Current f = 10 MHz 11 pA/

in- Input Noise Current f = 10 MHz 11 pA/

NF Noise Figure 50Ω System, AV = 7, 10 MHz 8 dB

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LMH6554

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

Input Characteristics

IBI+ / IBI- −75 −29 20 µA

TCIbi Input Bias Current Temperature

Drift

8 µA/°C

IBID Input Bias Current (Note 10) VCM = 0V, VID = 0V,

IBOFFSET = (IB- - IB+)/2

−10 1 10 μA

TCIbo Input Bias Current Diff Offset

Temperature Drift (Note 7)

0.006 µA/°C

CMRR Common Mode Rejection Ratio DC, VCM = 0V, VID = 0V 83 dB

RIN Differential Input Resistance Differential 19 Ω

CIN Differential Input Capacitance Differential 1 pF

CMVR Input Common Mode Voltage

Range

CMRR > 32 dB ±1.25 ±1.3 V

Output Performance

Output Voltage Swing (Note 7) Single-Ended Output ±1.35 ±1.42 V

IOUT Output Current (Note 7) VOUT = 0V ±120 ±150 mA

ISC Short Circuit Current One Output Shorted to Ground

VIN = 2V Single-Ended (Note 6)

150 mA

Output Balance Error ΔVOUT Common Mode /ΔVOUT

Differential, ΔVOD = 1V, f < 1 Mhz

−64 dB

Output Common Mode Control Circuit

Common Mode Small Signal

Bandwidth

VIN+ = VIN− = 0V 500 MHz

Slew Rate VIN+ = VIN− = 0V 200 V/μs

VOSCM Input Offset Voltage Common Mode, VID = 0, VCM = 0V −16 −6.5 4 mV

IOSCM Input Offset Current (Note 9) 6 18 μA

Voltage Range ±1.18 ±1.25 V

CMRR Measure VOD, VID = 0V 82 dB

Input Resistance 180 kΩ

Gain ΔVOCM/ΔVCM 0.99 0.995 1.0 V/V

Miscellaneous Performance

ZTOpen Loop Transimpedance Gain Differential 700 kΩ

PSRR Power Supply Rejection Ratio DC, ΔV+ = ΔV− = 1V 74 95 dB

ISSupply Current (Note 7)RL = ∞46 52 57

Enable Voltage Threshold Single 5V Supply 2.5 V

Disable Voltage Threshold Single 5V Supply 2.5 V

Enable/Disable Time 15 ns

ISD Supply Current, Disabled Enable=0, Single 5V supply 450 510 570

600

μA

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LMH6554

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.

Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating

of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where

TJ > TA. See Applications Section for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation.

Individual parameters are tested as noted.

Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is

PD = (TJ(MAX)– TA) / θJA. All numbers apply for packages soldered directly onto a PC Board.

Note 4: The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Section

for more details.

Note 5: Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-

Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

Note 6: Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Information for more

details.

Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will

also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.

Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality

Control (SQC) methods.

Note 9: Negative input current implies current flowing out of the device.

Note 10: IBI is referred to a differential output offset voltage by the following relationship: VOD(OFFSET) = IBI*2RF

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LMH6554

Connection Diagram

14 Lead LLP

30073202

Top View

Pin Descriptions

Pin No. Pin Name Description

1 V+ Positive Supply

2 VCM Output Common Mode Control

3 V- Negative Supply

4 +FB Feedback Output +

5 -IN Negative Input

6 +IN Positive Input

7 -FB Feedback Output -

8 V- Negative Supply

9 VEN Enable. Active high

10 V+ Positive Supply

11 NC No Connect

12 -OUT Negative Output

13 +OUT Positive Output

14 NC No Connect

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

14 Lead LLP

LMH6554LE

AJA

1k Units Tape and Reel

LEE14ALMH6554LEE 250 Units Tape and Reel

LMH6554LEX 4.5k Units Tape and Reel

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LMH6554

Typical Performance Characteristics VS = ±2.5V (TA = 25°C, RF = 200Ω, RG =

90Ω, RT = 76.8Ω, RL = 200Ω, AV = +2, for single ended in, differential out, unless specified).

Frequency Response vs. RF

30073251

Frequency Response vs. Gain

30073211

Frequency Response vs. RL

30073252

Frequency Response vs. Output Voltage (VOD)

30073213

Frequency Response vs. Capacitive Load

30073217

Suggested ROUT vs. Capacitive Load

30073218

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LMH6554

0.5 VPP Pulse Response Single Ended Input

30073253

2 VPP Pulse Response Single Ended Input

30073254

4 VPP Pulse Response Single Ended Input

30073255

Distortion vs. Frequency Single Ended Input

30073228

Distortion vs. Output Common Mode Voltage

30073233

Distortion vs. Output Common Mode Voltage

30073234

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LMH6554

Distortion vs. Output Common Mode Voltage

30073235

3rd Order Intermodulation Products vs VOUT

30073248

OIP3 vs Output Power POUT

30073249

OIP3 vs Center Frequency

30073250

Maximum VOUT vs. IOUT

30073236

Minimum VOUT vs. IOUT

30073237

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LMH6554

Overdrive Recovery

30073240

PSRR

30073241

CMRR

30073242

Balance Error

30073243

Open Loop Transimpedance

30073238

Closed Loop Output Impedance

30073239

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LMH6554

Differential S-Parameter Magnitude vs. Frequency

30073246

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LMH6554

Application Information

The LMH6554 is a fully differential, current feedback amplifier

with integrated output common mode control, designed to

provide low distortion amplification to wide bandwidth differ-

ential signals. The common mode feedback circuit sets the

output common mode voltage independent of the input com-

mon mode, as well as forcing the V+ and V− outputs to be

equal in magnitude and opposite in phase, even when only

one of the inputs is driven as in single to differential conver-

sion.

The proprietary current feedback architecture of the

LMH6554 offers gain and bandwidth independence with ex-

ceptional gain flatness and noise performance, even at high

values of gain, simply with the appropriate choice of RF1 and

RF2. Generally RF1 is set equal to RF2, and RG1 equal to

RG2, so that the gain is set by the ratio RF/RG. Matching of

these resistors greatly affects CMRR, DC offset error, and

output balance. A maximum of 0.1% tolerance resistors are

recommended for optimal performance, and the amplifier is

internally compensated to operate with optimum gain flatness

with RF value of 200Ω depending on PCB layout, and load

resistance.

The output common mode voltage is set by the VCM pin with

a fixed gain of 1 V/V. This pin should be driven by a low

impedance reference and should be bypassed to ground with

a 0.1 µF ceramic capacitor. Any unwanted signal coupling into

the VCM pin will be passed along to the outputs, reducing the

performance of the amplifier.

The LMH6554 can be configured to operate on a single 5V

supply connected to V+ with V- grounded or configured for a

split supply operation with V+ = +2.5V and V− = −2.5V. Oper-

ation on a single 5V supply, depending on gain, is limited by

the input common mode range; therefore, AC coupling may

be required. Split supplies will allow much less restricted AC

and DC coupled operation with optimum distortion perfor-

mance.

The LMH6554 is equipped with an enable pin (VEN) to reduce

power consumption when not in use. The VEN pin, when not

driven, floats high (on). When the VEN pin is pulled low the

amplifier is disabled and the amplifier output stage goes into

a high impedance state so the feedback and gain set resistors

determine the output impedance of the circuit. For this reason

input to output isolation will be poor in the disabled state and

the part is not recommended in multiplexed applications

where outputs are all tied together.

Fully Differential Operation

The LMH6554 will peform best in a fully differential configu-

ration. The circuit shown in Figure 1 is a typical fully differential

application circuit as might be used to drive an analog to dig-

ital converter (ADC). In this circuit the closed loop gain is

AV=VOUT/VIN=RF/RG, where the feedback is symmetric. The

series output resistors, RO, are optional and help keep the

amplifier stable when presented with a capacitive load. Refer

to the Driving Capacitive Loads section for details.

When driven from a differential source, the LMH6554 pro-

vides low distortion, excellent balance, and common mode

rejection. This is true provided the resistors RF, RG and RO

are well matched and strict symmetry is observed in board

layout. With an intrinsic device CMRR of greater than 70 dB,

using 0.1% resistors will give a worst case CMRR of around

50 dB for most circuits.

The circuit configuration shown in Figure 1 was used to mea-

sure differential S-parameters in a 100Ω environment at a

gain of 1 V/V. Refer to the Differential S-Parameter vs. Fre-

quency Plots in the Typical Performance Characteristics sec-

tion for measurement results.

30073257

FIGURE 1. Differential S-Parameter Test Circuit

Single Ended Input To Differential

Output Operation

In many applications, it is required to drive a differential input

ADC from a single ended source. Traditionally, transformers

have been used to provide single to differential conversion,

but these are inherently bandpass by nature and cannot be

used for DC coupled applications. The LMH6554 provides

excellent performance as a single-ended input to differential

output converter down to DC. Figure 2 shows a typical appli-

cation circuit where an LMH6554 is used to produce a bal-

anced differential output signal from a single ended source.

30073258

FIGURE 2. Single Ended Input with Differential Output

When using the LMH6554 in single-to-differential mode, the

complimentary output is forced to a phase inverted replica of

the driven output by the common mode feedback circuit as

opposed to being driven by its own complimentary input. Con-

sequently, as the driven input changes, the common mode

feedback action results in a varying common mode voltage at

the amplifier's inputs, proportional to the driving signal. Due

to the non-ideal common mode rejection of the amplifier's in-

put stage, a small common mode signal appears at the out-

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LMH6554

puts which is superimposed on the differential output signal.

The ratio of the change in output common mode voltage to

output differential voltage is commonly referred to as output

balance error. The output balance error response of the

LMH6554 over frequency is shown in the Typical Perfor-

mance Characteristics section.

To match the input impedance of the circuit in Figure 2 to a

specified source resistance, RS, requries that RT || RIN = RS.

The equations governing RIN and AV for single-to-differential

operation are also provide in Figure 2. These equations, along

with the source matching condition, must be solved iteratively

to achieve the desired gain with the proper input termination.

Component values for several common gain configuration in

a 50Ω environment are given in Table 1.

Table 1. Gain Component Values for 50Ω System

Gain RFRGRTRM

0dB 200Ω 191Ω 62Ω 27.7Ω

6dB 200Ω 91Ω 76.8Ω 30.3Ω

12dB 200Ω 35.7Ω 147Ω 37.3Ω

Single Supply Operation

Single 5V supply operation is possible: however, as dis-

cussed earlier, AC input coupling is recommended due to

input common mode limitations. An example of an AC cou-

pled, single supply, single-to-differential circuit is shown in

Figure 3. Note that when AC coupling, both inputs need to be

AC coupled irrespective of single-to-differential or differential-

differential configuration. For higher supply voltages DC cou-

pling of the inputs may be possible provided that the output

common mode DC level is set high enough so that the

amplifier's inputs and outputs are within their specified oper-

ation ranges.

30073260

FIGURE 3. AC Coupled for Single Supply Operation

Split Supply Operation

For optimum performance, split supply operation is recom-

mended using +2.5V and −2.5V supplies; however, operation

is possible on split supplies as low as +2.35V and −2.35V and

as high as +2.65V and −2.65V. Provided the total supply volt-

age does not exceed the 4.7V to 5.3V operating specification,

non-symmetric supply operation is also possible and in some

cases advantageous. For example, if a 5V DC coupled oper-

ation is required for low power dissipation but the amplifier

input common mode range prevents this operation, it is still

possible with split supplies of (V+) and (V-). Where (V+)-(V-)

= 5V and V+ and V- are selected to center the amplifier input

common mode range to suit the application.

Driving Analog To Digital

Converters

Analog-to-digital converters present challenging load condi-

tions. They typically have high impedance inputs with large

and often variable capacitive components. Figure 5 shows the

LMH6554 driving an ultra-high-speed Gigasample ADC the

ADC10D1500. The LMH6554 common mode voltage is set

by the ADC10D1500. The circuit in Figure 5 has a 2nd order

bandpass LC filter across the differential inputs of the AD-

C10D1500. The ADC10D1500 is a dual channel 10–bit ADC

with maximum sampling rate of 3 GSPS when operating in a

single channel mode and 1.5 GSPS in dual channel mode.

Figure 4 shows the SFDR and SNR performance vs. frequen-

cy for the LMH6554 and ADC10D1500 combination circuit

with the ADC input signal level at −1dBFS. In order to properly

match the input impedance seen at the LMH6554 amplifier

inputs, RM is chosen to match ZS || RT for proper input bal-

ance. The amplifier is configured to provide a gain of 2 V/V in

single to differential mode. An external bandpass filter is in-

serted in series between the input signal source and the

amplifier to reduce harmonics and noise from the signal gen-

erator.

30073265

FIGURE 4. LMH6554/ADC10D1500 SFDR and SNR

Performance vs. Frequency

The amplifier and ADC should be located as close together

as possible. Both devices require that the filter components

be in close proximity to them. The amplifier needs to have

minimal parasitic loading on it's outputs and the ADC is sen-

sitive to high frequency noise that may couple in on its inputs.

Some high performance ADCs have an input stage that has

a bandwidth of several times its sample rate. The sampling

process results in all input signals presented to the input stage

mixing down into the first Nyquist zone (DC to Fs/2).

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LMH6554

30073266

FIGURE 5. Driving a 10-bit Gigasample ADC

Output Noise Performance and

Measurement

Unlike differential amplifiers based on voltage feedback ar-

chitectures, noise sources internal to the LMH6554 refer to

the inputs largely as current sources, hence the low input re-

ferred voltage noise and relatively higher input referred cur-

rent noise. The output noise is therefore more strongly

coupled to the value of the feedback resistor and not to the

closed loop gain, as would be the case with a voltage feed-

back differential amplifier. This allows operation of the

LMH6554 at much higher gain without incurring a substantial

noise performance penalty, simply by choosing a suitable

feedback resistor.

Figure 6 shows a circuit configuration used to measure noise

figure for the LMH6554 in a 50Ω system. A feedback resistor

value of 200Ω is chosen for the LLP package to minimize

output noise while simultaneously allowing both high gain (7

V/V) and proper 50Ω input termination. Refer to the section

titled Single Ended Input Operation for calculation of resistor

and gain values. Noise figure values at various frequencies

are shown in the plot titled Noise Figure in the Typical Per-

formance Characteristics section.

30073261

FIGURE 6. Noise Figure Circuit Configuration

Driving Capacitive Loads

As noted previously, capacitive loads should be isolated from

the amplifier output with small valued resistors. This is par-

ticularly the case when the load has a resistive component

that is 500Ω or higher. A typical ADC has capacitive compo-

nents of around 10 pF and the resistive component could be

1000Ω or higher. If driving a transmission line, such as 50Ω

coaxial or 100Ω twisted pair, using matching resistors will be

sufficient to isolate any subsequent capacitance. For other

applications see the Suggested ROUT vs. Capacitive Load

charts in the Typical Performance Characteristics section.

Balanced Cable Driver

With up to 5.68 VPP differential output voltage swing the

LMH6554 can be configured as a cable driver. The LMH6554

is also suitable for driving differential cables from a single

ended source as shown in Figure 7.

30073262

FIGURE 7. Fully Differential Cable Driver

Power Supply Bypassing

The LMH6554 requires supply bypassing capacitors as

shown in Figure 8 and Figure 9. The 0.01 μF and 0.1 μF ca-

pacitors should be leadless SMT ceramic capacitors and

should be no more than 3 mm from the supply pins. These

capacitors should be star routed with a dedicated ground re-

turn plane or trace for best harmonic distortion performance.

Thin traces or small vias will reduce the effectiveness of by-

pass capacitors. Also shown in both figures is a capacitor from

the VCM and VEN pins to ground. These inputs are high

impedance and can provide a coupling path into the amplifier

for external noise sources, possibly resulting in loss of dy-

namic range, degraded CMRR, degraded balance and higher

distortion.

30073263

FIGURE 8. Split Supply Bypassing Capacitors

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LMH6554

30073264

FIGURE 9. Single Supply Bypassing Capacitors

Power Dissipation

The LMH6554 is optimized for maximum speed and perfor-

mance in a small form factor 14 lead LLP package. To ensure

maximum output drive and highest performance, thermal

shutdown is not provided. Therefore, it is of utmost impor-

tance to make sure that the TJMAX is never exceeded due to

the overall power dissipation.

Follow these steps to determine the maximum power dissi-

pation for the LMH6554:

1. Calculate the quiescent (no-load) power: PAMP = ICC *

(VS), where VS = V+ − V-. (Be sure to include any current

through the feedback network if VCM is not mid-rail).

2. Calculate the RMS power dissipated in each of the output

stages: PD (rms) = rms ((VS − V+OUT) * I+OUT) + rms

((VS − V-OUT) * I-OUT), where VOUT and IOUT are the

voltage and the current measured at the output pins of

the differential amplifier as if they were single ended

amplifiers and VS is the total supply voltage.

3. Calculate the total RMS power: PT = PAMP + PD.

The maximum power that the LMH6554 package can dissi-

pate at a given temperature can be derived with the following

equation:

PMAX = (150° − TAMB)/ θJA, where TAMB = Ambient temperature

(°C) and θJA = Thermal resistance, from junction to ambient,

for a given package (°C/W). For the 14 lead LLP package,

θJA is 60°C/W.

NOTE: If VCM is not 0V then there will be quiescent current

flowing in the feedback network. This current should be in-

cluded in the thermal calculations and added into the quies-

cent power dissipation of the amplifier.

ESD Protection

The LMH6554 is protected against electrostatic discharge

(ESD) on all pins. The LMH6554 will survive 2000V Human

Body model and 250V Machine model events. Under normal

operation the ESD diodes have no affect on circuit perfor-

mance. There are occasions, however, when the ESD diodes

will be evident. If the LMH6554 is driven by a large signal while

the device is powered down the ESD diodes will conduct . The

current that flows through the ESD diodes will either exit the

chip through the supply pins or will flow through the device,

hence it is possible to power up a chip with a large signal

applied to the input pins. Using the shutdown mode is one

way to conserve power and still prevent unexpected opera-

tion.

Board Layout

The LMH6554 is a high speed, high performance amplifier. In

order to get maximum benefit from the differential circuit ar-

chitecture board layout and component selection is very crit-

ical. The circuit board should have a low inductance ground

plane and well bypassed broad supply lines. External com-

ponents should be leadless surface mount types. The feed-

back network and output matching resistors should be

composed of short traces and precision resistors (0.1%). The

output matching resistors should be placed within 3 or 4 mm

of the amplifier as should the supply bypass capacitors. Refer

to the section titled Power Supply Bypassing for recommen-

dations on bypass circuit layout. Evaluation boards are avail-

able through the product folder on National’s web site.

By design, the LMH6554 is relatively insensitive to parasitic

capacitance at its inputs. Nonetheless, ground and power

plane metal should be removed from beneath the amplifier

and from beneath RF and RG for best performance at high

frequency.

With any differential signal path, symmetry is very important.

Even small amounts of asymmetry can contribute to distortion

and balance errors.

Evaluation Board

National Semiconductor suggests the following evaluation

boards to be used with the LMH6554:

Device Package Evaluation Board

Ordering ID

LMH6554LE 14 Lead LLP LMH6554LE-

EVAL

These evaluation boards can be shipped when a device sam-

ple request is placed with National Semiconductor.

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LMH6554

Physical Dimensions inches (millimeters) unless otherwise noted

14-Pin LLP

NS Package Number LEE14A

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LMH6554

Notes

LMH6554 2.8 GHz Ultra Linear Fully Differential Amplifier

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