Linear Products TPIC43T01 Application Brief The TPIC43T01 is an integrated motor controller designed to provide precision RPM (revolutionper-minute) control to a 3-phase brushless dc motor. The TPIC43T01 outputs are predrivers for six external power NMOS FETs or an integrated power array such as the TPIC1310. The TPIC1310 Power+ 0.01 F result of trr in the low-side LDMOS drain-body diode during rising voltage transitions at OUTx pin. Since TPIC43T01 implements PWM (pulsed-width-modulation) switching in the high-side, the current spike will occur every PWM cycle. Use of the 0.1 F filter capacitor prevents trr current from falsely being detected as motor winding current by the RSENSE resistor. Array can be used with motors of 15 W or less provided the system thermal impedance is minimized. Figure 1 illustrates a typical application using the TPIC43T01 and TPIC1310. Note the 0.1 F capacitor connected from TPIC1310 VDD pins to ground. This capacitor is needed to filter fast current spikes which can occur in the half-H drive stages of the TPIC1310 power array. These narrow current spikes are the TPIC43T01 and TPIC1310 Chipset Considerations 0.1 F RSENSE CP1 (23) CP2 VCP (24) (22) 0.1 F (25) SENSE VDD (15) TPIC43T01 47 F (20) VCC Pre-FET Drivers (26) PHC OUTC (14) (27) UGC UGC (13) (28) LGC LGC (12) (29) LGB LGB (11) VDD (1) TPIC1310 Power+ Array (30) PHB OUTB (8) (31) UGB UGB (5) (32) LGA LGA (4) (33) UGA UGA (3) (34) PHA OUTA (2) SOURCE (9) M 3-Phase BLM SUB/GND (10) Figure 1. Connections for TPIC43T01 and TPIC1310 Chipset Power+ Array is a trademark of Texas Instruments Application Brief RSENSE Component Selection TPIC43T01 Discrete NMOS Considerations An external sense resistor, RSENSE, in the current limit detection circuitry of the TPIC43T01, translates the current level to voltage VSENSE, and that voltage is then compared to internal voltage thresholds. Once VSENSE reaches VIT(lim) threshold of 0.5 V, the internally controlled on-time of the PWM cycle is shortened, or duty-cycle reduced, implementing a cycle-bycycle peak current control loop. Selection of RSENSE value is: For motors greater than approximately 15 W, the TPIC43T01 device can be connected to control six power NMOS FETs configured as a three-half-H bridge. Figure 2 illustrates a typical application using the TPIC43T01 and discrete power FETs. The discrete power NMOS drive stage also requires 0.1 F, or higher, capacitance connected from the drains of high-side NMOS transistors to ground. This capacitance is needed to filter fast current spikes which can occur in the half-H drive stage. RSENSE V + 0.5 Ipeak It is advisable to select a resistor type for RSENSE with minimal inductance. This will minimize possible noise problems from inductive ringing which could occur by switching motor current on and off through this resistor at the PWM rate. Power rating is also a concern for RSENSE which can be calculated by: Power + R(0.5 V) 2 SENSE FG Considerations Frequency Generator Description The TPIC43T01 controller is designed to work with a variable reluctance speed pickup commonly 0.01 F 0.1 F VCC 47 F RSENSE CP1 (23) CP2 VCP (24) (22) (20) VCC (25) SENSE 0.1 F (27) UGC (26) PHC (28) LGC (31) UGB TPIC43T01 Pre-FET Drivers (30) PHB (29) LGB (32) LGA (33) UGA (34) PHA Figure 2. Connections for TPIC43T01 and Discrete Power NMOS FETs M 3-Phase BLM referred to as FG, or frequency generator. The ac signal from this FG circuit provides motor RPM feedback to close the phase-lockloop (PLL). Physically, the FG system consists of two parts: 1. A winding which is typically a serpentine trace on the motor module printed circuit board (PCB) 2. A multiple-pole ring magnet attached to the rotor which rotates in close proximity to the serpentine winding on the PCB The ring magnet pole-pairs cutting the serpentine PCB traces induce a variable reluctance ac signal in the FG winding with some integer number of cycles per rotor revolution. This integer count is called the FG count, which is determined by the number of serpentines in the PCB trace, and plays a role in determining the actual RPM based on the internal reference frequency to the PLL. set at 1/4 to 1/5 of the output PWM frequency. Refer to Figure 4. When used with the TPIC43T01 controller, the FG winding is electrically biased to a common-mode dc level and the ac output signal is connected differentially to an amplifier to gain up the signal level. This amplified signal is then fed to a comparator circuit with zerocrossing detection and one-sided hysteresis (see Figure 3). Selection of the external gain setting resistors and a filter capacitor are important to achieving low RPM ripple. FG Winding Design Choosing the number of FG windings is required in setting the motor's RPM. The TPIC43T01 support software provides a function which allows the user to enter three parameters and the desired motor RPM is calculated. Those three parameters are: 1. Crystal oscillator frequency, fCRYSTAL 2. Selected internal divide-down to set PLL reference frequency 3. An FG winding count or number of FG cycles per motor revolution, FG# An external filter must be included in the FG feedback circuit to attenuate noise picked up by the speed sense traces. The filter components should be selected such that FGOut frequency (fSPEED) is centered in the pass band of the filter. The zero crossing point should be FGSOut The formula for RPM calculation is: MotorRPM CRYSTAL x 60 + PLLdivider (RPM) x FG# FG COMPARATOR FGS Buffer - Comp + FGOut R Q C1 S R1 - Comp + FGIn- - R2 Band-Gap Buffer + FG Amp 1/2 VDD + 180mV C2 FG Winding Op-Amp FGIn+ + - Figure 3. FG Signal Conditioning Functional Block Diagram 1/2 VDD GAIN Gain = R1/R2 FREQUENCY fZERO fSPEED fPOLE ~1/5*fPWM fPWM Figure 4. FG Signal Conditioning Input Filter Response Figure 5. FG Winding Layout Example Figure 5 illustrates layout of a typical FG winding showing the serpentine traces. the tachometer output. Figure 6 shows the schematic hookup for this configuration. Alternative Tachometer Input Hall-Effect Input Considerations If the motor system has a tachometer capable of 5 V digital levels, the FG amplifier can be configured such that the output is a current source that can be overdriven by The TPIC43T01 controller will accommodate differential signals from naked Hall-effect position sensors. These sensors are electrically equivalent to a resistor bridge with a differential output voltage source having a magnitude proportional to the level of magnetic flux or gauss. To ensure proper operation, the Hall-effect sensors must be biased such that their common-mode output voltage, shown in Figure 7 as Vcm, is within the TPIC43T01 input operating range for the Hall signal conditioning circuit. As shown in FGS Buffer FGSOut FG COMPARATOR 200 A Tachometer FGOut - Comp + R Q S FGIn- - Comp + - Band-Gap Buffer + FG Amp Op-Amp FGIn+ 1/2 VDD + 180mV + 1/2 VDD - Figure 6. Tachometer Control of FG Interface Vsupply OUT- Naked Hall Sensor OUT+ IN1+ (37) Ccm GND IN1- (38) Rbias Vcm OUT- Naked Hall Sensor OUT+ IN2+ (1) Hall Decode Logic Ccm GND IN2- (2) Vcm OUT- Naked Hall Sensor OUT+ GND IN3+ (3) Ccm IN3- (4) Vcm TPIC43T01 Figure 7. Naked Hall-Effect Sensor Interface the schematic, the bias nodes of the Hall sensors can be connected in parallel with the Rbias resistor. The value of the series resistor, Rbias, can be chosen based on the parallel resistance of the three Hall sensors. taken during PCB layout to avoid routing phase drive traces in close proximity to any of the six Hall signals. A common-mode capacitor, typically 0.01 F, can be placed between each of the Hall differential signals to reduce noise. The Hall sensor-to-output control commutation sequence is presented in Table 1. The direction of motor rotation is determined by the F/R input. A low level input to this pin will sequence the motor in a clockwise direction, and a high level in a counter-clockwise direction. Refer to Figures 8 and 9 for illustrations of the Hall-effect input signals and their associated commutation steps. Oscilloscope trace 1 is IN1+, trace 2 is IN2+, and trace 3 is IN3+. In higher power motor applications, noise generated from PWM switching motor phase currents can couple into the output impedance of the naked Hall sensors. Therefore, precautions should be Figure 8. Hall-Effect Commutation Sequence for Clockwise Rotation Table 1. Hall Position Sensor Input Gray-Code Logic COMMUTATION STEP IN1 A B F/R = LOW F/R HIGH PHASE A IN2 IN3 IN1 IN2 IN3 UPPER LOWER L L H H H L L H H H L L PWM Note 1 C L H L H L H PWM Note 1 D H H L E H L L L L H L H H ON F H L H L H L ON PHASE B UPPER LOWER PWM Note 1 ON ON PWM Note 1 Illegal L L L L L L all OFF Illegal H H H H H H all OFF Figure 9. Hall-Effect Commutation Sequence for Counter-Clockwise Rotation LOWER ON ON NOTE: Refer to the TPIC43T01 datasheet. PHASE C UPPER PWM Note 1 PWM Note 1 Resistor values for the 2.5 V voltage divider shown in the schematic are non-critical. The RPULLUP resistor for the Hall sensor outputs assume the sensors selected have open collector outputs. The value for RPULLUP should be per the Using Digital Hall-Effect Position Sensors The TPIC43T01 position sensor inputs can be configured to accommodate use of digital Halleffect position sensors. Figure 10 shows one possible configuration. Hall device specification. If the 5 V supply for this alternate Hall sensor implementation is from the TPIC43T01 VDD pin, care must be taken not to exceed the specified current. 5V RPULLUP VCC 20 k OUT Digital Hall Sensor GND IN1+ (37) 2.5V IN1- (38) RPULLUP VCC OUT Digital Hall Sensor IN2+ (1) IN2- (2) GND RPULLUP VCC OUT Digital Hall Sensor IN3+ (3) IN3- (4) GND 0.01 F Figure 10. Digital Hall-Effect Sensor Interface 20 k TPIC43T01 Hall Decode Logic Printed in U.S.A. 3/98 SLIT117 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. 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