SH-2: SH7604 Product Brief
SH7600 Series 32-Bit RISC Embedded Processor
PMH12TO002D2
Rev 0.2
January 16, 1997
Overview
The SH7600 Series is a reduced instruction set computer (RISC) that integrates a Hitachi-original RISC
CPU and appropriate peripheral functions to minimize the components or modules required for system
configuration.
The CPU has a RISC-type instruction set. Basic instructions can be executed in one clock cycle (36 ns),
dramatically improving instruction execution speed. Operating up to 28.7 MHz, this processor also
incorporates 4 kbytes of cache memory, a 32-bit internal architecture, and a 32-bit multiply and accumulate
unit (MAC) for enhanced data-processing ability. As a result, the SH-2 enables high-performance systems
to be constructed with advanced functionality at low cost, even in applications such as real-time control that
require operations at very high speeds.
The SH7604 includes on-chip peripheral functions such as an interrupt controller, a direct memory access
controller (DMAC), a division unit (DIVU), timers (free running timer/FRT and watchdog), and a serial
communications interface (SCI). External memory support functions enable direct connection to SDRAM,
DRAM, PSRAM, ROM, and peripheral I/O. Such features minimize the number of modules required for
system configuration, and can reduce system costs.
Features
• 28.7 MHz at 5 V, 20 MHz at 3.3 V
• SH7604: 4-kbyte, Four-Way Set Associative Cache Memory
• RISC Central Processing Unit (CPU)
32-bit internal data paths/32-bit external data paths
Five-stage pipeline
Sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers
• On-chip multiply and accumulate unit
Multiplication operations (32 × 32 → 64 bits) executed in 2 to 3 cycles
MAC operations (32 × 32 → 64 + 64 bits) executed in 2 to 3 cycles
• Operating modes:
Clock mode selected from the combination of an on-chip oscillator module, a double-frequency
circuit, clock output, PLL synchronization, and 90° phase change
Slave/master mode
Processing mode
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• Processing states:
Power-on reset/manual reset
Exception processing
Program execution
Power-down (sleep, standby, and moduel stop modes)
Bus-released
On-chip Lock Pulse Generator (CPG)
Selectable double-frequency circuit, clock output, PLL synchronization or 90° phase change
• Bus State Controller (BSC)
Supports interface to SDRAM, PSRAM, DRAM, ROM, and peripheral I/O
Supports external memory (32/16/8-bit external data bus) access
Memory refresh and burst access functions
Wait states can be inserted by external WAIT signal
• Two-Channel Direct Memory Access Controller (DMAC)
DMA transfers between external memory, external I/O, and on-chip peripheral modules
Selectable priorities and modes
Dual or single address transfer mode
• Division Unit (DIVU)
64/32 → 32…32 and 32/32 → 32…32 divisions
Overflow interrupt
• Interrupt Controller (INTC)
Five external interrupt pins
Eleven internal interrupt sources
Sixteen programmable priority levels
• 16-Bit Free Running Timer (FRT)
Input selects from three internal/external clocks
Input capture and output compare
Counter overflow, compare match, and input capture interrupt
• Watchdog Timer (WDT)
• One-channel SCI with full duplex and asynchronous/synchronous selectable modes
• User Break Controller (UBC) for generating interrupts to simplify debugging
• Operating temperature: –20°C to 75°C
• Package: 144-pin Quad Flat Pack (QFP)
• Process: 0.8 micron technology
• Complete development system support
SH-2: SH7604 Product Brief
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Related Manuals
• SH Series Overview
• SH7604 Hardware Manual
• SH7000/7600 Programming Manual
See also http://www.halsp.hitachi.com.
Block Diagram
MULT
Cache
address array
Cache
controller
Cache
data
array
External bus
interface
Clock pulse
generator
Bus state
controller
User break
controller
16-bit free
running
timer
Serial
communi-
cation
interface
Watchdog
timer
Operating-
mode
controller
Exception
processing
interrupt
controller
CPU
DIVU
Direct
memory
access
controller
(× 2 channels)
Vector address
Peripheral data bus
Peripheral address bus
Internal interrupt signal
Internal address bus
Internal data bus
Cache address bus
Cache data bus
Block Diagram (SH7604)
SH-2: SH7604 Product Brief
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Instruction Set By Classification (Total: 61 Types)
Table 1 Data Transfer (5 Types)
Operation Code Function
MOV Data transfer, immediate data transfer, peripheral module, and structural data transfers
MOVA Effective address transfer
MOVT T-bit transfer
SWAP Swap of upper and lower bytes
XTRCT Extraction of middle of connected registers
Table 2 Arithmetic Operations (20 Types)
Operation Code Function
ADD Binary addition
ADDC Binary addition with carry
ADDV Binary addition with overflow check
CMP/cond. Comparison
DIV1 Division
DIV0S Initialization of signed division
DIV0U Initialization of unsigned division
DMULS Double-length signed multiplication
DMULU Double-length unsigned multiplication
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC Multiplication and accumulation
MULS Signed multiplication
MULU Unsigned multiplication
NEG Negation
NEGC Negation with carry
SUB Binary subtraction
SUBC Binary subtraction with carry
SUBV Binary subtraction with underflow check
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Table 3 Logic Operations (6 Types)
Operation Code Function
AND Logic AND
NOT Bit inversion
OR Logical OR
TAS Memory test and bit set
TST Logical AND and T bit set
XOR Exclusive OR
Table 4 Shift Instructions (10 Types)
Operation Code Function
ROTL One-bit left rotation
ROTR One-bit right rotation
ROTCL One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAL One-bit arithmetic left shift
SHAR One-bit arithmetic right shift
SHLL One-bit logical left shift
SHLLn n-bit logical left shift
SHLR One-bit logical right shift
SHLRn n-bit logical right shift
Table 5 Branch Instructions (9 Types)
Operation Code Function
BF Conditional branch (T = 0)
BT Conditional branch (T = 1)
BRA Unconditional branch
BRAF Unconditional branch
BSR Branch to subroutine procedure
BRSF Branch to subroutine procedure
JMP Unconditional branch
JSR Branch to subroutine procedure
RTS Return from subroutine procedure
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Table 6 System Control (11 Types)
Operation Code Function
CLRT T bit clear
CLRMAC MAC register clear
LDC Load to control register
LDS Load to system register
NOP No operation
RTE Return from exception processing
SETT T bit set
SLEEP Shift into power-down mode
STC Storing control register data
STS Storing system register data
TRAPA Trap exception processing
DC Characteristics (5 V)
Table 7 DC Characteristics (Condition VCC = 5.0 V ± 10%, Ta = –20 to +75° C)
Item Symbol Min Typ Max Unit Measurement Conditions
Current
consumption Ordinary
operation ICC — 60 80 mA f = 8 MHz
— 80 100 mA f = 16 MHz
— 110 160 mA f = 28.7 MHz
Sleep — 30 55 mA f = 8 MHz
— 50 70 mA f = 16 MHz
— 80 100 mA f = 28.7 MHz
Standby — 1 15 µA Ta ≤ 50°C
——60µA50°C < Ta
SH-2: SH7604 Product Brief
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AC Characteristics (5 V)
Table 8 LSI Clock Timing (VCC = 5.0 V ± 10%, Ta = –20 to +75°C)
Item Symbol Min Max Unit
Operating frequency fOP 4 28.7 MHz
Clock cycle time tcyc 35 143*1 or 250*2ns
Clock high pulse width tCH 8*1 or 15*2—ns
Clock low pulse width tCL 8*1 or 15*2—ns
Clock rise time tCR —5 ns
Clock fall time tCF —5 ns
EXTAL clock input frequency fEX 4 8 MHz
EXTAL clock input cycle time tEXcyc 125 250 ns
EXTAL clock input low level pulse width tEXL 50 — ns
EXTAL clock input high level pulse width tEXH 50 — ns
EXTAL clock input rise time tEXR —5 ns
EXTAL clock input clock fall time tEXF —5 ns
Power-on oscillation settling time tOSC1 10 — ms
Software standby oscillation settling time 1 tOSC2 10 — ms
Software standby oscillation settling time 2 tOSC3 10 — ms
PLL synchronization settling time tPLL 1— µs
Notes 1. With PLL circuit 1 operating.
2. With PLL circuit 1 not used.
SH-2: SH7604 Product Brief
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DC Characteristics (3.3 V)
Table 9 DC Characteristics (Condition VCC = 3.0 to 5.5 V, Ta = –20 to +75° C)
Item Symbol Min Typ Max Unit Measurement Conditions
Input high- RES, NMI, MD5– VIH VCC×0.9 — VCC + 0.3 V During standby
level MD0 VCC×0.9 — VCC + 0.3 V Normal operation
voltage EXTAL, CKIO VCC×0.9 — VCC + 0.3 V
Other input pins VCC×0.7 — VCC + 0.3 V
Input low- RES, NMI, MD5– VIL –0.3 — VCC×0.1 V During standby
level MD0 –0.3 — VCC×0.1 V Normal operation
voltage Other input pins –0.3 — VCC×0.1 V
Input leak RES |Iin| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V
current NMI, MD5–MD0 — — 1.0 µA Vin = 0.5 to VCC – 0.5 V
Other input pins — — 1.0 µA Vin = 0.5 to VCC – 0.5 V
3-state leak
current (while
off)
A26–A0, D31–D0,
BS, CS3–CS0,
RD/WR, RAS, CAS,
WE3-WE0, RD,
IVECF
|ISTI| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V
Output All output pins VOH VCC – 0.5 — — V IOH = –200 µA
high-level
voltage VCC – 1.0 — — V IOH = –1 mA
Output
low-level
voltage
All output pins VOL — — 0.4 V IOL = 1.6 mA
Input capaci- RES Cin — — 15 pF Vin = 0 V
tance NMI — — 15 pF f = 1 MHz
All other input pins
(D31–D0) — — 15 pF Ta = 25°C
SH-2: SH7604 Product Brief
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Table 9 DC Characteristics (Condition VCC = 3.0 to 5.5 V, Ta = –20 to +75° C) (cont)
Item Symbol Min Typ Max Unit Measurement Conditions
Current Ordinary operation ICC — 25 30 mA f = 8 MHz
consump- — 45 55 mA f = 16 MHz
tion — 60 70 mA f = 28.7 MHz
Sleep — 15 20 mA f = 8 MHz
— 30 40 mA f = 16 MHz
— 40 50 mA f = 28.7 MHz
Standby — 1 5 µA Ta ≤ 50°C
——20µA50°C < Ta
Notes: 1. When no PLL is used, do not release the PLLVCC and PLLVSS pins. Connect PLLVCC to VCC
and PLLVSS to VSS.
2. Current consumption values shown are the values at which all output pins are without load under
conditions of VIH min = VCC - 0.5 V, VIL max = 0.5 V.
AC Characteristics (3.3 V)
Table 10 Clock Timing (VCC = 3.0 to 0.5 V, Ta = –20 to +75°C)
Item Symbol Min Max Unit
Operating frequency fOP 4 20 MHz
Clock cycle time tcyc 35 143*1 or 250*2 ns
Clock high pulse width tCH 8*1 or 15*2 —ns
Clock low pulse width tCL 8*1 or 15*2 —ns
Clock rise time tCR —5 ns
Clock fall time tCF —5 ns
EXTAL clock input frequency fEX 4 8 MHz
EXTAL clock input cycle time tEXcyc 125 250 ns
EXTAL clock input low level pulse width tEXL 50 — ns
EXTAL clock input high level pulse width tEXH 50 — ns
EXTAL clock input rise time tEXR —5 ns
EXTAL clock input clock fall time tEXF —5 ns
Power-on oscillation settling time tOSC1 10 — ms
Software standby oscillation settling time 1 tOSC2 10 — ms
Software standby oscillation settling time 2 tOSC3 10 — ms
PLL synchronization settling time tPLL 1— µs
Notes: 1. With PLL circuit 1 operating.
2. With PLL circuit 1 not used.
SH-2: SH7604 Product Brief
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Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D11
D12
D13
VCC
D14
VSS
D15
D16
D17
D18
D19
D21
D22
D23
VCC
D24
VSS
D25
D26
VCC
D28
VSS
D29
D30
VCC
D20
VSS
D27
29
30
31
32
33
34
35
36
D31
A0
A2
VSS
A3
A4
A5
A1
CAP1
MD1
VSS(PLL)
MD0
VCC(PLL)
SCK
TXD
RXD
FTCI
FTI
VSS
FTOA
VCC
FTOB
WDTOVF
BREQ/BGR
BACK/BRLS
VSS
N.C
WAIT
CKE
RD
VSS
CASLL/DQMLL/
VCC
CASLH/DQMLU/
CASHL/DQMUL/
CASHH/DQMUU/
108
107
106
105
104
103
102
101
100
99
98
94
93
92
91
90
89
88
87
85
84
83
82
81
97
96
95
86
CAS/OE
RAS/CE
VSS
RD/WR
BS
CS3
CS2
CS1
80
79
77
76
75
74
73
78
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A6
A7
A8
VCC
A9
VSS
A10
A11
A12
A13
A14
A16
A17
A18
VCC
A19
VSS
A20
A21
VCC
A23
VSS
A24
A25
VCC
A15
VSS
A22
65
66
67
68
69
70
71
72
A26
DACK0
DACK1
VSS
DREQ0
DREQ1
CS0
VCC
D10
D9
D8
VSS
D7
VCC
D6
D5
D4
D3
VSS
D2
VCC
D1
D0
IRL0
IRL1
IRL2
IRL3
NMI
IVECF
VCC
RES
VSS
MD5
MD4
CKIO
MD3
144
143
142
141
140
139
138
137
136
135
134
130
129
128
127
126
125
124
123
121
120
119
118
117
133
132
131
122
XTAL
VSS
EXTAL
VCC
CKPREQ/CKM
CKRACK
MD2
CAP2
116
115
113
112
111
110
109
114
SH-2
(Top view)
HD6417604
Note: WE3: CASHH/DQMUU/WE3
WE2: CASHL/DQMUL/WE2
WE1: CASHH/DQMUU/WE1
WE0: CASHL/DQMUL/WE0
Do not connect anything to pins labeled N.C.
Package Dimensions
SH-2: SH7604 Product Brief
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22.0 ± 0.3
20
108 73
72
37
136
109
144
22.0 ± 0.3
0.22 ± 0.07 0.10 M
0.1 2.70
3.05 max
0.17 ± 0.05
0.10
1.0 ± 0.2
0.5
0–10ϒ
0.5 ± 0.1
+0.20
–0.16
SH-2: SH7604 Product Brief
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When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.