ANM078 How to Replace Dallas DS80C320/DS80C323 by TS80C51U2 1. Introduction Dallas Semiconductor developed a family of C51 microcontrollers running out of 4 clocks per cycle while the standard 80C51 run out of 12 clocks per cycle. With a significant number of instructions using more cycles than in the original 80C51, the average speed increase over the complete instruction set is 2.1 (Dallas indicate 2.5 in its datasheet). Atmel Wireless & Microcontrollers' approach on the new C51X2 core used in the TS80C51U2 has been to run all instructions at 6 clocks per cycle without changing the number of cycle for each instruction. Dallas implements some features such as dual datapointer, Watchdog etc... in a way not compatible with the other sources of C51 microcontrollers such as Philips or Atmel Wireless & Microcontrollers. Explaining how to adapt a software to Atmel Wireless & Microcontrollers is the primary objective of this application note. Finally Dallas implements some specific features such as: ring oscillator, stretch MOVX for external access. These features are not found in standard implementation of the C51 architecture such as Atmel Wireless & Microcontrollers, Philips, Intel, etc... The following application note lists them. 2. Features list The following table list all features present on DS80C320/DS80C323 or TS80C32X2. Table 1. DS80C320/DS80C323 and TS80C51U2 features Feature Four I/O ports Three 16 bit timer/counters Description DALLAS ATMEL Ports 0, 1, 2, 3 Y Y Timer 0, 1, 2 Y Y Y Y DPTR0 , DPTR1 Y Y Stretch external Data Read and Write Y N 256 Bytes internal RAM Dual Data Pointer Stretch MOVX Power Save Modes Power Fail Reset Ring Oscillator Idle mode (peripheral operating), Power Down Mode Y Y Brown-Out Power monitoring, including Early Warning Y N Ring Oscillator start immediately after Stop mode. Microcontroller run from the ring oscillator while the main Xtal oscillator is starting. Y N Y Y Programmable Watchdog 2 full duplex UARTs 1 Baud Rate Generator Support Framing Error, Automatic address recognition Y Y Additional Baud Rate generator for UARTs N Y External Interrupt Sources Interrupt Priority Levels Power-Off Flag Once Mode 6 2 Priority levels programmable for each interrupt sources 2 4 Distinguish between Cold Rest and Warm Reset N Y On Chip Emulation N Y Maximum operating Frequency 4.5 to 5.5 volts DS80C320 : 33MHz (70MHz equivalent) TS80C51U2-V version : 30MHz (60MHz equivalent). Maximum operating Frequency 2.7 to 5 volts DS80C323 : 18MHz (38MHz equivalent only Com temperature) TS80C51U2-L version : 20MHz (40MHz equivalent in Com. and Ind. Temperature ranges). Rev. B - 28 April 2000 1 ANM078 3. Pinout The following table shows the DS80C320/DS80C323 and TS80C51U2 pinout. (NAMEb to indicate active low signal). Table 2. DS80C320/DS80C323 and TS80C51U2 pinout DIP PLCC TQFP VQFP SIGNAL NAME DIFFERENCE IN ATMEL TS80C51U2 40 44 38 Vcc No difference 20 22,23 16,17 V ss PLCC pin 22 Vss pin 23 NC VQFP pin 16 Vss pin 17 NC 9 18 19 29 30 39 38 37 36 35 34 33 32 10 20 21 32 33 43 42 41 40 39 38 37 36 4 14 15 26 27 37 36 35 34 33 32 31 30 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 2 3 4 5 6 7 8 9 24 25 26 27 28 29 30 31 40 41 42 43 44 1 2 3 18 19 20 21 22 23 24 25 10 11 12 13 14 15 16 17 31 - 11 13 14 15 16 17 18 19 35 12 34 5 7 8 9 10 11 12 13 29 6 28 RST XTAL2 XTAL1 PSENb ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Port1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 A8 (P2.0) A9 (P2.1) A10 (P2.2) A11 (P2.3) A12 (P2.4) A13 (P2.5) A14 (P2.6) A15 (P2.7) Port3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 EAb NC NC - 1 39 NC No difference No difference No difference No difference No difference No difference No difference No difference but See note No difference but See note Only P1.4 Only P1.5 P1.6 and UART1 input see note P1.7 and UART1 output see note No difference No difference No difference No difference No difference No difference No difference No difference No difference No difference Serial Port1 input see note Serial Port1 output see note Optional Vss DESCRIPTION / COMMENT Positive Supply Ground. On TS80C51U2 PLCC44 pin 23 and VQFP44 pin 17 can be connected to Vss to be compatible with Dallas DS80C320/DS80C323 pinout. Reset. Need external capacitor with ATMEL Xtal1 is the input of the oscillator inverter, Xtal2 is the output Program Store Enable (b to indicate active low) Address Latch Enable AD0-7 Port0 is the multiplexed address bus Port Alternate P1.0 T2 P1.1 T2EX P1.2 RXD1 P1.3 TXD1 P1.4 INT2 P1.5 INT3b P1.6 INT4 P1.7 INT5b A15-A8 (Port2) Function External I/O Timer/counter2 Timer/Counter2 Capture/Reload Serial Port1 input Serial Port1 output External interrupt External interrupt External interrupt External interrupt Port Alternate Function P3.0 RXD0 Serial Port0 input P3.1 TXD0 Serial Port0 output P3.2 INT0b External interrupt 0 P3.3 INT1b External interrupt 1 P3.4 T0 Timer0 input P3.5 T1 Timer1 input P3.6 WRb External Data Memory Write P3.7 RDb External Data Memory Read External Access (b to indicate active low) 100K pull up resistor in TS80C51U2 Pins can be left not connected on TS80C51U2 for pinout compatibility with Dallas DS80C320/DS80C323 Note : TS80C51U2 Serial Port1 input/output can be located on different positions depending on AUXR bit M1UA1 and M0UA_1 bit. See note 5 UART below. 2 Rev. B - 28 April 2000 ANM078 4. SFR memory map Most TS80C51U2 Special Function Registers and DS80C320/DS80C323 Special Function Registers are identical (address, content and reset value). However some differences exist. The purpose of this chapter is to highlight the DS80C320/DS80C323 registers that are not identically present in the TS80C51U2. When the same feature is implemented in the DS80C320/DS80C323 and in the TS80C51U2 but use different SFRs to control it, a detailed description of the Software changes to replace DS80C320/DS80C323 by TS80C51U2 is given in specific notes below. The following table lists the DS80C320/DS80C323 Special Function Registers, and gives the equivalent registers for the TS80C51U2. Table 3. DS80C320/DS80C323 SFRs REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT2 BIT 1 BIT 0 ADDR SP DPL DPH 81h 82h 83h DPL1 84h DPH1 85h DPS PCON TCON TMOD TL0 TL1 TH0 TH1 0 0 SMOD SMOD 0 SMOD1 SMOD _0 0_0 TF1 TR1 GATE C/Tb COMMENT FOR TS80C51U2 Same on TS80C51U2 Same on TS80C51U2 Same on TS80C51U2 TS80C51U2 DPL1 and DPL use address 82h (note1) No register at address 84h TS80C51U2 DPH1 and DPH use address 83h (note1) No register at address 85h SEL bit replaced by DPS bit in AUXR1 No register at adr. 86h in TS80C51U2 0 0 0 0 0 SEL 86h - POF GF1 GF1 GF0 GF0 STOP STOP IDLE IDLE 87h DS80C320/DS80C323 :SMOD (note 4) TS80C51U2 (note 4) TF0 M1 TR0 M0 IE1 GATE IT1 C/Tb IE0 M1 IT0 M0 88h 89h 8Ah 8Bh 8Ch 8Dh Same Same Same Same Same Same CKCON Dallas on on on on on on TS80C51U2 TS80C51U2 TS80C51U2 TS80C51U2 TS80C51U2 TS80C51U2 WD1,0 watchdog timeout . see WDTPRG bit S2,1,0 in TS80C51U2 see note 2 T2M, T1M, T0M (timer clock) see note 3 MD2, MD1, MD0 (Stretch MOVX) No stretch feature in TS80C51U2 See TS80C51U2 AUXR on table 4 Same on TS80C51U2 IE5,4,3,2 Extended External Interrupts Not present in the TS80C51U2 RGMD CPU clock select (XTAL / RING) No Ring oscillator in TS80C51U2 always run from XTAL RGSL : Start with Ring (see above) BGS : Band Gap Control , No Bandgap and no Brown-out in TS80C51U2 TS80C51U2 has no SFR at address 91h WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h EXIF IE5 IE4 IE3 IE2 - RGMD RGSL BGS 91h SCON0 SM0/ FE0 RB8_0 TI_0 RI_0 98h Same on TS80C51U2 P2.2 EX1 P2.1 ET0 P2.0 EX0 99h A0h A8h Same on TS80C51U2 Same on TS80C51U2 Same on TS80C51U2 A9h Same on TS80C51U2 AAh B0h Same on TS80C51U2 Same on TS80C51U2 AUXR ATMEL SBUF0 P2 IE SADDR0 SADDR1 SADDR1 P3 SM1_0 SM2_0 REN_0 TB8_0 P2.7 EA P3.7 Rev. B - 28 April 2000 P2.6 ES1 P3.6 P2.5 ET2 P3.5 P2.4 ES0 P3.4 P2.3 ET1 P3.3 P3.2 P3.1 P3.0 3 ANM078 REGISTER BIT 7 IP SADEN0 SADEN1 SCON1 - SM0/ FE1 BIT 6 BIT 5 BIT 4 BIT 3 PS1 PT2 PS0 PT1 SM1_1 SM2_1 REN_1 TB8_1 BIT2 BIT 1 BIT 0 ADDR PT0 PX0 B8h B9h BAh Same on TS80C51U2 Same on TS80C51U2 Same on TS80C51U2 RB8_1 TI_1 RI_1 C0h Same on TS80C51U2 C1h Same on TS80C51U2 Interrupt status for clock control : register not present in TS80C51U2 Time access control : Register not present in TS80C51U2 SBUF1 STATUS PIP HIP LIP 1 1 1 1 1 C5h TA C7h T2CON TF2 EXF2 RCLK T2MOD - - - TCLK EXEN2 - - COMMENT FOR TS80C51U2 PX1 TR2 C/T2b - T2OE CP/ RL2 DCEN C8h Same on TS80C51U2 C9h CAh Same on TS80C51U2 RCAP2L Same on TS80C51U2 RCAP2H TL2 TH2 PSW CY AC F0 RS1 RS0 OV FL P h CBh CCh CDh D0h WDCON SMOD1 POR EPFI PFI WDIF WTRF EWT RWT D8h ACC E0h EIE - - - EWDI EX5 EX4 EX3 EX2 B E8h F0h EIP - - - PWDI PX5 PX4 PX3 PX2 F8h Same on TS80C51U2 Same on TS80C51U2 Same on TS80C51U2 Same on TS80C51U2 Control/status register not present in TS80C51U2 see Note 2 Same on TS80C51U2 Enable Watchdog interrupt and Enable Extended interrupt 2 to 5 . Register and the features not present in TS80C51U2 Same on TS80C51U2 Watchdog interrupt and Extended interrupts 2 to 5 . EIP register and features not present in TS80C51U2 Table 4. TS80C51U2 SFRs not present in the DS80C320/DS80C323 REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT2 BIT 1 BIT 0 ADDR. COMMENT AUXR M1UA_1 M0_UA_1 - - - - - AO 8Eh M1UA_1 , M0_UA_1 UART1 I/O position selection see note 5 UART above AO : ALE Output disable during internal code fetch. AO=0 (reset) ALE always on AO=1 ALE disable (not applicable in ROMless device) CKCON - - - - - - - X2 8Fh Clear X2 for 12 clocks per cycle (reset value) Set X2 for 6 clocks per cycle. BRL BRL7 BRL6 BRL5 BRL4 BRL3 BRL2 BRL1 BRL0 9Ah Additional Baud Rate Generator reload register (reset 00h) See note 5 BDRCON - - BRR SPD SRC 9Bh See note 5 - - 9Ch See note 5 A2h Data Pointer selection see Note 1 above Clear to select DPTR0 (reset) Set to select DPTR1 A6h Watchdog enable/reset register See note2 BDRCON_1 SMOD1_1 AUXR1 SMOD0_1 TBCK_0 RBCK_0 RCLK_1 TCLK_1 TBCK_1 RBCK_1 - - - - - - - DPS WDTPRG T4 T3 T2 T1 T0 S2 S1 S0 A7h Watchdog control (use S2,S1,S0 only) IPH - PSH_1 PT2H PSH_0 PT1H PX1H PT0H PX0H B7h Interrupt priority. See note 6 WDTRST See reset value for all registers on TS80C51U2 datasheet page 2 table 2 4 Rev. B - 28 April 2000 ANM078 Note 1: Dual Data Pointers TS80C512U2 two 16-bit data pointers (DPTR0 and DPTR1) are mapped at the same SFR addresses 82h for DPL and 83h DPH. The register AUXR1 (SFR address A2h) contains one single bit DPS. With DPS=0 DPTR0 is selected and DPH + DPL present the value of DPTR0. With DPS=1 DPTR1 is selected and DPH + DPL present the value of DPTR1. In Dallas DS80C320/DS80C323 the 2 16 bit data pointers (DPTR0 and DPTR1) are mapped at different SFR addresses 82h for DPL0, 83h for DPH0 and 84h for DPL1, 85h for DPH1. The DPTR selection bit is SEL in DPS register at address 86h. Remark: Atmel Wireless & Microcontrollers implementation of the dual data pointer is compatible with Philips. Note 2: Watchdog Atmel Wireless & Microcontrollers watchdog timeout period in the TS80C51U2 is programmed by register WDTRG (address A7h) bit S0 S1 S2, see value on TS80C51U2 datasheet page 40. The timeout is programmable from (2141)*6 clocks to (221-1)*6 clocks: from 3.26mS to 418mS @30MHz. Atmel Wireless & Microcontrollers watchdog is enabled and reset by writing 1Eh then E1h in the WDTRST register (address A6h). Upon timeout, the watchdog generates a reset; the reset is available as an output on the reset pin. The reset pulse is 96 XTAL clock periods. Dallas watchdog timeout period is programmed by CKCON register (address 8Eh) WD1 and WD0 bit 6 and 7. The timeout is programmable from (217+512) clocks to (226+512) clocks: from 3.98mS to 2033mS @33MHz. Dallas watchdog is controlled by WDCON (address D8h) register. This register includes an enable bit: EWT and a restart bit RWT. The same register display 2 status bits: WDIF advanced timeout interrupt flag (512 clocks before timeout). And the full timeout flag WTRF (reset generated). Dallas watchdog control bit RWT, EWT, WDIF are protected by the Timed access protection using TA register (address C7h) Writing AAh then 55h in the TA register opens a 3 cycles window where the protected bits above can be changed. The TA register protection mechanism doesn't exist in the TS80C51U2, it is replaced by a similar mechanism: dual write into WDTRST as described above. Note: WDCON register also includes the following bits: PFI: Power Fail early warning: No Power Fail supported in the TS80C51U2 EPFI: enable Power Fail SMOD1: SMOD bit for UART1. Select double baud rate in mode 1 2 3 (not documented in the Dallas datasheet) see UART note 5 below. POR: Power On Reset status. Note 3: Timer clock The TS80C51U2 timer 0,1,2 and the additional Baud Rate Generator (BRG) are clocked by the same clock as the CPU: Xtal/12 if CKCON bit X2 = 0, Xtal/6 if CKCON bit X2 =1. (note CKCON address = 8Fh) The Dallas DS80C320/DS80C323 CKCON register address 8Eh bit T2M, T1M, T0M control the speed of the respective timers. If bit is cleared (reset value) 12 clocks per timer cycle is used. If bit is set, 4 clocks per cycle are used. Remark: Using TS80C51U2 to replace a DS80C320 or DS80C323, most likely the X2 mode will be selected in the TS80C51U2 to achieve 6 clock per cycles for the CPU. The timers will also run at 6 clocks per cycle. Their programming must be changed to recover the timing value they had with DS80C320/DS80C323 running at 4 clocks per cycle or 12 clocks per cycle depending upon T2M, T1M, T0M values. Rev. B - 28 April 2000 5 ANM078 Note 4: PCON UART control TS80C512U2 PCON register (address 87h) contains the SMOD1_0 and SMOD0_0 control bit for UART0: SMOD1_0 select double baud rate in mode 1, 2, 3 and SMOD0_0 select access to Framing Error FE bit in SCON0. Atmel Wireless & Microcontrollers also have the Power Off Flag Feature with POF bit included in PCON register. Note: SMOD1_1 and SMOD0_1 control for UART1 are located in BDRCON_1 register (see table 4 above). Dallas DS80C320/DS80C323 PCON register (same address than Atmel Wireless & Microcontrollers 87h) contains SMOD_0 not documented but most likely the select double baud rate in mode 1, 2, 3 for UART0 and SMOD0 to select Framing Error FE bit in SCON0 and SCON1. SMOD_1 is available in WDCON register. Dallas does not support the Power Off Flag See also note 5 UART below. Note 5: UART TS80C51U2 includes an additional baud rate generator that can be used for UART0 and UART1. All modes supported by Dallas DS80C320/DS80C323 are also available in the TS80C51U2. The Baud rate generator can be selected for UART0 and or UART1. See TS80C51U2 datasheet page 25, 30, 31 for description of BRL, BDRCON BDRCON_1. In TS80C51U2 the Serial Port1 input and output pin locations are programmable. One configuration is fully compatible with the Serial Port1 input and output pin locations in the DS80C320/DS80C323. In the TS80C51U2, the pin locations for the Serial Port1 are programmed by the bit M1UA_1 and M0UA_1 in the AUXR register (see table 4 above). The following table indicates the pin position. Table 5. Serial Port1 pin position in TS80C51U2 M1UA_1 M0UA_1 RXD1/TXD1 (DIP40) RXD1/TXD1 (PLCC44) RXD1/TXD1 (VQFP44) 0 0 1 1 0 1 0 1 UART1 disabled NA P1.2/P1.3 (pin3/pin4) P1.6/P1.7 (pin7/pin8) UART1 disabled pin6/pin12 P1.2/P1.3 (pin4/pin5) P1.6/P1.7 (pin8/pin9) UART1 disabled pin28/pin34 P1.2/P1.3 (pin42/pin43) P1.6/P1.7 (pin2/pin3) COMMENT Same as DS80C320 The following table gives for Dallas DS80C320/DS80C323 and TS80C51U2 the different timers that can be used as Baud Rate Generator. TS80C51U2 offers the same modes as Dallas plus additional modes. Table 6. Serial Ports timer option for Baud Rate DALLAS Serial Port 0 Timer1 Timer2 Serial Port 1 Timer1 ATMEL Timer1 Timer2 Ad. Baud Rate Generator Timer1 Timer2 Ad. Baud Rate Generator In Dallas DS80C320/DS80C323 Timer1 and Timer2 can be programmed separately to use 12 clocks or 4 clocks per timer cycle. In TS80C51U2, Timer1 Timer2 and the additional Baud Rate Generator can be programmed to all use 6 clocks per timer cycle or 12 clocks per timer cycles: see note 3 Timer clock above. 6 Rev. B - 28 April 2000 ANM078 When replacing a Dallas DS80C320/DS80C323 by a TS80C51U2, Timer1 and Timer2 programming have to be changed to compensate for the different number of clock per timer cycles. Another possibility is to use the additional Baud Rate generator that Atmel Wireless & Microcontrollers added in the TS80C51U2. The equations below give: the Baud Rate frequency as a function of the programming options and the Baud Rate Reload value to use as a function of the needed Baud Rate frequency. Serial Port 1 2SMOD1_1 * 2X2 * Fxtal Baud_Rate = 2 * 2 * 6(1-SPD) * 16 * [256-BRL] 2SMOD1_1 BRL = * 2X2 Fxtal * 256 - 2 * 2 * 6(1-SPD) * 16 * Baud_Rate Serial Port 0 2SMOD1_0 * 2X2 Fxtal * Baud_Rate = 2 * 2 * 6(1-SPD) * 16 * [256-BRL] 2SMOD1_0 * 2X2 * Fxtal BRL = 256 - 2 * 2 * 6(1-SPD) * 16 * Baud_Rate SMOD1_0 and SMOD1_1 : see BDRCON_1 register description in Note 4, Note 5 and Table 4 X2 : see CKCON register description in Note 3 and Table 4 SPD : see BDRCON register in Table 4 Note 6: Interrupt TS80C51U2 has a 4 level priority interrupt system. Whereas the DS80C320/DS80C323 only have 2 levels priority interrupt system. TS80C51U2 includes an additional IPH Interrupt priority register (address B7h) IP together with IPH provide a 2 bit coding to define 4 priority levels for the 7 following interrupts: UART1, Timer2, UART0, Timer1, External Interrupt1, Timer0, External Interrupt0. See Table 7: comparison natural interrupt priority assuming all sources have the same priority defined in IP (DS80C320/DS80C323) or IP and IPH (TS80C51U2) Note: with IPH reset value being 00h, TS80C51U2 defaults to 2 priority levels and is fully compatible with DS80C320. Rev. B - 28 April 2000 7 ANM078 Table 7. Interrupt priority DALLAS ATMEL Level Level Name Description PFI Power Fail interrupt See also note 7 on Reset 1 - 33h INT0 External interrupt 0 2 1 03h TF0 Timer 0 3 2 0Bh INT1 External interrupt 1 4 3 13h TF1 Timer 1 5 4 1Bh TI0 or RI0 UART0 6 5 23h Timer 2 7 6 2Bh TI1 or RI1 UART1 8 7 3Bh INT2 External interrupt2 9 - 43h INT3 External interrupt3 10 - 4Bh INT4 External interrupt4 11 - 53h INT5 External interrupt5 12 - 5Bh WDTI Watchdog timer (advance interrupt) 13 - 63h SCON0 TF2 SCON1 Vector Comment Warning ATMEL SCON 1 interrupt vector at 33h Note 7: Reset, Power Fail and Power-Off Flag Dallas DS80C320/DS80C323 Reset input includes an internal RC network for Power-up reset. For TS80C51U2, an external Capacitor between Reset input and Vcc positive supply is necessary (1F typical). In the Dallas DS80C320/DS80C323, an internal band gap reference is used to define a Reset Threshold level Vrst. The circuit will wait until Vcc exceed Vrst, then wait for 65536 clock cycles to apply the internal Reset. If Vcc falls below Vrst, the circuit will reset itself. In the TS80C51U2, at power up, the RC composed with internal resistor and external capacitor (see above) will insure that a proper reset pulse is generated inside the circuit. A Schmitt trigger is built inside the chip in order to maintain a reset pulse long enough in case of slow Vcc ramp-up. The internal oscillator also includes a special mechanism to block the distribution of the clock inside the chip until the oscillator is stabilized with large enough oscillations The Dallas DS80C320/DS80C323 includes a Power Fail Interrupt with top priority. PFI interrupt can be enabled using the EPFI bit in WDCON register. PFI is an early warning interrupt generated before Vcc falls below the Vrst threshold level that will generate a reset. There is no Power Fail Interrupt mechanism in the TS80C51U2. TS80C51U2 includes a Power-Off flag: the POF bit in PCON register is set at power-up. POF bit is cleared when an external or Watchdog reset generates a Reset. Note POF is not operational under 4.5 Volts supply. Note: In the DS80C320/DS80C323 the Power Fail Interrupt vector is 33h. In the TS80C51U2 the Second Serial Port interrupt vector is 33h. See note 6. 8 Rev. B - 28 April 2000 ANM078 5. DC Parameters Hereafter a DC parameters comparison table for DS80C320 and DS80C323 versus TS80C51U2 Table 8. DC Parameters for standard voltage (5 volts) Symbol VIL VIH VIH DS80C320 TS80C51U2 Unit Min Max Min Max -0.3 2 3.5 +0.8 Vcc+0.3 Vcc+0.3 -0.5 0.2Vcc+0.9 0.7Vcc 0.2Vcc - 0.1 Vcc +0.5 Vcc +0.5 0.3 0.45 1.0 0.3 0.45 1 0.3 0.45 VOL Port1 Port3 0.45 VOL Port0 0.45 VOL Port2 0.45 VOL ALE, PSEN 1 0.3 0.45 1 0.45 V V V V V V V 2.4 VOH ALE PSEN Vcc-0.3 Vcc-0.7 Vcc-1.5 2.4 Vcc-0.3 Vcc-0.7 Vcc-1.5 VOH Port0 2.4 2.4 V 2.4 V Vcc-1.5 (Note 2) 2.4 IIL Port1,3 IL Port0 ITL Port1,3 RST ICCop ICCidle IPD V Vcc-0.3 Vcc-0.7 Vcc-1.5 (Note 1) Vcc-0.3 Vcc-0.7 VOH Port2 VOH Port1, Port3 V -55 -300 50 +300 -650 170 45 25 1 (80) -10 50 -50 A +10 -650 200 33 15 50 A A k mA mA A Comments Input low voltage Input high voltage except XTAL1, RST Input high voltage XTAL1, RST IOL=100A IOL=1.6mA IOL=3.5mA IOL=200A IOL=3.2mA IOL=7.0mA IOL=100A IOL=1.6mA IOL=3.2mA IOL=3.5mA IOL=200A IOL=3.2mA IOL=7.0mA IOH=-50A IOH=-200A IOH=-3.2mA IOH=-7.0mA IOH=-8.0mA IOH=-200A IOH=-3.2mA IOH=-7.0mA IOH=-8.0mA IOH=-10A IOH=-30A IOH=-60A IOH=-8.0mA See Note1 IOH=-10A IOH=-30A IOH=-50A IOH=-60A IOH=-1.5mA See Note2 VOL=0.45V Vin=2V 25MHz clock (TS80C51U2 in X2 mode) 25MHz clock (TS80C51U2 in X2 mode) DS80C320 80 A if Band Gap on Note 1 : On TS80C51U2 During a 0 to 1 transition on Port2 when external program memory or external data memory addressing , a pull-up 100 time stronger than the pull-up insuring the DC VOH : roughly 8mA IOH boosts the transition, as described in the C51 family Hardware description (page 9 to 11). Same value on Dallas DS80C320. Rev. B - 28 April 2000 9 ANM078 Note 2 : On TS80C51U2 During a 0 to 1 transition on Port1 and 3, a pull-up 100 time stronger than the pull-up insuring the DC VOH : roughly 8mA IOH boosts the transition for 2 clock periods, as described in the C51 family Hardware description (page 9 to 11). Same mechanism and same value on Dallas DS80C320. Table 9. DC Parameters for standard voltage (2.7 volts) Symbol VIL VIH VIH VOL Port1 Port3 VOL Port0 VOL Port2 VOL ALE, PSEN VOH ALE PSEN VOH Port0 VOH Port2 VOH Port1, Port3 IIL Port1,3 IL Port0 ITL Port1,3 RST ICCop ICCidle IPD DS80C323 TS80C51U2 Unit Min Max Min Max -0.3 0.7Vcc 0.7Vcc+ 0.25 +0.2Vcc Vcc+0.3 Vcc+0.3 -0.5 0.2Vcc+0.9 0.7Vcc 0.2Vcc - 0.1 Vcc +0.5 Vcc +0.5 V V V 0.45 V 0.45 V 0.45 V 0.45 V 0.4 0.4 0.4 0.4 Vcc-0.4 V 0.9Vcc Vcc-0.4 0.9Vcc Vcc-0.4 V 0.9Vcc Vcc-0.4 Vcc-0.4 V Note 1 0.9Vcc Note 2 Vcc-0.4 -30 -300 50 +300 -400 170 10 (typ) 6(typ) 1 (40) -10 50 V Comments Input low voltage Input high voltage except XTAL1, RST Input high voltage XTAL1, RST IOL=0.8mA IOL=1.6mA IOL=1.6mA IOL=3.2mA IOL=0.8mA IOL=3.2mA IOL=1.6mA IOL=3.2mA IOH=-15A IOH=-40A IOH=-3.0mA IOH=-40A IOH=-3.0mA IOH=-10A IOH=-15A IOH=-3mA See Note 1 IOH=-10A IOH=-1.5mA See Note 2 -50 A VOL=0.45V +10 A Vin=2V -650 200 12(max) 5.6(max) 30 A k mA mA A 18MHz clock (TS80C51U2 in X2 mode) 18MHz clock (TS80C51U2 in X2 mode) DS80C320 40 A if Band Gap on Note 1 : On TS80C51U2 During a 0 to 1 transition on Port2 when external program memory or external data memory addressing , a pull-up 100 time stronger than the pull-up insuring the DC VOH : roughly 3mA IOH boost the transition, as described in the C51 family Hardware description (page 9 to 11). Same value on Dallas DS80C320. Note 2 : On TS80C51U2 During a 0 to 1 transition on Port1 and 3, a pull-up 100 time stronger than the pull-up insuring the DC VOH : roughly 1.5mA IOH boost the transition for 2 clock periods, as described in the C51 family Hardware description (page 9 to 11). Same mechanism and same value on Dallas DS80C320. 10 Rev. B - 28 April 2000 ANM078 6. AC Parameters The following table 9 shows the AC parameters for DS80C320 and TS80C51U2 at 5 volts and DS80C323 and TS80C51U2 at 2.7 volts. All parameters are defined for variable clock unless an absolute value is given. All values are in nanoSecond (ns). When T is present in an equation, T is the Xtal clock period in nanoSecond. Table 10. AC Parameters comparison DS80C320/DS80C323 versus TS80C51U2 @ 5 volts and @ 2.7 volts Symbol Parameter Cond. 80C320 (5 volts) TS80C51U2 (5 volts) DS80C323 (2.7 volts) TS80C51U2 (2.7 volts) TLHLL ALE pulse width Min. 1.5T-10 T-8 1.5T-10 T-15 TAVLL Address valid to ALE Min. 0.5T-11 0.5T-13 0.5T-11 0.5T-20 TLLAX Address hold after ALE Min. 0.25T-5 0.5T-13 0.25T-5 0.5T-20 TLLIV ALE to valid instruction Max. 2.5T-27 2T-22 2.5T-27 2T-35 TLLPL ALE to PSEN Min. 0.25T-7 0.5T-8 0.25T-7 0.5T-15 TPLPH PSEN pulse width Min. 2.25T-7 1.5T-15 2.25T-7 1.5T-25 TPLIV PSEN to valid instruction Max. 2.25T-21 1.5T-25 2.25T-21 1.5T-45 TPXIX Input inst hold after PSEN Min. 0 0 0 0 TPXIZ Input inst float after PSEN Max. T-5 0.5T-5 T-5 0.5T-15 TAVIV Address low to valid inst. Max. 3T-27 2.5T-30 3T-27 2.5T-45 TAVIV Address high to valid inst. Max. 3.5T-33 2.5T-30 3.5T-33 2.5T-45 TPLAZ PSEN low to address float Max. See note 10 See note 10 Note : DS80C320 : TPLAZ address held in a weak latch until overdriven by external memory Symbol TRLRH Parameter RD pulse width Cond. 80C320 (5 volts) TS80C51U2 (5 volts) DS80C323 (2.7 volts) TS80C51U2 (2.7 volts) Min. 2T-11 3T-15 2T-11 3T-25 TWLWH WR pulse width Min. 2T-11 3T-15 2T-11 3T-25 TRLDV RD to valid data in Max. 2T-25 2.5T-23 2T-25 2.5T-30 TRHDX Data hold after RD Min. 0 0 0 0 TRHDZ Data float after RD Max. T-5 T-15 T-5 T-25 TLLDV ALE to valid data in Max. 2.5T-26 4T-35 2.5T-26 4T-45 TAVDV Address_L to valid data in Max. 3T-24 4.5T-50 3T-24 4.5T-65 TAVDV Address_H to valid data in TLLWL ALE to WR or RD TAVWL Address_L to WR or RD TAVWL Address_H to WR or RD TQVWX TQVWH TWHQX Data hold after WR Min. TRLAZ RD low to address float Max. TWHLH WR or RD high to ALE Min. / Max. 0 / 10 0.5T-10 / 0.5T+10 0 / 10 0.5T-20 / 0.5T+20 TXLXL Serial port clock cycle Min. 12T 6T Not Available 6T Max. 3.5T-32 4.5T-50 3.5T-32 4.5T-65 Min. / Max. 0.5T-5 / 0.5T+6 1.5T-20 / 1.5T+20 0.5T-5 / 0.5T+6 1.5T-30 / 1.5T+30 Min. T-9 2T-20 T-9 2T-30 Min. 1.5T-9 2T-20 1.5T-9 2T-30 Data valid to WR edge Min. -9 0.5T-10 -9 0.5T-20 Data setup to WR edge Min. 3.5T-10 T-7 0.5T-8 3.5T-20 T-7 0 0.5T-15 0 TQVXH Output setup to clock Min. 10T 5T-50 Not Available 5T-50 TXHQX Output hold after clock Min. 2T 2T-20 Not Available 2T-20 Rev. B - 28 April 2000 11 ANM078 Symbol Parameter Cond. 80C320 (5 volts) TS80C51U2 (5 volts) DS80C323 (2.7 volts) TS80C51U2 (2.7 volts) TXHDX Input hold after clock Min. T 0 Not Available 0 TXHDV Clock to input valid Max. 11T 5T-133 Not Available 5T-133 Load capacitance at 5 volts TS80C51U2 load capacitance for Port0,1,2,3 = 50pF , load capacitance ALE/PSEN = 30pF @5volts. Dallas DS80C320 load capacitance for Port1,2,3 = 80pF , load capacitance for Port0, ALE/PSEN = 100pF @5volts. Load capacitance at 2.7 volts TS80C51U2 load capacitance for Port1,2,3 = 80pF , load capacitance Port0, ALE/PSEN = 100pF @2.7volts. DALLAS DS80C320 load capacitance for Port1,2,3 = 80pF , load capacitance for Port0, ALE/PSEN = 100pF @2.7volts. 7. References 7.1. Atmel Wireless & Microcontrollers references - TS80C51U2 Datasheet Rev C - Aug. 24, 1999. 80C51 Hardware Description Manual Rev. E - Jan. 14, 1997. C51 family Programmer's Guide and Instruction Set Rev. E - Jan. 14, 1997. 7.2. DALLAS references - 12 DS80C320/DS80C323 datasheet Rev 9/22/1999. Rev. B - 28 April 2000