ANM078 - Atmel Corporation - Datasheet.Directory

Rev. B - 28 April 2000 1

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How to Replace Dallas DS80C320/DS80C323 by TS80C51U2

1. Introduction

Dallas Semiconductor developed a family of C51 microcontrollers running out of 4 clocks per cycle while the

standard 80C51 run out of 12 clocks per cycle. With a significant number of instructions using more cycles than

in the original 80C51, the average speed increase over the complete instruction set is 2.1 (Dallas indicate 2.5 in

its datasheet). Atmel Wireless & Microcontrollers' approach on the new C51X2 core used in the TS80C51U2 has

been to run all instructions at 6 clocks per cycle without changing the number of cycle for each instruction.

Dallas implements some features such as dual datapointer, Watchdog etc… in a way not compatible with the other

sources of C51 microcontrollers such as Philips or Atmel Wireless & Microcontrollers. Explaining how to adapt

a software to Atmel Wireless & Microcontrollers is the primary objective of this application note.

Finally Dallas implements some specific features such as: ring oscillator, stretch MOVX for external access. These

features are not found in standard implementation of the C51 architecture such as Atmel Wireless & Microcontrollers,

Philips, Intel, etc… The following application note lists them.

2. Features list

The following table list all features present on DS80C320/DS80C323 or TS80C32X2.

Table 1. DS80C320/DS80C323 and TS80C51U2 features

Maximum operating Frequency 4.5 to 5.5 volts

DS80C320 : 33MHz (70MHz equivalent) TS80C51U2-V version : 30MHz (60MHz equivalent).

Maximum operating Frequency 2.7 to 5 volts

DS80C323 : 18MHz (38MHz equivalent only Com temperature) TS80C51U2-L version : 20MHz (40MHz equivalent

in Com. and Ind. Temperature ranges).

Feature Description DALLAS ATMEL

Four I/O ports Ports 0, 1, 2, 3 Y Y

Three 16 bit timer/counters Timer 0, 1, 2 Y Y

256 Bytes internal RAM YY

Dual Data Pointer DPTR0 , DPTR1 Y Y

Stretch MOVX Stretch external Data Read and Write Y N

Power Save Modes Idle mode (peripheral operating), Power Down Mode Y Y

Power Fail Reset Brown-Out Power monitoring, including Early Warning Y N

Ring Oscillator Ring Oscillator start immediately after Stop mode. Microcontroller run from

the ring oscillator while the main Xtal oscillator is starting. YN

Programmable Watchdog YY

2 full duplex UARTs Support Framing Error, Automatic address recognition Y Y

1 Baud Rate Generator Additional Baud Rate generator for UARTs N Y

External Interrupt Sources 62

Interrupt Priority Levels Priority levels programmable for each interrupt sources 2 4

Power-Off Flag Distinguish between Cold Rest and Warm Reset N Y

Once Mode On Chip Emulation N Y

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3. Pinout

The following table shows the DS80C320/DS80C323 and TS80C51U2 pinout. (NAMEb to indicate active low signal).

Table 2. DS80C320/DS80C323 and TS80C51U2 pinout

Note : TS80C51U2 Serial Port1 input/output can be located on different positions depending on AUXR bit M1UA-

1 and M0UA_1 bit. See note 5 UART below.

DIP PLCC TQFP

VQFP SIGNAL

NAME DIFFERENCE IN ATMEL

TS80C51U2 DESCRIPTION/COMMENT

40 44 38 Vcc No difference Positive Supply

20 22,23 16,17 V ss PLCCpin22Vsspin23NC

VQFP pin 16 Vss pin 17 NC

Ground.

On TS80C51U2 PLCC44 pin 23 and VQFP44 pin 17

can be connected to Vss to be compatible with Dallas

DS80C320/DS80C323 pinout.

9 10 4 RST No difference Reset. Need external capacitor with ATMEL

19 20

21 14

15 XTAL2

XTAL1 No difference Xtal1 is the input of the oscillator inverter, Xtal2 is the

output

29 32 26 PSENb No difference Program Store Enable (b to indicate active low)

30 33 27 ALE No difference Address Latch Enable

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

No difference AD0-7 Port0 is the multiplexed address bus

Port1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

No difference

No difference but See note

Only P1.4

Only P1.5

P1.6 and UART1 input see note

P1.7 and UART1 output see note

Port Alternate Function

P1.0 T2 External I/O Timer/counter2

P1.1 T2EX Timer/Counter2 Capture/Reload

P1.2 RXD1 Serial Port1 input

P1.3 TXD1 Serial Port1 output

P1.4 INT2 External interrupt

P1.5 INT3b External interrupt

P1.6 INT4 External interrupt

P1.7 INT5b External interrupt

A8 (P2.0)

A9 (P2.1)

A10 (P2.2)

A11 (P2.3)

A12 (P2.4)

A13 (P2.5)

A14 (P2.6)

A15 (P2.7)

No difference A15-A8 (Port2)

Port3

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

No difference

Port Alternate Function

P3.0 RXD0 Serial Port0 input

P3.1 TXD0 Serial Port0 output

P3.2 INT0b External interrupt 0

P3.3 INT1b External interrupt 1

P3.4 T0 Timer0 input

P3.5 T1 Timer1 input

P3.6 WRb External Data Memory Write

P3.7 RDb External Data Memory Read

31 35 29 EAb No difference External Access (b to indicate active low)

- 12 6 NC Serial Port1 input see note

- 34 28 NC Serial Port1 output see note 100K pull up resistor in TS80C51U2

- 1 39 NC Optional Vss Pins can be left not connected on TS80C51U2 for pinout

compatibility with Dallas DS80C320/DS80C323

Rev. B - 28 April 2000 3

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4. SFR memory map

Most TS80C51U2 Special Function Registers and DS80C320/DS80C323 Special Function Registers are identical

(address, content and reset value). However some differences exist. The purpose of this chapter is to highlight the

DS80C320/DS80C323 registers that are not identically present in the TS80C51U2. When the same feature is

implemented in the DS80C320/DS80C323 and in the TS80C51U2 but use different SFRs to control it, a detailed

description of the Software changes to replace DS80C320/DS80C323 by TS80C51U2 is given in specific notes below.

The following table lists the DS80C320/DS80C323 Special Function Registers, and gives the equivalent registers

for the TS80C51U2.

Table 3. DS80C320/DS80C323 SFRs

SP 81h Same on TS80C51U2

DPL 82h Same on TS80C51U2

DPH 83h Same on TS80C51U2

DPL1 84h TS80C51U2 DPL1 and DPL use address

82h (note1) No register at address 84h

DPH1 85h TS80C51U2 DPH1 and DPH use address

83h (note1) No register at address 85h

DPS 0000000SEL86h

SEL bit replaced by DPS bit in AUXR1

No register at adr. 86h in TS80C51U2

PCON SMOD

SMOD1

SMOD

0_0

POF GF1

GF1 GF0

GF0 STOP

STOP IDLE

IDLE 87h DS80C320/DS80C323 :SMOD (note 4)

TS80C51U2 (note 4)

TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h Same on TS80C51U2

TMOD GATE C/Tb M1 M0 GATE C/Tb M1 M0 89h Same on TS80C51U2

TL0 8Ah Same on TS80C51U2

TL1 8Bh Same on TS80C51U2

TH0 8Ch Same on TS80C51U2

TH1 8Dh Same on TS80C51U2

CKCON

Dallas

AUXR

ATMEL

WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh

WD1,0 watchdog timeout . see

WDTPRG bit S2,1,0 in TS80C51U2 see

note 2

T2M, T1M, T0M (timer clock) see note 3

MD2, MD1, MD0 (Stretch MOVX) No

stretch feature in TS80C51U2

See TS80C51U2 AUXR on table 4

P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h Same on TS80C51U2

EXIF IE5 IE4 IE3 IE2 - RGMD RGSL BGS 91h

IE5,4,3,2 Extended External Interrupts

Not present in the TS80C51U2

RGMD CPU clock select (XTAL /

RING) No Ring oscillator in

TS80C51U2 always run from XTAL

RGSL : Start with Ring (see above)

BGS : Band Gap Control , No Bandgap

and no Brown-out in TS80C51U2

TS80C51U2 has no SFR at address 91h

SCON0 SM0/

FE0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h Same on TS80C51U2

SBUF0 99h Same on TS80C51U2

P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h Same on TS80C51U2

IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h Same on TS80C51U2

SADDR0

SADDR1 A9h Same on TS80C51U2

SADDR1 AAh Same on TS80C51U2

P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h Same on TS80C51U2

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Table 4. TS80C51U2 SFRs not present in the DS80C320/DS80C323

See reset value for all registers on TS80C51U2 datasheet page 2 table 2

IP - PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h Same on TS80C51U2

SADEN0 B9h Same on TS80C51U2

SADEN1 BAh Same on TS80C51U2

SCON1 SM0/

FE1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 C0h Same on TS80C51U2

SBUF1 C1h Same on TS80C51U2

STATUS PIP HIP LIP 1 1111C5h

Interrupt status for clock control : register

not present in TS80C51U2

TA C7h Time access control : Register not present

in TS80C51U2

T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2b CP/

RL2 C8h Same on TS80C51U2

T2MOD - - - - - - T2OE DCEN C9h Same on TS80C51U2

RCAP2L CAh

hSame on TS80C51U2

RCAP2H CBh Same on TS80C51U2

TL2 CCh Same on TS80C51U2

TH2 CDh Same on TS80C51U2

PSW CY AC F0 RS1 RS0 OV FL P D0h Same on TS80C51U2

WDCON SMOD1 POR EPFI PFI WDIF WTRF EWT RWT D8h Control/status register not present in

TS80C51U2 see Note 2

ACC E0h Same on TS80C51U2

EIE - - - EWDI EX5 EX4 EX3 EX2 E8h Enable Watchdog interrupt and Enable

Extended interrupt 2 to 5 . Register and

the features not present in TS80C51U2

B F0h Same on TS80C51U2

EIP - - - PWDI PX5 PX4 PX3 PX2 F8h Watchdog interrupt and Extended

interrupts 2 to 5 . EIP register and

features not present in TS80C51U2

AUXR M1UA_1 M0_UA_1 - - - - - AO 8Eh

M1UA_1 , M0_UA_1 UART1 I/O position

selection see note 5 UART above

AO : ALE Output disable during internal

code fetch.

AO=0 (reset) ALE always on

AO=1 ALE disable (not applicable in

ROMless device)

CKCON - - - - - - - X2 8Fh Clear X2 for 12 clocks per cycle (reset

value)

Set X2 for 6 clocks per cycle.

BRL BRL7 BRL6 BRL5 BRL4 BRL3 BRL2 BRL1 BRL0 9Ah Additional Baud Rate Generator reload

BDRCON - - - BRR TBCK_0 RBCK_0 SPD SRC 9Bh See note 5

BDRCON_1 SMOD1_1 SMOD0_1 RCLK_1 TCLK_1 TBCK_1 RBCK_1 - - 9Ch See note 5

AUXR1 - - - - - - - DPS A2h Data Pointer selection see Note 1 above

Clear to select DPTR0 (reset)

Set to select DPTR1

WDTRST A6h Watchdog enable/reset register See note2

WDTPRG T4 T3 T2 T1 T0 S2 S1 S0 A7h Watchdog control (use S2,S1,S0 only)

IPH - PSH_1 PT2H PSH_0 PT1H PX1H PT0H PX0H B7h Interrupt priority. See note 6

Rev. B - 28 April 2000 5

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Note 1: Dual Data Pointers

TS80C512U2 two 16-bit data pointers (DPTR0 and DPTR1) are mapped at the same SFR addresses 82h for DPL

and 83h DPH. The register AUXR1 (SFR address A2h) contains one single bit DPS. With DPS=0 DPTR0 is

selected and DPH + DPL present the value of DPTR0. With DPS=1 DPTR1 is selected and DPH + DPL present

the value of DPTR1.

In Dallas DS80C320/DS80C323 the 2 16 bit data pointers (DPTR0 and DPTR1) are mapped at different SFR

addresses 82h for DPL0, 83h for DPH0 and 84h for DPL1, 85h for DPH1. The DPTR selection bit is SEL in

DPS register at address 86h.

Remark: Atmel Wireless & Microcontrollers implementation of the dual data pointer is compatible with Philips.

Note 2: Watchdog

Atmel Wireless & Microcontrollers watchdog timeout period in the TS80C51U2 is programmed by register WDTRG

(address A7h) bit S0 S1 S2, see value on TS80C51U2 datasheet page 40. The timeout is programmable from (214-

1)*6 clocks to (221-1)*6 clocks: from 3.26mS to 418mS @30MHz.

Atmel Wireless & Microcontrollers watchdog is enabled and reset by writing 1Eh then E1h in the WDTRST

reset pin. The reset pulse is 96 XTAL clock periods.

Dallas watchdog timeout period is programmed by CKCON register (address 8Eh) WD1 and WD0 bit 6 and 7.

The timeout is programmable from (217+512) clocks to (226+512) clocks: from 3.98mS to 2033mS @33MHz.

Dallas watchdog is controlled by WDCON (address D8h) register. This register includes an enable bit: EWT and

a restart bit RWT. The same register display 2 status bits: WDIF advanced timeout interrupt flag (512 clocks

before timeout). And the full timeout flag WTRF (reset generated).

Dallas watchdog control bit RWT, EWT, WDIF are protected by the Timed access protection using TA register

(address C7h) Writing AAh then 55h in the TA register opens a 3 cycles window where the protected bits above

can be changed.

The TA register protection mechanism doesn’t exist in the TS80C51U2, it is replaced by a similar mechanism:

dual write into WDTRST as described above.

Note: WDCON register also includes the following bits:

PFI: Power Fail early warning: No Power Fail supported in the TS80C51U2

EPFI: enable Power Fail

SMOD1: SMOD bit for UART1. Select double baud rate in mode123(not documented in the Dallas

datasheet) see UART note 5 below.

POR: Power On Reset status.

Note 3: Timer clock

The TS80C51U2 timer 0,1,2 and the additional Baud Rate Generator (BRG) are clocked by the same clock as the

CPU: Xtal/12 if CKCON bit X2 = 0, Xtal/6 if CKCON bit X2 =1. (note CKCON address = 8Fh)

The Dallas DS80C320/DS80C323 CKCON register address 8Eh bit T2M, T1M, T0M control the speed of the

respective timers. If bit is cleared (reset value) 12 clocks per timer cycle is used. If bit is set, 4 clocks per cycle are used.

Remark: Using TS80C51U2 to replace a DS80C320 or DS80C323, most likely the X2 mode will be selected in

the TS80C51U2 to achieve 6 clock per cycles for the CPU. The timers will also run at 6 clocks per cycle. Their

programming must be changed to recover the timing value they had with DS80C320/DS80C323 running at 4 clocks

per cycle or 12 clocks per cycle depending upon T2M, T1M, T0M values.

6 Rev. B - 28 April 2000

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Note 4: PCON UART control

TS80C512U2 PCON register (address 87h) contains the SMOD1_0 and SMOD0_0 control bit for UART0: SMOD1_0

select double baud rate in mode 1, 2, 3 and SMOD0_0 select access to Framing Error FE bit in SCON0.

Atmel Wireless & Microcontrollers also have the Power Off Flag Feature with POF bit included in PCON register.

Note: SMOD1_1 and SMOD0_1 control for UART1 are located in BDRCON_1 register (see table 4 above).

Dallas DS80C320/DS80C323 PCON register (same address than Atmel Wireless & Microcontrollers 87h) contains

SMOD_0 not documented but most likely the select double baud rate in mode 1, 2, 3 for UART0 and SMOD0

to select Framing Error FE bit in SCON0 and SCON1. SMOD_1 is available in WDCON register.

Dallas does not support the Power Off Flag

See also note 5 UART below.

Note 5: UART

TS80C51U2 includes an additional baud rate generator that can be used for UART0 and UART1. All modes

supported by Dallas DS80C320/DS80C323 are also available in the TS80C51U2. The Baud rate generator can be

selected for UART0 and or UART1.

See TS80C51U2 datasheet page 25, 30, 31 for description of BRL, BDRCON BDRCON_1.

In TS80C51U2 the Serial Port1 input and output pin locations are programmable. One configuration is fully

compatible with the Serial Port1 input and output pin locations in the DS80C320/DS80C323.

In the TS80C51U2, the pin locations for the Serial Port1 are programmed by the bit M1UA_1 and M0UA_1 in

the AUXR register (see table 4 above).

The following table indicates the pin position.

Table 5. Serial Port1 pin position in TS80C51U2

The following table gives for Dallas DS80C320/DS80C323 and TS80C51U2 the different timers that can be used

as Baud Rate Generator. TS80C51U2 offers the same modes as Dallas plus additional modes.

Table 6. Serial Ports timer option for Baud Rate

In Dallas DS80C320/DS80C323 Timer1 and Timer2 can be programmed separately to use 12 clocks or 4 clocks

per timer cycle. In TS80C51U2, Timer1 Timer2 and the additional Baud Rate Generator can be programmed to

all use 6 clocks per timer cycle or 12 clocks per timer cycles: see note 3 Timer clock above.

M1UA_1 M0UA_1 RXD1/TXD1

(DIP40) RXD1/TXD1

(PLCC44) RXD1/TXD1

(VQFP44) COMMENT

0 0 UART1 disabled UART1 disabled UART1 disabled

0 1 NA pin6/pin12 pin28/pin34

1 0 P1.2/P1.3 (pin3/pin4) P1.2/P1.3 (pin4/pin5) P1.2/P1.3 (pin42/pin43) Same as DS80C320

1 1 P1.6/P1.7 (pin7/pin8) P1.6/P1.7 (pin8/pin9) P1.6/P1.7 (pin2/pin3)

DALLAS ATMEL

Serial Port 0 Timer1

Timer2

Timer1

Timer2

Ad. Baud Rate Generator

Serial Port 1 Timer1 Timer1

Timer2

Ad. Baud Rate Generator

Rev. B - 28 April 2000 7

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When replacing a Dallas DS80C320/DS80C323 by a TS80C51U2, Timer1 and Timer2 programming have to be

changed to compensate for the different number of clock per timer cycles. Another possibility is to use the

additional Baud Rate generator that Atmel Wireless & Microcontrollers added in the TS80C51U2. The equations

below give: the Baud Rate frequency as a function of the programming options and the Baud Rate Reload value

to use as a function of the needed Baud Rate frequency.

Serial Port 1

2SMOD1_1 *2X2 *Fxtal

Baud_Rate =

2*2*6(1-SPD) *16 *[256-BRL]

2SMOD1_1 *2X2 *Fxtal

BRL = 256 -

2*2*6(1-SPD) *16 *Baud_Rate

Serial Port 0

2SMOD1_0 *2X2 *Fxtal

Baud_Rate =

2*2*6(1-SPD) *16 *[256-BRL]

2SMOD1_0 *2X2 *Fxtal

BRL = 256 -

2*2*6(1-SPD) *16 *Baud_Rate

SMOD1_0 and SMOD1_1 : see BDRCON_1 register description in Note 4, Note 5 and Table 4

X2 : see CKCON register description in Note 3 and Table 4

SPD : see BDRCON register in Table 4

Note 6: Interrupt

TS80C51U2 has a 4 level priority interrupt system. Whereas the DS80C320/DS80C323 only have 2 levels priority

interrupt system.

TS80C51U2 includes an additional IPH Interrupt priority register (address B7h) IP together with IPH provide a 2

bit coding to define 4 priority levels for the 7 following interrupts: UART1, Timer2, UART0, Timer1, External

Interrupt1, Timer0, External Interrupt0.

See Table 7: comparison natural interrupt priority assuming all sources have the same priority defined in IP

(DS80C320/DS80C323) or IP and IPH (TS80C51U2)

Note: with IPH reset value being 00h, TS80C51U2 defaults to 2 priority levels and is fully compatible with DS80C320.

8 Rev. B - 28 April 2000

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Table 7. Interrupt priority

Note 7: Reset, Power Fail and Power-Off Flag

Dallas DS80C320/DS80C323 Reset input includes an internal RC network for Power-up reset. For TS80C51U2,

an external Capacitor between Reset input and Vcc positive supply is necessary (1µF typical).

In the Dallas DS80C320/DS80C323, an internal band gap reference is used to define a Reset Threshold level Vrst.

The circuit will wait until Vcc exceed Vrst, then wait for 65536 clock cycles to apply the internal Reset. If Vcc

falls below Vrst, the circuit will reset itself.

In the TS80C51U2, at power up, the RC composed with internal resistor and external capacitor (see above) will

insure that a proper reset pulse is generated inside the circuit. A Schmitt trigger is built inside the chip in order

to maintain a reset pulse long enough in case of slow Vcc ramp-up. The internal oscillator also includes a special

mechanism to block the distribution of the clock inside the chip until the oscillator is stabilized with large enough

oscillations

The Dallas DS80C320/DS80C323 includes a Power Fail Interrupt with top priority. PFI interrupt can be enabled

using the EPFI bit in WDCON register. PFI is an early warning interrupt generated before Vcc falls below the

Vrst threshold level that will generate a reset.

There is no Power Fail Interrupt mechanism in the TS80C51U2.

TS80C51U2 includes a Power-Off flag: the POF bit in PCON register is set at power-up. POF bit is cleared when

an external or Watchdog reset generates a Reset. Note POF is not operational under 4.5 Volts supply.

Note: In the DS80C320/DS80C323 the Power Fail Interrupt vector is 33h. In the TS80C51U2 the Second Serial

Port interrupt vector is 33h. See note 6.

Name Description DALLAS

Level ATMEL

Level Vector Comment

PFI Power Fail interrupt See also note 7 on Reset 1 - 33h

INT0 External interrupt 0 2 1 03h

TF0 Timer 0 3 2 0Bh

INT1 External interrupt 1 4 3 13h

TF1 Timer 1 5 4 1Bh

SCON0 TI0 or RI0 UART0 6 5 23h

TF2 Timer 2 7 6 2Bh

SCON1 TI1 or RI1 UART1 8 7 3Bh Warning ATMEL SCON 1

interrupt vector at 33h

INT2 External interrupt2 9 - 43h

INT3 External interrupt3 10 - 4Bh

INT4 External interrupt4 11 - 53h

INT5 External interrupt5 12 - 5Bh

WDTI Watchdog timer (advance interrupt) 13 - 63h

Rev. B - 28 April 2000 9

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5. DC Parameters

Hereafter a DC parameters comparison table for DS80C320 and DS80C323 versus TS80C51U2

Table 8. DC Parameters for standard voltage (5 volts)

Note 1 : On TS80C51U2 Duringa0to1transition on Port2 when external program memory or external data

memory addressing , a pull-up 100 time stronger than the pull-up insuring the DC VOH : roughly 8mA IOH

boosts the transition, as described in the C51 family Hardware description (page 9 to 11). Same value on Dallas

DS80C320.

Symbol DS80C320 TS80C51U2 Unit Comments

Min Max Min Max

VIL -0.3 +0.8 -0.5 0.2Vcc - 0.1 V Input low voltage

VIH 2 Vcc+0.3 0.2Vcc+0.9 Vcc +0.5 V Input high voltage except XTAL1, RST

VIH 3.5 Vcc+0.3 0.7Vcc Vcc +0.5 V Input high voltage XTAL1, RST

VOL

Port1 Port3 0.45

0.3

0.45

1.0 VIOL=100µA

IOL=1.6mA

IOL=3.5mA

VOL

Port0 0.45

0.3

0.45

1VIOL=200µA

IOL=3.2mA

IOL=7.0mA

VOL

Port2 0.45

0.3

0.45

IOL=100µA

IOL=1.6mA

IOL=3.2mA

IOL=3.5mA

VOL

ALE, PSEN 0.45

0.3

0.45

1VIOL=200µA

IOL=3.2mA

IOL=7.0mA

VOH

ALE

PSEN

2.4

Vcc-0.3

Vcc-0.7

Vcc-1.5

IOH=-50µA

IOH=-200µA

IOH=-3.2mA

IOH=-7.0mA

IOH=-8.0mA

VOH

Port0 2.4

Vcc-0.3

Vcc-0.7

Vcc-1.5 V

IOH=-200µA

IOH=-3.2mA

IOH=-7.0mA

IOH=-8.0mA

VOH

Port2 2.4

Vcc-0.3

Vcc-0.7

Vcc-1.5

(Note 1)

IOH=-10µA

IOH=-30µA

IOH=-60µA

IOH=-8.0mA See Note1

VOH

Port1, Port3 2.4

2.4

Vcc-0.3

Vcc-0.7

Vcc-1.5

(Note 2)

IOH=-10µA

IOH=-30µA

IOH=-50µA

IOH=-60µA

IOH=-1.5mA See Note2

IIL

Port1,3 -55 -50 µA VOL=0.45V

IL Port0 -300 +300 -10 +10 µA

ITL Port1,3 -650 -650 µA Vin=2V

RST 50 170 50 200 kΩ

ICCop 45 33 mA 25MHz clock (TS80C51U2 in X2 mode)

ICCidle 25 15 mA 25MHz clock (TS80C51U2 in X2 mode)

IPD 1 (80) 50 µA DS80C320 80 µA if Band Gap on

10 Rev. B - 28 April 2000

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Note 2 : On TS80C51U2 Duringa0to1transition on Port1 and 3, a pull-up 100 time stronger than the pull-up

insuring the DC VOH : roughly 8mA IOH boosts the transition for 2 clock periods, as described in the C51

family Hardware description (page 9 to 11). Same mechanism and same value on Dallas DS80C320.

Table 9. DC Parameters for standard voltage (2.7 volts)

Note 1 : On TS80C51U2 Duringa0to1transition on Port2 when external program memory or external data

memory addressing , a pull-up 100 time stronger than the pull-up insuring the DC VOH : roughly 3mA IOH

boost the transition, as described in the C51 family Hardware description (page 9 to 11). Same value on Dallas

DS80C320.

Note 2 : On TS80C51U2 Duringa0to1transition on Port1 and 3, a pull-up 100 time stronger than the pull-up

insuring the DC VOH : roughly 1.5mA IOH boost the transition for 2 clock periods, as described in the C51

family Hardware description (page 9 to 11). Same mechanism and same value on Dallas DS80C320.

Symbol DS80C323 TS80C51U2 Unit Comments

Min Max Min Max

VIL -0.3 +0.2Vcc -0.5 0.2Vcc - 0.1 V Input low voltage

VIH 0.7Vcc Vcc+0.3 0.2Vcc+0.9 Vcc +0.5 V Input high voltage except XTAL1, RST

VIH 0.7Vcc+ 0.25 Vcc+0.3 0.7Vcc Vcc +0.5 V Input high voltage XTAL1, RST

VOL

Port1 Port3 0.4 0.45 V IOL=0.8mA

IOL=1.6mA

VOL

Port0 0.4 0.45 V IOL=1.6mA

IOL=3.2mA

VOL

Port2 0.4 0.45 V IOL=0.8mA

IOL=3.2mA

VOL

ALE, PSEN 0.4 0.45 V IOL=1.6mA

IOL=3.2mA

VOH

ALE

PSEN

Vcc-0.4

Vcc-0.4 0.9Vcc VIOH=-15µA

IOH=-40µA

IOH=-3.0mA

VOH

Port0 Vcc-0.4 0.9Vcc V IOH=-40µA

IOH=-3.0mA

VOH

Port2 Vcc-0.4

Vcc-0.4

0.9Vcc

Note 1 VIOH=-10µA

IOH=-15µA

IOH=-3mA See Note 1

VOH

Port1, Port3 Vcc-0.4 0.9Vcc

Note 2 VIOH=-10µA

IOH=-1.5mA See Note 2

IIL

Port1,3 -30 -50 µA VOL=0.45V

Port0 -300 +300 -10 +10 µA Vin=2V

ITL Port1,3 -400 -650 µA

RST 50 170 50 200 kΩ

ICCop 10 (typ) 12(max) mA 18MHz clock (TS80C51U2 in X2 mode)

ICCidle 6(typ) 5.6(max) mA 18MHz clock (TS80C51U2 in X2 mode)

IPD 1 (40) 30 µA DS80C320 40 µA if Band Gap on

Rev. B - 28 April 2000 11

ANM078

6. AC Parameters

The following table 9 shows the AC parameters for DS80C320 and TS80C51U2 at 5 volts and DS80C323 and

TS80C51U2 at 2.7 volts. All parameters are defined for variable clock unless an absolute value is given.

All values are in nanoSecond (ns). When T is present in an equation, T is the Xtal clock period in nanoSecond.

Table 10. AC Parameters comparison DS80C320/DS80C323 versus TS80C51U2 @ 5 volts and @ 2.7 volts

Note : DS80C320 : TPLAZ address held in a weak latch until overdriven by external memory

Symbol Parameter Cond. 80C320

(5 volts) TS80C51U2

(5 volts) DS80C323

(2.7 volts) TS80C51U2

(2.7 volts)

TLHLL ALE pulse width Min. 1.5T-10 T-8 1.5T-10 T-15

TAVLL Address valid to ALE Min. 0.5T-11 0.5T-13 0.5T-11 0.5T-20

TLLAX Address hold after ALE Min. 0.25T-5 0.5T-13 0.25T-5 0.5T-20

TLLIV ALE to valid instruction Max. 2.5T-27 2T-22 2.5T-27 2T-35

TLLPL ALE to PSEN Min. 0.25T-7 0.5T-8 0.25T-7 0.5T-15

TPLPH PSEN pulse width Min. 2.25T-7 1.5T-15 2.25T-7 1.5T-25

TPLIV PSEN to valid instruction Max. 2.25T-21 1.5T-25 2.25T-21 1.5T-45

TPXIX Input inst hold after PSEN Min. 0 0 0 0

TPXIZ Input inst float after PSEN Max. T-5 0.5T-5 T-5 0.5T-15

TAVIV Address low to valid inst. Max. 3T-27 2.5T-30 3T-27 2.5T-45

TAVIV Address high to valid inst. Max. 3.5T-33 2.5T-30 3.5T-33 2.5T-45

TPLAZ PSEN low to address float Max. See note 10 See note 10

Symbol Parameter Cond. 80C320

(5 volts) TS80C51U2

(5 volts) DS80C323

(2.7 volts) TS80C51U2

(2.7 volts)

TRLRH RD pulse width Min. 2T-11 3T-15 2T-11 3T-25

TWLWH WR pulse width Min. 2T-11 3T-15 2T-11 3T-25

TRLDV RD to valid data in Max. 2T-25 2.5T-23 2T-25 2.5T-30

TRHDX Data hold after RD Min. 0 0 0 0

TRHDZ Data float after RD Max. T-5 T-15 T-5 T-25

TLLDV ALE to valid data in Max. 2.5T-26 4T-35 2.5T-26 4T-45

TAVDV Address_L to valid data in Max. 3T-24 4.5T-50 3T-24 4.5T-65

TAVDV Address_H to valid data in Max. 3.5T-32 4.5T-50 3.5T-32 4.5T-65

TLLWL ALE to WR or RD Min. / Max. 0.5T-5 / 0.5T+6 1.5T-20 / 1.5T+20 0.5T-5 / 0.5T+6 1.5T-30 / 1.5T+30

TAVWL Address_L to WR or RD Min. T-9 2T-20 T-9 2T-30

TAVWL Address_H to WR or RD Min. 1.5T-9 2T-20 1.5T-9 2T-30

TQVWX Data valid to WR edge Min. -9 0.5T-10 -9 0.5T-20

TQVWH Data setup to WR edge Min. 3.5T-10 3.5T-20

TWHQX Data hold after WR Min. T-7 0.5T-8 T-7 0.5T-15

TRLAZ RD low to address float Max. 0 0

TWHLH WR or RD high to ALE Min. / Max. 0 / 10 0.5T-10 / 0.5T+10 0 / 10 0.5T-20 / 0.5T+20

TXLXL Serial port clock cycle Min. 12T 6T Not Available 6T

TQVXH Output setup to clock Min. 10T 5T-50 Not Available 5T-50

TXHQX Output hold after clock Min. 2T 2T-20 Not Available 2T-20

12 Rev. B - 28 April 2000

ANM078

Load capacitance at 5 volts

TS80C51U2 load capacitance for Port0,1,2,3 = 50pF , load capacitance ALE/PSEN = 30pF @5volts.

Dallas DS80C320 load capacitance for Port1,2,3 = 80pF , load capacitance for Port0, ALE/PSEN = 100pF @5volts.

Load capacitance at 2.7 volts

TS80C51U2 load capacitance for Port1,2,3 = 80pF , load capacitance Port0, ALE/PSEN = 100pF @2.7volts.

DALLAS DS80C320 load capacitance for Port1,2,3 = 80pF , load capacitance for Port0, ALE/PSEN = 100pF

@2.7volts.

7. References

7.1. Atmel Wireless & Microcontrollers references

- TS80C51U2 Datasheet Rev C – Aug. 24, 1999.

- 80C51 Hardware Description Manual Rev. E – Jan. 14, 1997.

- C51 family Programmer’s Guide and Instruction Set Rev. E – Jan. 14, 1997.

7.2. DALLAS references

- DS80C320/DS80C323 datasheet Rev 9/22/1999.

TXHDX Input hold after clock Min. T 0 Not Available 0

TXHDV Clock to input valid Max. 11T 5T-133 Not Available 5T-133

Symbol Parameter Cond. 80C320

(5 volts) TS80C51U2

(5 volts) DS80C323

(2.7 volts) TS80C51U2

(2.7 volts)