SMSC COM20019I 3.3V Rev.C Page 1 Rev. 11-07-08
DATASHEET
COM20019I 3.3V Rev.C
Cost Competitive
ARCNET (ANSI 878.1)
Controller with 2K x 8
On-Chip RAM
Datasheet
Product Features
New Features:
− Data Rates up to 312.5 Kbps
− Programmable Reconfiguration Times
28 Pin PLCC and 48 Pin T QFP packag es; Lead-
Free RoHS Compliant packages also available
Ideal for Industrial/Factory/Building Automati on
and Transportation Applicati ons
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Media Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microprocessors
Automatically Detects Type of Microcontroller
Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
Eight, 256 Byte Pages Allow Four Pages TX and
RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler for Adjusting Network
Speed
Operating Temperature Ran ge of -40oC to +85oC
3.3V power supply with 5V tolerant I/O
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star,
Tree, Bus...)
CMOS, Single +3.3V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Packets Mode
Flexible Media Interface:
− RS485 Differential Driver Interface For Cost
Competitive, Low Power, High Reliability
ORDERING INFORMATION
Order Number(s):
COM20019I 3VLJP for 28 pin PLCC * package
COM20019I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compliant pack age
COM20019I 3V-HD for 48 pin TQF P package
COM20019I 3V-HT for 48 pin TQ FP Lead-Free RoHS Compliant package
* TQFP package is recommended for new design
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 2 SMSC COM20019I 3.3V Rev.C
DATASHEET
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMI TATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO
HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I 3.3V Rev.C Page 3 Rev. 11-07-08
DATASHEET
TABLE OF CONTENTS
Chapter 1 General Description.............................................................................................................6
Chapter 2 Pin Configurations...............................................................................................................7
Chapter 3 Description of Pin Functions...............................................................................................9
Chapter 4 Protocol Description...........................................................................................................12
4.1 NETWORK PROTOCOL................................................................................................................12
4.2 DATA RATES.................................................................................................................................12
4.3 NETWORK RECONFIGURATION ................................................................................................12
4.4 BROADCAST MESSAGES............................................................................................................13
4.5 EXTENDED TIMEOUT FUNCTION...............................................................................................13
4.5.1 Response Time.......................................................................................................................................13
4.5.2 Idle Time.................................................................................................................................................13
4.5.3 Reconfiguration Time..............................................................................................................................14
4.6 LINE PROTOCOL..........................................................................................................................14
4.6.1 Invitations To Transmit ...........................................................................................................................14
4.6.2 Free Buffer Enquiries..............................................................................................................................14
4.6.3 Data Packets ..........................................................................................................................................15
4.6.4 Acknowledgements.................................................................................................................................15
4.6.5 Negative Acknowledgements .................................................................................................................15
Chapter 5 System Description.............................................................................................................16
5.1 MICROCONTROLLER INTERFACE.............................................................................................16
5.1.1 High Speed CPU Bus Timing Support....................................................................................................19
5.2 TRANSMISSION MEDIA INTERFACE..........................................................................................21
5.2.1 Backplane Configuration.........................................................................................................................21
5.2.2 Differential Driver Configuration..............................................................................................................22
5.2.3 Programmable TXEN Polarity.................................................................................................................22
Chapter 6 Functional Description.......................................................................................................25
6.1 MICROSEQUENCER ....................................................................................................................25
6.2 INTERNAL REGISTERS................................................................................................................26
6.2.1 Interrupt Mask Register (IMR) ................................................................................................................26
6.2.2 Data Register..........................................................................................................................................27
6.2.3 Tentative ID Register..............................................................................................................................27
6.2.4 Node ID Register....................................................................................................................................27
6.2.5 Next ID Register .....................................................................................................................................27
6.2.6 Status Register.......................................................................................................................................27
6.2.7 Diagnostic Status Register .....................................................................................................................28
6.2.8 Command Register.................................................................................................................................28
6.2.9 Address Pointer Registers......................................................................................................................28
6.2.10 Configuration Register ........................................................................................................................28
6.2.11 Sub-Address Register.........................................................................................................................28
6.2.12 Setup 1 Register .................................................................................................................................28
6.2.13 Setup 2 Register .................................................................................................................................29
6.3 INTERNAL RAM ............................................................................................................................37
6.3.1 Sequential Access Memory....................................................................................................................37
6.3.2 Access Speed.........................................................................................................................................37
6.4 SOFTWARE INTERFACE .............................................................................................................37
6.4.1 Selecting RAM Page Size.......................................................................................................................38
6.4.2 Transmit Sequence.................................................................................................................................39
6.4.3 Receive Sequence..................................................................................................................................40
6.5 COMMAND CHAINING..................................................................................................................41
6.5.1 Transmit Command Chaining.................................................................................................................42
6.5.2 Receive Command Chaining..................................................................................................................42
6.6 RESET DETAILS...........................................................................................................................43
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 4 SMSC COM20019I 3.3V Rev.C
DATASHEET
6.6.1 Internal Reset Logic................................................................................................................................43
6.7 INITIALIZATION SEQUENCE .......................................................................................................43
6.7.1 Bus Determination..................................................................................................................................43
6.8 IMPROVED DIAGNOSTICS..........................................................................................................44
6.8.1 Normal Results:......................................................................................................................................45
6.8.2 Abnormal Results: ..................................................................................................................................45
6.9 OSCILLATOR ................................................................................................................................45
Chapter 7 Operational Description ....................................................................................................47
7.1 MAXIMUM GUARANTEED RATINGS*.........................................................................................47
7.2 DC ELECTRICAL CHARACTERISTICS........................................................................................47
Chapter 8 Timing Diagrams................................................................................................................50
Chapter 9 Package Outlines................................................................................................................64
9.1 28 Pin PLCC Package Outline and Parameters............................................................................64
9.2 48 Pin TQFP Package Outline and Parameters............................................................................65
Chapter 10 Appendix A......................................................................................................................66
10.1 NOSYNC Bit...................................................................................................................................66
10.2 EF Bit..............................................................................................................................................66
Chapter 11 Appendix B......................................................................................................................69
Chapter 12 Appendix C......................................................................................................................70
12.1 Software Identification of the COM20019I 3V Rev B and Rev C...................................................70
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I 3.3V Rev.C Page 5 Rev. 11-07-08
DATASHEET
LIST OF FIGURES
Figure 3.1 - COM20019I 3V OPERATION...................................................................................................................11
Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE............................................17
Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE...................................18
Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................19
Figure 5.4 - COM20019I 3V NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS .....................................21
Figure 5.5 - INTERNAL B L O C K D I A G R A M..................................................................................................................23
Figure 6.1 - SEQUENTIAL AC C ESS O P ERA TI ON ......................................................................................................37
Figure 6.2 - RAM BUFFER P A C KET CON F I G URA T I O N .............................................................................................39
Figure 6.3 - COMMAND CHAINING S TATUS R EGI STE R Q UEU E..............................................................................41
Figure 7.1 - AC MEASUREMENTS..............................................................................................................................49
Figure 8.1 - MULTIPLEXED BUS, 68XX-LIKE CONT ROL SIGNALS; READ CYCLE.................................................50
Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONT ROL SIGNALS; READ CYCLE.................................................51
Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONT ROL SIGNALS; WRITE CYCLE................................................52
Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONT ROL SIGNALS; WRITE CYCLE................................................53
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE........................................54
Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE........................................55
Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE........................................56
Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE........................................57
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ......................................58
Figure 8.10 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................59
Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................61
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT........................................................................................67
Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS .............................................................69
LIST OF TABLES
Table 5.1 - Typical Med ia .............................................................................................................................................24
Table 6.1 - Read Regi s t e r Su m m a r y.............................................................................................. ...............................25
Table 6.2 - Write Register Summary............................................................................................................................26
Table 6.3 - Status Register...........................................................................................................................................29
Table 6.4 - Diagnostic S t a t us R e g ist er......................................................................................... .................................30
Table 6.5 - Command Re gis t er.....................................................................................................................................31
Table 6.6 - Address Pointe r High Regist er....................................................................................................................32
Table 6.7 - Address Pointe r Lo w R egister.....................................................................................................................32
Table 6.8 - Sub Address R e gis t e r.................................................................................................................................33
Table 6.9 - Configuration Registe r................................................................................................................................33
Table 6.10 - Setup 1 Regist er.......................................................................................................................................34
Table 6.11 - Setup 2 Regist er.......................................................................................................................................35
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 6 SMSC COM20019I 3.3V Rev.C
DATASHEET
Chapter 1 General Description
SMSC's COM20019I 3V is a member of the family of Embedded ARCNET Controllers from Standard
Microsystems Corporation. The device is a general purpose communications controller for networking
microcontrollers and intelligent peripherals in industrial and embedded control environments using an
ARCNET protocol engine. T he flexible microcontroller and media interfaces, eight-page messag e support,
and extended temperature range of the COM20019I 3V make it the only true network controller optimized
for use in industrial and embedded applications. Using an ARCNET protocol engine is the ideal solution
for embedded control applications because it provides a deterministic token-passing protocol, a highly
reliable and proven net working scheme, and a data rate of up to 312.5 Kbps when using the COM2001 9I
3V.
A token-passing protocol provides predicta bl e respo nse times because each network event occurs within a
predetermined time interval, based upon the number of nodes on th e network. The deterministic nature of
ARCNET is essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the
Command Chaining feature, the maximum data rate, and the internal diagnostics make the COM20019I
3V the highest performance embedded communications device available. With only one COM20019I 3V
and one microcontroller, a complete communications node may be implemented.
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes,
please refer to th e ARCNET Local Area Network St andar d, available from Standard Microsystems
Corporation or the ARCN ET Designer's Ha ndbook, availab le f rom D atapoi nt Corporation.
For more detailed information on cabling options including RS485, transformer-coupled RS-485
and Fiber Optic interfaces, please refer to the following technical note which is available from
Standard Micr osystems Co rporation : Technical Note 7- 5 - Cabling Guid elines for the COM 20020
ULANC.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I 3.3V Rev.C Page 7 Rev. 11-07-08
DATASHEET
Chapter 2 Pin Configurations
24
23
22
21
20
19
18
17
16
15
14
13
nRD/nDS
nWR/DIR
nCS
nINTR
nRESET IN
nTXEN
RXIN
nPULSE2
nPULSE1
XTAL2
XTAL1
VDD
25 24 23 22 21 20 19
nCS
nINTR
nRESET IN
VSS
nTXEN
RXIN
nPULSE2
567891011
AD1
VSS
AD2
D3
D4
D5
D6
18
17
16
15
14
13
12
nPULSE 1
XTAL2
XTAL1
VDD
VSS
N/C
D7
1
2
3
4
5
6
7
8
9
10
11
12
A0/nMUX
A1
A2/ALE
AD0
AD1
AD2
D3
D4
D5
D6
D7
VSS
26
27
28
1
2
3
4
nWR/DIR
nRD/nDS
VDD
A2/ALE
AD0
A1
A0/nMUX
Packages: 24- Pin DIP or 28- Pin PLCC
Orde ring Informat ion:
COM20019
PACKAGE TYPE: P = Plastic, LJP = PLCC
TEMP RANGE: (Blank) = Commercial: 0°C to +70°C
I = Industrial: -40°C to +85°C
DEVICE TYPE: 20019 = Universal Local Area Network Controller
(with 2K x 8 RAM)
P
I
Package: 28-Pin PLCC
COM20019I 3V
28 PIN PLCC
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 8 SMSC COM20019I 3.3V Rev.C
DATASHEET
NOTE: BUSTMG pin is only TQFP package
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
N/C
N/C
A2/ALE
A1
A0/nMUX
VDD
N/C
VSS
N/C
nRD/nDS
VDD
nWR/DIR
D7
N/C
N/C
N/C
N/C
VSS
N/C
VDD
XTAL1
XTAL2
VSS
nPULSE1
AD0
AD1
N/C
AD2
N/C
VSS
D3
VDD
D4
D5
VSS
D6
nCS
VDD
nINTR
N/C
VDD
nRESET
VSS
nTXEN
RXIN
N/C
BUSTMG
nPULSE2
COM20020I
48 PIN TQFP
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SMSC COM20019I 3.3V Rev.C Page 9 Rev. 11-07-08
DATASHEET
Chapter 3 Description of Pin Functions
PIN NO NAME SYMBOL I/O DESCRIPTION
PLCC TQFP MICROCONTROLLER INTERFACE
1, 2,
3 44, 45,
46 Address
0-2 A0/nMUX
A1
A2/ALE
IN
IN
IN
On a non-multiplexed mode, A0-A2 are address
input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A1 is connected to an internal pull-up resistor .
4, 5, 6,
8, 9,
10, 11,
12
1, 2, 4,
7, 9, 10,
12, 13
Data 0-7 AD0-AD2,
D3-D7 I/O On a non-multiplexed bus, thes e signals are used
as the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address
lines (latched by ALE) and as the lo w data lines.
D3-D7 are always used for data onl y. These signals
are connected to internal pull-up resistors.
26 37 nWrite/
Direction nWR/DIR IN
nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
27 39 nRead/
nData
Strobe
nRD/nDS IN
nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
23 31 nReset In nRESET IN
Hardware reset signal. Active Low.
24 34 nInterrupt nINTR OUT
Interrupt signal output. Active Low.
25 36
nChip
Select nCS IN
Chip Select input. Active Low.
- 26
Read/Write
Bus Timing
Select
BUSTMG IN
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU Timing.
L: High speed timing mode (only for non-
multiplexed bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
NOTE:
BUSTMG pin does not exist in PLCC package.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 10 SMSC COM20019I 3.3V Rev.C
DATASHEET
PIN NO NAME SYMBOL I/O DESCRIPTION
PLCC TQFP TRANSMISSION MEDIA INTERFACE
18
19
24
25
nPulse 1
nPulse 2
nPULSE1
nPULSE2
OUT
I/O
In Normal Mode, these active low signals carry the
transmit data information, encoded in pulse format
as DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull
or open-drain), while the nPU LSE2 sig nal provides
a clock with frequency of doubled data rate.
nPULSE1 is connected to a weak internal pull-up
resistor on the open/drain driver in backplane
mode.
20 28 Receive In RXIN IN
This signal carries the receive data information from
the line transceiver.
21 29
nTransmit
Enable nTXEN OUT
Transmission Enable signal. Active polarity is
programmable through the nPULSE2 pin.
nPULSE2 floating before power-up;
nTXEN active lo w
nPULSE2 grounded befor e power-up;
nTXEN active high (this optio n is only available in
Back Plane mode)
16
17 21
22 Crystal
Oscillator XTAL1
XTAL2 IN
OUT An external crystal should be conn ected to these
pins. Oscillation frequency range is from 10 MHz to
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 wit h a 390ohm pull-up
resistor, and XTAL2 should be left floating.
15, 28 8, 20,
32, 43 Power
Supply VDD PWR
+3.3 Volt power supply pins.
7, 14,
22 6, 11,
18, 23,
30, 41
Ground VSS PWR
Ground pins.
13 3, 5,
14-17,
19, 27,
33, 35,
38, 40,
42, 47,
48
N/C N/C
Non-connection
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SMSC COM20019I 3.3V Rev.C Page 11 Rev. 11-07-08
DATASHEET
Figure 3.1 - COM20019I 3V OPERATION
Invitation
to Transmit to
this ID?
YN
Free Buffer
Enqui ry to
this ID? SOH?
YN
YN
RI?
Write SID
to Buffer
DID
=0?
DID
=ID?
Write Buffer
with Packet
CRC
OK?
LENGTH
OK?
DID
=0?
DID
=ID?
SEND ACK
N
Y
N
Y
N
YN
Broadcast
Enabled? N
Y
N
No Activity
for 656
uS?
Y
N
Set NID=ID
Start Timer:
T=(255-ID)
Activity
On Line? Y
N
T=0?
Set RI
RI?
Transmit
NAK
Transmit
ACK
Set NID=ID
Write ID to
RAM Buffer
Send
Reconfigure
Burst
Power On
Reconfigure
Timer has
Timed Out
Start
Reconfiguration
Timer (6.72 S)*
TA?
Broadcast? Transmit
Free Buffer
Enquiry No
Activity
Pass the
Token
Set TA
Y
N
ACK?
NAK?
1
No
Activity NY
Increment
NID
Send
Packet
Was Packet
Broadcast?
No
Activity
N
ACK? Set TMA
Set TA
x 1.168 mS
for 597.6
us?
for 597.6
us?
for 597.6
us?
YN
N
Y
YN
NY
N
N
N
N
1
Y
Y
Y
YY
Y
Y
N
Y
Read Node ID
ID refers to the identification number of the ID assigned to this node.
NID refers to the next identification number that receives the token
after this ID passes it.
-
-
-
-
SID refers to the source identification.
DID refers to the destination identification.
SOH refers to the start of header character; preceeds al l data packets.
-
YN
* Reconfig timer is programmable via setup2 register bits 1, 0.
Note - All time values are valid for 312.5 Kbps.
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Rev. 11-07-08 Page 12 SMSC COM20019I 3.3V Rev.C
DATASHEET
Chapter 4 Protocol Description
4.1 NETWORK PROTOCOL
Communication on the network is based on a token passing protocol. Establishment of the network
configuration and management of the network protocol are handled entirely by the COM20019I 3V's
internal microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a
data packet and its destination ID into the COM20019I 3V's internal RAM buffer, and issuing a command
to enable the transmitter. When the COM20019I 3V next receives the token, it verifies that the receiving
node is ready by first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits
an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If the rece iving node
cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcK nowledge message
and the transmitter passes the token. Once it has been esta blished that the receiving no de can accept the
packet and transmission is complete, the receiving node verifies the packet. If the packet is received
successfully,
the receiving node transmits an ACKnowledge message (or nothing if it is not received successfully)
allowing the transmitter to set the appropriate status bits to indicate succes sful or unsuccessful delivery of
the packet. An interrupt mask permits the C OM20019I 3V to generate an interrupt to th e processor when
selected status bits become true. Figure 3.1 - COM20019I 3V OPERATION is a flow chart illustrating the
internal operation of the COM20019I 3V con nected to a 20 MHz crystal oscillator.
4.2 DATA RATES
The COM20019I 3V is capable of supporting data rates from 156.25 Kbps to 312.5 Kbps. The following
protocol description assumes a 312.5 Kbps data rate. For slower data rates, an internal clock divider
scales down the clock frequency. Thus all timeout values are scaled as shown in the following table:
Example: IDLE LINE Timeout @ 312.5 Kb p s = 656 μs. IDLE LINE Timeout for 156.2 Kbps is 65 6 μs * 2 =
1.3 ms
INTERNAL CLOCK
FREQUENCY CLOCK PRESCALER DATA RATE TIMEOUT SCALING FACTOR
(MULTIPLY BY)
20 MHz Div. by 64
Div. by 128 312.5 Kbps
156.25 Kbps 1
2
4.3 NETWORK RECONFIGURATION
A significant advantage of the COM20019I 3V is its abilit y to adapt to changes on the network. Whenever
a new node is activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new
COM20019I 3V is turned on (creating a ne w active node on the net work), or if the COM20019I 3V has not
received an INVITATION TO TRANSMIT for 6.72S, or if a software reset occurs, the COM20019I 3V
causes a NETWORK RECONFIGURATION by sending a RECONFIGURE BURST consisting of eight
marks and one space repeated 765 times. The purpose of this burst is to terminate all activity on the
network. Since this burst is longer tha n any other t ype of tr ansmissi on, the burst will interfere with the next
INVITATION TO TRANSMIT, destroy the token and keep any other node from assuming control of the
line.
When any COM20019I 3V se nses an id le lin e for greater th an 656μS, which occurs only when t he toke n Is
lost, each COM20019I 3V starts an internal timeout equal to 1.168mS times the quantity 255 minus its own
ID. The COM20019I 3V starts network reconfiguration by sending a n invitation to transmit first to itself and
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I 3.3V Rev.C Page 13 Rev. 11-07-08
DATASHEET
then to all other nodes by decrementing the destination Node ID. If the timeout expires with no line
activity, the COM20019I 3V starts sending INVITATION TO TRANSMIT with the Destination ID (DID)
equal to the currently stored NID. Within a given network, only one COM20019I 3V will timeout (the one
with the highest ID number). After sending the INVIT ATION TO TRANSMIT , the COM20019I 3V waits for
activity on the line. If there is no activity for 597.6uS, the COM20019I 3V increments the NID value and
transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If activity appears before
the 597.6S timeout expires, the COM20019I 3V releases control of the line. During NETWORK
RECONFIGURATION, INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).
Each COM20019I 3V on the net work will finall y have s aved a NID va lue equ al to the ID of the COM20019I
3V that it released control to. At this point, control is passed directly from one node to the next with no
wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK
RECONFIGURATION occurs. When a node is powered of f, the previous node attempts to pass the token
to it by issuing an INVITATION TO TRANSMIT. Since this node does not respond, the previous node
times out and transmits another INVITATION TO TRANSMIT to an incremented ID and eventually a
response will be received.
The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the
propagation delay between nodes, and the highest ID number on the network, but is typically within the
range of 192 to 488 mS.
4.4 BROADCAST MESSAGES
Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network
simultaneously. ID zero is reserved for this feature and no node on the n etwork can be assigned ID z ero.
To broadcast a message, the transmitting node's processor simply loads the RAM buffer with the data
packet and sets the DID equal to zero. Figure 4 illustrates the position of each byte in the packet with the
DID residing at address 0X01 or 1 Hex of the current page selected in the "Enable Transmit from Page
fnn" command. Each individual node has the ability to ignore broadcast messages by setting the most
significant bit of the "Enable Receive to Page fnn" command to a logic "0".
4.5 EXTENDED TIMEOUT FUNCTION
There are three timeouts associated with the COM20019I 3V operation. The values of these timeouts are
controlled by bits 3 and 4 of the Configuration Register and bit 5 of the Setup 1 Register.
4.5.1 Response Time
The Response Time determines the maximum propagation delay allowed between any two nodes, and
should be chosen to be larger than the round trip propagation delay between the two furthest nodes on
the network plus the maximum turn around time (the time it takes a particular COM20019I 3V to start
sending a message i n response to a received message) which is approximately 101.6 μS. The round trip
propagation delay is a function of the transmission media and network topology. For a typical system
using RG62 coax in a baseband system, a one way cable propagation delay of 248 μS translates to a
distance of about 32 miles. The flow chart in Figure 3.1 uses a value of 597.6 μS (248 + 248 + 101.6) to
determine if any node will res pond.
4.5.2 Idle Time
The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 3.1 illustrates that during a
NETWORK RECONFIGURATION one node will continu ally transmit INVITAT IONS TO TRANSMIT until it
encounters an active node. All other nodes on the net work must distinguish bet ween this operation and an
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 14 SMSC COM20019I 3.3V Rev.C
DATASHEET
entirely idle line. During NETWORK RECONFIGURATION, activity will appear on the line every 656 μS.
This 656 μS is equal to the Response Time of 597.6 μS plus the time it takes the COM20019I 3V to start
retransmitting another message (usually anot her INVITATION TO TRANSMIT).
4.5.3 Reconfiguration Time
If any node does not receive the token within the Reconfiguration T ime, the node will initiate a NETWORK
RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate
over longer distances than the 32 mil es stated earlier. Thelogic levels on these bits control the ma ximum
distances over which the COM20019I 3V can operate by controlling the three timeout values described
above. For proper network operation, all COM20019I 3V's connected to the same network must have the
same Response Time, Idle T ime, and Reconfiguration Time.
4.6 LINE PROTOCOL
The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval
and ended with a stop interval. Unlike asynchronous protocols, there is a constant amount of time
separating each data byte. On a 312.5 K bps network, each b yte takes exactly 11 clock intervals of 3.2 μS
each. As a result, one byte is transmitted every 35.2 μS and the time to transmit a message can be
precisely determined. The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line
activity and a logic "1" is defined as a negative pulse of 1.6 uS duration. A transmission starts with an
ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent,
with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of
transmission can be performed as described below:
4.6.1 Invitations To Transmit
An Invitation To Transmit is used to pass the token from one no de to another and is sent by the following
sequence:
An ALERT BURST
An EOT (End Of T ransmission: ASCII code 04H)
Two (repeated) DID (Destination ID) characters
ALERT
BURST EOT DID DID
4.6.2 Free Buffer Enquiries
A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the
following sequence:
An ALERT BURST
An ENQ (ENQuiry: ASCII code 85H)
Two (repeated) DID (Destination ID) characters
ALERT
BURST ENQ DID DID
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SMSC COM20019I 3.3V Rev.C Page 15 Rev. 11-07-08
DATASHEET
4.6.3 Data Packets
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:
An ALERT BURST
An SOH (Start Of Header--ASCII code 01H)
An SID (Sourc e ID) character
Two (repeated) DID (Destination ID) characters
A singl e COUNT character which is the 2's complement of the number of data b ytes to follow if a
short packet is sent, or 00H followed by a COUNT character if a long packet is sent.
N data bytes where COUNT = 256-N (or 512-N for a long pa cket)
Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1.
A
LERT
BURST SOH SID DID DID COUNT data data CRC CRC
4.6.4 Acknowledgements
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE
BUFFER ENQUIRIES and is sent by the follo wing sequence:
An ALERT BURST
An ACK (ACKnowledgement--ASCII code 86H) character
ALERT BURST ACK
4.6.5 Negative Acknowledgements
A Negative Acknowledgemen t is used as a negative response to FREE BUFFER ENQUIRIES and is sent
by the following sequence:
An ALERT BURST
A NAK (Negativ e Acknowledgement--ASCII code 15H) character
ALERT BURST NAK
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DATASHEET
Chapter 5 System Description
5.1 MICROCONTROLLER INTERFACE
The top halves of Figure 5.1 and Figure 5.2 illustrate typical COM20019I 3V interfaces to the
microcontrollers. The interfaces consist of a 8-bit data bus, an address bus and a control bus. In order to
support a wide range of microcontroll ers without requiring glue logic a nd without increasing the n umber of
pins, the COM20019I 3V automatical ly detects and adapts to the type of microcontroller bein g used. Upon
hardware reset, the COM20019I 3V first determines whether the read and write control signals are
separate READ and WRITE signals (like the 80XX) or DIRECTION and DATA STROBE (like the 68XX).
To determine the type of control signals, the device requires the software to execute at least one write
access to external memory before attempting to access the COM20019I 3V. The device defaults to 80XX-
like signals. Once the type of control signals are det ermined, the COM20019I 3V remains in this interface
mode until the next hardware reset occurs. The second determination the COM20019I 3V makes is
whether the bus is multiplexed or non-multiplexed. To determine the type of bus, the device requires the
software to write to an odd memory locati on followed by a read from an odd location before attempting to
access the COM20019I 3V. T he signal on the A0 pin duri ng the odd location access tell s the COM20019I
3V the type of bus. Since multiplexed operation requires A0 to be active low, activity on the A0 line tells
the COM20019I 3V that the bus is non-multiplexed. The device defaults to multiplexed operation. Both
determinations may be made simultaneousl y by performing a WRITE followed by a READ operation to an
odd location within the COM20019I 3V Address space 20019 registers. Once the type of bus is
determined, the COM20019I 3V remains in this interface mode until har dware reset occurs.
Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be
changed until hardware reset. Refer to Description of Pin Functions section for details on the related
signals. All accesses to the internal RAM and the inter nal registers are controlled by the COM20019I 3V.
The internal RAM is accessed via a pointer-based scheme (refer to the Sequential Access Memory
section), and the internal registers are accessed via direct addressing. Many peripherals are not fast
enough to take advantage of high-speed microcontrollers. Since microcontrollers do not typically have
READY inputs, standard p eripherals cannot extend cycles t o extend the access time. The access time of
the COM20019I 3V, on the other hand, is so fast that it does not need to limit the speed of the
microcontroller. The COM20019I 3V is designed to be flexible so that it is independent of the
microcontroller speed.
The COM20019I 3V provides for no wait state arbitration via direct addres sing to its internal registers and
a pointer based addressing scheme to access its internal RAM. The pointer may be used in auto-
increment mode for typical sequential buffer empt ying or loading, or it can be taken out of auto-increment
mode to perform random accesses to the RAM. The data within the RAM is accessed through the data
register. Data being read is prefetched from memory and placed into the data register for the
microcontroller to read. It is important to notice that only by writing a new address pointer (writing to an
address pointer lo w), one obtains the contents of CO M20019I 3V internal RAM. Performing only read fr om
the Data Register does not load new data from the internal RAM. During a write operation, the data is
stored in the data register and then written into memory. Whenever the pointer is loaded for reads with a
new value, data is immediatel y prefetched to prepare for the first read operation.
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SMSC COM20019I 3.3V Rev.C Page 17 Rev. 11-07-08
DATASHEET
Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE
AD0-AD7
nINT1
RESET
nRD
nWR
A15
AD0-AD2, D3-D7
nCS
nRESET
nRD/nDS
nWR/DIR
nINTR
A2/BALE
ALE
XTAL1
XTAL2
GND
RXIN
nPULSE1
nPULSE2
nTXEN
8051
COM20022
Differential Driver
Configuration
Media Interface
may be replac ed
with Figure A, B or C.
*
RXIN
nPULSE1
nPULSE2
TXEN
GND
+5V
100 Ohm
BACKPLANE CONFIGURATION
FIGUR E A
RXIN
nPULSE1
FIGURE B
Receiver
HFD3212-002
2
+5V
7
6
Transmitter
HFE4211-014
+5V
3
2 Fiber Interface
(ST Connectors)
2
6
7
NOTE: COM20022 must be in backplane mode
75176B or
Equiv.
A0/nMUX
27 pF 27 pF
XTAL2
XTAL1
20 MHz
XTAL
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DATASHEET
Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE
D0-D7
nIRQ1
nRES
nIOS
R/nW
A7
D0-D7
A0/nMUX
A0
XTAL1
XTAL2
A1
A1
nCS
nRESET
nRD/nDS
nWR/nDIR
nINTR
A2/BALE
A2
RXIN
nPULSE1
nPULSE2
TXEN
GND
Different ial Driv er
Configuration
6801
COM20022
Media Interface
may be replaced
with Figure A, B or C.
*
75176B or
Equiv.
XTAL1 XTAL2
27 pF 27 pF
20MHz
XTAL
RXIN
nPULSE1
nPULSE2
nTXEN
GND
Traditiona l Hy br id
Configuration
RXIN
nPULSE1
nPULSE2
17, 19,
4, 13, 14
5.6K
1/2W
5.6K
1/2W
0.01 uF
1KV
12
11
-5V
0.47
uF 10
uF
+
3
0.47
uF
+
+5V
uF
10
6
FIGURE C
HYC9088
HYC9068 or
N/C
*Valid for 2. 5 M bps only.
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SMSC COM20019I 3.3V Rev.C Page 19 Rev. 11-07-08
DATASHEET
5.1.1 High Speed CPU Bus Timing Support
High speed CPU bus support was adde d to the COM20019I 3V. The reasoning behind this is as follows:
With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable
before the read signal is acti ve and remain after the read signal is inactive. But the H igh Speed CPU bu s
timing doesn't adhere to these timings. For example, a RISC type single chip microcontroller (like the
HITACHI SH-1 series) changes I/O address at the same time as the read signal. Therefore, several
external logic ICs would be require d to connect to this microcontro ller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal
DIAG register read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read
(nRD) signals. The decoder will generate a noise spike at the above tight timing. The DIAG register is
cleared by the spike signal without reading itself. T his is unexpected operation. Reading the internal R AM
and Next Id Register have the same mechanism as reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU
interface to support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address
(A2-A0) and Chip Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal
delayed nRD signal. The internal real read signal is the more delayed nRD signal. But the rising edge of
nRD doesn't delay. By this modification, the internal real address and Chip Select are stable while the
internal real read signal is active. Refer to F igure 5.3 below.
Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled.
Also, the nRD signal is not delayed, because the above sampling and delaying paths decrease the data
access time of the read cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which
generates the clearing pulse for the Diagnostic register and generates the starting pulse of the RAM
Arbitration. Typical delay time between nRD and nRD1 is around 15nS and bet ween nRD1 and nRD2 is
around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some
wait cycles to extend the width without any impact on performance.
The BUSTMG pin (TQFP package only) is used to support this function. It is used to Enable/Disable the
High Speed CPU Read and Write function. It is defined as: BUST MG = 0, the High Speed CPU Read and
A2-A0, nCS
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
VALID
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Rev. 11-07-08 Page 20 SMSC COM20019I 3.3V Rev.C
DATASHEET
Write operations are enabled; BUST MG = 1, the High Speed CPU Read a nd Write operat ions are disabl ed
if the RBUSTMG bit is 0. If BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are
enabled (see definition of RBUSTMG bit below).
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
z For 28-Pin PLCC package (BUSTMG is tied to 1 internally)
RBUSTMG BIT BUS TIMING MODE
0 Normal Speed C PU Read and Wri te
1 High Speed CPU Read and Normal Speed CPU Write
z For 48-Pin TQFP package
BUSTMG PIN RBUSTMG BIT BUS TIMING MODE
0 X High Speed CPU Read and Write
1 0 Normal Speed CPU Read and Write
1 1 High Speed CPU Rea d and Normal Speed CPU Write
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DATASHEET
5.2 TRANSMISSION MEDIA INTERFACE
The bottom halves of Figures 2 and 3 illustrate the COM20019I 3V interface to the transmission media
used to connect the node to the network. Table 1 lists different types of cable which are suitable for
ARCNET applications. (Refer to Note 5.1)
The user may interface to the cable of choice in one of thre e ways:
Note 5.1 Please refer to TN7-5 – Cabling Guidelines for the COM20020 ULA NC, available from SMSC, for
recommended cabling distance, terminatio n, and node count for ARCNET nodes.
5.2.1 Backplane Configuration
The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications
like backplanes and instrumentation. T his mode is advant ageous bec aus e it saves components, cost, and
power.
Since the Backplane Configuration encodes data differently than the traditional Hybrid Configuration,
nodes utilizing the Backplane Configuration cannot communicate directly with nodes utilizing the
Traditional Hybrid Configuration. The Backplane Configuration does not isolate the node from the media
nor protects it from Common Mode noise, but Common Mode Noise is less of a problem in short
distances.
The COM20019I 3V supplies a programmable output driver for Backplane Mode operation. Apush/pull or
open drain driver can be selected by programming the P1MODE bit of the Setup 1 Register (see register
descriptions for details). The COM2001 9I 3V defaults to an open drain output.
The Backplane Configuration provides for direct connection between the COM20019I 3V and the media.
Only one pull-up resistor (in open drain configuration of the output driver) is required somewhere on the
media (not on each individual node). The nPULSE1 signal, in this mode, is an open drain or push/pull
driver and is used to directl y drive the medi a. It issues a 1. 6µS negative pulse to trans mit a logic "1". Note
that when used in the open-drain mode, the COM20019I 3V does not have a fail/safe input on the RXIN
pin. The nPULSE1 signal actually contains a weak pull-u p resistor. This pull- up should not take th e place
of the resistor required on the media for open drain mode.
Figure 5.4 - COM20019I 3V NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS
In typical applications, the serial backplane is terminated at both ends and a bias is provided by the
external pull-up resistor.
COM20022I 3V COM20022I 3V COM20022I 3V
+VCC
RBIAS +VCC +VCC
RBIAS RBIAS
RT RT
75176B or
Equiv.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 22 SMSC COM20019I 3.3V Rev.C
DATASHEET
The RXIN signal is directly connected to the cable via an internal Schmitt trigger. A negative pulse on this
input indicates a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane
applications, RXIN is connected to nPULSE 1 to make the serial backplane data line. A ground line (from
the coax or twisted pair) should run in parallel with the signal. For applications requiring different treatment
of the receive signal (like filtering or squelching), nPULSE1 and RXIN remain as independent pins.
External differential drivers/receivers for increased range an d common mode noise rejection, for example,
would require the signals to be independent of one another. When the device is in Backplane Mode, the
clock provided by the nPULSE2 signal may be used for encoding the data into a different encoding
scheme or other synchronous operations needed on the serial data stream.
5.2.2 Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled
configuration recommended for applications like car-area networks or other cost-sensitive applications
which do not require direct compatibility with existing ARCNET nodes and do not require isolation.
The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional
Hybrid Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not
isolate the node from the media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable
and the COM20019I 3V. The nPULSE1 signal transmits the data, prov ided the Transmit Enable signal is
active. The nPULSE1 signal issues a 1. 6µS negative pulse to transmit a logic "1". Lack of pulse indic ates
a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20019I 3V is disabled
during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive.
5.2.3 Programmable TXEN Polarity
To accommodate transceivers with active high ENABLE pins, the COM20019I 3V contains a
programmable TXEN output. To program the TXEN pin for an active high pulse, the nPULSE2 pin should
be connected to ground. To retain the normal active low polarity, nPULSE2 should be left open. The
polarity determination is made at power on reset and is valid only for Backplane Mode operation. The
nPULSE2 pin should remain grounded at all times if an active high polarity is desired.
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DATASHEET
Figure 5.5 - INTERNAL BLOCK DIAGRAM
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
STATUS/
COMMAND
REGISTER
RESET
LOGIC
RECONFIGURATION
TIMER NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
ADDRESS
DECODING
CIRCUITRY 2K x 8
AD0-AD2,
BUS
ARBITRATION
CIRCUITRY
nPULSE1
nPULSE2
nTXEN
nINTR
nRESET
RAM
A0/nMUX
A1
A2/BALE
nRD/nDS
nWR/DIR
nCS
D3-D7
RXIN
XTAL1
XTAL2
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DATASHEET
Table 5.1 - Typ i c a l Me d i a
CABLE TYPE NOMINAL
IMPEDANCE ATTENUATION PER 1000 FT.
AT 5 MHZ
RG-62 Belden #86262 93Ω 5.5dB
RG-59/U Belden #89108 75Ω 7.0dB
RG-11/U Belden #89108 75Ω 5.5dB
IBM Type 1 (See Note 5.2)
Belden #89688 150Ω 7.0dB
IBM Type 3 (See Note 5.2)
Telephone Twisted Pair Belden
#1155A
100Ω 17.9dB
COMCODE 26 AWG Twisted Pair
Part #105-064-703 105Ω 16.0dB
Note 5.2 Non-plenum-rated cables of this type are also available.
Note: For more detailed information on Cabling options includin g RS-485, transformer-coupled RS-485 an d Fiber
Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from
Standard Microsystems Corporation.
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DATASHEET
Chapter 6 Functional Description
6.1 MICROSEQUENCER
The COM20019I 3V contains an internal microsequencer which performs all of the control operations
necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20019I 3V derives a 625 kHz and a 312.5 kHz clo ck from the output clock of the Clock Multipl ier.
These clocks provide the rate at which the instructions are executed wit hin the COM20019I 3V. The 625
kHz clock is the rate at which the program counter operat es, while the 312.5 kHz clock is the rate at which
the instructions are executed. T he microprogram
is stored in the ROM and the instructions are fetched and then placed into the instruction registers. One
register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20019I 3V proceeds to execute the
instruction. When a no-op instruction is encountered, the microsequencer enters a timed loop and the
program counter is temporarily stop pe d unti l the lo op is c omplete. Whe n a jump instructi on is enco unter ed,
the program counter is loaded with the jump address from the ROM. The COM20019I 3V contains an
internal reconfiguration timer which interrupts the microsequencer if it has timed out. At this point the
program counter is cleared and the MYRECON bit of the Diagnostic Status Register is set.
Table 6.1 - Read Register Summary
REGISTER MSB READ LSB ADDR
STATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/
TTA 00
DIAG.
STATUS MY-
RECON DUPID RCV-
ACT TOKEN EXC-
NAK TENTID NEW
NEXTID X 01
ADDRESS
PTR HIGH RD-
DATA AUTO-
INC X X X A10 A9 A8
02
ADDRESS
PTR LOW A7 A6 A5 A4 A3 A2 A1 A0
03
DATA D7 D6 D5 D4 D3 D2 D1 D0
04
SUB ADR (R/W)* (R/W)* X X X SUB-AD2 SUB-AD1
SUB-
AD0 05
CONFIG-
URATION RESET CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-AD1 SUB-
AD0 06
TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0
07-0
NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0
07-1
SETUP1 P1
MODE FOUR
NAKS X RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB 07-2
NEXT ID NXT ID7 NXT ID6 NXT ID5 NXT ID4 NXT ID3 NXT
ID2 NXT ID1 NXT
ID0 07-3
SETUP2 RBUS-
TMG X X X EF
NO-
SYNC RCN-
TM1 RCM-
TM2 07-4
Note*: (R/W) These bits can be Written or Read. For more information see Appendix C.
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DATASHEET
Table 6.2 - Write Register Summary
ADDR MSB WRITE LSB REGISTER
00 RI/TR1 0 0 0 EXCNAK RECON NEW
NEXTID TA/
TTA INTERRUPT
MASK
01 C7 C6 C5 C4 C3 C2 C1 C0
COMMAND
02 RD-
DATA AUTO-
INC 0 0 0 A10 A9 A8
ADDRESS
PTR HIGH
03 A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS
PTR LOW
04 D7 D6 D5 D4 D3 D2 D1 D0 DAT A
05 (R/W)* (R/W)* 0 0 0 SUB-AD2 SUB-
AD1 SUB-
AD0 SUBADR
06 RESET CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-
AD1 SUB-
AD0 CONFIG-
URATION
07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID
07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID
07-2 P1-
MODE FOUR
NAKS 0 RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB SETUP1
07-3 0 0 0 0 0 0 0 0 TEST
07-4 RBUS-
TMG 0 0 0 EF NO-
SYNC RCN-
TM1 RCN-
TM0 SETUP2
Note*: (R/W) These bits can be Written or Read. For more inform ation see Appendix C.
6.2 INTERNAL REGISTERS
The COM20019I 3V contains 14 internal registers. Tables 2 and 3 illustrate the COM20019I 3V register
map. All undefined bits are read as undefine d and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20019I 3V is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be e nabled to generate an interrupt. The bit positi ons in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or T A interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the correspondin g mask bit is set to log ic "1" again, un less the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
New Next ID interrupt is cleared by readi ng the Next ID Register. The Interrupt Mask Register d efaults to
the value 0000 0000 upon hardware reset.
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6.2.2 Data Register
This read/write 8-bit register is used as the chan nel through which the data to and from the RAM passes.
The data is placed in or retrieved from the address location presently specified by the address pointer.
The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the
Data Register is loaded with the contents of COM20019I 3V Internal Memor y upon writing Address Poi nter
low only once.
6.2.3 Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configurati on Register and SUB ADR Register). The Tentative ID Re gister
can be used while the node is on-line to build a network map of those nodes existing on the network. It
minimizes the need for operator interaction wit h the network. The node determines the existence of other
nodes by placing a Node ID value in the T entative ID Register and waiting to see if the Tentative ID bit of
the Diagnostic Status Register gets set. The network map developed by this method is only valid for a
short period of time, since nodes may join or depart from the network at any time. When using the
Tentative ID feature, a node cannot detect the existence of the next logical node to which it passes the
token. The Next ID Register will hold the ID value of that node. T he Tentative ID Register defaults to the
value 0000 0000 upon h ardware reset only.
6.2.4 Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Node ID Register
contains the unique value which identifies this particular node. Each node on the network must have a
unique Node ID value at all times. The Duplicate ID bit of the Diagnostic Status Register helps the user
find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the
DUPID bit. The core of the COM20019I 3V does not wake up until a Node ID other than zero is written
into the Node ID Register. During this time, no microcode i s executed, no tokens are passed b y this node,
and no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID
Register, the core wakes up but will not join the net work until the TXEN bit of the Configuration Register is
set. While the Transmitter is disable d, the Receiver portion of the device is still f unctional and will provide
the user with useful information about the network. T he Node ID Register defaults to the value 00 00 0000
upon hardware reset only.
6.2.5 Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Next ID Register
holds the value of the Node ID to which the COM20019I 3V will pass the token. W hen used in conjunction
with the Tentative ID Register, the Next ID Register can provide a complete network map. The Next ID
Register is updated each time a nod e enters/leaves the network or when a network reconfiguration occurs.
Each time the microsequencer updates the Next ID Register, a Ne w Next ID interrupt is generated. T his bit
is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or software reset.
6.2.6 Status Register
The COM20019I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6,
are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the
Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20019I 3V, the
COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these
bits exist in and are controlled by the Configuration Register. The Status Register conte nts are defined as
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in Table 4, but are defined differently during the Command Chaining operation. Please refer to the
Command Chaining section for the d efinition of the Status Register during Command Chaining operation.
The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset.
6.2.7 Diagnostic Status Register
The Diagnostic Status Register contai ns seven read-o nl y bits which hel p the user troubles hoot the network
or node operation. Various combinations of these bits and the TXEN bit of the Configuration Register
represent different situations. All of these bits, except the Excessive NAcK bit and th e New Next ID bit, are
reset to logic "0" upon reading the Diagnostic Status Register or upon software or hardware reset. The
EXCNAK bit is reset by the "POR Clear Flags" command or upon software or hardware reset. The
Diagnostic Status Register defaults to the value 0000 000X upon either h ardware or software reset.
6.2.8 Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any
combinations of written data other than thos e listed in T abl e 5 are not permi tted and may r esult in i ncorrect
chip and/or network operation.
6.2.9 Address Pointer Registers
These read/write registers are each 8- bits wide and are us ed for addressin g the internal RA M. New point er
addresses should be written by first writing to the High Register and then writing to the Low Register
because writing to the Low Register loads th e address. The contents of the Address Pointer Hig h and Low
Registers are undefined upon hardware reset. Writing to Address Pointer low loads the address.
6.2.10 Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the
COM20019I 3V. The Configuration Register defaults to the value 0001 1000 upon hardware reset only.
SUBAD0 and SUBAD1 point to the selection in Register 7.
6.2.11 Sub-Address Register
The sub-address register is new to the COM20019I 3V, previously a reserved register. Bi ts 2, 1 and 0 are
used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the
Configuration register on th e COM20020B. They are e xactly same as those in t he Sub- Address register. If
the SUBAD1 and SUBAD0 bits in the Configuration register are changed, the SUBAD1and SUBAD0 in
the Sub-Address register are also changed. SUBAD2 is a new sub-addre ss bit. It is used to access the 1
new Set Up register, SETUP2. This register is selected by setting SUBAD2=1. The SUBAD2 bit is cleared
automatically by writing the Configuratio n register.
6.2.12 Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (see the bit definitions of the Co nfiguration Reg ister). The Setup 1 Register allows the user to
change the network speed (data rate) or the arbitration speed independently, invoke the Receive All
feature and change the nPULSE1 driver type. The data rate may be slowed to 156.25Kbps and/or the
arbitration speed may be slowed by a factor of t wo. The Setup 1 Register defau lts to the value 0000 000 0
upon hardware reset only.
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6.2.13 Setup 2 Register
The Setup 2 Register is new to the COM20019I 3V. It is an 8-bit read/write register accessed when the
Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definition s of the Sub Address Register).
This register contains bits for various functions. The RBUSTMG bit is used to Disable/Enable Fast Read
function for High Speed CPU bus support. T he EF bit is used to ena ble the new timing for certain functions
in the COM20019I 3V (if EF = 0, the timing is the same as in the COM20020 Rev. B). See Appendix “A”.
The NOSYNC bit is used to enable the NOSYNC function during initialization. If this bit is reset, the line
has to be idle for the RAM initialization sequ ence to be written. If set, the line does not have to be idle for
the initialization sequence to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for
shorter time periods has the benefit of shortened n etwork reconfiguration periods. T he time periods sho wn
in the table on the follo wing page are limited by a maxim um number of nodes in the net work. These time-
out period values are for 312.5 Kbps. For other data rates, scale the time-out period time values
accordingly; the maximum node count remains the same.
RCNTM1 RCNTM0 TIME-OUT PERIOD MAX NODE
COUNT
0 0 6.72 S Up to 255 nodes
0 1 1.68 S Up to 64 nodes
1 0 840 mS Up to 32 nodes
1 1 420 mS* Up to 16 nodes
(See Note 6.1)
Note 6.1 The node ID value 255 must exist in the network for the 420 mS time-out to be valid.
Table 6.3 - Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Receiver
Inhibited RI T his bit, if high, indicates that the receiver is not enabled because
either an "Enable Receive to Page fnn " command was never
issued, or a packet has been deposited into the RAM buffer page
fnn as specified by the last "Enable Rec eive to Page fnn"
command. No messages will be received until this command is
issued, and once the message has been received, the RI bit is
set, thereby inhibiting the receiver. The RI bit is cleared by
issuing an "Enable Receive to Page fnn" command. This bit,
when set, will cause an interrupt if the corresponding bit of the
Interrupt Mask Register (IMR) is also set. When this bit is set and
another station attempts to send a packet to this station, this
station will send a NAK.
6,5 (Reserved) These bits are undefined.
4 Power On Reset POR This bit, if high, indicates that the COM20019I 3V has been reset
by either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
3 Test TEST This bit is intended for test and dia gnostic purposes. It is a logic
"0" under normal operating conditio ns.
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BIT BIT NAME SYMBOL DESCRIPTION
2 Reconfiguration RECON
This bit, if high, indicates that the Line Idle Timer has timed out
because the RXIN pin was idle for 656S. The RECON bit is
cleared during a "Clear Flags" command. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit of the Diagnostic Status Register to determine
whether there are consecutive re configurations caused by this
node.
1
Transmitter
Message
Acknowledged
TMA This bit, if high, indicates that the packet transmitted as a result of
an "Enable Transmit from Page fnn" command has been
acknowledged. This bit should onl y be considered valid after the
TA bit (bit 0) is set. Broadcast messages are never
acknowledged. The TMA bit is cleared by is suing the "Enable
Transmit from Page fnn" command.
0 Transmitter
Available TA This bit, if high, indicates that the transmitter is available for
transmitting. This bit is set when the last byte of scheduled
packet has been transmitted out, or upon execution of a "Disable
Transmitter" command. The TA bit is cleared by issuing the
"Enable Transmit from Page fnn" command after the node next
receives the token. This bit, when set, will cause an interrupt if
the corresponding bit in the IMR is also set.
Table 6.4 - Diagnostic Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 My
Reconfiguration MY-
RECON This bit, if high, indicates that a past reconfiguration was caused
by this node. It is set when the Lost Token Timer times out, and
should be typically read following an interrupt caused by RECON.
Refer to the Improved Diagnostics section for further detail.
6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node ID Register
matches both Destination ID characters of the token and a
response to this token has occurred. T railing zero's are also
verified. A logic "1" on this bit indicates a duplicate Node ID, thus
the user should write a new value into the Node ID Register. This
bit is only useful for duplicate ID detection when the device is off
line, that is, when the transmitter is disabled. When the device is
on line this bit will be set every time the devi ce gets the token.
This bit is reset automatically upon reading the Diagnostic Status
Register. Refer to the Improved Diagnostics section for further
detail.
5 Receive
Activity RCVACT T his bit, if high, indicates that data activity (logic "1") was
detected on the RXIN pin of the device. Refer to the Improved
Diagnostics section for further detail.
4 Token Seen TOKEN
This bit, if high, indicates that a token has be en seen on the
network, sent by a node other than this one. Refer to the
Improved Diagnostic section for further detail.
3 Excessive NAK EXCNAK
This bit, if high, indicates that either 128 or 4 Negative
Acknowledgements have occu rred in response to the Free Buffer
Enquiry. This bit is cleared upon the "POR Clear Flags"
command. Reading the Diagnostic Status Register does not
clear this bit. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set. Refer to the Improved
Diagnostics section for further detail.
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BIT BIT NAME SYMBOL DESCRIPTION
2 Tentative ID TENTID
This bit, if high, indicates that a response to a token whose DID
matches the value in the Tentative ID Register has occurred.
The second DID and the trailing zero's are not checked. Since
each node sees ever y token p assed around the network, this
feature can be used with the device o n-lin e in order to build and
update a network map. Refer to the Improved Diagnostics
section for further detail.
1 New Next ID NEW
NXTID This bit, if high, indicates that the Next ID Register has been
updated and that a node has either joined or left the network.
Reading the Diagnostic Status Register d oes not clear this bit.
This bit, when set, will cause an interrupt if the correspon ding bit
in the IMR is also set. The bit is cleared by reading the Next ID
Register.
0 (Reserved) This bi t is undefined.
Table 6.5 - Command Register
DATA COMMAND DESCRIPTION
0000 0000 Clear
Transmit
Interrupt
This command is used only in the Command Chaining
operation. Please refer to the Command Chaining section for
definition of this command.
0000 0001 Disable
Transmitter This command will cancel any pending transmit command
(transmission that has not yet started) and will set the T A
(Transmitter Available) status bit to logic "1" when th e
COM20019I 3V next receives the token.
0000 0010 Disable
Receiver This command will cancel any pending receive command. If the
COM20019I 3V is not yet receiving a packet, the RI (Receiver
Inhibited) bit will be set to logic "1" the ne xt time the token is
received. If packet reception is already underway, reception will
run to its normal conclusion.
b0fn n100 Enable
Receive to
Page fnn
This command allows the COM20019I 3V to receive data
packets into RAM buffer page fnn and resets the RI status bit to
logic "0". The values placed in the "nn" bits indicate the page
that the data will be received into (page 0, 1, 2, or 3). If the
value of "f" is a logic "1", an offset of 256 bytes will be added to
that page specified in "nn", al lowing a finer resolution of the
buffer. Refer to the Selecting RAM Page Size section for further
detail. If the value of "b" is logic "1", the device will also receive
broadcasts (transmissions to ID zero). The RI status bit is set to
logic "1" upon successful receptio n of a message.
00fn n011 Enable
Transmit from
Page fnn
This command prepares the COM20019I 3V to begin a transmit
sequence from RAM buffer page fnn the next time it receives
the token. The values of the "nn" bits indicate which page to
transmit from (0, 1, 2, or 3). If "f" is logic "1", an offset of 256
bytes is the start of the page specified in "nn", allowing a finer
resolution of the buffer. Refer to the Selecting RAM Page Size
section for further detail. When this command is loaded, the TA
and TMA bits are reset to logic "0". The TA bit is set to logic "1"
upon completion of the transmit sequence. The TMA bit will
have been set by this time if the device has receive d an AC K
from the destination node. The ACK is strictly hardware level,
sent by the receiving node before its microcontroller is even
aware of message reception. Refer to Figure 1 for details of the
transmit sequence and its relation to the TA and T M A status
bits.
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DATA COMMAND DESCRIPTION
0000 c101 Define
Configuration This command defines the maximum length of packets that may
be handled by the device. If "c" is a logic "1", the device
handles both long and short packets. If "c" is a logic "0", the
device handles only short packets.
000r p110 Clear Flags This command resets certain status bits of the COM20019I 3V.
A logic "1" on "p" resets the POR status bit and the E XCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON
status bit.
0000 1000 Clear
Receive
Interrupt
This command is used only in the Command Chaining
operation. Please refer to the Command Chaining section for
definition of this command.
Table 6.6 - Address Pointer High Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Data RDDATA
This bit tells the COM20019I 3V whether the follo wing
access will be a read or write. A logic "1" pr epares the
device for a read, a logic "0" prepares it for a write.
6 Auto Increment AUTOINC
This bit controls whether the address pointer will
increment automatically. A logic "1" on this bit allows
automatic increment of the pointer after each access,
while a logic "0" disables this function. Please refer to the
Sequential Access Memory section for further detail.
5-3 (Reserve d) These bits are undefined. They must be 0.
2-0 Address 10-8 A10-A8 These bits hold the upper three address bits which
provide addresses to RAM.
Table 6.7 - Address Pointer Low Register
BIT BIT NAME SYMBOL DESCRIPTION
7-0 Address 7-0 A7-A0
These bits hold the lo wer 8 address bits which provide the
addresses to RAM.
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Table 6 .8 - Sub Address Register
BIT BIT NAME SYMBOL DESCRIPTION
7-3 Reserved These bits are undefined. T hey must be 0.
2,1,0 Sub Address 2,1,0 SUBAD
2,1,0
These bits determine which register at ad dress 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0 0 0 Tentative ID \ (Same
0 0 1 Node ID \ as in
0 1 0 Setup 1 / Config
0 1 1 Next ID / Register)
1 0 0 Setup 2
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Re gister.
Table 6.9 - Configuration Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Reset RESET
A software reset of the COM20019I 3V is executed by
writing a logic "1" to this bit. A software reset does not reset
the microcontroller interface mode, nor does it affect the
Configuration Register. T he only registers that the software
reset affect are the Status Register, the Next ID Register,
and the Diagnostic Status Register. This bit must be
brought back to logic "0" to release the reset .
6 Command
Chaining Enable CCHEN
This bit, if high, enables the Command Cha in ing operation
of the device. Please refer to the Command Chaining
section for further details. A low level on this bit ensures
software compatibility with previous SMSC ARCNET
devices.
5 Transmit Enable TXEN When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, an d nTXEN
pin inactive. When high, it enables the ab ove signals to be
activated during transmissions. This bit defaults lo w upon
reset. This bit is typically enabled once the Node ID is
determined, and never disabled duri ng normal operation.
Please refer to the Improved Diagnostics section for details
on evaluating network activit y.
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BIT BIT NAME SYMBOL DESCRIPTION
4,3 Extended
Timeout 1,2 ET1, ET2 These bits allow the network to operate over longer
distances than the default maximum 32 miles by controlling
the Response, Idle, and Reconfiguration Times. All nodes
should be configured with the same timeout values for
proper network operation. For the COM20019I 3V with a 20
MHz crystal oscillator, the bit combinations follo w:
ET2
0
0
1
1
ET1
0
1
0
1
Response
Time (mS)
9.548
4.774
2.387
0.597
Idle Time
(mS)
10.496
5.248
2.624
0.656
Reconfig
Time (S)
13.44
13.44
13.44
6.72
Note: These values are for 312.5 Kbps and
RCNTMR[1,0]=00. Reconfiguration time is chan ged by the
RCNTMR1 and RCNTMR0 bits.
2 Backplane BACK-
PLANE
A logic "1" on this bit puts the device into Backplane Mode
signaling which is used for Open Drain and Differential
Driver interfaces. This bit must be set to ‘1’ at the
COM20019I 3V.
1,0 Sub Address 1,0 SUBAD
1,0
These bits determine which register at ad dress 07 may be
accessed. The combinations are as follows:
SUBAD1 SUBAD0 Register
0 0 Tentative I
0 1 Node ID
1 0 Setup 1
1 1 Next ID
See also the Sub Address Register.
Table 6.10 - Setup 1 Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Pulse1 Mode P1MODE
This bit determines the type of PULSE1 output driver used
in Backplane Mode. When high, a push/pu ll output is
used. When low, an open drain output is use d. T he
default is open drain.
6 Four NACKS FOUR
NACKS This bit, when set, will cause the EXNACK bit in the
Diagnostic Status Register to set after four NACKs to Free
Buffer Enquiry are detected by the COM20019I 3V. This
bit, when reset, will set the EXNACK bit after 128 NACKs
to Free Buffer Enquiry. The default is 128.
5 Reserved Do not set. It must be 0.
4 Receive All RCVALL This bit, when set, allows the COM20019I 3V to receive all
valid data packets on the network, regardless of their
destination ID. This mode can be used to implement a
network monitor with the transmitter on- or off-line. Note
that ACKs are only sent for packets received with a
destination ID equal to the COM2001 9I 3V's programmed
node ID. This feature can be used to put the COM2001 9I
3V in a 'listen-only' mode, where the transmitter is
disabled and the COM20019I 3V is not passing tokens.
Defaults low.
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BIT BIT NAME SYMBOL DESCRIPTION
3,2,1 Clock Prescaler
Bits 3,2,1 CKP3,2,1 These bits are used to determine the data rate of the
COM20019I 3V. The following table is for a 20 MHz
crystal:
CKP3
0
1
CKP2
1
0
CKP1
1
0
DIVISOR
64
128
SPEED
312.5 Kbs
156.25 Kbs
Note: The lowest data rate achievable by the COM20019I
3V is 156.25 Kbs. Defaults to 011 or 312.5 Kbps.
0 Slow Arbitration
Select SLOWARB This bit, when set, will divide the arbitration clock by 2.
Memory cycle times will increase when slo w arbitration is
selected.
Defaults to low.
Table 6.11 - Setup 2 Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Bus Timing
Select RBUSTMG This bit is used to Disable/Enable the High Speed CPU
Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable.
That is, if BUSTMG (pin 26: Only for TQFP package) = 1
and RBUSTMG = 1, High Speed CPU Read operations are
enabled.
It does not influence write operation. High speed CPU
Read operation is onl y for non-multiplexed bus.
6,5,4 Reserved These bits are undefined. They must be 0.
3 Enhanced
Functions EF This bit is used to enable the new enhanced functions in the
COM20019I 3V. EF = 0: Disable (Default), EF = 1: Enable.
If EF = 0, the timing and function is the same as in the
COM20020, Revision B. See appendix “A”. EF bit must be
‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
2 No Synchronous NOSYNC
This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Defau lt) The line must
be idle for the RAM initialization sequenc e to be written.
NOSYNC= 1, Disable:) The line does not ha ve to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
1,0 Reconfiguration
Timer 1, 0 RCNTM1,0 These bits are used to program the reconfiguration timer as
a function of maximum node count. T hese bits set the time
out period of the reconfiguration timer as shown below. The
time out periods shown are for 312.5 Kbps.
RCNTM1 RCNTM0 Time Out
Period Max Node Count
0 0 6.72 S Up to 255 nod es
0 1 1.68 S Up to 64 nodes
1 0 840 mS Up to 32 nodes
1 1 420 mS* Up to 16 nodes
Note*: The node ID value 255 must exist in the network for
420 mS timeout to be valid.
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Address P ointer R egister
Low
2K x 8
RAM
11
Data Register
8
I/O Address 04H
I/O A ddress 03H
11-Bit Counter
Memory
Address Bus
Memory
D ata B us
D0-D7
High
I/O Address 02H
INTERNAL
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Figure 6.1 - SEQUENTIAL ACCESS OPERATION
6.3 INTERNAL RAM
The integration of the 2K x 8 RAM in the COM20019I 3V represents significant real estate savings. The
most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the
integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external
latch, and multiplexed address/data bus and control functions which were necessary to interface to the
RAM. The integration of RAM represents significant cost savings because it isolates the s ystem designer
from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs,
and layout complexity.
6.3.1 Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory,
the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is
channeled to and from the microcontroll er via the 8-bit data register. For example: a packet in the internal
RAM buffer is read by the microcontroller by writing the corresponding address into the Address Pointer
High and Low Registers (offsets 02H and 03H). Note that the High Register should be written first,
followed by the Low Register, because writing to the Low Register loads the address. At this point the
device accesses that location and places the corresponding data into the data register. The
microcontroller then reads the data register ( offset 04H) to obtain the data at the specified location. If the
Auto Increment bit is set to logic "1", the device will automatically increment the address and place the
next byte of data into the data register, aga in to be read by the microc ontroller. This process is continued
until the entire packet is read out of RAM. Refer to Figure 7 for an illustration of the Sequential Access
operation. When switching between reads and writes, the pointer must first be written with the starting
address. At least one cycle time should separate the pointer being loaded and the first read (see timing
parameters).
6.3.2 Access Speed
The COM20019I 3V is able to accommodate very fast access cycles to its registers and buffers. Arbitration
to the buffer does not slow down the cycle because the pointer based access method allows data to be
prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the
temporary register and then written to memory.
For systems which do not require quick access time, the arbitration clock ma y b e slowed down by setting
bit 0 of the Setup1 Register equal t o logic "1". Since the S lo w Arbitration f eature divides t he input cl ock b y
two, the duty cycle of the input clock may be relaxed.
6.4 SOFTWARE INTERFACE
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The microcontroller interfaces to the COM20019I 3V via software by accessing the various registers.
These actions are described in the Internal Registers section. The software flow for accessing the data
buffer is based on the Sequential Access scheme. T he basic sequence is as follows:
Disable Interrupts
Write to Pointer Register High (specifying Auto-Increment mode)
Write to Pointer Register Low (this loads the address)
Enable Interrupts
Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
The pointer may now be read to determine how many transfers were completed.
The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is
generally limited to the initializ ation sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the
transmit and receive sequences and to know how the internal RAM buffer is properly set up. The
sequence of events that tie these actions together is discussed as follows.
6.4.1 Selecting RAM Page Size
During normal oper ation, the 2K x 8 of RAM is divided into four pa ges of 512 bytes each. The page to be
used is specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies
page 0, 1, 2, or 3. This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set
to logic "1", an offset of 256 bytes is added to the page specified. F or e xample: to transmit from the second
half of page 0, the command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing
0010 0011 to the Command Register. This allows a finer resolution of the buffer pages without affecting
software compatibility. This scheme is useful for applications which frequently use packet sizes of 256
bytes or less, especially for microcontroller s ystems with limited memor y capacit y. The remaining p ortions
of the buffer pages which are not allocated for current transmit or receive packets may be used as
temporary storage for previou s network data, packets to be sent later, or as extra memo ry for the system,
which may be indirectly accessed.
If the device is configured to handle both long and short packets (see "Define Configuration" command),
then receive pages should al ways be 512 b ytes long because the user n ever knows what the length of the
receive packet will be. In this case, the transmit pages may be made 256 bytes long, leaving at least 512
bytes free at any given time. Even if the Command Chaining operation is being used,
512 bytes is still guaranteed to be free because Command Chaining only requires two pages for transmit
and two for receive (in this case, two 256 byte pages for transmit and two 512 byte pages for receive,
leaving 512 bytes free). Please note that it is the responsibility of software to reserve 512 bytes for each
receive page if the dev ice is configured to handle lo ng packets. T he COM20019I 3V doe s not check pag e
boundaries during reception. If the device is configured to handle only short packets, then both transmit
and receive pages may be allocated as 256 bytes long, freeing at least 1KB yte at any given time.
Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because
Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four
256 byte pages, leaving 1K free).
The general rule which may be applied to determine where in RAM a pa ge begins is as follows:
Address = (nn x 512) + (f x 256).
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Figure 6.2 - RAM BUFFER PACKET CONFIGURATION
6.4.2 Transmit Sequence
During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and
writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long
packets are enabled, the COM20019I 3V interprets the packet as either a long or sh ort packet, depending
on whether the buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in
Figure 8. Address 0 contains the Source Identifier (SID); Address 1 contains the Destination Identifier
(DID); Address 2 (COUNT) contains, for short packets, the value 256-N, where N represents the number
of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long
packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the
number of information bytes in the message. The SID in Address 0 is used by the receiving node to reply to
the transmitting node. The COM20019I 3V puts the local ID in this location, therefore it is not necessary to
write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a
long packet may contain between 257 and 508 data bytes. A minimum value of 257 exists on a long
packet so that the COUNT is expressible in eight bits. This leaves three exception packet lengths which
do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of these
SID
DID
COUNT = 256-N
NO T US ED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
D ATA BYTE N
NOT USED
SID
DID
0
COUNT = 512-N
NOT USED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
SHORT PACKET
FORMAT LONG PACKET
FORMAT
A
DDRESS ADDRESS
0
1
2
COUNT
255
511
N = D ATA PACK ET LENG TH
SID = SOURCE ID
DID = DESTIN ATION I D
(DID = 0 FOR BRO ADCASTS)
0
1
2
COUNT
511
3
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lengths must be sent, the user must add d ummy bytes to the packet in order to make the packet fit into a
long packet.
Once the pack et is writt en int o the buff er, the micro contro ller a waits a lo gic "1" on t he T A bit, indicat ing t hat a
previous transmit command has concluded and another may be issued. Each time the message is loaded
and a transmit command issued, it will take a variable amount of time before the message is transmitted,
depending on the traffic on the network and the location of the token at the time the transmit command was
issued. The c onclu sion of t he Transm it Comma nd will gener ate an interrupt if the Interrupt Mask allows it. If
the device is conf igu red for the Command Chaining operation, please see the Command Chaining se ction for
further detail on the transmit sequence. Once the TA bit becomes a logic "1", the microcontroller may issue
the "Enable Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the
message is not a BROADCAST, the COM20019I 3V automatically sends a FREE BUFFER ENQUIRY to the
destination node in order to send the message. At this point, one of four possibilities may occur.
The first possibility is if a free buffer is available at the destination node, in which case it responds with an
ACKnowledgement. At this point, the COM20019I 3V fetches the data from the Transmit Buffer and performs
the transmit sequence. If a successful transmit sequence is completed, the TMA bit and the TA bit are set to
logic "1". If the packet was not transmitted successfully, TMA will not be set. A successful transmission
occurs when the receiving node responds to the packet with an ACK. An unsuccessful transmission occurs
when the receiving node does not re sp ond to the pa cket.
The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative
AcKnowledgement. A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the
token is passed on from the transmitting node to the next node. The next time the transmitter receives the
token, it will again transmit a FREE BUFFER ENQUIRY. If a NAK is again received, the token is again
passed onto t he next node. The Excessive NAK bit of the Diagnos tic Status Register is us ed to prevent an
endless sending of FBE's and NAK's. If no limit of FBE-NAK sequences existed, the transmitting node would
continue issuing a Free Buffer Enquiry, even th ough it would continuo usly receive a NAK as a response . The
EXCNAK bit gen era tes an i nterrup t (if enabled) in o rde r to tell the microcontroller to disable the transmitter via
the "Disable Transmitter" command. This causes the transmission to be abandoned and the TA bit to be set
to a logic "1" when the node next receives the token, while the TMA bit remains at a logic "0". Please refer to
the Improved Diagnosti cs section for further detail on the EXCNAK bit.
The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node
does not resp ond at all. I n this case, the TA bit is set to a logi c "1", while t he TMA bit r emains at a logic "0".
The user should de termine w hethe r the node should try to reissue the transmit command.
The fourth possibil ity is if a non-tradit ional res ponse is r eceived (som e pattern other tha n ACK or NAK, such
as noise). In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the
next node to time out, thus generating a network reconfiguration.
The "Disable Transmitter" command may be used to cancel any pending transmit command when the
COM20019I 3V next receives the token. Normally, in an active network, this command will set the TA status
bit to a lo gic "1" when th e token is rece ived. If the "Dis able Tran smitter" c ommand d oes not cause t he TA bit
to be set in the time it takes the token to make a round trip through the network, one of three situations exists.
Either the node is disconnected from the network, or there are no other nodes on the network, or the external
receive circuitry has failed. These situations can be determined by either using the improved diagnostic
features of the COM20019I 3V or using another software timeout which is greater than the worst case time
for a round trip token pa ss, which occu rs when all nodes tran smi t a maximu m leng th message .
6.4.3 Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous
reception has concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt
Mask Register is set to logic "1". Otherwise, the microcontroller must periodically check the Status
Register. Once the microcon troller is alerted to the fact that the previous reception has concluded, it may
issue the "Enable Receive to Page fnn" command, which resets the RI bit to logic "0" and selects a new
page in the RAM buffer. Again, the appropriate buffer size is specified in the "Define Configuration"
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command. Typically, the page which just received the data packet will be read by the microcontroller at
this point. Once the "Enable Receive to Page fnn" command is issued, the microcontrolle r attends to other
duties. There is no way of knowing ho w long the ne w reception will take, since another node ma y transmit
a packet at any time. When another node does transmit a packet to this node, and if the "Define
Configuration" command has enabled the reception of long packets, the COM20019I 3V interprets the
packet as either a long or short packet, depending on whether the content of the buffer location 2 is zero or
non-zero. The format of the buffer is shown in Figure 9. Address 0 contains the Source Identifier (SID),
Address 1 contains the Destination Identifier (DID), and Address 2 contains, for short packets, the value
256-N, where N repr esents t he mess age le ngth, or for lon g packets, the value 0, i ndic ating that it is ind eed
a long packet. In the latter case, Address 3 contains the value 512-N, where N represents the message
length. Note that on reception, the COM20019I 3V deposits packets into the RAM buffer in the same
format that the transmitting node arranges them, which allows for a message to be received and then
retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the
packet is received and stored correctly in the selected buffer, the COM20019I 3V sets the RI bit to logic "1"
to signal the microcontroller that the reception is compl ete.
Figu re 6.3 - COMMAND CHAINING STATUS REGISTER QUEUE
6.5 COMMAND CHAINING
The Command Chaining oper ation allows consecutive transmissions and r eceptions to occur without host
microcontroller intervention.
Through the use of a dual t wo-level FIF O, commands to be transmitted and received, as well as the status
bits, are pipelined.
In order for the COM20019I 3V to be compatible with previous SMSC AR CNET device drivers, the device
defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the
Command Chaining Mode must be enabled via a logic "1" on bit 6 of the Configuration Register.
In Command Chaining, the Status Register appears as in Figure 6.3.
The following is a list of Com mand Chaini ng guidelines for the soft ware programmer. Further deta il can be
found in the Transmit Command Chaining and Receive Command Chai ning sections.
The device is designed such that the interrupt service routine latency does not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given
time. The commands may be given in any order.
Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the
device, along with their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Availabl e) for transmit
operations and TRI (Rising T ransition of Receiver Inhibited) for receive operations. TTA is set upon
completion of a packet transmission only. TRI is set upon completion of a p acket reception only.
Typically there is no need to mask the TTA and TRI bits after clearing the interrupt.
TRI RI TA POR TEST RECON
TMA TTA
TMA TTA
TRI
MSB LSB
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The traditional TA and RI bits are still available to reflect the present status of the device.
6.5.1 Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20019I 3V
responds in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the
specified page. The T A bit can be used to see if there is currently a transmission pending, but the TA bit is
really meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for
the device in the Command Chaining mode.
In the Command Chaining Mode, at an y time after the first command is issued, the proc essor can issue a
second "Enable Transmit from Page fnn" command. The COM20019I 3V stores the fact that the second
transmit command was issued, along with the page number.
After the first transmission is completed, the COM20019I 3V updates the Status Register by setting the
TTA bit, which generates an interrupt. The interrupt service routine should read the Status Register. At
this point, the TTA bit will be found to be a logic "1" a nd the T MA (Transmit Message A ckno wledge) bit will
tell the processor whether the transmission was successful. After reading the Status Register, the "Clear
Transmit Interrupt" command is issued, thus resetting the TTA bit and clearing the interrupt. Note that
only the "Clear T ransmit Interrupt" command will clear the TTA bit and the interrupt. It is not necessary,
however, to clear the bit or the interrupt right away because the status of the transmit operati on is double
buffered in order to retain the results of the first transmission for analysis by the processor. This
information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note
that the interrupt will remain active until the command is issued, and the second interrupt will not occur
until the first interrupt is acknowledged. The COM20019I 3V guarantees a minimum of 200nS (at EF=1)
interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether
the appropriate transmission was a success. The TMA bit should only be considered valid after the
corresponding TTA bit has been set to a logic "1". The TMA bit never causes an interrupt.
When the token is received again, the second transmission will be automatically initiated after the first is
completed by using the stored "Enable Transmit from Page fnn" command. The operation is as if a new
"Enable Transmit from Page fnn" command has just been issued. After the first Transmit status bits are
cleared, the Status Register will again be updated with the results of the second transmission and a
second interrupt resulting from the second transmission will occur. The COM20019I 3V guarantees a
minimum of 200ns (at EF=1) interrupt inactive time interval before the following edge.
The Transmitter Available (TA) bit of the Interrupt Mask Register no w masks only the TTA bit of the Status
Register, not the TA bit as in the non-chai ning mode. Since the TT A bit is only set upon transmission o f a
packet (not by RESET), and since the TTA bit ma y easily be reset by issuing a "Clear Transmit Interrupt "
command, there is no need to use the TA bit of the Interrupt Mask Register to mask interrupts generated
by the TTA bit of the Status Register.
In Command Chaining mode, the "Disable T ransmitter" command will cancel the oldest transmissi on. This
permits canceling a packet destined for a no de not ready to receive. If both packets should be canceled,
two "Disable Transmitter" comm ands should be issued.
6.5.2 Receive Command Chaining
Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable
Receive from Page fnn" commands.
After the first packet is received into the first specified page, the TRI bit of the Status Register will be set to
logic "1", causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the
interrupt service routine will read the Status Register. At this point, the RI bit will be found to be a logic "1".
After reading the Status Register, the "Clear Receiv e Interrupt" command should be issu ed, thus resetting
the TRI bit and clearing the interrupt. Note that onl y the "Clear Receive Interrupt" command will clear the
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TRI bit and the interrupt. It is not necessary, ho wever, to clear the bit or the interrupt right away because
the status of the receive operation is double buffered in order to retain the results of the first reception for
analysis by the processor, therefore the information will remain in the Status Register until the "Clear
Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive
Interrupt" command is issued, and the second interrupt will be stored until the first interrupt is
acknowledged. A minimum of 200nS (at EF=1) interrupt inactive time interval between interrupts is
guaranteed.
The second reception will occur as soon as a second packet is sent to the node, as long as the second
"Enable Receive to Page fnn" command was issued. The operation is as if a new "Enable Receive to
Page fnn" command has just been issued. After the first Receive status bits are cleared, the Status
Register will again be updated with the results of the second reception and a second interrupt resulting
from the second reception will occur.
In the COM20019I 3V, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI
bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon
reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a "Clear
Receive Interrupt" command, there is no need to use the RI bit of the Interrupt Mask Register to mask
interrupts generated by the TRI bit of the Status Register. In Command Chaining mode, the "Disable
Receiver" command will cancel the oldest reception, unless the reception has already begun. If both
receptions should be canceled, two "Disable Receiver" commands shoul d be issued.
6.6 RESET DETAILS
6.6.1 Internal Reset Logic
The COM20019I 3V includes special reset circuitry to guarantee smooth operation during reset. Special
care is taken to assure proper operation in a variety of systems and modes of operation. The COM20019I
3V contains digital filter circuitr y and a Schmitt Trigger on the nRESET signal to reject glitches in order to
ensure fault-free operation.
The COM20019I 3V supports two reset options; software and hardware reset. A software reset is
generated when a logic "1" is written to bit 7 of the Configuration Register. The device remains in reset a s
long as this bit is set. The software reset does not affect the microcontroller interface modes determined
after hardware reset, nor does it affect the contents of the Address Pointer Registers, the Configuration
Register, or the Setup1 Register. A hardware reset occurs when a low signal is asserted on the nRESET
input. The minimum reset pulse width is 5TXTL. This pulse width is used by the internal digital filter, which
filters short glitches to allow only valid resets to occur.
Upon reset, the transmitter portion of the device is disab led and the intern al registers assume those states
outlined in the Internal Registers section. After the nRESET signal is removed the user may write to the
internal registers. Since writing a non-zero value to the Node ID Register wakes up the COM20019I 3V
core, the Setup1 Register should be written before the Node ID Register. Once the Node ID Register is
written to, the COM20019I 3V reads the value and exec utes t wo write cycles to the RAM buffer. Address 0
is written with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen
arbitrarily, and is meant to provide assurance of proper microsequencer operation.
6.7 INITIALIZATION SEQUENCE
6.7.1 Bus Determination
Writing to and reading from an odd address location from the COM20019I 3V's address space causes the
COM20019I 3V to determine the appropriate bus interface. When the COM20019I 3V is powered on the
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internal registers may be written to. Since writing a non-zero value to the Node ID Register wakes up the
core, the Setup1 Register should be written to before the Node ID Register. Until a non-zero value is
placed into the NID Register, no microcode is executed, no tokens are passed by this node, and no
reconfigurations are generated by this node. Once a non-zero value is placed in the register, the core
wakes up, but the node will not attempt to join the network until the TX Enable bit of the Configuration
Register is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first
observe the Receive Activity and the Token Seen bits of the Diag nostic Stat us Register to verif y the health
of the receiver and the network.
Next, the uniqueness of the Node ID value placed in the Node ID Regis ter is determined. The TX Enable
bit should still be a logic "0" until it is ensured that the Nod e ID is unique. If this node ID alrea dy exists, the
Duplicate ID bit of the Diagnostic Status Register is set after a maximum of 6.72S (or 13.44S if the ET1
and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the
COM20019I 3V compares the value in the Node ID Register with the DID's of the token, and determines
whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared.
The user may then attempt a new ID value, wait 6.72S before checking the Duplicate ID bit, and repeat the
process until a unique Node ID is found. At this point, the T X Enable bit may be set to allow the node to
join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the
MYRECON bit of the Diagnostic Status Register.
The Tentative ID Register may be used to build a net work map of all the nodes on the network, even on ce
the COM20019I 3V has joined the network. Once a value is placed in the Tentative ID Register, the
COM20019I 3V looks for a response to a token whose DID matches the Tentative ID Register. The
software can record this inform ation and continue placing T entative ID values into the register to continue
building the net work map. A complete network map is only valid until nodes are added to or deleted from
the network. Note that a node cannot detect the existence of the next logical node on the network when
using the Tentative ID. To determine the ne xt logical node, the software should read the Next ID Register.
6.8 IMPROVED DIAGNOSTICS
The COM20019I 3V allows the user to better manag e the operation of the network through the use of the
internal Diagnostic Status Register.
A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this
node expired, causing a rec onfigurati on by this node. After the Reconfiguration (RE CON) bit of the Status
Register interrupts the microcontroller , the interrupt service routine will t ypically read the MYRECON bit of
the Diagnostic Status Register. Reading the Diagnostic Status Register resets the MYRECON bit.
Successive occurrences of a logic "1" o n the MYRECON bi t indic ates that a prob lem exis ts with this nod e.
At that point, the transmitter should be disabled so that the entire n et work is not held do wn while the nod e
is being evaluated.
The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with
the same ID does not exist on the network. Once it is determined that the ID in the Node ID Register is
unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic
transmit function. This allows the node to join the network.
The Receive Activity (RCVACT) bit of the Diagnostic Status Register will be set to a logic "1" whenever
activity (logic "1") is detected on the RXIN pin.
The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network
(except those tokens transmitted by this node).
The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual
events are occurring on the network, the user may find it valuable to use the T XEN bit of the Configuration
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Register to qualify events. Different combinations of the RCVACT, TOKEN, and TXEN bits, as shown
indicate different situations:
6.8.1 Normal Results:
RCVACT=1, TOKEN=1, TXEN=0: The nod e is not part of the net work. The network is operating pr operly
without this node.
RCVACT=1, TOKEN=1, TXEN=1: The node sees rece ive activity and sees the token. T he basic transmit
function is enabled. Network and node are operating properly.
MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node network.
6.8.2 Abnormal Results:
RCVACT=1, TOKEN=0, TXEN=X: The node sees receive activity, but does not see the token. Either no
other nodes exist on the network, some type of data corruption exists, the media driver is malfunctioning,
the topology is set up incorrectly, there is noise on the network, or a reconf iguration is occurring.
RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled.
The transmitter and/or receiver are not functioning properly.
RCVACT=0, TOKEN=0, TXEN=0: No receive activity and basic transmit function disabled. This node is
not connected to the net work.
The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in
software. This function is necessar y to limit the number of times a sender issues a F BE to a node with no
available buffer. When the destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs,
the EXCNAK bit of the sender is set, generating an interrupt. At this point the software may abandon the
transmission via the "Disable T ransmitter" command. This sets the TA bit to logic "1" wh en the node next
receives the token, to allow a different transmission to occur. The timeout value for the EXNACK bit (128
or 4) is determined by the FOUR-NAKS bit on the Setup1 Register.
The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the
wraparound counter of the EXCNAK bit. W hen the EXCNAK bit goes high, indicating 128 or 4 NAKs, the
"POR Clear Flags" command maybe issued to reset the bit so that it will go high again after another
count of 128 or 4. The software may count the number of times the EXCNAK bit goes high, and once the
final count is reached, the "Disable Transmitter" command may be issued.
The New Next ID bit permits the software to detect the withdrawal or addition of nodes to the network.
The Tentative ID bit allo ws the user to build a net work map of those nodes existing on the net work. This
feature is useful because it minimizes the need for human intervention. When a value placed in the
Tentative ID Register matches the Node ID of another node on the net work, the TENTID bit is set, telling
the software that this NODE ID already exists on the network. The software should periodically place
values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated network map.
6.9 OSCILLATOR
The COM20019I 3V contains circuitry which, in conjunction with an external parallel resonant crystal or
TTL clock, forms an oscillator.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 46 SMSC COM20019I 3.3V Rev.C
DATASHEET
If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No
external resistor is required, sinc e the COM20019I 3V contains an internal resistor. The crystal must have
an accuracy of 0.020% or better. The oscillation frequency range is from 10 MHz to 20 MHz.
The crystal must have an acc uracy of 0. 010% or b etter when the inter nal clock multipli er is turned o n. T he
oscillation frequency must be 20MHz when the internal clock multiplier is turned on.
The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock
for other devices.
The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a
390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left uncon nected.
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SMSC COM20019I 3.3V Page 47 Rev. 11-07-08
DATASHEET
Chapter 7 Operational Description
7.1 MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range..................................................................................................0oC to +70oC
Storage Temperature Range ................................................................................................-55oC to +150oC
Lead Temperature (soldering, 10 seconds) .......................................................................................+325 oC
Positive Voltage on any pin except XTAL1 and X T AL2, with respect to ground ................................... +5.5V
Positive Voltage on XTAL1 and XTAL2 pin, with respect to ground ................................................ VDD+0.3V
Negative Voltage on any pin, with respect to ground............................................................................. -0.3V
Maximum VDD ..........................................................................................................................................+5V
* Stresses above those listed may cause permane nt damage to the device. This is a stress rating o nly and
functional operation of the device at these or any other condition above those indicated in the operatio nal
sections of this specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes or "glitches" on their outputs when the AC power is switched on or off. In addition, voltage
transients on the AC power line may appear on the DC output. If this possibilit y exists it is suggested that
a clamp circuit be used.
7.2 DC ELECTRICAL CHARACTERISTI CS
VDD=3.3V±5%
TA=-40oC to +85oC
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Input Voltage 1
(All inputs except XTAL1)
High Input Voltage 1
(All inputs except XTAL1)
VIL1
VIH1
-0.3
2.0
0.8
5.5
V
V
TTL Level
Low Input Voltage 2
(XTAL1)
High Input Voltage 2
(XTAL1)
VIL2
VIH2
-0.3
0.8xVDD
0.2xVDD
VDD+0.3
V
V
External Clock Input
Low Output Voltage 1
(nTXEN)
High Output Voltage 1
(nTXEN)
VOL1
VOH1
2.4
0.4
V
V
ISINK=4mA
ISOURCE=-2mA
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DATASHEET
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Output Voltage 2
(AD0-AD2, D3-D7, nINTR,
nPULSE1 in Push/Pull
Mode, nPULSE2)
High Output Voltage 2
(AD0-AD2, D3-D7, nINTR,
nPULSE1 in Push/Pull
Mode, nPULSE2)
VOL2
VOH2
2.4
0.4 V
V
ISINK=8mA
ISOURCE=-4mA
Low Output Voltage 3
(nPULS E1 in Open-Drain
Mode)
VOL3 0.4 V ISINK=8mA
Open Drain Driver
Dynamic VDD Supply
Current IDD
25
mA
312.5 Kbps
All Outputs Open
Input Pull-up Current
(nPULSE1 in Open-Drain
Mode, A1, AD0-AD2,
D3-D7, BUSTMG)
Input Leakage Current
(All inputs except A1,
AD0-AD2, D3-D7,
XTAL1, BUSTMG)
IP
IL
80 200
±10
µA
µA
VIN=0 .0V
VSS < VIN < VDD
CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V)
Output and I/O pins capacitive load specified as follows:
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Input Capacitance CIN 5.0 pF
Output Capacitance 1
(All outputs except
XTAL2)
COUT1
45
pF
Maximum
Capacitive Load
which can be
supported by ea ch
output.
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SMSC COM20019I 3.3V Page 49 Rev. 11-07-08
DATASHEET
Figure 7.1 - AC MEASUREMENTS
0.4V
AC Mea sureme nts are take n at the foll owing poi nts:
Inputs:
2.4V
1.4V 50%
50%
0.4V
2.4V
1.4V
0.8V
Outputs:
2.0V
0.8V
2.0V
Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin.
Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".
t
t
t
t
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DATASHEET
Chapter 8 Timing Diagrams
Figure 8.1 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
A
D0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
DIR t9 t10
nDS
t11
t12
t13 t14
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
nDS High to Data High Impedance
Cycle Time (nDS Low to Next Ti me Low)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
20
10
10
10
15
0
4TARB*
10
10
20
20
60
20
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: RBUSTMG bit = 0
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLO W ARB = 1
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time sp ecified i n the micr ocon troller' s datashee t
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
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DATASHEET
Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
A
D0-AD2, VALID
nCS
t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
nRD t9
t10
nWR t13 t11 t12
Note 3
Note 2
MUST BE: RBUSTMG bit = 0
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hol d fro m ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
nRD High to Data High Impedance
Cycle Time (nRD Low to Next Time Low)
20
10
10
10
15
0
4TARB*
40
20
nS
nS
nS
nS
nS
nS
nS
20
20
60
20
20
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
nWR to nRD Low
t8
t9
t10
t11
t12
t13
nS
nS
nS
nS
nS
nS
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 52 SMSC COM20019I 3.3V Rev.C
DATASHEET
Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
A
D0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
DIR
t9 t10
Note 2
t8**
nDS
t11
t12
t13 t14
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
20
10
10
10
15
10
4TARB*
10
10
20
20
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
DIR Setup to nDS Active
DIR Hold from nDS Inactive
30
ALE High Width
ALE Low Width
nDS Low Width
nDS H igh Width
Cycle Time (nDS to Next )**
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubl ed when conside ring back-to-bac k COM20019 cycles.
Note 1:
Any cycle occurring a f ter a wri te to Add ress Pointer L ow Register r equire s a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Note 2:
**
TARB is the Arbitration Clock Perio d
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Write cycle fo r Add ress Pointer Low Register occurring after an access to
Data Register requires a minimu m o f 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
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SMSC COM20019I 3.3V Page 53 Rev. 11-07-08
DATASHEET
Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
A
D0-AD2, VALID
nCS t1
t3
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
Note 2
t8**
nWR
t9
t10
nRD t13 t11 t12 t8
Note 3
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
20
10
10
10
15
10
4TARB*
20
20
20
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High 30
ALE High Width
ALE Low Width
nWR Low Width
nWR High Width
nRD to nWR Low
Cycle Time (nWR to Next )**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLO W ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's da tasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edg e of nWR to the leading edge of the
next nWR.
Note 2:
**
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 54 SMSC COM20019I 3.3V Rev.C
DATASHEET
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
A
0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
15
10
5**
0
nS
nS
nS
nS
Address Setup to nRD Activ e
Address Hold from nRD Inactiv e
nCS Setup to n RD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to V alid Data
nRD High to Data High Impedance
4TARB*
0
60
20
20
40**
20
nS
nS
nS
nS
nS
nS
CASE 1: RBUSTMG bit = 0
nRD Low Width
nRD Hig h W i dth
nWR to nRD Low
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
nCS may become active after control becomes activ e, but the access time (t6)
will now be 45 nS measured from the leading edge of nCS.
**
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doub led wh en considering back-to-back COM20019 cycles.
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trai ling edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trai ling edge of nWR to the
leading edge of nRD.
**
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DATASHEET
A
0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
-5
0
-5
0
nS
nS
nS
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD L ow to Valid Data
nRD High to Data High Impedance
4TARB*+30
0
100
30
20
60**
20
nS
nS
nS
nS
nS
nS
nRD Low Width
nRD High Width
nWR to nRD Low
CASE 2: RBUSTMG bit = 1
The Microcontroller typically accesses the COM20019 on ev e ry other cycle.
Therefore , the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 56 SMSC COM20019I 3.3V Rev.C
DATASHEET
Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
15
10
5**
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Inactiv e 4TARB*
nS
nS
nS
nS
nS
nS
t8 nS
nDS Low to Valid Data 40**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impede nce
nDS Low W idth
nDS High Width
20
10
10
0
60
20
CASE 1: RBUSTMG bit = 0
The Microcontroller typically accesses the COM20019 on ev ery other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
nCS may become active after control becomes active, b u t the a ccess time (t8) will
now be 45n S me asu red from th e l eading edge of nCS.
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
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DATASHEET
Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
-5
0
-5
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS In a ctive 4TARB*+30
nS
nS
nS
nS
nS
nS
t8 nSnDS Low to Valid Data 60**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impedence
nDS Low Width
nDS High Width
20
10
10
0
100
30
CASE 2: RBUSTMG bit = 1
The Microcontroller typically accesses the COM20019 on ev ery other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
** t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2.
TARB is the Arbit ra tion C l o c k Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLO W ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Note 2: Read cycle for Addr e ss Pointer Low/High Reg i st e r s occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the lead i ng edge of the ne xt nDS.
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 58 SMSC COM20019I 3.3V Rev.C
DATASHEET
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Data Hold from nWR Hi g h
nWR Low Width
nWR High Width
nRD to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
Note 3
t5**
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR Hig h
min
15
5
10
20
20
20
max
4TARB*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold from nWR Inactive 10 nS
Cycle Time (nWR to Next )**
***: nCS may become active after control becomes active , but the data setup time will no w
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20019 on e very other cycle.
Therefo re, the cycle tim e specified in the microcontr oller's datasheet
should be doubled when considering back-to-bac k COM20019 cycles.
Note 1:
Note 2: A ny cycle occurrin g a f te r a write to the Ad dress Pointer Lo w Re gi ste r
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Write cycle for Address Pointer Low Register occurring aft er a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Po inter Low Register occurring after a read from Data
Register requires a minimum of 5T ARB from the trailing edge of nRD to the
leading edge of nWR.
**
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SMSC COM20019I 3.3V Page 59 Rev. 11-07-08
DATASHEET
CASE 2 is supported for TQFP Package ONLY
Data Hold from nWR Hi g h
nWR Low Width
nWR High Width
nRD to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
Note 3
t5**
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR Hig h
min
15
5
10
20
20
20
max
4TARB*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold from nWR Inactive 10 nS
Cycle Time (nWR to Next )**
***: nCS may become active after control becomes active , but the data setup time will no w
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20019 on e very other cycle.
Therefo re, the cycle tim e specified in the microcontr oller's datasheet
should be doubled when considering back-to-bac k COM20019 cycles.
Note 1:
Note 2: A ny cycle occurrin g a f te r a write to the Ad dress Pointer Lo w Re gi ste r
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Write cycle for Address Pointer Low Register occurring aft er a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Po inter Low Register occurring after a read from Data
Register requires a minimum of 5T ARB from the trailing edge of nRD to the
leading edge of nWR.
**
Figure 8.10 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 60 SMSC COM20019I 3.3V Rev.C
DATASHEET
Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
t6**
Parameter min max units
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS to Next Time )**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
nDS Low Wid th
nDS High Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
15
10
5
0
10
4TARB*
10
30***
10
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data availabl e.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SL OW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the next nDS.
Write cycle fo r Address Pointer Low Registers occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
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SMSC COM20019I 3.3V Page 61 Rev. 11-07-08
DATASHEET
CASE 2 is supported for TQFP Package ONLY
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
t6**
Parameter min max units
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS to Next Time )**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
15
10
5
0
10
4TARB*
10
30***
10
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
TARB is the Arbi tration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore , the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the next nDS.
Write cycle for Address Pointer Low Registers o ccu rri n g after a n access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 11-07-08 Page 62 SMSC COM20019I 3.3V Rev.C
DATASHEET
nPULSE1 t2 t3
RXIN t10
t11
nPULSE2 t5 t6
(Internal Clk)
t4
t1
t7
nTXEN
t9 t8
LAST BIT
(3200 nS BIT TIME)
t13
t12
Parameter min typ max units
t2
t3
t4
t5
t6
t7
t8
t10
t11
t12
nPULSE1 Pulse Width
nPULSE1 Period
nPULSE2 Low to nPULSE1 Low
nPULSE2 High Time
nPULSE2 Low Time
nPULSE2 Period
nPULSE2 High to nTXEN High
RXIN Active Pulse Width
RXIN Period
nS
nS
nS
nS
nS
nS
nS
nS
nS
1600*
3200*
800*
800*
1600*
1600*
3200*
50
50
-25
10
t1 nPULSE2 High t o nTXEN Low -25 50 nS
(First Rising Edge on nPULSE2 after Last Bit Time)
t9 nTXEN Low to first nPULSE1 Low** 5500 5700 nS
-25
RXIN Inactive Pulse Width 20 nS
t13 Beginning Last Bit Time to nTXEN High** 3900 nS
4100
Above values are for 312.5 Kbps.
Other Data Rates are shown below.
TDR is the Data Rate Pe riod
*t5, t6 = TDR/4
*t2, t7, t10 = TDR/2
*t3, t11 = TDR
**t9 = x TDR +/- 100 nS
7
4
**t13 = x TDR +/- 100 nS
5
4
Figure 8.13 - BACKPLANE MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the differential driver or the cable)
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DATASHEET
t1
t3
Parameter
Input Clock High Time
Input Clock Period
min
20
50
max units
nS
nS
XTAL1
t1
t4 Input Clock F requency* 100
t2 Input Clock Lo w Time nS
t3
20
typ
10
t2
20 MHz
t5 Frequency Accu racy* -200 200 ppm
Note*: t4 and t5 are applied to crystal oscillaton.
4.0V 1.0V 50% of VDD
Figure 8.14 - TTL INPUT TIMING ON XTAL1 PIN
t1
Parameter
nRESET Pulse Width***
min max units
nRESET
t1
t2 nINTR High to Next nINTR Low
typ
t2
nINTR
5TXTL*
EF = 0
EF = 1 TDR**/2
4TXTL*
Note*: TXTL is per iod of external XTAL oscillation frequency.
Note **: TDR is period of Data Rate (i.e. at 312.5 Kbps, TDR = 3200 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
Figure 8.15 - RESET AND INTERRUPT TIMING
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DATASHEET
Chapter 9 Package Outlines
9.1 28 Pin PLCC Package Outline and Parameters
A
A1
B
B1
C
D
D1
D2
D3
E
F
G
R
.160-.180
.090-.120
.013-.021
.026-.032
.020-.045
.485-.495
.450-.456
.390-.430
.300 REF
.050 BSC
.042-.056
.042-.048
.025-.045
DIM 28L
J .000-.020
NOTES:
All dime nsions are in inches.
Circle indicatin g pin 1 can appe ar on a to p surface as shown on the drawing or
right above it o n a beve led ed ge.
1.
2.
PIN NO.
1
GEJ
D3
JD1
D
J
B1
B
A
A1
C
D2
F
R
Base
Plane
Seating
Plane
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DATASHEET
9.2 48 Pin TQFP Package Outline and Parameters
MIN NOMINAL MAX REMARK
A ~ ~ 1.6 Overall Package Height
A1 0.05 0.10 0.15 Standoff
A2 1.35 1.40 1.45 Body Thickness
D 8.80 9.00 9.20 X Span
D/2 4.40 4.50 4.60 1/2 X Span Measure from Centerline
D1 6.90 7.00 7.10 X body Size
E 8.80 9.00 9.10 Y Span
E/2 4.40 4.50 4.60 1/2 Y Span Measure from Centerline
E1 6.90 7.00 7.10 Y body Size
H 0.09 ~ 0.20 Lead Frame Thickness
L 0.45 0.60 0.75 Lead Foot Length from Centerline
L1 ~ 1.00 ~ Lead Length
e 0.50 Basic Lead Pitch
θ 0o ~ 7o Lead Foot Angle
W 0.17 ~ 0.27 Lead Width
R1 0.08 ~ ~ Lead Shoulder Radius
R2 0.08 ~ 0.20 Lead Foot Radius
ccc ~ ~ 0.0762 Coplanarity (Assemblers)
ccc ~ ~ 0.08 Coplanarity (Test House)
Note 1: Controlling Unit: millimeter
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Rev. 11-07-08 Page 66 SMSC COM20019I 3.3V Rev.C
DATASHEET
Chapter 10 Appendix A
This appendix describes the function of the NOSYNC and EF bits.
10.1 NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by
enabling or disabling the SYNC command during initialization. It is defined as follows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line
has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not
have to be idle for the RAM initialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes t he Node ID, the COM20019I 3V will write "D1"h data t o Address
000h and Node-ID to Address 001h of it s internal RAM within 96uS. These values are read as part of the
diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will
report it as a device diagnostic failure. These writes are controlled by a micro-program which sometimes
waits if the line is active; SYNC is the micro-program command that causes the wait. When the micro-
program waits, the initial RA M write does not occur, which causes the diagn ostic error. Thus in this case,
if the line is not idle, the initialization sequence may not be written, which will be reported as a device
diagnostic failure.
However, the initialization sequence and diagnostics of the COM20019I 3V should be independent of the
network status. This is accomplished through some additional logic to decode the program counter,
enabled by the NOSYNC bit . When it finds t hat t he micro-p rogram is in th e initializat ion r outin e, it disable s
the SYNC command. In this case, the initialization will not be held up by the line status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to
be written.
10.2 EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the
new internal operati on timing (the t iming is the same as in the COM20020 Rev. B); EF=1: Enable the n ew
internal operation timing.
The EF bit controls the following timing/logic refinements in the COM20019I 3V:
A) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt and
Clear Flag command and by reading the Next-ID register. This minimum disable time is changed by the
Data Rate.
Setting the EF bit will change t he minimum disable t ime to always be m ore than 200 nS. This is done b y
changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock is always
less than 20MHz .
B) Synchronize the Pre-Scalar Output
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DATASHEET
The Pre-Scalar is used to cha nge the data rat e. The output clock is sel ected by CKP3-1 bi ts in the Set-Up
register. The CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not
synchronized between the CPU and COM20019I 3V. Thus, changing the CKP3-1 timing does not
synchronize with the internal clocks of Pre-Scalar, and ch anging CKP3- 1 may cause spike noise to ap pear
on the output clock line.
Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for
synchronizing the CKP3-1 with Pre-Scalar’s internal clocks.
C) Shorten The Write Interval Time To The Command Register
The COM20019I 3V limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rate. It's 800 nS at the 312.5 Kbps and 1.6 μS at the
156.25 Kbps. This 1.6 μS is very long for CPU.
Setting the EF bit will change the clock sourc e from OSCK clock (8 times frequenc y of data rate) to XT AL
clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS.
D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20019I 3V has a write prohibition period for writing the Enable Transmit/Receive Commands.
This period is started by the T A or RI bit (Status Reg.) returning to High. This prohibit ion period is caused
by setting the TA/RI bit with a pulse signal. It is 3.2 μS at 156.25 Kbps. This period may be a problem
when using interrupt processi ng. The interrupt occurs when the RI bit returns to High. The CPU writes the
next Enable Receive C ommand to the other page immediat ely. In this case, the interval t ime between the
interrupt and writing Command is shorter than 3.2 μS.
Setting the EF bit will cause the TA/ RI bit to return to Hig h upon release of t he pulse signal for set ting the
TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1.
Tx/R x completed
T A /RI bit
Setting Pu lse
nIN T R pin
prohibition pe riod
EF=1 Tx/Rx completed
T A /RI bit
Setting Pu lse
nINTR pin
EF=0
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT
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DATASHEET
The EF bit also controls the resolution of the following issues from the COM20020 Rev. B:
A) Network MAP Generation
Tentative I D is used for gener ating t he Network MAP, but it sometimes detect s a non-e xist ent node. Every
time the Tentative-I D register is written, the effect of t he old Tentative-ID remains active for a while, which
results in an incorrect network map. It can be avoided by a carefully coded software routine, but this
requires the programmer to have deep knowledge of how the COM20019I 3V works. Duplicate-ID is
mainly used for generating the Network MAP. This has the same issue as Tentative-ID.
A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when
the COM20019I 3V detects a write operation to Tentative-ID or Node-ID register. With this change,
programmers can use the Tentat ive-I D or Duplicat e-I D f or gener at ing t he n et work MAP without an y issues.
This change is Enabled/ Disabled by the EF bit.
B) Mask Register Reset
The Mask register is reset by a soft reset in the COM20020 Rev. A, but is not reset in Rev. B. T he Mask
register is related to the Status and Diagnostic register, so it should be reset by a soft reset. Otherwise,
every time the soft reset happens, the COM20020 Rev. B generates an unnecessary interrupt since the
status bits RI and TA are back to one by the soft reset.
This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft
reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in
the Configuration register. This solution is Enabled/Disabled by the EF bit.
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DATASHEET
Chapter 11 Appendix B
ISA Bus
AEN
SA15-SA4
SD7-SD0
nIOR
nIOW
SA2-SA0
IRQm
nIOCS16
DRQn
nDACK
TC
nREFRESH
RESETDRV
12
12 bit
Comparators
LS688x2
nG
PP=Q QI/O Address Seeting (DIP Switches)
16 bit Bus
Transceivers
LS245
AB
DIR nG
3
D7-D0
nRD
nWR
A2-A0
nINTR
nRESET
nCS
8
3
Schmitt-Trigger Buffer
12 COM20019
8
A
Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS
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Rev. 11-07-08 Page 70 SMSC COM20019I 3.3V Rev.C
DATASHEET
Chapter 12 Appendix C
12.1 Software Identification of the COM20019I 3V Rev B and Rev C
In order t o pr op erl y writ e sof t ware t o work with t he CO M20 019I 3V Rev B a nd C it is nec es sar y to be ab le to i dent if y t he
different revisions of the part.
To identify the COM20019I 3V Revision foll ow the following procedure:
1. Write 0x00 to Register-5
2. Read Register-5 Æ The value read from Register-5 must be 0x00.
3. Write 0xC0 to Register-5
4. Read Register-5*
* If the value read from Register-5 is 0x80 then the part is a COM20019I 3V Rev B
* If the value read from Register-5 is 0xC0 then the part is a COM20019I 3V Rev C
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