DS26F32MQML
DS26F32MQML Quad Differential Line Receivers
Literature Number: SNOSAS5
DS26F32MQML
Quad Differential Line Receivers
General Description
The DS26F32 is a quad differential line receiver designed to
meet the requirements of EIA Standards RS-422 and RS-
423, and Federal Standards 1020 and 1030 for balanced
and unbalanced digital data transmission.
The DS26F32 offers improved performance due to the use
of state-of-the-art L-FAST bipolar technology. The L-FAST
technology allows for higher speeds and lower currents by
utilizing extremely short gate delay times. Thus, the
DS26F32 features lower power, extended temperature
range, and improved specifications.
The device features an input sensitivity of 200 mV over the
input common mode range of ±7.0V. The DS26F32 provides
an enable function common to all four receivers and TRI-
STATE ®outputs with 8.0 mA sink capability. Also, a fail-safe
input/output relationship keeps the outputs high when the
inputs are open.
The DS26F32 offers optimum performance when used with
the DS26F31 Quad Differential Line Driver.
Features
nInput voltage range of ±7.0V (differential or common
mode) ±0.2V sensitivity over the input voltage range
nHigh input impedance
nOperation from single +5.0V supply
nInput pull-down resistor prevents output oscillation on
unused channels
nTRI-STATE outputs, with choice of complementary
enables, for receiving directly onto a data bus
Ordering Information
NS Part Number SMD Part Number NS Package Number Package Description
DS26F32ME/883 5962–7802005M2A E20A 20LD Leadless Chip Carrier
DS26F32MJ/883 5962–7802005MEA J16A 16LD Ceramic DIP
DS26F32MW/883 5962–7802005MFA W16A 16LD Ceramic FLatpack
DS26F32MWG/883 5962–7802005MZA WG16A 16LD Ceramic SOIC
DS26F32MER-QML 5962R7802005M2A E20A 20LD Leadless Chip Carrier
DS26F32MJR-QML 5962R7802005QEA J16A 16LD Ceramic DIP
DS26F32MWR-QML 5962R7802005QFA W16A 16LD Ceramic FLatpack
DS26F32MJ-QMLV 5962–7802005VEA J16A 16LD Ceramic DIP
DS26F32MW-QMLV 5962–7802005VFA W16A 16LD Ceramic FLatpack
DS26F32MWG-QMLV 5962–7802005VZA WG16A 16LD Ceramic SOIC
DS26F32MJRQMLV 5962R7802005VEA
100k rd(Si)
J16A 16LD Ceramic DIP
DS26F32MWRQMLV 5962R7802005VFA
100k rd(Si)
W16A 16LD Ceramic FLatpack
DS26F32MWGRQMLV 5962R7802005VZA
100k rd(Si)
WG16A 16LD Ceramic SOIC
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
March 2006
DS26F32MQML Quad Differential Line Receivers
© 2006 National Semiconductor Corporation DS201633 www.national.com
Connection Diagrams
20163301
Top View
16-Lead Ceramic DIP Pictured
See NS Package Number WG16A, J16A or W16A
20163307
20-Lead Ceramic Leadless Chip Carrier
See NS Package Number E20A
Function Table
(Each Receiver)
Differential Inputs Enables Outputs
V
ID
=(V
I
+)−(V
I
−) E E OUT
V
ID
≥0.2V H X H
XL H
V
ID
≤−0.2V H X L
XL L
XLHZ
H = High Level
L = Low Level
X = Immaterial
DS26F32MQML
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Absolute Maximum Ratings (Note 1)
Storage Temperature Range −65˚C ≤T
A
≤+150˚C
Operating Temperature Range −55˚C ≤T
A
≤+125˚C
Lead Temperature (soldering, 60 sec) 300ËšC
Supply Voltage 7.0V
Common Mode Voltage Range ±25V
Differential Input Voltage ±25V
Enable Voltage 7.0V
Output Sink Current 50 mA
Maximum Power Dissipation (P
D max
at 25ËšC (Note 2), (Note 3) 500 mW
Thermal Resistance
θ
JA
Ceramic DIP 100ËšC/W
Ceramic Flatpack 142ËšC/W
Leadless Chip Carrier 87ËšC/W
θ
JC
Junction-to- case See MIL-STD-1835
Recommended Operating Range
Operating Temperature −55˚C ≤T
A
≤+125˚C
Supply Voltage 4.5V to 5.5V
Radiation Features
DS26F32MJRQMLV 100 krads (Si)
DS26F32MWRQMLV 100 krads (Si)
DS26F32MWGRQMLV 100 krads (Si)
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp ËšC
1 Static tests at 25
2 Static tests at 125
3 Static tests at -55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at -55
7 Functional tests at 25
8A Functional tests at 125
8B Functional tests at -55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at -55
12 Settling time at 25
13 Settling time at 125
14 Settling time at -55
DS26F32MQML
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DS26F32 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
DC: V
CC
= 5V (Note 7)
Symbol Parameter Conditions Notes Min Max Units Sub-
groups
I
In
Input Current Pin under test
V
CC
= 4.5V, V
I
= 15V
Other inputs -15V ≤V
I
≤+15V
2.3 mA 1, 2, 3
Pin under test
V
CC
= 5.5V, V
I
= -15V
Other inputs -15V ≤V
I
≤+15V
-2.8 mA 1, 2, 3
I
IL
Logical "0" Enable Current V
CC
= 5.5V, V
En
= 0.4V -360 µA 1, 2, 3
I
IH
Logical "1" Enable Current V
CC
= 5.5V, V
I
= 2.7V 10 µA 1, 2, 3
I
I
Logical "1" Enable Current V
CC
= 5.5V, V
I
= 5.5V 50 µA 1, 2, 3
V
IK
Input Clamp Voltage (Enable) V
CC
= 4.5V, I
I
= -18mA -1.5 V 1, 2, 3
V
OH
Logical "1" Output Voltage V
CC
= 4.5V, I
OH
= -440µA,
∆V
I
=1V,VEn=.8=V
En
2.5 V 1,2,3
V
OL
Logical "0" Output Voltage V
CC
= 4.5V, VEn =0.8V = V
En
,
I
OL
= 4mA, ∆V
I
= -1V
0.4 V 1,2,3
V
CC
= 4.5V, VEn = 8V = V
En
,
I
OL
= 8mA, ∆V
I
= -1V
.45 V 1,2,3
I
CC
Supply Current V
CC
= 5.5V, All V
I
= Gnd,
V
En
= 0V, V
En
=2V
50 mA 1, 2, 3
I
OZ
Off-State Output Current V
CC
= 5.5V, V
O
= 0.4V,
V
En
= 0.8V, V
En
=2V
-20 µA 1, 2, 3
V
CC
= 5.5V, V
O
= 2.4V,
V
En
= 0.8V, V
En
=2V
20 µA 1, 2, 3
R
I
Input Resistance -15 ≤V
CM
≤15V 14 KΩ1, 2, 3
V
Th
Differential Input Voltage V
CC
= 4.5V, V
OUT
=V
OL
or V
OH
-7V ≤V
CM
≤7V,
V
En
=V
En
= 2.5V
(Note 4) -0.2 0.2 V 1, 2, 3
V
CC
= 5.5V, V
OUT
=V
OL
or V
OH
-7V ≤V
CM
≤7V,
V
En
=V
En
= 2.5V
(Note 4) -0.2 0.2 V 1, 2, 3
V
IL
Logical "0" Input Voltage
(Enable)
V
CC
= 5.5V (Note 4) 0.8 V 1, 2, 3
V
IH
Logical "1" Input Voltage
(Enable)
V
CC
= 4.5V (Note 4) 2.0 V 1, 2, 3
I
SC Min
Output Short Circuit Current V
CC
= 4.5V, V
O
= 0V,
∆V
I
=1V
-15 mA 1, 2, 3
I
SC Max
Output Short Circuit Current V
CC
= 5.5V, V
O
= 0V,
∆V
I
=1V
-85 mA 1, 2, 3
DS26F32MQML
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DS26F32 Electrical Characteristics (Continued)
AC Parameters
The following conditions apply, unless otherwise specified.
AC: V
CC
= 5V (Note 7)
Symbol Parameter Conditions Notes Min Max Units Sub-
groups
t
PLH
C
L
= 50pF (Note 6) 23 nS 9
(Note 6) 31 nS 10, 11
C
L
= 15pF (Note 5) 22 nS 9
(Note 5) 30 nS 10, 11
t
PHL
C
L
= 50pF (Note 6) 23 nS 9
(Note 6) 31 nS 10, 11
C
L
= 15pF (Note 5) 22 nS 9
(Note 5) 30 nS 10, 11
t
PZH
Enable Time C
L
= 50pF (Note 6) 18 nS 9
(Note 6) 29 nS 10, 11
C
L
= 15pF (Note 5) 16 nS 9
(Note 5) 27 nS 10, 11
t
PZL
Enable Time C
L
= 50pF (Note 6) 20 nS 9
(Note 6) 29 nS 10, 11
C
L
= 15pF (Note 5) 18 nS 9
(Note 5) 27 nS 10, 11
t
PHZ
Disable Time C
L
= 50pF (Note 6) 55 nS 9
(Note 6) 62 nS 10, 11
C
L
= 5pF (Note 5) 20 nS 9
(Note 5) 27 nS 10, 11
t
PLZ
Disable Time C
L
= 50pF (Note 6) 30 nS 9
(Note 6) 42 nS 10, 11
C
L
= 5pF (Note 5) 18 nS 9
(Note 5) 30 nS 10, 11
DC Drift Parameters
This section applies to -QMLV devices only. Devices shall be read & recorded at T
A
= 25ËšC before and after each burn-in and
shall not change by more than the limits indicated. The delta rejects shall be included in the PDA calculation.
Symbol Parameter Conditions Notes Min Max Units Sub-
groups
V
OH
Logical "1" Output Voltage V
CC
= 4.5V, I
OH
= -440µA,
∆V
I
= 1V, VEn = 0.8V = V
En
-250 250 mV 1
V
OL
Logical "0" Output Voltage V
CC
= 4.5V, I
OL
= 4mA,
∆V
I
= -1V, VEn = 0.8V = V
En
-45 45 mV 1
V
CC
= 4.5V, I
OL
= 8mA,
∆V
I
= -1V, VEn = 0.8V = V
En
-45 45 mV 1
I
I
Input Current Pin under test
V
CC
= 4.5V, V
I
= 15V
Other inputs -15V ≤V
I
≤+15V
-0.28 0.28 mA 1
Pin under test
V
CC
= 5.5V, V
I
= -15V
Other inputs -15V ≤V
I
≤+15V
-0.28 0.28 mA 1
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Derate J package 10.0mW/ËšC above +25ËšC, derate W package 7.1mW/ËšC above +25ËšC, derate E package 11.5mW/ËšC above +25ËšC.
Note 3: Power dissipation must be externally controlled at elevated temperatures.
Note 4: Parameter tested go-no-go only.
Note 5: Tested at 50pF guarantees limit at 15pF & 5pF.
Note 6: Tested at 50pF, system capacitance exceeds 5pF to 15pF.
Note 7: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space
environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in Mil-Std-883, Method 1019.5, Condition A
20163302
FIGURE 1. Logic Symbol
20163303
FIGURE 2. Load Test Circuit for Three-State Outputs
20163304
FIGURE 3. Propagation Delay (Notes 8, 9, 10)
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Typical Application
20163305
Note 8: Diagram shown for ENABLE Low.
Note 9: S1 and S2 of Load Circuit are closed except where shown.
Note 10: Pulse Generator of all Pulses: Rate ≤1.0 MHz, ZO=50Ω,t
r≤6.0 ns, tf≤6.0 ns.
Note 11: All diodes are IN916 or IN3064.
Note 12: CLincludes probe and jig capacitance.
FIGURE 4. Enable and Disable Times (Notes 8, 9, 10)
20163306
FIGURE 5.
DS26F32MQML
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Revision History
Released Revision Section Originator Changes
03/01/06 A New Release, Corporate format L. Lytle 1 MDS data sheet converted into one Corp.
data sheet format. MNDS26F32M-X-RH Rev
0C0 will be archived.
DS26F32MQML
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Physical Dimensions inches (millimeters) unless otherwise noted
20LD Leadless Chip Carrier (E)
NS Package Number E20A
Ceramic Dual-In-Line Package (J)
NS Package Number J16A
DS26F32MQML
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