1
®
FN6168.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88550A
Synchronous Step-Down Controller with
Sourcing and Sinking LDO Regulator
ISL88550A integrates a synchronous buck PWM controlle r
to generate VDDQ, a sourcing and sinking LDO linear
regulator to generate VTT, and a 10mA reference output
buffer to generate VTTR. The buck controller drives two
external N-Channel MOSFETs to generate output voltages
down to 0.7V from a 2V to 25V input with output currents up
to 15A. The LDO can source up to 2.5A and sink up to -2.0A
continuously. Both the LDO output and the 10mA reference
buffer output can be made to track the REFIN voltage via a
built-in resisti v e divider. These features make the
ISL88550A ideally suited for DDR memo ry applications in
desktops, notebooks and graphics cards.
The PWM controller in the ISL88550A uses constant-on-time
PWM architecture with a programmable switching frequency
of up to 600kHz. This control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
high efficiency and a relatively constant switching frequency.
The ISL88550A offers full programmable UVP/OVP and skip
mode options ideal in portable application s . Skip mode
allows for improved efficiency at lighter loads.
The VTT and VTTR outputs track to VREFIN/2. The high
bandwidth of this LDO regulator allows excellent transient
response without the need for bulk capacitors, thus reducing
the cost and size.
The buck controller and LDO regulators are provided with
independent current limits. Adjustable loss-less fold-back
current limit for the buck regul ator is achieved by monitoring
the drain-to-source voltage drop of the low side synchronous
MOSFET. Once overcurrent is removed, the regulator is
allowed to enter soft-start again. This helps minimize power
dissipation during short-circuit condition. Additionally,
overvoltage and undervoltage protection mechanisms are
built in. The ISL88550A allow flexible sequencing and
standby power management using SHDNA#, and STBY#
inputs.
Features
Pb-Free (RoHS Compliant)
Buck Controller
Constant-On PWM with 100ns Load-St ep Response
Start-up with Pre-biased Output Voltage
Up to 95% Efficiency
2V to 25V Input Voltage Range
2.5V Fixed or 0.7V to 3.5V Adjustable Output
200kHz/300kHz/450kHz/600kHz Switching Frequ encies
Programmable Current Limit with Foldback Capability
1.7ms Digital Soft-Start and Independent Shutdown
Overvoltage/Undervoltage Protection Option
Power-Good Window Comparator
LDO Section
Fully Integrated VTT and VTTR Capability
VTT has +2.5A/-2.0A Sourcing/Sinking Capability
Start-Up with Pre-Biased Output Voltage
VTT and VTTR Outputs Track VREFIN/2
VTT and VTTR 1% of VREFIN/2
Low All-Ceramic Output Capacitor Designs
1.0V to 2.8V Input REFIN Range
Analog Soft-Start Option and Independent Shutdown
Power-Good Window Comparator
Applications
DDR, DDR II and DDR III Memory Power Supplies
Desktop Computers
Notebooks and Desknotes
Graphics Cards
Game Consoles
Networking and RAID
Ordering Information
PART NUMBER (Note) PART MARKING TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. #
ISL88550AIRZ ISL88 550AIRZ -40 to +85 28 Ld 5×5 TQFN L28.5x5B
ISL88550AIRZ-T* ISL88 550AIRZ -40 to +85 28 Ld 5×5 TQFN Tape and Reel L28.5x5B
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Data Sheet April 23, 2008
2FN6168.3
April 23, 2008
Pinout ISL88550A
(28 LD TQFN)
TOP VIEW
SS
VTTS
VTTR
PGND2
VTT
VTTI
REFIN
TP0
SHDNA#
AVDD
SKIP#
GND
PGND1
VDD
FB
OUT
VIN
UGATE
PHASE
BOOT
LGATE
1
2
3
4
5
6
7
21
20
19
18
17
16
15
28 27 26 25 24 23 22
8 9 10 11 12 13 14
STBY#
POK2
POK1
ILIM
REF
OVP/UVP
TON
ISL88550A
3FN6168.3
April 23, 2008
Absolute Maximum Ratings Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +25V
VDD, AVDD, VTTI to GND. . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6V
SHDNA#, REFIN to GND. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6V
SS, POK1, POK2, SKIP#, ILIM, FB to GND . . . . . . . . . .-0.3V to 6V
STBY#, TON, REF, UVP/OVP to GND . . . . . .-0.3V to AV DD + 0.3V
OUT, VTTR to GND . . . . . . . . . . . . . . . . . . . . .-0.3V to AVDD + 0.3V
LGATE to PGND1 . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
UGATE to PHASE . . . . . . . . . . . . . . . . . . . . -0.3V to VBOOT + 0.3V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V
VTT to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VTTI + 0.3V
VTTS to GND. . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to AVDD + 0.3V
PGND1, PGND2 to GND. . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
REF Short Circuit to GND.. . . . . . . . . . . . . . . . . . . . . . . .Continuous
Thermal Resistance θJA (°C/W) θJC (°C/W)
28 Ld TQFN Package (Notes 1, 2). . . . 32 2.5
Operating Conditions
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . -65°C + 150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.
3. Following are target specifications. Final limits may change as a result of characterization.
Electrical Specifications VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V,
FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, tON = OPEN, TA = -40°C to
+85°C, Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested. (Note 4).
PARAMETER CONDITIONS MIN TYP MAX UNIT
MAIN PWM CONTROLLER
VIN Input Voltage Range 225V
VDD, AVDD Input Voltage Range 4.5 5.5 V
Output Adjust Range 0.7 3.5 V
Output Voltage Accuracy (Note 5) FB = OUT 0.693 0.7 0.707 V
FB = GND 2.470 2.5 2.53 V
Soft-Start Ramp Time Rising edge of SHDNA# to full current limit 1.7 ms
ON-Time VIN = 15V,
VOUT = 1.5V
(Note 6)
tON = GND (600kHz) 170 194 219 ns
tON = REF (450kHz) 213 243 273 ns
tON = OPEN (300kHz) 316 352 389 ns
tON = AVDD (200kHz) 461 516 571 ns
Minimum, OFF-Time (Note 6) 200 300 450 ns
VIN Quiescent Supply Current 25 40 µA
VIN Shutdown Supply Current SHDNA# = STBY# = GND 1 5 µA
Combined AVDD and VDD Quiescent Supply
Current All on (PWM, VTT, and VTTR on), VFB = 0.75V 2.5 5 mA
STBY# = GND (only VTTR and PWM on),
VFB = 0.75V 12mA
Combined AVDD and VDD Shutdown Supply
Current SHDNA# = STBY# = GND 2 10 µA
AVDD Undervoltage Lockout Threshold Rising edge of AVDD 4.1 4.25 4.4 V
Hysteresis 50 mV
REFERENCE
Reference Voltage AVDD = 4.5V to 5.5V; IREF = 0µA to 130µA 1.98 2 2.02 V
Reference Load Regulation IREF = 0µA to 50µA 0.01 V
ISL88550A
4FN6168.3
April 23, 2008
REF Undervoltage Lockout VREF rising 1.93 V
Hysteresis 300 mV
FAULT DETECTION
OVP Trip Threshold (Referenced to Nominal
VOUT)UVP/OVP = AVDD 110 114 118 %
UVP Trip Level Referred to Nominal VOUT 65 70 75 %
POK1 Trip Level Referred to Nominal VOUT Lower level, falling edge, 1% hysteresis 87 90 93 %
Upper level, rising edge, 1% hysteresis 107 110 113 %
POK2 Trip Level Referred to Nominal VTTS
and VTTR Lower level, falling edge, 1% hysteresis 87.5 90 92.5 %
Upper level, rising edge, 1% hysteresis 107.5 110 112.5 %
POK2 Disable Threshold (Measured at
REFIN) VREFIN rising (Hysteresis = 75mV typical) 0.7 0.9 V
UVP Blanking Time From rising edge of SHDNA# 8 14 25 ms
OVP, UVP, POK_ Propagation Delay 10 µs
POK_ Output Low Voltage ISINK = 4mA 0.3 V
POK_ Leakage Current VPOK_ = 5.5V, VFB = 0.8V, VTTS = 1.3V 1 µA
ILIM Adjustment Range 0.25 2.00 V
ILIM Input Leakage Current 0.1 µA
Current Limit Threshold (Fixed)
PGND1 to PHASE ILIM = AVDD 45 50 55 mV
Current Limit Threshold (Adjustable)
PGND1 to PHASE VILIM = 2V 170 200 235 mV
Current-Limit Threshold (Negative Direction)
PGND1 to PHASE SKIP# = AVDD -75 -60 -45 mV
Current-Limit Threshold (Negative Direction)
PGND1 to PHASE SKIP# = AVDD, ILIM = 2V -250 mV
Current-Limit Threshold (Zero Crossing)
PGND1 to PHASE 3mV
Thermal Shutdown Threshold Rising 150 °C
Hysteresis 15 °C
INTERNAL BOOT DIODE
VD Forward Voltage PVCC - VBOOT, IF = 10mA 0.60 0.70 V
IBOOT_LEAKAGE Leakage Current VBOOT = 25V, PHASE = 20V, PVCC = 5V 300 500 nA
MOSFET DRIVERS
UGATE Gate Driver ON-Resistance VBOOT - VPHASE = 5V 1.5 5 Ω
LGATE Gate Driver ON-Resistance in High
State 1.5 5 Ω
LGATE Gate Driver ON-Resistance in Low
State 0.6 3 Ω
Dead Time (Additional to Adaptive Delay) LGATE rising 30 ns
UGATE rising 30 ns
INPUTS AND OUTPUTS
Logic Input Threshold High (SHDNA#, SKIP#,
STBY#) Rising edge 1.2 1.7 2.20 V
Hysteresis 225 mV
Logic Input Current (SHDNA#, SKIP#, STBY#) -1 1 µA
FB Input Logic Level Low (2.5V output) 0.1 V
Electrical Specifications VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V,
FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, tON = OPEN, TA = -40°C to
+85°C, Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested. (Note 4). (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNIT
ISL88550A
5FN6168.3
April 23, 2008
Input Bias Current (FB) -0.1 0.1 µA
Four-Level Input Logic Levels
(tON, OVP/UVP) High AVDD - 0.4 V
Floating 3.15 3.85 V
REF 1.65 2.35 V
Low 0.5 V
Logic Input Current (tON, OVP/UVP, Note 5) -3 +3 µA
OUT Input Resistance FB = GND 125 250 500 kΩ
FB Adjustable Mode 125 250 500 kΩ
OUT Discharge Mode ON-Resistance 15 30 Ω
LINEAR REGULATORS (VTTR AND VTT)
VTTI Input Voltage Range 1.0 2.8 V
VTTI Supply Current IVTT = IVTTR = 0 0.1 1 mA
VTTI Shutdown Current SHDNA# = STBY# = GND 10 µA
REFIN Input Impedance VREFIN = 2.5V 17 20 27 kΩ
REFIN Range 1.0 2.8 V
VTT, VTTR UVLO Threshold (Measured at
OUT) 0.01 0.1 0.2 V
Soft-Start Charge Current VSS = 0 4 µA
VTT internal MOSFET High-Side
ON-Resistance IVTT = -100mA, VVTTI = 1.5V, AVDD = 4.5V
(TJ= +125°C) 0.10 0.28 Ω
VTT internal MOSFET Low-Side
ON-Resistance IVTT = 100mA, AVDD = 4.5V (TJ = +125°C) 0.18 0.43 Ω
VTT Output Accuracy (Referenced to VTTR) VREFIN = 1.8V or 2.5V, IVTT = ±5mA -1.5 1.5 %
VTT Load Regulation VREFIN = 2.5V, IVTT = 0A to ±1.5A 1 %
VREFIN = 1.8V, IVTT = 0A to ±1.5A 1 %
VTT Positive Current Limit VTT = 0 2.5 3.0 4.0 A
VTT Negative Current Limit VTT = VTTI -3.5 -2.5 -2.0 A
VTTS Input Current VVTTS = 1.5V, VTT Open 0.1 1 µA
VTTR Output Error (Referenced to VREFIN/2) VREFIN = 1.8V, IVTTR = 0mA -1.25 1.25 %
VTTR Current Limit VTTR = 0 or VTTI ±20 ±40 ±60 mA
NOTES:
4. Limits established by characterization and are not production tested.
5. When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error comparator threshold by
50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than the trip level by approximately 1.5%
due to slope compensation.
6. On-time and off-time specifications are measured from 50% point to 50% point at the UGA TE pin with PHASE = GND, VBOOT = 5V, and a 250pF
capacitor connected from UGATE to PHASE. Actual in-circuit times may differ due to MOSFET switching speeds.
Electrical Specifications VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V,
FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, tON = OPEN, TA = -40°C to
+85°C, Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested. (Note 4). (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNIT
ISL88550A
6FN6168.3
April 23, 2008
Pin Descriptions
PIN NAME FUNCTION
1TONt
ON On-T ime Selection-Control Input. This four-level logic input sets the nominal UGATE on-time. Connect
to GND, REF, AVDD, or leave tON unconnected to select the following nominal switching frequencies:
tON = AVDD (200kHz)
tON = OPEN (300kHz)
tON = REF (450kHz)
tON = GND (600kHz)
2 OVP/UVP Overvoltage/Undervoltage Protection Control Input. This four-level logic input enables or disables the
Overvoltage and/or Undervoltage Protection. The overvoltage limit is 116% of the nominal output voltage.
The undervoltage limit is 70% of the nominal output voltage. Discharge mode is enabled when OVP is also
enabled. Connect the OVP/UVP pin to the following pins for the desired function:
OVP/UVP = AVDD (Enable OVP and discharge mode, enable UVP)
OVP/UVP = OPEN (Enable OVP and discharge mode, disable UVP)
OVP/UVP = REF (Disable OVP and discharge mode, enable UVP)
OVP/UVP = GND (Disable OVP and discharge mode, disable UVP)
3 REF +2.0V Reference Voltage Output. Bypass to GND with a 0.1µF (min) bypass capacitor. REF can supply
50µA for external loads. Can be used for setting voltage for ILIM. REF turns off when SHDNA#, STBY# are
low.
4 ILIM Current-Limit Threshold Adjustment for Buck Regulator. The current-limit threshold across PGND and
PHASE is 0.1x the voltage at ILIM. Connect ILIM to a resistive-divider (typically from REF) to set the
current-limit threshold between 25mV and 200mV (with 0.25V to 2V at ILIM). Connect to A VDD to select the
50mV default current-limit threshold.
5 POK1 Buck Power-Good Open-Drain Output. POK1 is low when the Buck output voltage is more than 10% above
or below the normal regulation point or during soft-start. POK1 is high impedance when the output is in
regulation and the soft-start circuit has terminated. POK1 is low in shutdown.
6 POK2 LDO Power-Good Open-Drain Output. In normal mode, POK2 is low when either VTTR or VTTS is more
than 10% above or below the normal regulation point, which is typically REFIN/2. In standby mode, POK2
responds only to VTTR input. POK2 is low in shutdown, and when VREFIN is less than 0.8V.
7 STBY# S tand-By Pin. Tie to low for low quiescent mode where the VTT output is disabled with high impedance but
the VTTR buffer is kept alive if SHDNA# is high. POK2 takes input from only VTTR in this mode. VTT is
discharged to 0V when SHDNA# = GND. PWM output can be on or off depending on the state of SHDNA#.
8 SS Soft-Start Control Pin for VTT and VTTR. Connect a capacitor (C9 in "Typical Application Circuit" on
page 22) from SS to GND (see Soft-S t art capacitor Selection in “LDO Section” on page 1). Leave SS open
to disable soft-start. SS discharged to GND when SHDNA# = GND
9 VTTS Sensing Pin for Termination Supply Output. Normally tied to VTT pin to allow accurate regulation to ½ the
REFIN voltage. Connected to a resistor divider from VTT to GND to regulate VTT to higher than ½ the
REFIN voltage.
10 VTTR Termination Reference Voltage. VTTR tracks the value of the VTT output.
11 PGND2 Power Ground for the VTT and VTTR.
12 VTT Termination Power Supply Output. Tie VTT to VTTS to regulate to VREFIN/2.
13 VTTI Power Supply Input Voltage for VTT. Normally tied to output of buck regulator for DDR application.
14 REFIN External Reference Input. This is used to regulate the VTT and VTTR outputs to VREFIN/2
15 FB Feedback Input for Buck Output. Connect to GND for a +2.5V fixed output. For an adjustable output (0.7V
to 5.5V), connect FB to a resistive-divider from the output voltage. FB regulates to +0.7V.
16 OUT Output Voltage Sense Connection. Connect directly to the positive terminal of the buck capacitors. OUT
senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the "T ypical
Application Circuit" on page 22). OUT also serves as the buck output’s feedback input in fixed-output
modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an
internal 20Ω resistor connected between OUT and ground.
17 VIN Input Voltage Sense Connection. Connect to input power source. VIN is used only to set the PWM on-time
one-shot timer. This pin can range from 2V to 25V.
18 UGATE High-Side Gate-Driver Output. Swings from PHASE to BOOT. UGATE is low when in shutdown or UVLO.
ISL88550A
7FN6168.3
April 23, 2008
19 PHASE External Inductor Connection. Connect PHASE to the input side of the inductor. PHASE is used for both
current limit and the return supply of the UGATE driver.
20 BOOT Boost Flying-Capacitor Connection. Connect to an external capacitor according to the "Typical Application
Circuit" on page 22 (Figure 29). See “Boost-Supply Capacitor Selection (Buck)” on page 21.
21 LGATE Synchronous Rectifier Gate-Driver Output. Swings from PGND to VDD.
22 VDD Supply Input for the LGATE Gate Drive. Connect to +4.5V to +5.5V system supply voltage. Bypass to
PGND1 with a 4.7µF ceramic capacitor.
23 PGND1 Power Ground for BUCK Controller. Conn ect PGND1 externally to the underside of the exposed pad.
24 GND Analog Ground for both BUCK and LDO. Connect externally to the underside of the exposed pad.
25 SKIP# Pulse-Skipping Control Input. Connect to AVDD for low-noise, forced-PWM mode. Connect to GND to
enable pulse-skipping operation.
26 AVDD Analog Supply for both BUCK and LDO. Bypass to GND with a 1.0µF ceramic capacitor. A 10Ω internal
resistor is connected between VDD and AVDD.
27 SHDNA# Shutdown Control Input A. Use to control Buck output. A rising edge on SHDNA# clears the overvoltage
and undervoltage protection fault latches (see Tables 2 and 3). Connect AVDD for normal operation.
28 TP0 Test Pin. Must be connected to GND externally.
Pin Descriptions (Continued)
PIN NAME FUNCTION
Typical Operating Characteristics VIN = 12V, VDDQ = 1.8V, tON = GND, SKIP# = AVDD, circuit of Figure 29, TA = +25°C,
unless otherwise noted.
FIGURE 1. EFFICIENCY vs LOAD (1.8V) (tON = GND) FIGURE 2. SWITCHING FREQUENCY vs LOAD (tON = GND)
0
10
20
30
40
50
60
70
80
90
100
0.001 0.010 0.100 1.000 10.000
LOAD (A)
EFFICIENCY (%)
3VIN - SKIP
25VIN - SKIP
12VIN - SKIP
3VIN - PWM
12VIN - PWM
25VIN - PWM
0.001 0.010 0.100 1.000 10.000
LOAD (A)
0
100
200
300
400
500
600
700
FREQUENCY (kHz)
12VIN - PWM
25VIN - PWM
3VIN - PWM
3VIN - SKIP
12VIN - SKIP
25VIN-SKIP
ISL88550A
8FN6168.3
April 23, 2008
FIGURE 3. SWITCHING FREQUENCY vs INPUT VOL T AGE
(tON = GND) FIGURE 4. SWITCHING FREQUENCY vs TEMPERA TURE
(tON = GND)
FIGURE 5. VDDQ REGULATION vs LOAD (1.8V) FIGURE 6. VDDQ OUTPUT vs INPUT VOLTAGE (1.8V)
FIGURE 7. OUTPUT RIPPLE vs LOAD (1.8V) (tON = GND) FIGURE 8. VTT REGULATION vs VTT LOAD
Typical Operating Characteristics VIN = 12V, VDDQ = 1.8V, tON = GND, SKIP# = AVDD, circuit of Figure 29, TA = +25°C,
unless otherwise noted. (Continued)
400
425
450
475
500
525
550
575
600
625
650
675
700
4 6 8 101214161820222426
VIN (V)
FREQUENCY (kHz)
IOUT = 0A
IOUT = 12A
450
470
490
510
530
550
570
590
-40 -30 -20 -10 0 10 20 30 40 50 70 80 90 100
TEMPERATURE (°C)
FREQUENCY (kHz)
60
IOUT = 12A
IOUT = 0A
0.001 0.010 0.100 1.000 10.000
LOAD (A)
1.775
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
VDDQ (V)
3VIN - PWM
3V
IN
- SKIP
12VIN - PWM
12VIN - SKIP
25VIN - PWM
25VIN - SKIP
1.775
1.780
1.785
1.790
1.795
1.800
4 6 8 10 12 14 16 18 20 22 24 26
VIN (V)
VDDQ (V)
IOUT = 0A
IOUT = 12A
0.001 0.010 0.100 1.000 10.000
LOAD (A)
0
10
20
30
40
50
60
OUTPUT RIPPLE (mV)
3VIN - PWM
3VIN - SKIP
12VIN - PWM
12VIN - SKIP
25VIN - PWM
25VIN - SKIP
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
-3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5
LOAD (A)
VTT (V)
ISL88550A
9FN6168.3
April 23, 2008
FIGURE 9. VTTR REGULATION vs VTTR LOAD FIGURE 10. LOAD TRANSIENT (VDDQ)
FIGURE 11. LOAD TRANSIENT (VTT -1.5A TO 1.5A) FIGURE 12. POWER-UP WAVEFORMS
FIGURE 13. POWER-DOWN WAVEFORMS FIGURE 14. VDDQ START-UP AND SHUTDOWN INTO HEAVY
LOAD, DISCHARGE DISABLED
Typical Operating Characteristics VIN = 12V, VDDQ = 1.8V, tON = GND, SKIP# = AVDD, circuit of Figure 29, TA = +25°C,
unless otherwise noted. (Continued)
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
LOAD (A)
VTTR (mV)
-0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04
VDDQ
100mV/DIV
VTT
100mV/DIV
VTTR
100mV/DIV
IVDDQ
10A/DIV
20µs/DIV
IVTT = 1.5A, IVTTR = 15mA
10A
0A
IVDDQ = 12A, IVTTR = 15mA
20µs/DIV
VDDQ
100mV/DIV
VTT
100mV/DIV
VTTR
100mV/DIV
IVTT
2A/DIV
100µs/DIV
VDDQ
1V/DIV
VTT
1V/DIV
VTTR
1V/DIV
VIN
10V/DIV
VDD = 5V, IVDDQ = 12A, IVTT = 1.5A, IVTTR = 15mA
100µs/DIV
VDDQ
1V/DIV
VTT
1V/DIV
VTTR
1V/DIV
VIN
10V/DIV
VDD = 5V, IVDDQ = 12A, IVTT = 1.5A, IVTTR = 15mA
1ms/DIV
VDDQ
1V/DIV
VTT
500mV/DIV
POK1
5V/DIV
SHDNA#
5V/DIV
IVDDQ = 12A, IVTT = 1.5A
ISL88550A
10 FN6168.3
April 23, 2008
FIGURE 15. VDDQ ST ART -UP AND SHUTDOWN INTO LIGHT
LOAD, DISCHARGE ENABLED FIGURE 16. VTT, VTTR START-UP AND SHUTDOWN
FIGURE 17. OVERVOL TAGE AND TURN-OFF OF BUCK
OUTPUT FIGURE 18. SHORT CIRCUIT AND RECOVERY OF VDDQ
FIGURE 19. SHORT CIRCUIT A ND RECOVERY OF VDDQ FIGURE 20. SHORT CIRCUIT AND RECOVERY OF VTT
Typical Operating Characteristics VIN = 12V, VDDQ = 1.8V, tON = GND, SKIP# = AVDD, circuit of Figure 29, TA = +25°C,
unless otherwise noted. (Continued)
2ms/DIV
VDDQ
1V/DIV
VTT
500mV/DIV
POK1
5V/DIV
SHDNA#
5V/DIV
RVDDQ = 10Ω, RVTT = 20Ω
200µs/DIV
VTT
500mV/DIV
VTTR
500mV/DIV
POK2
1V/DIV
STBY#
5V/DIV
IVTT = 1.5A, IVTTR = 15mA
50µs/DIV
UGATE
2V/DIV
VDDQ
500mV/DIV
LGATE
2V/DIV
VTT
500mV/DIV
100µs/DIV
VDDQ
1V/DIV
IVDDQ
10A/DIV
VIN
10V/DIV
IIN
5A/DIV
UVP DISABLE, FOLDBACK CURRENT LIMIT
50µs/DIV
VDDQ
1V/DIV
IVDDQ
10A/DIV
VIN
10V/DIV
IIN
5A/DIV
UVP ENABLE
100µs/DIV
VTT
500mV/DIV
IVTT
2A/DIV
ISL88550A
11 FN6168.3
April 23, 2008
ON-TIME
COMPUTE
TRIG
1-SHOT
tON
Q
TRIG
tOFF
Q1-SHOT
+
-
INTREF
INTREF
1.16 x
QUAD LEVEL
DECODER
BLANK
OVP/UVP
LATCH
+
-
+
-
VDD - 1V
1.0V
PHASE
PHASE
ZERO CROSSING
BUCK ON/OFF
BIAS
VTT ON/OFF
VTTR ON/OFF
+
-
20ms
TIMER
POR
0.7 x INTREF
+
-
+
-
INTREF+10%
INTEREF-10%
NFB
DECODER
VOUT = 2.5V DISCHARGE
LOGIC
VDD
2V
REFERENCE
INTREF
+
-
+
-
INTREF/2 + 10%
+
-
+
-
INTREF/2 + 10%
INTEREF/2 - 10%
N
+
-
OUT 0.1V
POWER-DOWN
N
+
-
+
-
N
N
VDD
VDD
CURRENT
LIMIT
REFIN/2
OUT
PGND2
VTT ILIM
VIN
LGATE
PGND1
ILIM
OUT
SKIP#
AVDD
GND
REF
VTTS
REFIN
VTTI
VTT
PGND2
VTTR
SS
POK2
FB
POK1
STBY#
SHDNA#
OVP/UVP
TON
S
RQ
S
RQ
+
-
SHUTDOWN
DECODER
10Ω
10kΩ
10kΩ
BOOT
UGATE
PHASE
VDD
+
+
ON/OFF
INTEREF/2% - 10%
FIGURE 21. FUNCTIONAL BLOCK DIAGRAM
+
+
-
+
-
ISL88550A
12 FN6168.3
April 23, 2008
Detailed Description
The ISL88550A combines a synchronous buck PWM
controller, an LDO linear regulator, and a 10mA referen ce
output. The buck controller drives two external N-Channel
MOSFETs to deliver load currents up to 15A and generates
voltages down to 0.7V from a +2V to +25V input. The LDO
Linear Regulator can source up to 2.5A and sink up to -2.0A
continuously. These features make the ISL88550A ideally
suited for DDR memory application.
The ISL88550A buck regulator is equipped with a fixed
switching frequency up to 600kHz constant on-time PWM
architecture. This control scheme handles wide input/output
voltage ratios with ease, and provides 100ns “instant-on”
response to load transients while maintaining high efficiency
with relatively constant switching frequency.
The buck controller (LDO) and buffered reference output are
provided with independent current limits. Lossless fold-back
current limit in the buck regulator is achieved by monitoring
the drain to source voltage drop of the low side FET. The
ILIM input is used to adjust this current limit. Overvoltage
protection is achieved by latching the low side synchro nous
FET on and the high side FET off when the output voltage is
over 116% of its set output. It also features an optional
undervoltage protection by latching the MOSFET drivers to
the OFF state during an overcurrent condition when the
output voltage is lower than 70% of the regulated output.
Once the overcu rre n t con d i ti on is rem ove d , th e re gu l at o r is
allowed to soft-start again. This helps minimize power
dissipation during a short circuit condition.
The current limit in the LDO and buffered reference output is
+3.0A/-2.5A and ±40mA respectively and neither have the
overvoltage or undervoltage protection. When the current
limit in either output is reached, the output no longer
regulates the voltage, but will regulate the current to the
value of the current limit.
+5V Bias Supply (VDD and AVDD)
The ISL88550A requires an external +5V bias supply in
addition to the input voltage (VIN). Keeping the bias supply
external to the IC improves the efficiency and eliminates the
cost associated with the +5V linear regulator th at would
otherwise be needed to supply the PWM circuit and the gate
drivers. VDD, AVDD and VIN can be connected together if
the input source is a fixed +4.5V to +5.5V sup ply.
VDD is the supply input for the Buck regulator’s MOSFET
drivers, and AVDD supplies the pow er for the rest of the IC.
The current from the AVDD and VDD power supply must
supply the current for the IC and the gate drive for the
MOSFET’s. This maximim current can be estimated in
Equation 1:
Where IVDD + IAVDD are the quiescent supp l y c urre n ts into
VDD; AVDD, QG1 and QG2 are the total gate charges of
MOSFETs Q1 and Q2 (at VGS = 5V) in the "Typical
Application Circuit" on page 22, and fSW is the switching
frequency.
Free-Running Constant-ON-Time PWM
The constant ON-time PWM control architecture is a pseudo
fixed frequency, constant on-time, current-mode regulator
with voltage feed forward (Figure 21). This architecture relies
on the output filter capacitor’s ESR to act as a current-sense
resistor , so the output ripple voltage provides the PWM ramp
signal. The control algorithm is simple: the high-side switch
ON-time is determined solely by a one-shot whose pulse
width is inversely proportional to input voltage and dire ctly
proportional to the output voltage. Another one-shot sets a
minimum off-time of 300ns typically. The ON-time one-shot
is triggered if the error comparator is low , the low-side switch
current is below the valley current-limit threshold, and the
minimum off-time one-shot has timed out.
ON-Time One Shot (tON)
The heart of the PWM core is the one-shot that sets the
high-side switch ON-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the ON-time in
response to input and output voltages. The high-side switch
ON-time is inversely proportional to the input voltage (VIN)
and is proportional to the output voltage, as shown in
Equation 2:
where K (the ON-time scale factor) is set by the tON input
connection (Table 1) and rDS(ON)Q2 is the ON-resistance of
the synchronous rectifier (Q2) in the "Typical Application
Circuit" on page 22. This algorith m results in a nearly
constant switching frequency despite the lack of a fixed
frequency clock generator . The benefits of a constant
switching frequency are two-fold:
1. The frequency can be selected to avoid noise-sensitive
regions such as the 455kHz IF band.
2. The inductor ripple-curre nt operating point remains
relatively constant, resulting in an easy design
methodology and predictable output voltage ripple.
The ON-time one-shot has good accuracy at the operating
points specified in the “Electrical Specifications” table
(approximately ±12.5% at 600kHz and 450kHz and ±10% at
200kHz and 300kHz) on page 3. ON-times at operating
points far removed from the conditions specified in the
“Electrical Specifica ti ons” table on page 3 can vary over a
wider range. For example, the 600kHz setting typically runs
approximately 10% slower with inputs much greater than 5V
due to the very short ON-times required.
The constant ON-time translates only roughly to a constant
switching frequency. The ON-times guaranteed in the
()
2G1GSWAVDDVDDBIAS QQxfIII +++= (EQ. 1)
()
(
)
IN
QONDSLOADOUT
on V
rIV
Kt 2
×
+
×= (EQ. 2)
ISL88550A
13 FN6168.3
April 23, 2008
“Electrical Specifications” table on page 3 are influe nced by
resistive losses and by switching delays in the high-side
MOSFET. Resistive losses, which include the indu ctor, both
MOSFETs, the output capacitors ESR, and any PC board
copper losses in the output a nd ground , tend to raise the
switching frequency as the load incre ases. The de ad-time
effect increases the ef fective ON -time, reduci ng the switching
frequency as one or both dead times are added to the
effective ON-time. The d ead time occurs only in PWM mode
(SKIP# = VDD) and during dynamic output volt age transitions
when the inductor current reverses at light or negative load
currents. With reversed inductor current, the inductor’s EMF
causes PHASE to go high earlier than normal, extending the
ON-time by a period equal to the UGATE-rising dead time. For
loads above the critica l conduction point, where the dead-time
effect is no longer a factor, the actual switching frequency is
shown in Equation 3:
where VDROP1 is the sum of the parasitic voltage drops in
the inductor disch arge path, including the synchronous
rectifier, the inductor, and any PC board resistances;
VDROP2 is the sum of the resistances in the charging path,
including the high-side switch (Q 1 in "Typical Application
Circuit" on page 22), the inductor and any PC board
resistances, and tON is the one-shot on-time (see “ON-Time
One Shot (tON)” on page 12).
Automatic Pulse-Skipping Mode (SKIP# = GND)
In skip mode, (SKIP# = GND), an inherent automatic
switchover to PFM takes place at light loads (Figure 22).
This switchover is affected by a comparator that truncates
the low-side switch ON-time at the inductor current’s zero
crossing. The zero-crossing comparator differentially senses
the inductor current across the syn c hronous rectifier
MOSFET (Q2 in "Typical Application Circuit" on page 2 2).
Once VPGND - PHASE drops below 5% of the current-limit
threshold (3mV for the default 50mV current-limit threshold),
the comparator forces LGATE lo w (see “Functional Block
Diagram” on page 11, Figure 21). This mech anism causes
the threshold between pulse-skipping PFM and nonskipping
PWM operation to coincide with the boundary between
continuous and discontinuous inductor-current operation
(also known as the critical conduction point). The load
current level at which PFM/PWM crossover occurs,
ILOAD(SKIP), is equal to one-half the peak-to-peak ripple
current, which is a function of the inductor value (see
Figure 22). This threshold is relatively constant, with only a
minor dependence on the input voltage (VIN).
where K is the ON-time scale factor (see Table 1). For
example, in the “Typical Applications Circuit” on page 22
(K =1.7µs, VOUT = 2.5V, VIN = 12V, and L = 1µH), the
pulse-skipping switchover occurs in Equation 5:
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used. The switching
waveforms can appear noisy an d asynchronous when light
loading causes pulse-skipping operation, but this is a normal
operating condition that results in high light-load efficiency.
Trade-offs in PFM noise vs light-load efficiency are made by
selection of inductor value. Generally, low inductor values
produce a broader efficiency vs load curve, while higher
values result in higher full-load efficiency (assuming that the
coil resistance remains fixed), and less output voltage ripple.
Penalties for using higher inducto r values include larger
physical size and degraded load-transient response,
especially at low input voltage leve ls.
DC output accuracy specifications refer to the threshol d of
the error comparator. When the inductor is in continuous
conduction, the ISL88550A regulates the valley of the output
ripple, so the actual DC output voltage is higher than the trip
level by 50% of the output ripple voltage. In discontinuous
conduction (SKIP# = GND and ILOAD < ILOAD(SKIP)), the
output voltage has a DC regulation level higher than the
error comparator threshold by approximately 1.5% due to
slope compensation.
()
2DROPINON
1DROPOUT
SW VVt VV
f+
+
=(EQ. 3)
()
×
=IN
OUTINOUT
SKIPLOAD VVV
L2 KV
I(EQ. 4)
A68.1
V12 V5.2V12
µH12 µs7.1V5.2 =
⎛−
×
×(EQ. 5)
ON-TIME TIME
I
L
VIN - VOUT
Δ I
t=
0
IPEAK
=
INDUCTOR CURRENT
ILOAD = IPEAK/2
FIGURE 22. PULSE SKIPPING/DISCONTINUOUS
CROSSOVER POINT
ISL88550A
14 FN6168.3
April 23, 2008
Force PWM Mode (SKIP# = AVDD)
The low-noise forced-PWM mode (SKIP# = AVDD) disables
the zero-crossing comparator, which controls the low-side
switch ON-time. This forces the low-side gate drive
waveform to constantly be the complement of the high-side
gate-drive waveform, so the inductor current reverses at light
loads while UGATE maintains a duty factor of VOUT/VIN.
Forced-PWM mode keeps the switching freq uency fairly
constant. However, forced-PWM operation comes at a cost
where the n o-l o ad VDD bias current remains between 2mA
and 20mA due to the external MOSFETs gate charge and
switching frequency. Forced-PWM mode is most useful for
reducing audio freque ncy noise, improving load-transient
response, and providing sink current capability for dynamic
output voltage adjustment.
Current Limit Buck Regulator (ILIM)
VALLEY CURRENT LIMIT
The current-limit circuit for the Buck Regulator portion of the
ISL88550A employs a unique “valley” cu rrent sensing
algorithm that senses the voltage drop across PHASE and
PGND1 and uses the ON-resistance of the rectifying
MOSFET (Q2 in the "T ypical Application Circuit" on page 22)
as the current sensing element. If the magnitude of the
current sense signal is above the valley current-limit
threshold, the PWM controller is not allowed to initiate a new
cycle (Figure 23). With Valley Current Limit sensing, the
actual peak current is greater than the valley current-limit
threshold by an amount equal to the inductor current ripple.
Therefore, the exact current limit characteristic and
maximum load capability are a function of the current-sense
resistance, inductor value and input voltage. When
combined with the undervoltage protection circuit, this
current-limit method is effective in almost every
circumstance.
In forced-PWM mode, the ISL88550A also implements a
negative current limit to prevent excessive reverse inductor
currents when the Buck Regulator output is sinking current.
The negative current-lim it threshold is set to approximately
120% of the positive current limit and tracks the positive
current limit when VILIM is adjusted. The current-limit
threshold is adjusted with an external resistor-divider at ILIM.
A 2µA to 20µA divider current is recommended for accuracy
and noise immunity.
The current-limit threshold adjustment range is from 25mV to
200mV. In the adjustable mode, the current limit threshold
voltage (from PHASE to PGND1) is precisely 1/10th the
voltage seen at ILIM. The threshold defaults to 50mV when
ILIM is connected to AVDD. The logic threshold for
switchover to the 50mV default value is approximately
AVDD -1V.
Carefully observe the PC board layout guidelines to ensure
that noise and DC errors do not corrupt the differential
current-sense signals seen between PHASE and PGND1.
TABLE 1. APPROXIMATE K-FACTOR ERRORS
tON SETTING TYPICAL K
FACTOR (µs)
K-FACTOR
ERROR
(10%)
MINIMUM VIN AT VOUT = 2.5V
(h = 1.5, SEE DROPOUT
PERFORMANCE SECTION) TYPICAL
APPLICATION COMMENTS
200kHz
(tON = AVDD)5.0 ±10 3.15 4-Cell Li+
Notebook Use for absolute best efficiency
300kHz
(tON = OPEN) 3.3 ±10 3.47 4-Cell Li+
Notebook Considered mainstream by current
standards
450kHz
(tON = REF) 2.2 ±12.5 4.13 3-Cell Li+
Notebook Useful in 3-cell systems for lighter loads
600kHz
(tON = GND) 1.7 ±12.5 5.61 +5V input Good operating point for compound
buck designs or desktop circuits.
ISL88550A
15 FN6168.3
April 23, 2008
POR, UVLO and Soft-Start
Internal Power-on reset (POR) occurs when AVDD rises
above approximately 2V, resetting the fault latch and the
soft-start counter, powering up the reference and preparing
the Buck Regulator for operation. Until AVDD reaches 4.25V
(typical), A VDD undervoltage lockout (UVLO) circuitry inhibits
switching. The controller inhibits switching by pulling UGA TE
low and holding LGATE low when OVP and shutdown
discharge are disabled (OVP/UVP = REF or GND) or forcing
LGATE high when OVP and shutdown discharge are
enabled (OVP/UVP = AVDD or OPEN). See Table 3 for
detailed truth table for OVP/UVP and Shutdown settings.
When AVDD rises above 4.25V, the controller activates the
Buck Regulator and initializes the internal soft-start. The
Buck Regulator’s internal soft-start allows a gradual increase
of the current limit level during start-up to reduce the input
surge currents. The ISL88550A divides the soft-start period
into five phases. During the first phase, the controller limits
the current limit to only 20% of the full current limit. If the
output does not reach regulation within 425µs, soft-start
enters the second phase and the current limit is increased by
another 20%. This process repeats until the maximum
current limit is reached after 1.7ms, or when the output
reaches the nominal regulation voltage, whichever occurs
first. Adding a capacitor in parallel with the external ILIM
resistors creates a continuously adjustable analog soft-start
function for the Buck Regulator’s output.
For most applications, LDO soft-start is not necessary
because output charging current is limited to approximately
3.0A. For 20µF LDO output capacitors, the minimum rise
time is about 30µs. However, soft-start in the LDO section
can be realized by tying a capacitor between the SS pin and
GND. When STBY# is driven low, or during thermal
shutdown of the LDO’s, the SS capacitor is discharged.
When STBY# is driven high or when the ther mal limit is
removed, an internal 4µA (typical) curren t charges the SS
capacitor. The resulting linear ramp voltage on SS linearly
increases the current-limit comparator thresholds to both the
VTT and VTTR outputs until full current limit is attained when
SS reaches approximately 1.6V. This lowering of the current
limit during start-up limits the initial in-rush current peaks,
particularly when driving higher output capacitances. For
good tracking, choose the value of the SS capacitor less
than 390pF. Leave SS floating to disable the soft-start
feature.
Power OK (POK1)
POK1 is an open-drain output for a window comparator that
continuously monitors VOUT. POK1 is actively held low when
SHDNA# is low and during the Buck Regulato r outputs
soft -start. After the digital soft-start terminates, POK1
becomes high impedance as long as the output voltage is
within ±10% of the nominal regulation voltage set by FB.
When VOUT drops 10% below or rises 10% above the
+
-
+
-
VDD - 1V
1.0V
LX
ILIM
ISL88550A
REF
9R
RRA
RBCILIM
CREF
FIGURE 23. ADJUSTABLE CURRENT LIMIT THRESHOLD
+
+
-
-
ILIMIT
ILOAD
IPEAK
INDUCTOR CURRENT
ILOAD(MAX)
Δ I
FIGURE 24. VALLEY CURRENT-LIMIT THRESHOLD
ISL88550A
16 FN6168.3
April 23, 2008
nominal regulation voltage, the ISL88550A pulls POK1 low.
Any fault condition forces POK1 low until the fault latch is
cleared by toggling SHDNA# or cycling AVDD power below
1V. For logic level output voltages, connect an external
pull-up resistor between POK1 and AVDD. A 100kΩ resistor
works well in most applications. Note that the POK1 window
detector is completely independent of the overvoltage and
undervoltage protection fault detectors and the state of
VTTS and VTTR.
SHDNA# and Output Discharge
The SHDNA# input corresponds to the Buck Reg ulator and
places the Buck Regulator’s portion of the IC in a low power
mode (see “Electrical Specifications” table on page 3).
SHDNA# is also used to reset a fault signal such as an
overvoltage or undervoltage fault.
When output discharge is enabled (OVP/UVP = AVDD or
open) and SHDNA# is pulled low, or if UVP is enabled
(OVP/UVP = AVDD) and VOUT falls to 70% of its regulation
set point, the ISL88550A discharges the Buck Regulator
output (via the OUT input) th rough an internal 15Ω switch to
ground. While the output is discharging, the PWM controller
is disabled, but the reference remains active to provide an
accurate threshold.
When output discharge is disabled (OVP/UVP = REF or
GND), the controller does not actively discharge the Buck
Output. Under these conditions, the Buck Output discharge
rate is determined by the load current and its output
capacitance. The Buck Regulator detects and latches the
discharge mode state set by OVP/UVP setting on start-up.
STBY#
The STBY# input is an active low input that is used to
shutdown only the VTT output. When STBY# is low, VTT is
high impedance, but the VTTR output is still active if
SHDNA# is high. VTT and VTTR are pulled to 0V when
SHDNA is low.
Power OK (POK2)
POK2 is the open-drain output for a window comparator that
continuously monitors the VTTS input and VTTR output.
POK2 is high impedance as long as the output voltage is
within ±10% of the nominal regulation voltage as set by
REFIN. When VVTTS or VVTTR rise 10% above or 10 %
below their nominal regulation voltage, the ISL88550A pulls
POK2 low. For logic level output voltages, connect an
external pull-up resistor between POK2 and AVDD. A 100kΩ
resistor works well in most applications. Note that the POK2
window detector is completely indep endent of the
overvoltage and undervoltage protection fault detectors and
the state of VDDQ.
Current Limit (LDO for VTT and VTTR Buffer)
The VTT output is a linear regulator that regulates the input
(VTTI) to ½ the VREFIN voltage. The feedback point for VTT
is at the VTTS input (see Figure 21). VTT is capable of
sourcing up to 2.5A and sinking up to -2.0A continuously.
The current limit for VTT and VTTR is typically +3.0A/-2.5A
and ±40mA respectively. When the current limit for either
output is reached, the outputs regulate the current not the
voltage. The current limits for both VTT and VTTR can be
reduced from their full values by forcing the voltage at the SS
pin below 1.6V (typical), or by tying a resistor (RSS) between
the SS pin and ground such that 4µA*RSS is less than 1.6V.
POK2 is pulled low when REFIN is <0.8V.
Fault Protection
The ISL88550A provides over voltage/undervol tage fault
protection in the buck controller. Select OVP/UVP to enable
and disable fault protection as shown in Table 3. Once
activated, the controller continuously monitors the output for
undervoltage and overvoltage fault conditions. Any VDDQ
shutdown due to OVP, UVP, OTP or SHDNA# = 0 should
also discharge VTT to 0V.
Overvoltage Protection (OVP)
When the output voltage rises above 114% of the nominal
regulation voltage and OVP is enabled (OVP/UVP = AVDD
or open), the OVP circuit sets the fault latch, shuts down the
PWM controller and immediately pulls UGATE low and
forces LGAT E high. Thi s turns on the synchronous rectifier
MOSFET with 100% duty cycle, rapidly discharging the
output capacitor and clamping the output to ground. Note
that immediately latching LGATE high can cause the output
voltage to go slightly negative due to energy stored in the
output LC circuit at the instant the OVP occurs. If the load
cannot tolerate a negative voltage, place a power Schottky
diode across the output to act as a reverse polarity clamp.
Toggle SHDNA# or cycle AVDD power below 1V to clear the
fault latch and restart the controller . OVP is disabled when
OVP/UVP is connected to REF or GND (see Table 3). OVP
only applies to the Buck Output. The VTT and VTTR Outputs
do not have overvoltage protection. When VDDQ is
discharged to 0V due to OVP, VTT is also discharged to 0V.
TABLE 2. SHUTDOWN AND STANDBY CONTROL LOGIC
SHDNA# STBY# BUCK
OUTPUT VTT VTTR
GND X OFF OFF
(Discharge to
0V)
OFF
(Tracking ½
REFIN)
AVDD GND ON OFF
(High
Impedance)
ON
AVDD AVDD ON ON ON
ISL88550A
17 FN6168.3
April 23, 2008
Undervoltage Protection (UVP)
When the output voltage drops below 70% of its regulation
voltage and UVP is enabled (OVP/UVP = A VDD or REF), the
controller sets the fault latch and begins the discharge mode
(see “SHDNA# and Output Discharge” on page 16). UVP is
ignored for 14ms (minimum) after start-up or after a rising
edge on SHDNA#. Toggle SHDNA# or cycle AVDD power
below 1V to clear the fault latch and restart the controller.
UVP is disabled when OVP/UVP is left open or connected to
GND (see Table 3). UVP only applies to the Buck Output.
The VTT and VTTR Outputs do not have undervoltage
protection. When VDDQ is discharged to 0V due to UVP,
VTT is also discharged to 0V.
Thermal Fault Protection
The ISL88550A features a thermal fault protection circuit,
which monitors the Buck Regulator of the IC, the Linear
Regulator (VTT) and the buffered output (VTTR). When the
junction temperature of the ISL88550A rises above +150°C,
a thermal sensor activates the fault latch, pulls POK1 low
and shuts down the buck converter using discharge mode
regardless of the OVP/UVP setting, and VTT is also
discharged to 0V. Toggle SHDNA# or cycle AVDD power
below 1V to reactivate the controller after the junction
temperature cools by +15°C.
Design Procedure
Firmly establish the input voltage range (VIN) and maximum
load curren t in th e bu ck regulator before cho o si ng a
switching frequency and inductor operating poi nt
(ripple-current ratio or LIR). The primary design trade-off lies
in choosing a good switching frequency and inductor
operating point, and the following four factors dictate the rest
of the design.
Input Voltage Range
The maximum value (VIN (MAX)) must accommodate the
worst-case, high AC adapter voltage. The minimum value
(VIN (MIN)) must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector
switches. If there is a choice, lower input voltages result in
better efficiency.
Maximum Load Current
There are two values to consider. The peak load current
(IPEAK) determines the instantaneous component stresses
and filtering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current (ILOAD)
determines the thermal stresses and thus drives the
selection of input capacitors, MOSFETs, and other critical
heat-contributing components.
Switching Frequency
This choice determines the basic trade-off between size and
efficiency. The optimal frequency is largely a function of
maximum input voltage, due to MOSFET switching losses
proportional to frequency and VIN2. The optimum frequency
is also a moving target, due to rapid improvements in
MOSFET technology that are making hig her frequencies
more practical.
Inductor Operating Point
This choice provides trade-offs: size vs efficiency and
transient response vs output ripple. Low inductor values
provide better transient response and smaller physical size
but also result in lower efficiency and higher output ripple
due to increased ripple currents. The minimum practical
inductor value is one that causes the circuit to operate at the
edge of critical conduction (where the inductor current just
touches zero with every cycle at maximum load). Inductor
values lower than this grant no further size-reduction benefit.
The optimum operating point is usually found between 20%
and 50% ripple current. When pulse skipping (SKIP# = low
at light loads), the inductor value also determines the load
current value at which PFM/PWM switchover occurs.
Setting the Output Voltage (Buck)
Preset Output Voltages
The ISL88550A allows the selecti on of common voltages
without requiring external components (Figure 25). Connect
FB to GND for a fixed 2.5V output, or connect FB directly to
OUT for a fixed 0.7 V out put.
TABLE 3. OVP/UVP FAULT PROTECTION
OVP/UVP DISCHARGE UVP PROTECTION OVP PROTECTION
AVDD 15Ω internal switch ON
UGATE/LGATE is low when SHDNA# = low for normal
shutdown
Enabled Enabled.
UGATE pulled low and LGATE forced high if
OVP detected
OPEN 15Ω internal switch ON
UGATE/LGATE is low when SHDNA# = low for normal
shutdown
Disabled Enabled.
UGATE pulled low and LGATE forced high if
OVP detected
REF 15Ω internal switch OFF
UGATE/LGATE is low when SHDNA# = low Enabled Disabled
GND 15Ω internal switch OFF
UGATE/LGATE is low when SHDNA# = low Disabled Disabled
ISL88550A