a Low Power 20 mW 2.3 V to 5.5 V Programmable Waveform Generator AD9833 FEATURES Digitally Programmable Frequency and Phase 20 mW Power Consumption at 3 V 0 MHz to 12.5 MHz Output Frequency Range 28-Bit Resolution (0.1 Hz @ 25 MHz Ref Clock) Sinusoidal/Triangular/Square Wave Outputs 2.3 V to 5.5 V Power Supply No External Components Required 3-Wire SPI(R) Interface Extended Temperature Range: -40C to +105C Power-Down Option 10-Lead MSOP Package GENERAL DESCRIPTION The AD9833 is a low power programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits; with a 25 MHz clock rate, resolution of 0.1 Hz can be achieved. Similarly, with a 1 MHz clock rate, the AD9833 can be tuned to 0.004 Hz resolution. The AD9833 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V. APPLICATIONS Frequency Stimulus/Waveform Generation Liquid and Gas Flow Measurement Sensory Applications--Proximity, Motion, and Defect Detection Line Loss/Attenuation Test and Medical Equipment Sweep/Clock Generators TDR The AD9833 has a power-down function (SLEEP). This allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part, e.g., the DAC can be powered down when a clock output is being generated. The AD9833 is available in a 10-lead MSOP package. FUNCTIONAL BLOCK DIAGRAM DGND AGND VDD CAP/2.5V ON-BOARD REFERENCE REGULATOR MCLK AVDD/ DVDD FULL-SCALE CONTROL 2.5V FREQ0 REG PHASE ACCUMULATOR (28-BIT) MUX FREQ1 REG 12 SIN ROM COMP 10-BIT DAC MUX MSB PHASE0 REG PHASE1 REG MUX DIVIDE BY 2 VOUT MUX CONTROL REGISTER R 200 SERIAL INTERFACE AND CONTROL LOGIC FSYNC SCLK AD9833 SDATA REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD9833-SPECIFICATIONS* Parameter Min SIGNAL DAC SPECIFICATIONS Resolution Update Rate VOUT Max VOUT Min VOUT TC DC Accuracy Integral Nonlinearity Differential Nonlinearity Typ Max Unit 10 0.65 38 200 1.0 0.5 LSB LSB dB dBc fMCLK = 25 MHz, fOUT = fMCLK/4096 fMCLK = 25 MHz, fOUT = fMCLK/4096 -60 -78 -60 1 dBc dBc dBc ms fMCLK = 25 MHz, fOUT = fMCLK/50 fMCLK = 25 MHz, fOUT = fMCLK/50 2.3 V to 2.7 V Power Supply 2.7 V to 3.6 V Power Supply 4.5 V to 5.5 V Power Supply 2.3 V to 2.7 V Power Supply 2.7 V to 3.6 V Power Supply 4.5 V to 5.5 V Power Supply 3 V V V V V V mA pF 60 -66 -56 1.7 2.0 2.8 VINL, Input Low Voltage 0.5 0.7 0.8 10 IINH/IINL, Input Current CIN, Input Capacitance POWER SUPPLIES VDD IDD Low Power Sleep Mode Test Conditions/Comments Bits MSPS V mV ppm/C 25 DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio 55 Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) Narrow Band ( 200 kHz) Clock Feedthrough Wake-Up Time LOGIC INPUTS VINH, Input High Voltage (VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 k for VOUT, unless otherwise noted.) fMCLK = 25 MHz, fOUT = fMCLK/4096 2.3 5.5 5.5 4.5 0.5 V mA mA IDD Code Dependent. See TPC 2. DAC Powered Down, MCLK Running *Operating temperature range is as follows: B Version: -40C to +105C; typical specifications are at 25C. Specifications subject to change without notice. 100nF VDD 10nF CAP/2.5V REGULATOR COMP 12 SIN ROM VOUT 10-BIT DAC 20pF AD9833 Figure 1. Test Circuit Used to Test Specifications -2- REV. A AD9833 TIMING CHARACTERISTICS* (VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.) Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 t7 t8 min t8 max t9 t10 t11 40 16 16 25 10 10 5 10 t4 - 5 5 3 5 ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min MCLK Period MCLK High Duration MCLK Low Duration SCLK Period SCLK High Duration SCLK Low Duration FSYNC to SCLK Falling Edge Setup Time FSYNC to SCLK Hold Time Data Setup Time Data Hold Time SCLK High to FSYNC Falling Edge Setup Time *Guaranteed by design, not production tested. Specifications subject to change without notice. t1 MCLK t2 t3 Figure 2. Master Clock t5 t11 t4 SCLK t7 t6 t8 FSYNC t10 t9 SDATA D15 D14 D2 D1 Figure 3. Serial Timing REV. A -3- D0 D15 D14 AD9833 ABSOLUTE MAXIMUM RATINGS* (TA = 25C, unless otherwise noted.) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V CAP/2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V Digital I/O Voltage to DGND . . . . . . -0.3 V to VDD + 0.3 V Analog I/O Voltage to AGND . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C MSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD9833BRM AD9833BRM-REEL AD9833BRM-REEL7 EVAL-AD9833EB -40C to +105C -40C to +105C -40C to +105C 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board RM-10 RM-10 RM-10 DJB DJB DJB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9833 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. A AD9833 PIN CONFIGURATION 10 VOUT COMP 1 VDD 2 AD9833 9 AGND 8 FSYNC TOP VIEW DGND 4 (Not to Scale) 7 SCLK CAP/2.5V 3 MCLK 5 6 SDATA PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function Power Supply 2 VDD Positive Power Supply for the Analog and the Digital Interface Sections. The on-board 2.5 V regulator is also supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 mF and a 10 mF decoupling capacitor should be connected between VDD and AGND. 3 CAP/2.5 V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board regulator (when VDD exceeds 2.7 V). The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5 V to DGND. If VDD is equal to or less than 2.7 V, CAP/2.5 V should be tied directly to VDD. 4 DGND Digital Ground. 9 AGND Analog Ground. Analog Signal and Reference 1 COMP A DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. 10 VOUT Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor is not required because the device has a 200 W resistor on board. Digital Interface and Control 5 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. 6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input. 7 SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge. 8 FSYNC Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device. REV. A -5- AD9833-Typical Performance Characteristics 5.5 5.5 -60 TA = 25C T A = 25C 5V 5.0 5.0 AVDD = 3V TA = 25C -65 5V 3V 4.0 3V 4.0 SFDR dB MCLK/7 -80 SFDR dB MCLK/50 -85 3.0 0 5 10 15 20 1 25 10 100 1k 10k 100k -90 1M 0 VDD = 3V TA = 25C -10 -45 -30 -60 -50 MCLK 18MHz MCLK 1MHz -60 SFDR dB MCLK/50 25 TA = 25C VDD = 3V fOUT = MCLK/4096 -50 MCLK 10MHz SNR (dB) SFDR (dB) SFDR dB MCLK/7 -55 -40 20 -40 VDD = 3V TA = 25C -20 -50 15 TPC 3. Narrow-Band SFDR vs. MCLK Frequency 0 -40 10 MCLK FREQUENCY (MHz) TPC 2. Typical IDD vs. fOUT for fMCLK = 25 MHz TPC 1. Typical Current Consumption vs. MCLK Frequency -45 5 fOUT (Hz) MCLK (MHz) SFDR (dBc) -75 3.5 3.5 3.0 4.5 SFDR (dBc) IDD (mA) I DD (mA) -70 4.5 -55 -60 -70 -65 -65 -80 MCLK 25MHz -70 5 7 9 11 13 15 17 19 21 -90 0.001 23 25 0.01 0.1 1 10 100 fOUT/f MCLK MCLK FREQUENCY (MHz) TPC 5. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies TPC 4. Wideband SFDR vs. MCLK Frequency 1000 -70 1.0 5.0 10 12.5 MCLK FREQUENCY (MHz) 25 TPC 6. SNR vs. MCLK Frequency 1.250 950 1.200 800 VREFOUT (V) WAKE-UP TIME (s) 2.3V 850 750 UPPER RANGE 1.225 900 5.5V 700 650 1.175 LOWER RANGE 1.150 600 1.125 550 500 -40 25 TEMPERATURE (C) TPC 7. Wake-Up Time vs. Temperature 105 1.100 -40 25 TEMPERATURE (C) 105 TPC 8. VREFOUT vs. Temperature -6- REV. A 0 0 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 0 RWB 100 VWB 30 FREQUENCY (Hz) 100k ST 100 SEC -90 -100 0 RWB 1K TPC 9. fMCLK = 10 MHz, fOUT = 2.4 kHz, Frequency Word = 000FBA9 5M ST 50 SEC VWB 300 FREQUENCY (Hz) -100 0 RWB 1K TPC 10. fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 2492492 0 0 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 dB 0 -50 -50 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 VWB 30 FREQUENCY (Hz) 100k ST 100 SEC -90 -100 0 RWB 300 VWB 100 FREQUENCY (Hz) 1M ST 100 SEC -100 0 RWB 1K TPC 13. fMCLK = 25 MHz, fOUT = 60 kHz, Frequency Word = 009D495 TPC 12. fMCLK = 25 MHz, fOUT = 6 kHz, Frequency Word = 000FBA9 0 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 dB 0 -10 dB 0 -50 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC TPC 15. fMCLK = 25 MHz, fOUT = 2.4 MHz, Frequency Word = 189374D REV. A 0 RWB 1K VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC TPC 16. fMCLK = 25 MHz, fOUT = 3.857 MHz = fMCLK/7, Frequency Word = 2492492 -7- 12.5M ST 100 SEC -50 -60 0 RWB 1K VWB 300 FREQUENCY (Hz) TPC 14. fMCLK = 25 MHz, fOUT = 600 kHz, Frequency Word = 0624DD3 -10 -50 5M ST 50 SEC -50 -60 -100 0 RWB 100 VWB 300 FREQUENCY (Hz) TPC 11. fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 5555555 -10 dB dB -50 -60 -100 dB dB 0 -10 dB dB AD9833 0 RWB 1K VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC TPC 17. fMCLK = 25 MHz, fOUT = 8.333 MHz = fMCLK/3, Frequency Word = 5555555 AD9833 TERMINOLOGY Integral Nonlinearity THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a(t) = sin(t). However, these are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of = 2f. This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01), and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. Differential Nonlinearity MAGNITUDE This is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. +1 6 0 4 2 Output Compliance The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9833 may not meet the specifications listed in the data sheet. -1 2 PHASE 4 6 2p 0 Spurious-Free Dynamic Range Figure 4. Sine Wave Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The spurious-free dynamic range (SFDR) refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of 200 kHz about the fundamental frequency. Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. DPhase = wDt Solving for w = DPhase / Dt = 2pf Solving for f and substituting the reference clock frequency for the reference period (1/ f MCLK = Dt ) Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9833, THD is defined as 2 2 2 2 f = DPhase f MCLK / 2p The AD9833 builds the output based on this simple equation. A simple DDS chip can implement this equation with three major subcircuits: numerically controlled oscillator + phase modulator, SIN ROM, and digital-to-analog converter. 2 V + V3 + V4 + V5 + V6 THD = 20 log 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Each of these subcircuits is discussed in the following section. Signal-to-Noise Ratio (SNR) The AD9833 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques. CIRCUIT DESCRIPTION SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There will be feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD9833's output spectrum. The internal circuitry of the AD9833 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a digital-to-analog converter, and a regulator. -8- REV. A AD9833 Numerically Controlled Oscillator Plus Phase Modulator Regulator This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 to 2. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9833 is implemented with 28 bits. Therefore, in the AD9833, 2 = 228. Likewise, the Phase term is scaled into this range of numbers 0 < Phase < 228 - 1. With these substitutions, the previous equation becomes VDD provides the power supply required for the analog section and the digital section of the AD9833. This supply can have a value of 2.3 V to 5.5 V. The internal digital section of the AD9833 is operated at 2.5 V. An on-board regulator steps down the voltage applied at VDD to 2.5 V. When the applied voltage at the VDD pin of the AD9833 is equal to or less than 2.7 V, the CAP/2.5 V and VDD pins should be tied together, thus bypassing the on-board regulator. FUNCTIONAL DESCRIPTION Serial Interface The AD9833 has a standard 3-wire serial interface that is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. f = Phase f MCLK / 2 28 where 0 < Phase < 228 - 1. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is given in Figure 3. The input to the phase accumulator can be selected either from the FREQ0 register or FREQ1 register, and is controlled by the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. The FSYNC input is a level triggered input that acts as a frame synchronization and chip enable. Data can be transferred into the device only when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC to SCLK falling edge setup time, t7. After FSYNC goes low, serial data will be shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. FSYNC may be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time, t8. Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low, FSYNC only going high after the 16th SCLK falling edge of the last word loaded. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers is added to the most significant bits of the NCO. The AD9833 has two phase registers; their resolution is 2/4096. SIN ROM To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, the SIN ROM uses the digital phase information as an address to a look-up table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary, as this would require a look-up table of 228 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires that the SIN ROM have two bits of phase resolution more than the 10-bit DAC. The SCLK can be continuous, or alternatively the SCLK can idle high or low between write operations but must be high when FSYNC goes low (t11). Powering Up the AD9833 The flow chart in Figure 7 shows the operating routine for the AD9833. When the AD9833 is powered up, the part should be reset. This will reset appropriate internal registers to zero to provide an analog output of midscale. To avoid spurious DAC outputs while the AD9833 is being initialized, the RESET bit should be set to 1 until the part is ready to begin generating an output. RESET does not reset the phase, frequency, or control registers. These registers will contain invalid data, and therefore should be set to a known value by the user. The RESET bit should then be set to 0 to begin generating an output. The data will appear on the DAC output eight MCLK cycles after RESET is set to 0. The SIN ROM is enabled using the MODE bit (D1) in the control register. This is explained further in Table XI. Digital-to-Analog Converter The AD9833 includes a high impedance current source 10-bit DAC. The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages. The DAC is configured for single-ended operation. An external load resistor is not required since the device has a 200 W resistor on board. The DAC generates an output voltage of typically 0.6 V p-p. REV. A Latency Associated with each asynchronous write operation in the AD9833 is a latency. If a selected frequency/phase register is loaded with a new word, there is a delay of seven to eight MCLK cycles before the analog output will change. (There is an uncertainty of one MCLK cycle, as it depends on the position of the MCLK rising edge when the data is loaded into the destination register.) -9- AD9833 Control Register The AD9833 contains a 16-bit control register that sets up the AD9833 as the user wants to operate it. All control bits, except MODE, are sampled on the internal negative edge of MCLK. Table II describes the individual bits of the control register. The different functions and the various output options from the AD9833 are described in more detail in the section following Table II. To inform the AD9833 that the contents of the control register will be altered, D15 and D14 must be set to 0 as shown below. Table I. Control Register D15 D14 0 0 D13 D0 CONTROL BITS SLEEP12 SLEEP1 RESET AD9833 PHASE ACCUMULATOR (28-BIT) SIN ROM (LOW POWER) 10-BIT DAC 0 MUX 1 MODE + OPBITEN DIVIDE BY 2 1 MUX 0 DIGITAL OUTPUT (ENABLE) VOUT DIV2 OPBITEN DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 B28 HLB FSELECT PSELECT 0 RESET SLEEP1 SLEEP12 OPBITEN 0 DIV2 0 MODE 0 Figure 5. Function of Control Bits Table II. Description of Bits in the Control Register Bit Name Function D13 B28 D12 HLB D11 D10 FSELECT PSELECT D9 D8 Reserved RESET D7 SLEEP1 Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains the 14 LSBs of the frequency word, and the next write will contain the 14 MSBs. The first two bits of each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both of the consecutive writes. Refer to Table IV for the appropriate addresses. The write to the frequency register occurs after both words have been loaded, so the register never holds an intermediate value. An example of a complete 28-bit write is shown in Table V. When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs. This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with D13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register. D13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When D13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register. The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator. The PSELECT bit defines whether the PHASE0 register or the PHASE1 register data is added to the output of the phase accumulator. This bit should be set to 0. RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale. RESET = 0 disables RESET. This function is explained further in Table IX. When SLEEP1 = 1, the internal MCLK clock is disabled, the DAC output will remain at its present value as the NCO is no longer accumulating. When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table X. -10- REV. A AD9833 Table II. Description of Bits in the Control Register (continued) Bit Name Function D6 SLEEP12 D5 OPBITEN D4 D3 Reserved DIV2 D2 D1 Reserved MODE D0 Reserved SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table X. The function of this bit, in association with D1 (MODE), is to control what is output at the VOUT pin. This is explained further in Table XI. When OPBITEN = 1, the output of the DAC is no longer available at the VOUT pin. Instead, the MSB (or MSB/2) of the DAC data is connected to the VOUT pin. This is useful as a coarse clock source. The bit DIV2 controls whether it is the MSB or MSB/2 that is output. When OPBITEN = 0, the DAC is connected to VOUT. The MODE bit determines whether it is a sinusoidal or a ramp output that is available. This bit must be set to 0. DIV2 is used in association with D5 (OPBITEN). This is explained further in Table XI. When DIV2 = 1, the MSB of the DAC data is passed directly to the VOUT pin. When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin. This bit must be set to 0. This bit is used in association with OPBITEN (D5). The function of this bit is to control what is output at the VOUT pin when the on-chip DAC is connected to VOUT. This bit should be set to 0 if the control bit OPBITEN = 1. This is explained further in Table XI. When MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. When MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, which results in a sinusoidal signal at the output. This bit must be set to 0. The analog output from the AD9833 is Frequency and Phase Registers The AD9833 contains two frequency registers and two phase registers, which are described in Table III. f MCLK /228 FREQREG where FREQREG is the value loaded into the selected frequency register. This signal will be phase shifted by Table III. Frequency/Phase Registers Register Size 2 p/ 4096 PHASEREG Description FREQ0 28 Bits Frequency Register 0. When the FSELECT bit = 0, this register defines the output frequency as a fraction of the MCLK frequency. FREQ1 28 Bits Frequency Register 1. When the FSELECT bit = 1, this register defines the output frequency as a fraction of the MCLK frequency. where PHASEREG is the value contained in the selected phase register. Consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted output anomalies. The flow chart in Figure 9 shows the routine for writing to the frequency and phase registers of the AD9833. PHASE0 12 Bits Phase Offset Register 0. When the PSELECT bit = 0, the contents of this register are added to the output of the phase accumulator. PHASE1 12 Bits Phase Offset Register 1. When the PSELECT bit = 1, the contents of this register are added to the output of the phase accumulator. REV. A Writing to a Frequency Register When writing to a frequency register, Bits D15 and D14 give the address of the frequency register. Table IV. Frequency Register Bits D15 D14 D13 0 1 1 0 MSB MSB -11- D0 14 FREQ0 REG Bits 14 FREQ1 REG Bits LSB LSB AD9833 If the user wants to change the entire contents of a frequency register, two consecutive writes to the same address must be performed since the frequency registers are 28 bits wide. The first write will contain the 14 LSBs, while the second write will contain the 14 MSBs. For this mode of operation, the control bit B28 (D13) should be set to 1. An example of a 28-bit write is shown in Table V. Table V. Writing 00FC00 to FREQ0 REG SDATA Input Result of Input Word 0010 0000 0000 0000 Control Word Write (D15, D14 = 00), B28 (D13) = 1, HLB (D12) = X FREQ0 REG Write (D15, D14 = 01), 14 LSBs = 0000 FREQ0 REG Write (D15, D14 = 01), 14 MSBs = 003F 0100 0000 0000 0000 0100 0000 0011 1111 Table VI. Writing 3FFF to the 14 LSBs of FREQ1 REG SDATA Input Result of Input Word 0000 0000 0000 0000 Control Word Write (D15, D14 = 00), B28 (D13) = 0; HLB (D12) = 0, i.e. LSBs FREQ1 REG Write (D15, D14 = 10), 14 LSBs = 3FFF RESET Bit Result 0 1 No Reset Applied Internal Registers Reset SLEEP Function Sections of the AD9833 that are not in use can be powered down to minimize power consumption. This is done using the SLEEP function. The parts of the chip that can be powered down are the internal clock and the DAC. The bits required for the SLEEP function are outlined in Table X. Table X. Applying the SLEEP Function SLEEP1 Bit SLEEP12 Bit Result 0 0 1 1 0 1 0 1 No Power-Down DAC Powered Down Internal Clock Disabled Both the DAC Powered Down and the Internal Clock Disabled DAC Powered Down This is useful when the AD9833 is used to output the MSB of the DAC data only. In this case, the DAC is not required so it can be powered down to reduce power consumption. Internal Clock Disabled When the internal clock of the AD9833 is disabled, the DAC output will remain at its present value as the NCO is no longer accumulating. New frequency, phase, and control words can be written to the part when the SLEEP1 control bit is active. The synchronizing clock is still active, which means that the selected frequency and phase registers can also be changed using the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Any changes made to the registers while SLEEP1 was active will be seen at the output after a certain latency. Table VII. Writing 00FF to the 14 MSBs of FREQ0 REG SDATA Input The RESET function resets appropriate internal registers to 0 to provide an analog output of midscale. RESET does not reset the phase, frequency, or control registers. When the AD9833 is powered up, the part should be reset. To reset the AD9833, set the RESET bit to 1. To take the part out of reset, set the bit to 0. A signal will appear at the DAC to output eight MCLK cycles after RESET is set to 0. Table IX. Applying RESET In some applications, the user does not need to alter all 28 bits of the frequency register. With coarse tuning, only the 14 MSBs are altered, while with fine tuning, only the 14 LSBs are altered. By setting the control bit B28 (D13) to 0, the 28-bit frequency register operates as two, 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. Bit HLB (D12) in the control register identifies which 14 bits are being altered. Examples of this are shown in Tables VI and VII. 1011 1111 1111 1111 RESET Function Result of Input Word 0001 0000 0000 0000 Control Word Write (D15, D14 = 00), B28 (D13) = 0, HLB (D12) = 1, i.e., MSBs 0100 0000 1111 1111 FREQ0 REG Write (D15, D14 = 01), 14 MSBs = 00FF VOUT Pin Writing to a Phase Register When writing to a phase register, Bits D15 and D14 are set to 11. Bit D13 identifies which phase register is being loaded. Table VIII. Phase Register Bits D15 D14 D13 D12 D11 1 1 1 1 0 1 X X MSB MSB D0 12 PHASE0 Bits 12 PHASE1 Bits LSB LSB The AD9833 offers a variety of outputs from the chip, all of which are available from the VOUT pin. The choice of outputs are the MSB of the DAC data, a sinusoidal output, or a triangle output. The OPBITEN (D5) and MODE (D1) bits in the control register are used to decide which output is available from the AD9833. This is explained further below and also in Table XI. MSB of the DAC Data The MSB of the DAC data can be output from the AD9833. By setting the OPBITEN (D5) control bit to 1, the MSB of the DAC data is available at the VOUT pin. This is useful as a coarse clock source. This square wave can also be divided by two before being output. The DIV2 (D3) bit in the control register controls the frequency of this output from the VOUT pin. -12- REV. A AD9833 The AD9833 is also suitable for signal generator applications. Because the MSB of the DAC data is available at the VOUT pin, the device can be used to generate a square wave. Sinusoidal Output The SIN ROM is used to convert the phase information from the frequency and phase registers into amplitude information that results in a sinusoidal signal at the output. To have a sinusoidal output from the VOUT pin, set the MODE (D1) bit to 0 and the OPBITEN (D5) bit to 0. With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. Triangle Output GROUNDING AND LAYOUT The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC will produce a 10-bit linear triangular function. To have a triangle output from the VOUT pin, set the MODE (D1) bit = 1. The printed circuit board that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes since it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD9833 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9833. If the AD9833 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9833. Note that the SLEEP12 bit must be 0 (i.e., the DAC is enabled) when using this pin. Table XI. Various Outputs from VOUT OPBITEN Bit MODE Bit DIV2 Bit VOUT Pin 0 0 1 1 1 0 1 0 0 1 X X 0 1 X Sinusoid Triangle DAC Data MSB/2 DAC Data MSB Reserved VOUT MAX VOUT MIN 2 4 6 Figure 6. Triangle Output APPLICATIONS Because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications. One of the areas where the AD9833 is suitable is in modulation applications. The part can be used to perform simple modulation, such as FSK. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833. In an FSK application, the two frequency registers of the AD9833 are loaded with different values. One frequency will represent the space frequency, while the other will represent the mark frequency. Using the FSELECT bit in the control register of the AD9833, the user can modulate the carrier frequency between the two values. The AD9833 has two phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. REV. A Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD9833 to avoid noise coupling. The power supply lines to the AD9833 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the other side. Good decoupling is important. The AD9833 should have supply bypassing of 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. Proper operation of the comparator requires good layout strategy. The strategy must minimize through proper layout of the PCB the parasitic capacitance between VIN and the SIGN BIT OUT pin by adding isolation using a ground plane. For example, in a 4-layer board, the CIN signal could be connected to the top layer and the SIGN BIT OUT connected to the bottom layer, so that isolation is provided by the power and ground planes between. -13- AD9833 DATA WRITE SEE FIGURE 9 SELECT DATA SOURCES WAIT 8/9 MCLK CYCLES INITIALIZATION SEE FIGURE 8 BELOW DAC OUTPUT VOUT = VREF 18 RLOAD/R SET (1 + (SIN(2(FREQREG fMCLK t /228 + PHASEREG/212)))) YES CHANGE PHASE? NO YES YES CHANGE FSELECT? CHANGE FREQUENCY? NO NO YES CHANGE FREQUENCY REGISTER? CHANGE PSELECT? YES NO CHANGE PHASE REGISTER? YES CHANGE DAC OUTPUT FROM SIN TO RAMP? YES NO CONTROL REGISTER WRITE (SEE TABLE XI) YES CHANGE OUTPUT TO A DIGITAL SIGNAL? NO Figure 7. Flow Chart for AD9833 Initialization and Operation INITIALIZATION APPLY RESET (CONTROL REGISTER WRITE) RESET = 1 WRITE TO FREQUENCY AND PHASE REGISTERS FREQ0 REG = FOUT0 / f MCLK 228 FREQ1 REG = FOUT1 / f MCLK 228 PHASE0 AND PHASE1 REG = (PHASESHIFT 212) / 2 (SEE FIGURE 9) SET RESET = 0 SELECT FREQUENCY REGISTERS SELECT PHASE REGISTERS (CONTROL REGISTER WRITE) RESET BIT = 0 FSELECT = SELECTED FREQUENCY REGISTER PSELECT = SELECTED PHASE REGISTER Figure 8. Initialization -14- REV. A AD9833 DATA WRITE WRITE A FULL 28-BIT WORD TO A FREQUENCY REGISTER? NO WRITE 14 MSBs OR LSBs TO A FREQUENCY REGISTER? NO WRITE TO PHASE REGISTER? YES YES YES (CONTROL REGISTER WRITE) B28 (D13) = 1 (CONTROL REGISTER WRITE) B28 (D13) = 0 HLB (D12) = 0/1 (16-BIT WRITE) WRITE TWO CONSECUTIVE 16-BIT WORDS (SEE TABLE V FOR EXAMPLE) YES WRITE ANOTHER FULL 28-BIT WORD TO A FREQUENCY REGISTER? D15, D14 = 11 D13 = 0/1 (CHOOSE THE PHASE REGISTER) D12 = X D11 ... D0 = PHASE DATA WRITE A 16-BIT WORD (SEE TABLES VI AND VII FOR EXAMPLES) WRITE 14MSBs OR LSBs TO A FREQUENCY REGISTER? WRITE TO ANOTHER PHASE REGISTER? YES NO NO YES NO Figure 9. Data Writes INTERFACING TO MICROPROCESSORS ADSP-2101/ ADSP-2103* The AD9833 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data/control information is being written to the AD9833, FSYNC is taken low and is held low while the 16 bits of data are being written into the AD9833. The FSYNC signal frames the 16 bits of information being loaded into the AD9833. AD9833* TFS FSYNC DT SDATA SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 10. ADSP-2101/ADSP-2103 to AD9833 Interface AD9833 to ADSP-21xx Interface AD9833 to 68HC11/68L11 Interface Figure 10 shows the serial interface between the AD9833 and the ADSP-21xx. The ADSP-21xx should be set up to operate in the SPORT transmit alternate framing mode (TFSW = 1). The ADSP-21xx is programmed through the SPORT control register and should be configured as follows: Figure 11 shows the serial interface between the AD9833 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting bit MSTR in the SPCR to 1. This provides a serial clock on SCK while the MOSI output drives the serial data line SDATA. Since the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows: * Internal clock operation (ISCLK = 1) * Active low framing (INVTFS = 1) * 16-bit word length (SLEN = 15) * SCK idles high between write operations (CPOL = 0) * Internal frame sync signal (ITFS = 1) * Data is valid on the SCK falling edge (CPHA = 1) * Generate a frame sync for each write (TFSR = 1) Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD9833 on the SCLK falling edge. REV. A When data is being transmitted to the AD9833, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data into the AD9833, PC7 is held low after the first 8 bits are transferred, and a second serial write operation is performed to the AD9833. Only after the second 8 bits have been transferred should FSYNC be taken high again. -15- AD9833 68HC11/68L11* DSP56002* AD9833* AD9833* PC7 FSYNC SC2 FSYNC MOSI SDATA STD SDATA SCLK SCK SCLK SCK *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. 68HC11/68L11 to AD9833 Interface Figure 13. DSP56002 to AD9833 Interface AD9833 to 80C51/80L51 Interface Figure 12 shows the serial interface between the AD9833 and the 80C51/80L51 microcontroller. The microcontroller is operated in mode 0 so that TxD of the 80C51/80L51 drives SCLK of the AD9833, while RxD drives the serial data line SDATA. The FSYNC signal is again derived from a bit programmable pin on the port (P3.3 being used in the diagram). When data is to be transmitted to the AD9833, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus only eight falling SCLK edges occur in each cycle. To load the remaining 8 bits to the AD9833, P3.3 is held low after the first 8 bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD9833 accepts the MSB first (the 4 MSBs being the control information, the next 4 bits being the address, while the 8 LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first. 80C51/80L51* AD9833* P3.3 FSYNC RxD SDATA TxD SCLK AD9833 EVALUATION BOARD The AD9833 Evaluation Board allows designers to evaluate the high performance AD9833 DDS modulator with a minimum of effort. To prove that this device will meet the user's waveform synthesis requirements, the user requires only a power supply, an IBM(R) compatible PC, and a spectrum analyzer along with the evaluation board. The DDS evaluation kit includes a populated, tested AD9833 printed circuit board. The evaluation board interfaces to the parallel port of an IBM compatible PC. Software is available with the evaluation board that allows the user to easily program the AD9833. A schematic of the evaluation board is shown in Figure 14. The software will run on any IBM compatible PC that has Microsoft Windows(R) 95, Windows 98, Windows ME, or Windows 2000 NT(R) installed. Using the AD9833 Evaluation Board The AD9833 evaluation kit is a test system designed to simplify the evaluation of the AD9833. An application note is also available with the evaluation board and gives full information on operating the evaluation board. Prototyping Area An area is available on the evaluation board for the user to add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. XO vs. External Clock *ADDITIONAL PINS OMITTED FOR CLARITY Figure 12. 80C51/80L51 to AD9833 Interface AD9833 to DSP56002 Interface Figure 13 shows the interface between the AD9833 and the DSP56002. The DSP56002 is configured for normal mode asynchronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal will frame the 16 bits (FSL = 0). The frame sync signal is available on pin SC2, but it needs to be inverted before being applied to the AD9833. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002. The AD9833 can operate with master clocks up to 25 MHz. A 25 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and, if required, an external CMOS clock connected to the part. Power Supply Power to the AD9833 evaluation board must be provided externally through pin connections. The power leads should be twisted to reduce ground loops. -16- REV. A AD9833 1 2 SCLK 3 SDATA 4 FSYNC 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 C11 10F VDD C2 0.1F DVDD C6 0.1F DVDD 3 C6 0.1F J1 SCLK SDATA CAP 2 18 7 SCLK 4 16 6 SDATA 2 VDD 14 8 VDD MCLK LK2 COMP FSYNC 1 5 MCLK VOUT C4 DVDD C5 0.1F DGND U3 4 AGND 9 OUT DGND Figure 14. Evaluation Board Layout Integrated Circuits AD9833BRU 74HCT244 OSC XTAL 25 MHz Capacitors C1, C2 C3 C4 C5, C6, C7, C9 C8, C10, C11 Resistor R1 100 nF Ceramic Capacitor 0805 10 nF Ceramic Capacitor Option for Extra Decoupling Capacitor 100 nF Ceramic Capacitor 10 mF Tantalum Capacitor 50 W Resistor Links LK1, LK2 2-Pin Sil Header Sockets MCLK VOUT Subminiature BNC Connector Connectors J1 J2, J3 REV. A VOUT 10 DVDD 28 29 30 31 32 33 34 35 36 U1 U2 U3 C3 0.01F U1 AD9833 U2 R1 50 C8 10F 1 6 FSYNC DVDD LK1 C1 0.1F 36-Pin Edge Connector PCB Mounting Terminal Block -17- C7 0.1F J2 J3 VDD C9 0.1F C10 10F AD9833 OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.23 0.08 0.15 0 0.27 0.17 SEATING PLANE 8 0 0.80 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA -18- REV. A AD9833 Revision History Location Page 6/03--Data Sheet changed from REV. 0 to REV. A. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 REV. A -19- -20- C02704-0-6/03(A)