MCM10143 8 X 2 MULTIPORT REGISTER FILE (RAM) r ~ 8x 2MULTIPORT REGISTER FILE (RAM) The MCM10143 is an 8 word by 2 bit multiport register file (RAM) capable of reading two locations and writing one loca- tion simultaneously. Two sets of eight latches are used for data storage in this LSI circuit. WRITE The word to be written is selected by addresses AgA2. Each bit of the word has a separate write enable to allow more flexibility in system design. A write occurs on the positive transition of the clock. Data is enabled by having the write enables at a low level when the clock makes the transition. To inhibit a bit from being written, the L sure bit enable must be at a high level when the clock goes low and not CERAMIC PACKAGE CASE 623 change until the clock goes high. Operation of the clock and the bit enables can be reversed. While the clock is low a positive transition of the bit enable will write that bit into the address selected by AgAg. READ When the clock is high any two words may be read out simulta- neously, as selected by addresses Bo-B2 and CgCg, including the word written during the preceding half clock cycle. When the clock goes low the addressed data is stored in the slaves. Level changes on PIN ASSIGNMENT the read address lines have no effect on the output until the clock again goes high. Read out is accomplished at any time by enabling output gates (Bo-B1), (CoC1). 2 tpd: Clock to Data out = 5ns (typ) 3 (Read Selected) 4 Address to Data out = 10ns (typ) 5 (Clock High} 6 Read Enable to Data out = 2.8 ns (typ) (Ctock high, Addresses present} 7 Pp = 610 MW/pkg (typ no load) 8 9 10 TRUTH TABLE "MODE INPUT OUTPUT " *Clock | WEg| WE, | Og | 04 | REg | REc | O89 | 081 | ACgf acy 12 Write LH L L H H Hi H L L L L Read H oO a a A L H H H H Read HL oO oO Oo L L H H H H Read L-*H-*L ]} oH H 2 L a H H H H Write Lt L L L H rt aT L L L L Read H oO y o | A L L H tl H **Note. Clock-occurs sequentially through Truth Table "Note. AO A2, 80.B2, and CO C2 are all set to sarne address location throughaut Tabie Ye Don't Care / 3-33MCM10143 BLOCK DIAGRAM _. 4 REg O- Multi- Output 2 > Slave q 6 plexer B-bit 1 by Gate t) OB, Bo a as Read B-bit 1 rm] ~ B-bit 1 8 [So Decoder | 82 Oo B Multi- Slave Ll output 3 5 a8 plexer B-bit 0 : O QB | B-bit 0 r ) B-bItO Write L WE 9 8x1 We sg: be arr, Ave Master Latches oo ~~ | Bit oO Clock o 24 14 Aa oO Write Alo 5 4m Decoder A2 9-13 A > Write 8x1 WE o3 Amplifier Master Latches Dy o Bit r~4 Bit 1 ~~ Muti. or Slave o Output 22 plexer C-bit 7 Gate L-0 QC, C-bit 1 mY Chit 1 Co 2 Read Cy O18 am Decoder O_ > C .. exer | 7] Sie Saw 24, pex C-bit 0 : QCg C-bit O em C-bit 0 RE 02 3-34MCM 10143 ELECTRICAL CHARACTERISTICS 0c +25C +75C Characteristics Symbol Min | Max | Min | Typ | Max | Min | Max Unit Power Supply Drain Current le - 150 - 118 | 150 - 150 | mAdc Input Current SinH uAdc Pins 10,11, 19 = 245 - 245 - 245 All other pins - 200 - 200 - 200 Switching Times @ ns Read Mode Address Input tatagt 40 | 15.3} 45 10 145 | 4.5 | 15.5 Read Enabie tRE-aB+ 114/53 112] 35150 [12] 55 Data tclock +QB~ 1.7 7.3 2.0 5.0 7.0 2.0 76 Setup Address tsetup(B Clock -) _ _ 8.5 | 55 - _ - Hold Address thold(Clock -B +) = |-15[-45] - aa Write Mode Setup Write Enable tsetup(WE-Clock+) | - ]70] 40] - ~ ~ tsetup(WE+Clock-) | _ 1.0 |-2.0) - 7 Address tsetup({A-Clock +) - ~ 80) 50) ~ ~ Data |_tsetup(D)-Clock+) | - | ~ [| 8.0 | 20] = = Hold Write Enable thoid (Clock +WE +) - - 85 | 25 - _ _ thold(Clock+WE-) | ~ | ~ | 10 [-20) - J | Address thold(Clock +A +) - - 10 |-3.0} - - Data thold(Clock+D+) | ~ | = {| 10 [-20[ a Write Pulse Width PWwe ~ - 8.0 | 5.0 - - _ Rise Time, Fall Time ty, tf 1.1 4.2 1.41 25 40 1.1 45 (20% to 80%) ac timing figures do not show all the necessary presetting conditions. 3- 35MCM10143 Va Access (Clock High) 5 _. Data (Address Selected) READ TIMING DIAGRAMS tRE+a8- Clack q. Setup and Hold 3-36 FIGURE 1 FIGURE 2 FIGURE 3 FIGURE 4MCM10143 { WRITE TIMING DIAGRAM Enable Setup WE me ee. -- "setup - Clock ----. Enable Hold thold We Disrble x Se ~ *setup he. -- thoid - ~ eee {_ Pulse Width | . Clock = Sf fect setup 4 - -t >> thoid + BN a tei a, Address Clock aoe tgetup- = thold- a _-_= Oo Of oO / } Nee ee ee Htsetup =" thold | crock \ i 3-37 a {f Clock eT FIGURE 5 FIGURE 6 FIGURE 7 FIGURE 8 FIGURE 9