AM27C010-70EI - Advanced Micro Devices

Publication# 10205 Rev. FAmendment/0

Issue Date: May 1995

2-56

Advanced

Micro

Devices

Am27C010

1 Megabit (131,072 x 8-Bit) CMOS EPROM

FINAL

DISTINCTIVE CHARACTERISTICS

■Fast access time

—55 ns

■Low power consumption

—20 µA typical CMOS standby current

■JEDEC-approved pinout

■Single +5 V power supply

■±10% power supply tolerance available

■100% Flashrite programming

— Typical programming time of 16 seconds

■Latch-up protected to 100 mA from –1 V to

VCC + 1 V

■High noise immunity

■Versatile features for simple interfacing

— Both CMOS and TTL input/output

compatibility

— Two line control functions

■Compact 32-pin DIP, PDIP, TSOP, PLCC

packages

GENERAL DESCRIPTION

The Am27C010 is a 1 Megabit ultraviolet erasable pro-

grammable read-only memory. It is organized as 128K

words by 8 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast sin-

gle address location programming. Products are avail-

able in windowed ceramic DIP packages as well as plas-

tic one time programmable (OTP) PDIP, TSOP, and

PLCC packages.

Typically, any byte can be accessed in less than 55 ns,

allowing operation with high-performance microproces-

sors without any WAIT states. The Am27C010 offers

separate Output Enable (OE) and Chip Enable (CE)

controls, thus eliminating bus contention in a multiple

bus microprocessor system.

AMD’s CMOS process technology provides high speed,

low power, and high noise immunity. Typical power con-

sumption is only 100 mW in active mode, and 100 µW in

standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in blocks,

or at random. The Am27C010 supports AMD’s Flashrite

programming algorithm (100 µs pulses) resulting in a

typical programming time of 16 seconds.

BLOCK DIAGRAM

VCC

VSS

Output Enable

Chip Enable

and

Prog Logic

Decoder

Output

Buffers

Gating

1,048,576

Bit Cell

Matrix

A0–A16

Address

Inputs

Data Outputs

DQ0–DQ7

10205F-1

VPP

PGM

AMD

2-57

Am27C010

PRODUCT SELECTOR GUIDE

Family Part No.

Ordering Part No:

VCC ±5% -55 -255

VCC ±10% -70 -90 -120 -150 -200

Max Access Time (ns) 55 70 90 120 150 200 250

CE (E) Access (ns) 55 70 90 120 150 200 250

OE (G) Access (ns) 35 35 40 50 65 75 75

Am27C010

CONNECTION DIAGRAMS

Top View DIP

Notes:

1. JEDEC nomenclature is in parentheses.

2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.

PLCC

VPP VCC

DQ0

A14

16 18

DQ1

DQ2

VSS

PGM (P)

A13

A11

OE (G)

A10

CE (E)

DQ7

DQ6

A16

A15

A12

DQ5

DQ4

DQ3

10205F-2

10205F-3

13130234

13 17 18 19 20161514

DQ0

A14

A13

OE (G)

A10

CE (E)

DQ7

A12

A15

A16

VPP

VCC

PGM (P)

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

A11

A11 OE

PGM

A13 DQ7

A14

16 18

VCC

VPP

A16

A15

A12

A10

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ0

DQ1

10205F-5

TSOP

Standard Pinout

AMD

2-58 Am27C010

A0–A16

DQ0–DQ7

CE (E)

PGM (P)

OE (G)

PIN DESIGNATIONS

A0–A16 = Address Inputs

CE (E) = Chip Enable Input

DQ0–DQ7 = Data Input/Outputs

OE (G) = Output Enable Input

PGM (P) = Program Enable Input

VCC =V

CC Supply Voltage

VPP = Program Voltage Input

VSS = Ground

LOGIC SYMBOL

10205F-4

AMD

2-59

Am27C010

ORDERING INFORMATION

UV EPROM Products

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the lo-

cal AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

DEVICE NUMBER

Am27C010

1 Megabit (131,072 x 8-Bit) CMOS UV EPROM

PACKAGE TYPE

D = 32-Pin Ceramic DIP (CDV032)

AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of:

BCD-55AM27C010

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended Commercial (–55°C to +125°C)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM27C010-55

AM27C010-70

AM27C010-90

AM27C010-120

AM27C010-150

AM27C010-200

AM27C010-255

DC, DCB, DI, DIB

DC, DCB, DE, DEB,

DI, DIB

DC, DCB, DI, DIB

AMD

2-60 Am27C010

ORDERING INFORMATION

OTP Products

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the lo-

cal AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

DEVICE NUMBER

Am27C010

1 Megabit (131,072 x 8-Bit) CMOS OTP EPROM

Valid Combinations

AM27C010-70

AM27C010-90

AM27C010-120

AM27C010-150

AM27C010-200

AM27C010-255

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin TSOP Standard Pinout (TS 032)

AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of:

CP-70AM27C010

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to + 85°C)

SPEED OPTION

See Product Selector Guide and Valid Combinations

PC, JC, EC, PI,

JI, EI

AMD

2-61

Am27C010

FUNCTIONAL DESCRIPTION

Erasing the Am27C010

In order to clear all locations of their programmed con-

tents, it is necessary to expose the Am27C010 to an

ultraviolet light source. A dosage of 15 W seconds/cm2 is

required to completely erase an Am27C010. This

dosage can be obtained by exposure to an ultraviolet

lamp—wavelength of 2537 A

°—with intensity of

12,000 µW/cm2

for 15 to 20 minutes. The Am27C010

should be directly under and about one inch from the

source and all filters should be removed from the UV

light source prior to erasure.

It is important to note that the Am27C010 and similar

devices will erase with light sources having wavelengths

shorter than 4000 A

°. Although erasure times will be

much longer than with UV sources at 2537 A

°, exposure

to fluorescent light and sunlight will eventually erase the

Am27C010 and exposure to them should be prevented

to realize maximum system reliability. If used in such an

environment, the package window should be covered

by an opaque label or substance.

Programming the Am27C010

Upon delivery or after each erasure the Am27C010 has

all 1,048,576 bits in the “ONE” or HIGH state. “ZEROs”

are loaded into the Am27C010 through the procedure

of programming.

The programming mode is entered when 12.75 V ±

0.25 V is applied to the VPP pin, CE and PGM are at VIL,

and OE is at VIH.

For programming, the data to be programmed is applied

8 bits in parallel to the data output pins.

The Flashrite algorithm reduces programming time by

using 100 µs programming pulses and by giving each

address only as many pulses as is necessary in order to

reliably program the data. After each pulse is applied to

a given address, the data in that address is verified. If

the data does not verify, additional pulses are given until

it verifies or the maximum is reached. This process is re-

peated while sequencing through each address of the

Am27C010. This part of the algorithm is done at

VCC = 6.25 V to assure that each EPROM bit is pro-

grammed to a sufficiently high threshold voltage. After

the final address is completed, the entire EPROM mem-

ory is verified at VCC = VPP = 5.25 V.

Please refer to Section 6 for programming flow chart

and characteristics.

Program Inhibit

Programming of multiple Am27C010 in parallel with dif-

ferent data is also easily accomplished. Except for CE,

all like inputs of the parallel Am27C010 may be com-

mon. A TTL low-level program pulse applied to an

Am27C010 CE input and VPP = 12.75 V ± 0.25 V, PGM

Low and OE High will program that Am27C010. A

high-level CE input inhibits the other Am27C010 de-

vices from being programmed.

Program Verify

A verify should be performed on the programmed bits to

determine that they were correctly programmed. The

verify should be performed with OE and CE at VIL , PGM

at VIH, and VPP between 12.5 V and 13.0 V.

Auto Select Mode

The auto select mode allows the reading out of a binary

code from an EPROM that will identify its manufacturer

and type. This mode is intended for use by programming

equipment for the purpose of automatically matching

the device to be programmed with its corresponding

programming algorithm. This mode is functional in the

25°C ± 5°C ambient temperature range that is required

when programming the Am27C010.

To activate this mode, the programming equipment

must force 12.0 V ± 0.5 V on address line A9 of the

Am27C010. Two identifier bytes may then be se-

quenced from the device outputs by toggling address

line A0 from VIL to VIH. All other address lines must be

held at VIL during auto select mode.

Byte 0 (A0 = VIL) represents the manufacturer code, and

byte 1 (A0 = VIH), the device code. For the Am27C010,

these two identifier bytes are given in the Mode Select

Table. All identifiers for manufacturer and device codes

will possess odd parity, with the MSB (DQ7) defined as

the parity bit.

Read Mode

The Am27C010 has two control functions, both of which

must be logically satisfied in order to obtain data at the

outputs. Chip Enable (CE) is the power control and

should be used for device selection. Output Enable (OE)

is the output control and should be used to gate data to

the output pins, independent of device selection. As-

suming that addresses are stable, address access time

(tACC) is equal to the delay from CE to output (tCE). Data

is available at the outputs tOE after the falling edge of

OE, assuming that CE has been LOW and addresses

have been stable for at least tACC–tOE.

Standby Mode

The Am27C010 has a CMOS standby mode which re-

duces the maximum VCC current to 100 µA. It is placed in

CMOS-standby when CE is at VCC ± 0.3 V. The

Am27C010 also has a TTL-standby mode which re-

duces the maximum VCC current to 1.0 mA. It is placed in

TTL-standby when CE is at VIH. When in standby mode,

the outputs are in a high-impedance state, independent

of the OE input.

AMD

2-62 Am27C010

Output OR-Tieing

To accommodate multiple memory connections, a two-

line control function is provided to allow for:

■Low memory power dissipation

■Assurance that output bus contention will not occur

It is recommended that CE be decoded and used as the

primary device-selecting function, while OE be made a

common connection to all devices in the array and con-

nected to the READ line from the system control bus.

This assures that all deselected memory devices are in

low-power standby mode and that the output pins are

only active when data is desired from a particular

memory device.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the rising

and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the device. At a minimum, a

0.1-µF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

VCC and VSS to minimize transient effects. In addition, to

overcome the voltage drop caused by the inductive ef-

fects of the printed circuit board traces on EPROM ar-

rays, a 4.7-µF bulk electrolytic capacitor should be used

between VCC and VSS for each eight devices. The loca-

tion of the capacitor should be close to where the power

supply is connected to the array.

MODE SELECT TABLE

Notes:

1. V

= 12.0 V

0.5 V

2. X = Either V

or V

3. A1–A8 = A10–A16 = V

4. See DC Programming Characteristics for VPP voltage during programming.

CE OE PGM A0 A9 VPP Outputs

Read VIL VIL XXX X D

OUT

Output Disable X VIH X X X X High-Z

Standby (TTL) VIH X X X X X High-Z

Standby (CMOS) VCC ± 0.3 V X X X X X High-Z

Program VIL VIH VIL XXV

PP DIN

Program Verify VIL VIL VIH XXV

PP DOUT

Program Inhibit VIH XXXXV

PP High-Z

Manufacturer

Code VIL VIL XV

IL VHX 01H

Device Code VIL VIL XV

IH VHX0E

Auto Select

(Note 3)

Mode Pins

AMD

2-63

Am27C010

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products –65°C to +125°C. . . . . . . . . . . . . . .

All Other Products –65°C to +150°C. . . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Voltage with Respect To VSS

All pins except A9,VPP,VCC –0.6 V to VCC + 0.5 V.

A9 and VPP –0.6 V to +13.5 V. . . . . . . . . . . . . . . .

VCC –0.6 V to +7.0 V. . . . . . . . . . . . . . . . . . . . . . .

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

transitions, the inputs may overshoot V

to –2.0 V for pe-

riods of up to 20 ns. Maximum DC voltage on input and I/O

pins is V

+ 0.5 V which may overshoot to V

+ 2.0 V for

periods up to 20ns.

2. For A9 and V

the minimum DC input is –0.5 V. During

transitions, A9 and V

may overshoot V

to –2.0 V for

periods of up to 20 ns. A9 and V

must not exceed 13.5 V

for any period of time .

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)0°C to +70°C. . . . . . .

Industrial (I) Devices

Ambient Temperature (TA) –40°C to +85°C. . . . .

Extended Commercial (E) Devices

Ambient Temperature (TA) –55°C to +125°C. . . .

Supply Read Voltages

VCC for Am27C010-XX5 +4.75 V to +5.25 V. . . . .

VCC for Am27C010-XX0 +4.50 V to +5.50 V. . . . .

VCC for Am27C010-55 +4.75 V to +5.25 V. . . . . . .

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

AMD

2-64 Am27C010

DC CHARACTERISTICS over operating range unless otherwise specified.

(Notes 1, 2, and 4)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

VOH Output HIGH Voltage IOH = –400 µA 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.45 V

VIH Input HIGH Voltage 2.0 VCC + 0.5 V

VIL Input LOW Voltage –0.5 +0.8 V

ILI Input Load Current VIN = 0 V to VCC 1.0 µA

ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA

ICC1 VCC Active Current CE = VIL, f = 10 MHz,

(Note 3) IOUT = 0 mA

ICC2 VCC TTL Standby Current CE = VIH 1.0 mA

ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 100 µA

IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 100 µA

C/I Devices

E Devices

60 mA

Notes:

1. V

must be applied simultaneously or before V

, and removed simultaneously or after V

2. Caution: The Am27C010 must not be removed from (or inserted into) a socket when V

or V

is applied.

3. I

CC1

is tested with

= V

to simulate open outputs.

4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is V

+ 0.5 V, which may overshoot to V

+ 2.0 V for periods less than 20 ns.

10205F-7

Figure 1. Typical Supply Current

vs. Frequency

VCC = 5.5 V, T = 25°C

Figure 2. Typical Supply Current

vs. Temperature

VCC = 5.5 V, f = 10 MHz

10205F-6

–75 –50 –25 0 25 50 75 100 125 150

12345678910

Supply Current

in mA

Supply Current

in mA

Frequency in MHz Temperature in °C

AMD

2-65

Am27C010

CAPACITANCE

Parameter Parameter

Symbol Description Test Conditions Typ Max Typ Max Typ Max Typ Max Unit

CIN Input

Capacitance VIN = 0 9 12 8 12 8 12 10 12 pF

COUT Output

Capacitance VOUT = 0 1315111411141214pF

CDV032 PL 032 PD 032

Notes:

1. This parameter is only sampled and not 100% tested.

2. T

= +25

C, F = 1 MHz

TS 032

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

(Notes 1, 3, and 4)

Parameter Test

JEDEC Standard Description Conditions -55 -70 -90 -120 -150 -200 -255 Unit

tAVQV tACC Address to CE = OE = Min – – – – – – –

Output Delay VIL Max 55 70 90 120 150 200 250 ns

tELQV tCE Chip Enable to OE = VIL Min – – – – – – –

Output Delay Max 55 70 90 120 150 200 250 ns

tGLQV tOE Output Enable to CE = VIL Min – – – – – – –

Output Delay Max 35 35 40 50 65 75 75 ns

tEHQZ tDF Min – – – – – – –

tGHQZ (Note 2) Max 25 25 25 35 35 40 40 ns

tAXQX tOH Output Hold from Min 0 0 0 0 0 0 0

Addresses, CE, Max – – – – – – – ns

or OE, whichever

occurred first

Notes:

1. V

must be applied simultaneously or before V

, and removed simultaneously or after V

2. This parameter is only sampled and not 100% tested.

3. Caution: The Am27C010 must not be removed from (or inserted into) a socket or board when V

or V

is applied.

4. Output Load: 1 TTL gate and C

= 100 pF

Input Rise and Fall Times: 20 ns

Input Pulse Levels: 0.45 V to 2.4 V

Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs

For the Am27C010-55:

Output Load: 1 TTL Gate and C

= 30 pF

Input Rise and Fall Times: 20 ns

Input Pulse Levels: 0 V to 3 V

Timing Measurement Reference Level: 1.5 V for inputs and outputs

Parameter

Symbols Am27C010

Chip Enable HIGH or

Output Enable HIGH,

whichever comes

first, to Output Float

AMD

2-66 Am27C010

SWITCHING TEST CIRCUIT

Device

Under

Test

+5.0 V

CL = 100 pF including jig capacitance (30 pF for –55)

6.2 kΩ

2.7 kΩ

Diodes = IN3064

or Equivalent

10205F-8

SWITCHING TEST WAVEFORM

AC Testing: Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤ 20 ns.

10205F-9

2.4 V

0.45 V

2.0 V

0.8 V

Test Points

2.0 V

0.8 V

Input Output

AMD

2-67

Am27C010

KEY TO SWITCHING WAVEFORMS

Must Be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will Be

Steady

Will Be

Changing

from H to L

Will Be

Changing

from L to H

Changing

State

Unknown

Center

Line is High

Impedence

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010

SWITCHING WAVEFORMS

Addresses

Output

10205F-10

Addresses Valid

High Z High Z

tCE

Valid Output

2.4

0.45

2.0

0.8 2.0

0.8

tACC

(Note 1)

tOE tDF

(Note 2)

tOH

Notes:

may be delayed up to t

ACC

–t

after the falling edge of the addresses without impact on t

ACC.

2. t

is specified from

, whichever occurs first.