1. General description
The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC138; 74HCT138 deco der accep t s three binary weighted addr ess input s ( A0, A1
and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0to Y7).
The 74HC138; 74HCT138 featur es three enable inp ut s: two ac tive LOW (E1 and E2) and
one active HIGH (E3). Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138
to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one
inverter.
The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one of
the active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Permanently tie unused enable inputs to their appropriate active HIGH- or
LOW-state.
The 74HC138; 74HCT138 is identical to the 74HC238; 74HCT238 but has inverting
outputs.
2. Features and benefits
Demultiplexing capability
Multiple input enab le for ea sy ex pansion
Complies with JEDEC standard no. 7A
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
Specified from −40 °Cto+85°C and from −40 °Cto+125°C
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 27 June 2012 Product data sheet
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 2 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Tempe rature range Name Description Version
74HC138N −40 °Cto+125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT138N
74HC138D −40 °Cto+125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74 HCT138D
74HC138DB −40 °Cto+125°C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT138DB
74HC138PW −40 °Cto+125°C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm SOT403-1
74HCT138PW
74HC138BQ −40 °Cto+125°C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5 ×3.5 × 0.85 mm
SOT763-1
74HCT138BQ
Fig 1. Logic symbol Fig 2. Functional diagram
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
A2
3
2
1
6
5
4E2
E1
E3
mna370
mna372
ENABLE
EXITING
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
A2 3-to-8
DECODER
3
2
1
6
5
4
E2
E1
E3
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 3 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
Fig 3. Logic diag ram
001aae059
Y6
Y7
E1
E2
E3
A0
A1
A2
Y4
Y5
Y2
Y3
Y0
Y1
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 4. Pin configuratio n DIP16, SO16, SSOP16 and
TSSOP16 Fig 5. Pin configuration DHVQFN16
74HC138
74HCT138
A0 VCC
A1 Y0
A2 Y1
E1 Y2
E2 Y3
E3 Y4
Y7 Y5
GND Y6
001aae061
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aae060
74HC138BQ
74HCT138BQ
Y7 Y5
E3 Y4
E2 Y3
E1 Y2
A2 Y1
A1 Y0
GND
Y6
A0
VCC
Transparent top view
7 10
6 11
5 12
413
3 14
2 15
8
9
1
16
terminal 1
index area
GND(1)
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 4 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
Table 2. Pin description
Symbol Pin Description
A0, A1, A2 1, 2, 3 address input A0, A1, A2
E1, E2 4, 5 enable input E1, E2 (act i v e LO W)
E3 6 enable input E3 (active HIGH)
Y0, Y1, Y2, Y 3, Y4, Y5, Y6, Y7 15, 14, 13, 12, 11, 10, 9, 7 output Y0, Y1, Y2, Y3, Y4, Y 5, Y6, Y7 (active LOW)
GND 8 ground (0 V)
VCC 16 positive supply voltage
Table 3. Function table[1]
Control Input Output
E1 E2 E3 A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HXXXXXHHHHHHHH
XHX
XXL
L L H L L L HHHHHHHL
L L H HHHHHHLH
LHLHHHHHLHH
L H H HHHHLHHH
H L L HHHLHHHH
H L H HHLHHHHH
H H L HLHHHHHH
H H H LHHHHHHH
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI>V
CC +0.5 V - ±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC +0.5V - ±20 mA
IOoutput curr en t VO = −0.5 V to (VCC +0.5V) - ±25 mA
ICC quiescent supply current - 50 mA
IGND ground current - −50 mA
Tstg storage temperature −65 +150 °C
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 5 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
8. Recommended operating conditions
9. Static characteristics
Ptot total power dissipation
DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
SSOP16 package [3] - 500 mW
TSSOP16 package [3] - 500 mW
DHVQFN16 package [4] - 500 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
Table 5. Recommended operating con ditions
Vol tages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC138 74HCT138 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 13 9 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 25 °C Tamb = −40 °C to
+85 °CTamb = −40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC138
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 6 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=−20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=−20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=−20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=−4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=−5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current per input pin; VI=V
IH or VIL;
VO=V
CC or GND;
other inputs at VCC or GND;
VCC =6.0V; I
O=0A
--±0.5 - ±5.0 - ±10
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 μA
CIinput
capacitance -3.5- pF
74HCT138
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=−20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO=−4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20μA - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current per input pin; VI=V
IH or VIL;
VO=V
CC or GND;
other inputs at VCC or GND;
VCC =5.5V; I
O=0A
--±0.5 - ±5.0 - ±10
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80 - 160 μA
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 25 °C Tamb = −40 °C to
+85 °CTamb = −40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 7 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
10. Dynamic characteristics
ΔICC additional
supply current VI=V
CC −2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; An inputs - 150 540 - 675 - 735 μA
per input pin; En inputs - 125 450 - 562.5 - 612.5 μA
per input pin; E3 input - 100 360 - 450 - 490 μA
CIinput
capacitance -3.5- pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 25 °C Tamb = −40 °C to
+85 °CTamb = −40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
Table 7. Dynam ic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions Tamb = 25 °C Tamb = −40 °C
to +85 °CTamb = −40 °C
to +125 °CUnit
Min Typ Max Min Max Min Max
For type 74HC138
tpd propagation
delay An to Yn; see Figure 6 [1]
VCC = 2.0 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC =5V; C
L=15pF - 12 - - - - - ns
VCC = 6.0 V - 12 26 - 33 - 38 ns
E3 to Yn; see Figure 6 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 20 - 38 - 45 ns
VCC =5V; C
L=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
EntoYn; see Figure 7 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 20 - 38 - 45 ns
VCC =5V; C
L=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
tttransition
time Yn; see Figure 6 and
Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[3] -67- - - - -pF
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 8 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
For type 74HCT138
tpd propagation
delay An to Yn; see Figure 6 [1]
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC =5V; C
L=15pF - 17 - - - - - ns
E3 to Yn; see Figure 6 [1]
VCC = 4.5 V - 18 40 - 50 - 60 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
EntoYn; see Figure 7 [1]
VCC = 4.5 V - 19 40 - 50 - 60 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
tttransition
time Yn; see Figure 6 and
Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[3] -67- - - - -pF
Table 7. Dynam ic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions Tamb = 25 °C Tamb = −40 °C
to +85 °CTamb = −40 °C
to +125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 9 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (An) and enable input (E3) to output (Yn) and transition time output (Yn)
mna373
An, E3
input
Yn
output
tPHL
tTHL
tPLH
GND
VCC
VM
VM
VOH
VOL tTLH
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Prop agation delay e na ble input (En) to output (Yn) and transition time output (Yn)
mna374
E1, E2
input
Yn
output
tPHL tPLH
GND
VCC
VM
VM
VOH
VOL tTHL tTLH
Table 8. Measurement points
Type Input Output
VMVM
74HC138 0.5VCC 0.5VCC
74HCT138 1.3 V 1.3 V
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 10 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Z o of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Load circuitry for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC138 VCC 6ns 15pF, 50 pF 1 kΩopen GND VCC
74HCT138 3 V 6 ns 15 pF, 50 pF 1 kΩopen GND VCC
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 11 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
12. Package outline
Fig 9. Package outline SOT38-4 (DIP16)
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 12 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Fig 10. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 13 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Fig 11. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 14 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Fig 12. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 15 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Fig 13. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 16 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
Table 11. Revision history
Document ID Release date Data sheet status Change notice Doc. number Supersedes
74HC_HCT138 v.4 20120627 Product data sheet - - 74HC_HCT138 v.3
Modifications: •The format of this data sheet has been redesigned to comply with
the new identity guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new comp any name where
appropriate.
•SOT38-1 changed to SOT38-4.
74HC_HCT138 v.3 20051223 Product data sheet - - 74HC_HCT138_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
•Section 3 “Ordering information”, Section 5 “Pinning information” and Section 12 “Package
outline”: Added DHVQFN package information
•Section 9 “Static characteristics”: Added from the family specification
74HC_HCT138_CNV v.2 19970827 Product
specification ---
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 17 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe propert y or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT138 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 27 June 2012 18 of 19
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 June 2012
Document id entifier: 74HC_HCT13 8
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19