700 MHz to 2.7 GHz Quadrature Demodulator ADL5382 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM CMRF CMRF RFIP RFIN CMRF VPX 23 24 22 21 20 19 VPA 1 ADL5382 18 VPB COM 2 BIAS GEN 17 VPB BIAS 3 16 QHI 0 90 VPL 4 VPL 5 14 IHI VPL 6 13 ILO 7 CML 8 9 10 LOIP LOIN CML 15 QLO 11 12 CML COM 07208-001 Operating RF and LO frequency: 700 MHz to 2.7 GHz Input IP3 33.5 dBm @ 900 MHz 30.5 dBm @1900 MHz Input IP2: >70 dBm @ 900 MHz Input P1dB: 14.7 dBm @ 900 MHz Noise figure (NF) 14.0 dB @ 900 MHz 15.6 dB @ 1900 MHz Voltage conversion gain: ~4 dB Quadrature demodulation accuracy Phase accuracy: ~0.2 Amplitude balance: ~0.05 dB Demodulation bandwidth: ~370 MHz Baseband I/Q drive: 2 V p-p into 200 Single 5 V supply Figure 1. APPLICATIONS Cellular W-CDMA/CDMA/CDMA2000/GSM Microwave point-to-(multi)point radios Broadband wireless and WiMAX GENERAL DESCRIPTION The ADL5382 is a broadband quadrature I-Q demodulator that covers an RF input frequency range from 700 MHz to 2.7 GHz. With a NF = 14 dB, IP1dB = 14.7 dBm, and IIP3 = 33.5 dBm at 900 MHz, the ADL5382 demodulator offers outstanding dynamic range suitable for the demanding infrastructure direct-conversion requirements. The differential RF inputs provide a well-behaved broadband input impedance of 50 and are best driven from a 1:1 balun for optimum performance. The fully balanced design minimizes effects from second-order distortion. The leakage from the LO port to the RF port is <-65 dBc. Differential dc offsets at the I and Q outputs are typically <10 mV. Both of these factors contribute to the excellent IIP2 specifications which is >60 dBm. Excellent demodulation accuracy is achieved with amplitude and phase balances ~0.05 dB and ~0.2, respectively. The demodulated in-phase (I) and quadrature (Q) differential outputs are fully buffered and provide a voltage conversion gain of ~4 dB. The buffered baseband outputs are capable of driving a 2 V p-p differential signal into 200 . The ADL5382 is fabricated using the Analog Devices, Inc., advanced Silicon-Germanium bipolar process and is available in a 24-lead exposed paddle LFCSP. The ADL5382 operates off a single 4.75 V to 5.25 V supply. The supply current is adjustable with an external resistor from the BIAS pin to ground. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2012 Analog Devices, Inc. All rights reserved. ADL5382 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Emitter Follower Buffers ........................................................... 13 Applications ....................................................................................... 1 Bias Circuit .................................................................................. 13 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 14 General Description ......................................................................... 1 Basic Connections ...................................................................... 14 Revision History ............................................................................... 2 Power Supply............................................................................... 14 Specifications..................................................................................... 3 Local Oscillator (LO) Input ...................................................... 14 Absolute Maximum Ratings ............................................................ 5 RF Input ....................................................................................... 15 ESD Caution .................................................................................. 5 Baseband Outputs ...................................................................... 15 Pin Configuration and Function Descriptions ............................. 6 Error Vector Magnitude (EVM) Performance ........................... 16 Typical Performance Characteristics ............................................. 7 Low IF Image Rejection ............................................................. 17 Distributions for fRF = 900 MHz ............................................... 10 Example Baseband Interface ..................................................... 17 Distributions for fRF = 1900 MHz ............................................. 11 Characterization Setups ................................................................. 21 Distributions for fRF = 2700 MHz ............................................. 12 Evaluation Board ............................................................................ 23 Circuit Description ......................................................................... 13 Outline Dimensions ....................................................................... 27 LO Interface................................................................................. 13 Ordering Guide .......................................................................... 27 V-to-I Converter ......................................................................... 13 Mixers........................................................................................... 13 REVISION HISTORY 5/12--Rev. 0 to Rev. A Added JC = 3C/W to Table 2......................................................... 5 Added EPAD Note to Figure 2 ........................................................ 6 Updated Outline Dimensions ....................................................... 27 3/08--Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet ADL5382 SPECIFICATIONS VS = 5 V, TA = 25C, fLO = 900 MHz, fIF = 4.5 MHz, PLO = 0 dBm, BIAS pin open, ZO = 50 , unless otherwise noted. Baseband outputs differentially loaded with 450 . Loss of the balun used to drive the RF port was de-embedded from these measurements. Table 1. Parameter OPERATING CONDITIONS LO and RF Frequency Range LO INPUT Input Return Loss LO Input Level I/Q BASEBAND OUTPUTS Voltage Conversion Gain Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Output DC Offset (Differential) Output Common Mode 0.1 dB Gain Flatness Output Swing Peak Output Current POWER SUPPLIES Voltage Current DYNAMIC PERFORMANCE at RF = 900 MHz Conversion Gain Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) LO to RF RF to LO IQ Magnitude Imbalance IQ Phase Imbalance LO to IQ Noise Figure Noise Figure under Blocking Conditions DYNAMIC PERFORMANCE at RF = 1900 MHz Conversion Gain Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) LO to RF RF to LO IQ Magnitude Imbalance IQ Phase Imbalance LO to IQ Noise Figure Noise Figure under Blocking Conditions Condition Min Typ 0.7 LOIP, LOIN LO driven differentially through a balun at 900 MHz -6 QHI, QLO, IHI, ILO 450 differential load on I and Q outputs at 900 MHz 200 differential load on I and Q outputs at 900 MHz 1 V p-p signal, 3 dB bandwidth At 900 MHz -11 0 Differential 200 load Each pin VPA, VPL, VPB, VPX 4.75 -5 dBm each input tone -5 dBm each input tone RFIN, RFIP terminated in 50 LOIN, LOIP terminated in 50 RFIN, RFIP terminated in 50 With a -5 dBm interferer 5 MHz away -5 dBm each input tone -5 dBm each input tone RFIN, RFIP terminated in 50 LOIN, LOIP terminated in 50 RFIN, RFIP terminated in 50 With a -5 dBm interferer 5 MHz away Rev. A | Page 3 of 28 Unit 2.7 GHz +6 dB dBm 3.9 3.0 370 0.2 0.05 5 VPOS - 2.8 50 2 12 0 dBm LO input at 900 MHz BIAS pin open RBIAS = 4 k Max dB dB MHz Degrees dB mV V MHz V p-p mA 220 196 5.25 V mA mA 3.9 14.7 73 33.5 -92 -89 0.05 0.2 -43 14.0 19.9 dB dBm dBm dBm dBm dBc dB Degrees dBm dB dB 3.9 14.4 65 30.5 -71 -78 0.05 0.2 -41 15.6 20.5 dB dBm dBm dBm dBm dBc dB Degrees dBm dB dB ADL5382 Parameter DYNAMIC PERFORMANCE at RF = 2700 MHz Conversion Gain Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) LO to RF RF to LO IQ Magnitude Imbalance IQ Phase Imbalance LO to IQ Noise Figure Data Sheet Condition RFIP, RFIN Min -5 dBm each input tone -5 dBm each input tone RFIN, RFIP terminated in 50 , 1xLO appearing at RF port LOIN, LOIP terminated in 50 RFIN, RFIP terminated in 50 , 1xLO appearing at BB port Rev. A | Page 4 of 28 Typ 3.3 14.5 52 28.3 -70 -55 0.16 0.1 -42 17.6 Max Unit dB dBm dBm dBm dBm dBc dB Degrees dBm dB Data Sheet ADL5382 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VPA, VPL, VPB, VPX) LO Input Power RF Input Power Internal Maximum Power Dissipation JA JC Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 13 dBm (re: 50 ) 15 dBm (re: 50 ) 1230 mW 54C/W 3C/W 150C -40C to +85C -65C to +125C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 5 of 28 ADL5382 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 1 CMRF CMRF RFIP RFIN CMRF VPX VPA VPB 18 2 COM 3 BIAS VPB 17 QHI 16 ADL5382 VPL 5 VPL 6 VPL CML 7 TOP VIEW (Not to Scale) QLO 15 IHI 14 ILO 13 LOIP LOIN CML 8 9 10 CML COM 11 12 NOTES 1. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE. 07208-002 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 4 to 6, 17 to 19 2, 7, 10 to 12, 20, 23, 24 3 Mnemonic VPA, VPL, VPB, VPX 8, 9 LOIP, LOIN 13 to 16 ILO, IHI, QLO, QHI 21, 22 RFIN, RFIP COM, CML, CMRF BIAS EP Description Supply. Positive supply for LO, IF, biasing, and baseband sections. These pins should be decoupled to the board ground using appropriate-sized capacitors. Ground. Connect to a low impedance ground plane. Bias Control. A resistor (RBIAS) can be connected between BIAS and COM to reduce the mixer core current. The default setting for this pin is open. Local Oscillator Input. Pins must be ac-coupled. A differential drive through a balun (recommended balun is the M/A-COM ETC1-1-13) is necessary to achieve optimal performance. I Channel and Q Channel Mixer Baseband Outputs. These outputs have a 50 differential output impedance (25 per pin). The bias level on these pins is equal to VPOS - 2.8 V. Each output pair can swing 2 V p-p (differential) into a load of 200 . Output 3 dB bandwidth is 370 MHz. RF Input. A single-ended 50 signal can be applied to the RF inputs through a 1:1 balun (recommended balun is the M/A-COM ETC1-1-13). Ground-referenced inductors must also be connected to RFIP and RFIN (recommended values = 33 nH). Exposed Paddle. Connect to a low impedance thermal and electrical ground plane. Rev. A | Page 6 of 28 Data Sheet ADL5382 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, LO drive level = 0 dBm, RBIAS = open, RF input balun loss is de-embedded, unless otherwise noted. 20 2 TA = -40C TA = +25C TA = +85C INPUT P1dB 1 BASEBAND RESPONSE (dB) GAIN (dB), IP1dB (dBm) 0 15 10 GAIN 5 -1 -2 -3 -4 -5 -6 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) -8 07208-003 10 Figure 3. Conversion Gain and Input IP1 dB Compression Point (IP1dB) vs. RF Frequency 19 I CHANNEL Q CHANNEL 70 INPUT IP3 (I AND Q CHANNELS) 900 16 15 14 13 TA = -40C TA = +25C TA = +85C 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 12 700 07208-004 10 700 17 900 RF FREQUENCY (MHz) Figure 4. Input Third-Order Intercept (IIP3) and Input Second-Order Intercept Point (IIP2) vs. RF Frequency Figure 7. Noise Figure vs. RF Frequency 4 QUADRATURE PHASE ERROR (Degrees) 2.0 1.5 0.5 0 -0.5 -1.0 -2.0 700 TA = -40C TA = +25C TA = +85C 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) TA = -40C TA = +25C TA = +85C 3 2 1 0 -1 -2 -3 -4 700 07208-005 GAIN MISMATCH (dB) 1.0 -1.5 1100 1300 1500 1700 1900 2100 2300 2500 2700 07208-007 IIP3, IIP2 (dBm) NOISE FIGURE (dB) INPUT IP2 30 20 TA = -40C TA = +25C TA = +85C 18 50 40 1000 Figure 6. Normalized IQ Baseband Frequency Response 80 60 100 BASEBAND FREQUENCY (MHz) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 8. IQ Quadrature Phase Error vs. RF Frequency Figure 5. IQ Gain Mismatch vs. RF Frequency Rev. A | Page 7 of 28 07208-008 900 07208-006 -7 0 700 20 IP1dB NOISE FIGURE 50 10 IIP3 5 IIP3, IIP2 (dBm) 65 15 35 GAIN 20 0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 LO LEVEL (dBm) IP1dB 10 45 8 4 25 GAIN 2 15 -5 210 22 200 190 18 NOISE FIGURE -3 -2 -1 0 1 2 3 4 5 6 Figure 12. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs. LO Level, fRF = 1900 MHz 32 SUPPLY CURRENT (mA) 220 INPUT IP3 -4 LO LEVEL (dBm) 230 26 35 IIP3 6 TA = -40C TA = +25C TA = +85C 240 SUPPLY CURRENT 55 NOISE FIGURE 12 IIP3 (dBm) AND NOISE FIGURE (dB) IIP3 (dBm) AND NOISE FIGURE (dB) 30 65 14 250 TA = -40C TA = +25C TA = +85C IIP2, I CHANNEL 16 0 -6 Figure 9. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs. LO Level, fRF = 900 MHz 34 18 IIP3, IIP2 (dBm) IIP2, I CHANNEL 75 IIP2, Q CHANNEL 07208-012 80 IIP2, Q CHANNEL GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB) 20 Data Sheet 07208-009 GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB) ADL5382 180 14 28 INPUT IP3 24 20 NOISE FIGURE 16 12 170 8 RBIAS (k) 1 27 70 GAIN (dB), IP1dB (dBm), IIP2 I AND Q CHANNEL (dBm) 80 NOISE FIGURE (dB) 21 19 1900MHz 900MHz 17 15 60 50 900MHz: GAIN 900MHz: IP1dB 900MHz: IIP2, I CHANNEL 900MHz: IIP2, Q CHANNEL 1900MHz: GAIN 1900MHz: IP1dB 1900MHz: IIP2, I CHANNEL 1900MHz: IIP2, Q CHANNEL 40 30 20 10 -25 -20 -15 -10 -5 RF BLOCKER INPUT POWER (dBm) 0 5 07208-011 13 -30 100 Figure 13. IIP3 and Noise Figure vs. RBIAS, fRF = 1900 MHz 29 23 100 RBIAS (k) Figure 10. IIP3, Noise Figure, and Supply Current vs. RBIAS, fRF = 900 MHz 25 10 07208-013 10 07208-014 1 07208-010 160 100 10 Figure 11. Noise Figure vs. Input Blocker Level, fRF = 900 MHz, 1900 MHz (RF Blocker 5 MHz Offset) Rev. A | Page 8 of 28 0 1 10 RBIAS (k) Figure 14. Conversion Gain, IP1dB, IIP2_I, and IIP2_Q vs. RBIAS, fRF = 900 MHz, 1900MHz Data Sheet ADL5382 85 40 -20 I CHANNEL Q CHANNEL IIP3 35 75 IIP2 20 70 15 IP1dB 10 65 TA = -40C TA = +25C TA = +85C 0 10 -60 -70 -80 -90 20 30 40 60 50 BASEBAND FREQUENCY (MHz) -100 700 LO FREQUENCY (MHz) -10 -30 -20 -40 LEAKAGE (dBc) -20 -30 -40 -50 -50 -60 -70 -60 -80 -70 -90 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) -100 700 07208-016 LEAKAGE (dBm) 0 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 Figure 18. LO-to-RF Leakage vs. LO Frequency Figure 15. IP1dB, IIP3, and IIP2 vs. Baseband Frequency -80 700 900 07208-018 0 -50 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 07208-019 5 LEAKAGE (dBm) 25 -40 07208-015 IP1dB, IIP3 (dBm) 30 IIP2, I AND Q CHANNELS (dBm) -30 80 Figure 19. RF-to-LO Leakage vs. RF Frequency Figure 16. LO-to-BB Leakage vs. LO Frequency 0 0 -5 -5 -15 RETURN LOSS (dB) RETURN LOSS (dB) -10 -20 -25 -30 -35 -40 -10 -15 -20 -25 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) Figure 17. RF Port Return Loss vs. RF Frequency Measured on a Characterization Board through an ETC1-1-13 Balun with 33 nH Bias Inductors Rev. A | Page 9 of 28 -30 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 20. LO Port Return Loss vs. LO Frequency Measured on Characterization Board through an ETC1-1-13 Balun 07208-020 -50 700 07208-017 -45 ADL5382 Data Sheet DISTRIBUTIONS FOR fRF = 900 MHz 100 100 TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) 60 40 20 40 20 32 33 34 35 36 37 INPUT IP3 (dBm) 07208-021 31 0 45 Figure 21. IIP3 Distributions, fRF = 900 MHz 55 60 65 70 75 80 85 INPUT IP2 (dBm) Figure 24. IIP2 Distributions for I Channel and Q Channel, fRF = 900 MHz 100 100 TA = -40C TA = +25C TA = +85C 80 TA = -40C TA = +25C TA = +85C PERCENTAGE (%) 80 60 40 20 60 40 13 14 15 16 17 INPUT P1dB (dBm) 0 12.5 07208-022 12 14.0 14.5 15.0 15.5 Figure 25. Noise Figure Distributions, fRF = 900 MHz 100 TA = -40C TA = +25C TA = +85C 80 TA = -40C TA = +25C TA = +85C PERCENTAGE (%) 80 60 40 20 60 40 20 -0.1 0 0.1 GAIN MISMATCH (dB) 0.2 07208-023 0 -0.2 13.5 NOISE FIGURE (dB) Figure 22. IP1dB Distributions, fRF = 900 MHz 100 13.0 07208-025 20 0 PERCENTAGE (%) 50 07208-024 I CHANNEL Q CHANNEL 0 PERCENTAGE (%) 60 Figure 23. IQ Gain Mismatch Distributions, fRF = 900 MHz 0 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 QUADRATURE PHASE ERROR (Degrees) Figure 26. IQ Quadrature Phase Error Distributions, fRF = 900 MHz Rev. A | Page 10 of 28 07208-026 PERCENTAGE (%) 80 TA = -40C TA = +25C TA = +85C Data Sheet ADL5382 DISTRIBUTIONS FOR fRF = 1900 MHz 100 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) PERCENTAGE (%) 80 60 40 20 60 40 20 30 31 32 33 INPUT IP3 (dBm) 07208-027 29 0 45 Figure 27. IIP3 Distributions, fRF = 1900 MHz 100 65 70 75 80 85 TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) 60 40 20 60 40 14 15 16 17 INPUT P1dB (dBm) 0 14.0 07208-028 13 14.5 15.0 15.5 16.0 16.5 17.0 NOISE FIGURE (dB) Figure 28. IP1dB Distributions, fRF = 1900 MHz 07208-031 20 Figure 31. Noise Figure Distributions, fRF = 1900 MHz 100 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) 80 60 40 20 60 40 -0.1 0 0.1 GAIN MISMATCH (dB) 0.2 07208-029 20 Figure 29. IQ Gain Mismatch Distributions, fRF = 1900 MHz 0 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 QUADRATURE PHASE ERROR (Degrees) Figure 32. IQ Quadrature Phase Error Distributions, fRF = 1900 MHz Rev. A | Page 11 of 28 07208-032 PERCENTAGE (%) 80 PERCENTAGE (%) 60 Figure 30. IIP2 Distributions for I Channel and Q Channel, fRF = 1900 MHz TA = -40C TA = +25C TA = +85C 0 -0.2 55 INPUT IP2 (dBm) 100 0 12 50 07208-030 I CHANNEL Q CHANNEL 0 28 ADL5382 Data Sheet DISTRIBUTIONS FOR fRF = 2700 MHz 100 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) PERCENTAGE (%) 80 60 40 20 60 40 20 28 29 30 31 INPUT IP3 (dBm) 07208-033 27 0 45 Figure 33. IIP3 Distributions, fRF = 2700 MHz 100 65 70 75 80 85 TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) 60 40 20 60 40 14 15 16 17 INPUT P1dB (dBm) 0 16.0 07208-034 13 16.5 17.0 17.5 18.0 18.5 19.0 NOISE FIGURE (dB) Figure 34. IP1dB Distributions, fRF = 2700 MHz 07208-037 20 Figure 37. Noise Figure Distributions, fRF = 2700 MHz 100 100 TA = -40C TA = +25C TA = +85C TA = -40C TA = +25C TA = +85C 80 PERCENTAGE (%) 80 60 40 20 60 40 0 0.1 0.2 0.3 GAIN MISMATCH (dB) 07208-035 20 Figure 35. IQ Gain Mismatch Distributions, fRF = 2700 MHz 0 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 QUADRATURE PHASE ERROR (Degrees) Figure 38. IQ Quadrature Phase Error Distributions, fRF = 2700 MHz Rev. A | Page 12 of 28 07208-038 PERCENTAGE (%) 80 PERCENTAGE (%) 60 Figure 36. IIP2 Distributions for I Channel and Q Channel, fRF = 2700 MHz TA = -40C TA = +25C TA = +85C 0 -0.1 55 INPUT IP2 (dBm) 100 0 12 50 07208-036 I CHANNEL Q CHANNEL 0 26 Data Sheet ADL5382 CIRCUIT DESCRIPTION The ADL5382 can be divided into five sections: the local oscillator (LO) interface, the RF voltage-to-current (V-to-I) converter, the mixers, the differential emitter follower outputs, and the bias circuit. A detailed block diagram of the device is shown in Figure 39. BIAS The ADL5382 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). These mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers. ILO LOIP RFIN The differential RF input signal is applied to a resistively degenerated common base stage, which converts the differential input voltage to output currents. The output currents then modulate the two half frequency LO carriers in the mixer stage. MIXERS IHI RFIP V-TO-I CONVERTER EMITTER FOLLOWER BUFFERS POLYPHASE QUADRATURE PHASE SPLITTER The output emitter followers drive the differential I and Q signals off-chip. The output impedance is set by on-chip 25 series resistors that yield a 50 differential output impedance for each baseband port. The fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. For example, a 500 differential load has 1 dB lower effective gain than a high (10 k) differential load impedance. LOIN QLO 07208-039 QHI Figure 39. Block Diagram The LO interface generates two LO signals at 90 of phase difference to drive two mixers in quadrature. RF signals are converted into currents by the V-to-I converters that feed into the two mixers. The differential I and Q outputs of the mixers are buffered via emitter followers. Reference currents to each section are generated by the bias circuit. A detailed description of each section follows. LO INTERFACE The LO interface consists of a polyphase quadrature splitter followed by a limiting amplifier. The LO input impedance is set by the polyphase, which splits the LO signal into two differential signals in quadrature. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal. For optimal performance, the LO inputs must be driven differentially. BIAS CIRCUIT A band gap reference circuit generates the proportional-toabsolute temperature (PTAT) as well as temperature-independent reference currents used by different sections. The mixer current can be reduced via an external resistor between the BIAS pin and ground. When the BIAS pin is open, the mixer runs at maximum current and therefore the greatest dynamic range. The mixer current can be reduced by placing a resistance to ground; therefore, reducing overall power consumption, noise figure, and IIP3. The effect on each of these parameters is shown in Figure 10, Figure 13, and Figure 14. Rev. A | Page 13 of 28 ADL5382 Data Sheet APPLICATIONS INFORMATION BASIC CONNECTIONS LOCAL OSCILLATOR (LO) INPUT Figure 41 shows the basic connections schematic for the ADL5382. For optimum performance, the LO port should be driven differentially through a balun. The recommended balun is the M/A-COM ETC1-1-13. The LO inputs to the device should be ac-coupled with 1000 pF capacitors. The LO port is designed for a broadband 50 match from 700 MHz to 2.7 GHz. The LO return loss can be seen in Figure 20. Figure 40 shows the LO input configuration. POWER SUPPLY The nominal voltage supply for the ADL5382 is 5 V and is applied to the VPA, VPB, VPL, and VPX pins. Ground should be connected to the COM, CML, and CMRF pins. The exposed paddle on the underside of the package should also be soldered to a low thermal and electrical impedance ground plane. If the ground plane spans multiple layers on the circuit board, these layers should be stitched together with nine vias under the exposed paddle. The Application Note AN-772 discusses the thermal and electrical grounding of the LFCSP in detail. Each of the supply pins should be decoupled using two capacitors; recommended capacitor values are 100 pF and 0.1 F. LO INPUT 8 LOIP 9 LOIN 1000pF 07208-040 1000pF ETC1-1-13 Figure 40. Differential LO Drive The recommended LO drive level is between -6 dBm and +6 dBm. The applied LO frequency range is between 700 MHz and 2.7 GHz. ETC1-1-13 RFC 1000pF 1000pF 24 23 22 21 20 19 CMRF RFIP RFIN CMRF VPX VPOS 1 VPA 0.1F 33nH CMRF 33nH VPOS VPB 18 100pF 100pF 2 COM 0.1F VPB 17 3 BIAS QHI 16 QHI ADL5382 VPOS QLO 15 5 VPL IHI 14 6 VPL ILO 13 LOIP LOIN CML CML COM 100pF CML 7 8 9 10 11 12 1000pF QLO IHI ILO 1000pF ETC1-1-13 07208-041 0.1F 4 VPL LO Figure 41. Basic Connections Schematic Rev. A | Page 14 of 28 Data Sheet ADL5382 33nH 21 RFIN 22 RFIP 1000pF ETC1-1-13 1000pF RF INPUT 07208-042 33nH -10 -12 -14 -16 -18 -20 -22 -24 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 FREQUENCY (GHz) 2.7 2.9 07208-043 The RF inputs have a differential input impedance of approximately 50 . For optimum performance, the RF port should be driven differentially through a balun. The recommended balun is the M/A-COM ETC1-1-13. The RF inputs to the device should be ac-coupled with 1000 pF capacitors. Ground-referenced choke inductors must also be connected to RFIP and RFIN (the recommended value is 33 nH, Coilcraft 0603CS-33NX) for appropriate biasing. Several important aspects must be taken into account when selecting an appropriate choke inductor for this application. First, the inductor must be able to handle the approximately 40 mA of standing dc current being delivered from each of the RF input pins (RFIP, RFIN). The suggested 0603 inductor has a 600 mA current rating. The purpose of the choke inductors is to provide a very low resistance dc path to ground and high ac impedance at the RF frequency so as not to affect the RF input impedance. A choke inductor that has a selfresonant frequency greater than the RF input frequency ensures that the choke is still looking inductive and therefore has a more predictable ac impedance (jL) at the RF frequency. Figure 42 shows the RF input configuration. The differential RF port return loss is characterized as shown in Figure 43. S11 (dB) RF INPUT Figure 43. Differential RF Port Return Loss BASEBAND OUTPUTS The baseband outputs QHI, QLO, IHI, and ILO are fixed impedance ports. Each baseband pair has a 50 differential output impedance. The outputs can be presented with differential loads as low as 200 (with some degradation in gain) or high impedance differential loads (500 or greater impedance yields the same excellent linearity) that is typical of an ADC. The TCM9-1 9:1 balun converts the differential IF output to singleended. When loaded with 50 , this balun presents a 450 load to the device. The typical maximum linear voltage swing for these outputs is 2 V p-p differential. The bias level on these pins is equal to VPOS - 2.8 V. The output 3 dB bandwidth is 370 MHz. Figure 44 shows the baseband output configuration. QHI 16 QHI QLO 15 QLO IHI 14 IHI ILO 13 ILO 07208-044 Figure 42. RF Input Figure 44. Baseband Output Configuration Rev. A | Page 15 of 28 ADL5382 Data Sheet ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE 0 EVM is a measure used to quantify the performance of a digital radio transmitter or receiver. A signal received by a receiver would have all constellation points at the ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from the ideal locations. -5 -10 EVM (dB) -15 The ADL5382 shows excellent EVM performance for various modulation schemes. Figure 45 shows the EVM performance of the ADL5382 with a 16 QAM, 200 kHz low IF. -20 -25 -30 -35 -40 -50 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 -5 10 -20 Figure 47 exhibits multiple W-CDMA low-IF EVM performance curves over a wide RF input power range into the ADL5382. In the case of zero-IF, the noise contribution by the vector signal analyzer becomes predominant at lower power levels, making it difficult to measure SNR accurately. -25 -30 -35 -40 0 -45 -55 -45 -35 -25 -15 RF INPUT POWER (dBm) -5 -10 -15 Figure 45. EVM, RF = 900 MHz, IF = 200 kHz vs. RF Input Power for a 16 QAM 160 ksym/s Signal Figure 46 shows the zero-IF EVM performance of a 10 MHz IEEE 802.16e WiMAX signal through the ADL5382. The differential dc offsets on the ADL5382 are in the order of a few millivolts. However, ac coupling the baseband outputs with 10 F capacitors eliminates dc offsets and enhances EVM performance. With a 10 MHz BW signal, 10 F ac coupling capacitors with the 500 differential load results in a high-pass corner frequency of ~64 Hz, which absorbs an insignificant amount of modulated signal energy from the baseband signal. By using ac-coupling capacitors at the baseband outputs, the dc offset effects, which can limit dynamic range at low input power levels, can be eliminated. EVM (dB) -65 07208-045 -5 -75 -20 -25 -30 -35 0Hz 5MHz -40 -45 2.5MHz 7.5MHz -50 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 RF INPUT POWER (dBm) 07208-047 EVM (dB) 5 Figure 46. EVM, RF = 2.6 GHz, IF = 0 Hz vs. RF Input Power for a 16 QAM 10 MHz Bandwidth Mobile WiMAX Signal (AC-Coupled Baseband Outputs) -15 -50 -85 0 RF INPUT POWER (dBm) -10 07208-046 -45 0 Figure 47. EVM, RF = 1900 MHz, IF = 0 Hz, 2.5 MHz, 5 MHz, and 7.5 MHz vs. RF Input Power for a W-CDMA Signal (AC-Coupled Baseband Outputs) Rev. A | Page 16 of 28 Data Sheet ADL5382 COSLOt IF 0 IF -IF 0 +IF -90 0 +IF 0 +IF +90 LSB LO USB 0 0 +IF 07208-048 -IF SINLOt Figure 48. Illustration of the Image Problem LOW IF IMAGE REJECTION EXAMPLE BASEBAND INTERFACE The image rejection ratio is the ratio of the intermediate frequency (IF) signal level produced by the desired input frequency to that produced by the image frequency. The image rejection ratio is expressed in decibels. Appropriate image rejection is critical because the image power can be much higher than that of the desired signal, thereby plaguing the down conversion process. Figure 48 illustrates the image problem. If the upper sideband (lower sideband) is the desired band, a 90 shift to the Q channel (I channel) cancels the image at the lower sideband (upper sideband). Phase and gain balance between I and Q channels are critical for high levels of image rejection. In most direct conversion receiver designs, it is desirable to select a wanted carrier within a specified band. The desired channel can be demodulated by tuning the LO to the appropriate carrier frequency. If the desired RF band contains multiple carriers of interest, the adjacent carriers would also be down converted to a lower IF frequency. These adjacent carriers can be problematic if they are large relative to the wanted carrier as they can overdrive the baseband signal detection circuitry. As a result, it is often necessary to insert a filter to provide sufficient rejection of the adjacent carriers. Figure 49 shows the excellent image rejection capabilities of the ADL5382 for low IF applications, such as W-CDMA. The ADL5382 exhibits image rejection greater than 45 dB over a broad frequency range. 70 2.5MHz LOW IF 5MHz LOW IF IMAGE REJECTION (dB) 60 50 7.5MHz LOW IF 40 30 20 0 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 RF FREQUENCY (MHz) 07208-049 10 It is necessary to consider the overall source and load impedance presented by the ADL5382 and ADC input to design the filter network. The differential baseband output impedance of the ADL5382 is 50 . The ADL5382 is designed to drive a high impedance ADC input. It may be desirable to terminate the ADC input down to lower impedance by using a terminating resistor, such as 500 . The terminating resistor helps to better define the input impedance at the ADC input at the cost of a slightly reduced gain (see the Circuit Description section for details on the emitter-follower output loading effects). The order and type of filter network depends on the desired high frequency rejection required, pass-band ripple, and group delay. Filter design tables provide outlines for various filter types and orders, illustrating the normalized inductor and capacitor values for a 1 Hz cutoff frequency and 1 load. After scaling the normalized prototype element values by the actual desired cut-off frequency and load impedance, the series reactance elements are halved to realize the final balanced filter network component values. Figure 49. Image Rejection vs. RF Frequency for a W-CDMA Signal, IF = 2.5 MHz, 5 MHz, and 7.5 MHz Rev. A | Page 17 of 28 ADL5382 Data Sheet The balanced configuration is realized as the 0.54 H inductor is split in half to realize the network shown in Figure 50. LN = 0.074H NORMALIZED SINGLE-ENDED CONFIGURATION VS CN 14.814F 10 5 0 -5 -10 -15 RL= 500 -20 RS = 0.1 RL RS = 50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) 0.54H DENORMALIZED SINGLE-ENDED EQUIVALENT VS 0 fC = 1Hz 07208-051 RS = 50 Figure 51 and Figure 52 show the measured frequency response and group delay of the filter. MAGNITUDE RESPONSE (dB) As an example, a second-order Butterworth, low-pass filter design is shown in Figure 50 where the differential load impedance is 500 and the source impedance of the ADL5382 is 50 . The normalized series inductor value for the 10-to-1, load-to-source impedance ratio is 0.074 H, and the normalized shunt capacitor is 14.814 F. For a 10.9 MHz cutoff frequency, the single-ended equivalent circuit consists of a 0.54 H series inductor followed by a 433 pF shunt capacitor. Figure 51. Sixth-Order Baseband Filter Response 433pF 900 RL= 500 800 fC = 10.9MHz RL 2 = 250 RL = 250 2 0.27H Figure 50. Second-Order Butterworth, Low-Pass Filter Design Example A complete design example is shown in Figure 53. A sixth-order Butterworth differential filter having a 1.9 MHz corner frequency interfaces the output of the ADL5382 to that of an ADC input. The 500 load resistor defines the input impedance of the ADC. The filter adheres to typical direct conversion W-CDMA applications, where 1.92 MHz away from the carrier IF frequency, 1 dB of rejection is desired and 2.7 MHz away 10 dB of rejection is desired. Rev. A | Page 18 of 28 600 500 400 300 200 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (MHz) Figure 52. Sixth-Order Baseband Filter Group Delay 1.8 07208-052 RS = 25 2 433pF DELAY (ns) BALANCED CONFIGURATION VS 700 0.27H 07208-050 RS = 25 2 Data Sheet ADL5382 ETC1-1-13 RFC 1000pF 1000pF 33nH RFIP RFIN CMRF VPX 1 VPA 0.1F VPOS VPB 18 100pF 100pF 2 COM 27H 10H 27H 27H 10H 0.1F VPB 17 3 BIAS 27H CAC 10F ADC INPUT 19 ADC INPUT 20 500 21 10H 500 22 27H 68pF 23 27H 100pF 24 CMRF VPOS CMRF CAC 10F 270pF 33nH QHI 16 ADL5382 VPOS QLO 15 5 VPL IHI 14 6 VPL ILO 13 CML COM 9 10 11 12 68pF CML 8 100pF LOIN 7 CAC 10F 270pF LOIP 100pF CML 27H 27H 10H CAC 10F 1000pF 1000pF ETC1-1-13 LO Figure 53. Sixth-Order Low-Pass Butterworth, Baseband Filter Schematic Rev. A | Page 19 of 28 07208-053 0.1F 4 VPL ADL5382 Data Sheet 0 -5 -10 -15 -20 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 8H Figure 55. Fourth-Order Low-Pass W-CDMA Filter Magnitude Response 900 Figure 54. Fourth-Order Low-Pass W-CDMA Filter Schematic Figure 55 and Figure 56 illustrate the magnitude response and group delay response of the fourth-order filter, respectively. 800 DELAY (ns) 700 600 500 400 300 200 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 FREQUENCY (MHz) 1.6 1.8 2.0 07208-056 10H 07208-054 FREQUENCY (MHz) 07208-055 200 8H 100pF 680pF 50 10H 5 MAGNITUDE RESPONSE (dB) As the load impedance of the filter increases, the filter design becomes more challenging in terms of meeting the required rejection and pass band specifications. In the previous WCDMA example, the 500 load impedance resulted in the design of a sixth-order filter that has relatively large inductor values and small capacitor values. If the load impedance is 200 , the filter design becomes much more manageable. As shown in Figure 54, the resultant inductor and capacitor values become much more practical. Figure 56. Fourth-Order Low-Pass W-CDMA Filter Group Delay Response Rev. A | Page 20 of 28 Data Sheet ADL5382 CHARACTERIZATION SETUPS The two setups shown in Figure 57 and Figure 58 were used for making NF measurements. Figure 57 shows the setup for measuring NF with no blocker signal applied while Figure 58 was used to measure NF in the presence of a blocker. For both setups, the noise was measured at a baseband frequency of 10 MHz. For the case where a blocker was applied, the output blocker was at a 15 MHz baseband frequency. Note that great care must be taken when measuring NF in the presence of a blocker. The RF blocker generator must be filtered to prevent its noise (which increases with increasing generator output power) from swamping the noise contribution of the ADL5382. At least 30 dB of attention at the RF and image frequencies is desired. For example, assume a 915 MHz signal applied to the LO inputs of the ADL5382. To obtain a 15 MHz output blocker signal, the RF blocker generator is set to 930 MHz and the filters tuned such that there is at least 30 dB of attenuation from the generator at both the desired RF frequency (925 MHz) and the image RF frequency (905 MHz). Finally, the blocker must be removed from the output (by the 10 MHz low-pass filter) to prevent the blocker from swamping the analyzer. Figure 57 to Figure 59 show the general characterization bench setups used extensively for the ADL5382. The setup shown in Figure 59 was used to do the bulk of the testing and used sinusoidal signals on both the LO and RF inputs. An automated Agilent VEE program was used to control the equipment over the IEEE bus. This setup was used to measure gain, IP1dB, IIP2, IIP3, I/Q gain match, and quadrature error. The ADL5382 characterization board had a 9-to-1 impedance transformer on each of the differential baseband ports to do the differential-tosingle-ended conversion, which presented a 450 differential load to each baseband port, when interfaced with 50 test equipment. For all measurements of the ADL5382, the loss of the RF input balun (the M/A-COM ETC1-1-13 was used on RF input during characterization) was de-embedded. SNS OUTPUT RF ADL5382 VPOS CHAR BOARD I LO INPUT 6dB PAD HP 6235A POWER SUPPLY R1 50 AGILENT N8974A NOISE FIGURE ANALYZER LOW-PASS FILTER IEEE GND Q FROM SNS PORT CONTROL AGILENT 8665B SIGNAL GENERATOR PC CONTROLLER Figure 57. General Noise Figure Measurement Setup Rev. A | Page 21 of 28 07208-057 IEEE ADL5382 Data Sheet BAND-REJECT TUNABLE FILTER BAND-PASS TUNABLE FILTER 6dB PAD R&S SMT03 SIGNAL GENERATOR RF GND ADL5382 6dB PAD VPOS CHAR BOARD LOW-PASS FILTER I LO 6dB PAD HP 6235A POWER SUPPLY R&S FSEA30 SPECTRUM ANALYZER R1 50 Q HP87405 LOW NOISE PREAMP 07208-058 BAND-PASS CAVITY FILTER AGILENT 8665B SIGNAL GENERATOR Figure 58. Measurement Setup for Noise Figure in the Presence of a Blocker 3dB PAD RF AMPLIFIER 3dB PAD IN RF OUT 3dB PAD IEEE VP GND AGILENT 11636A 3dB PAD R&S SMT06 6dB PAD IEEE RF SWITCH MATRIX VPOS CHAR BOARD LO I 6dB PAD IEEE 6dB PAD AGILENT E3631 PWER SUPPLY RF INPUT AGILENT E8257D SIGNAL GENERATOR IEEE PC CONTROLLER IEEE R&S FSEA30 SPECTRUM ANALYZER Figure 59. General Characterization Setup Rev. A | Page 22 of 28 HP 8508A VECTOR VOLTMETER 07208-059 IEEE Q 6dB PAD ADL5382 IEEE RF GND INPUT CHANNELS A AND B R&S SMT06 Data Sheet ADL5382 EVALUATION BOARD The ADL5382 evaluation board is available. The board can be used for single-ended or differential baseband analysis. The default configuration of the board is for single-ended baseband analysis. T1 RFC C10 24 23 22 21 20 19 CMRF RFIP RFIN CMRF VPX L1 CMRF VPOS R1 1 VPA C1 C11 L2 R8 R7 R6 C8 C2 2 COM VPB 17 3 BIAS QHI 16 C9 R2 R9 QLO 15 5 VPL IHI 14 6 VPL ILO 13 T2 R16 LOIP LOIN CML CML COM C4 CML 7 8 9 10 11 12 QLO R10 R11 I OUTPUT OR IHI R4 R5 T3 C13 R13 ILO C6 C7 R12 T4 07208-060 C3 4 VPL R15 C12 R3 Q OUTPUT OR QHI R14 ADL5382 VPOS VPOS VPB 18 LO Figure 60. Evaluation Board Schematic Rev. A | Page 23 of 28 ADL5382 Data Sheet Table 4. Evaluation Board Configuration Options Component VPOS, GND R1, R3, R6 C1, C2, C3, C4, C8, C9 C6, C7, C10, C11 R4, R5, R9 to R16 L1, L2, R7, R8 T2, T3 C12, C13 T4 T1 R2 Function Power Supply and Ground Vector Pins. Power Supply Decoupling. Shorts or power supply decoupling resistors. These capacitors provide the required decoupling up to 2.7 GHz. AC Coupling Capacitors. These capacitors provide the required ac coupling from 700 MHz to 2.7 GHz. Single-Ended Baseband Output Path. This is the default configuration of the evaluation board. R14 to R16 and R4, R5, and R13 are populated for appropriate balun interface. R9, R10 and R11, R12 are not populated. Baseband outputs are taken from QHI and IHI. The user can reconfigure the board to use full differential baseband outputs. R9 to R12 provide a means to bypass the 9:1 TCM9-1 transformer to allow for differential baseband outputs. Access the differential baseband signals by populating R9 to R12 with 0 and not populating R4, R5, R13 to R16. This way the transformer does not need to be removed. The baseband outputs are taken from the SMAs of Q_HI, Q_LO, I_HI, and I_LO. Input Biasing. Inductance and resistance sets the input biasing of the common base input stage. The default value is 33 nH. IF Output Interface. TCM9-1 converts a differential high impedance IF output to a singleended output. When loaded with 50 , this balun presents a 450 load to the device. The center tap can be decoupled through a capacitor to ground. Decoupling Capacitors. C12 and C13 are the decoupling capacitors used to reject noise on the center tap of the TCM9-1. LO Input Interface. The LO is driven differentially. ETC1-1-13 is a 1:1 RF balun that converts the single-ended RF input to differential signal. RF Input Interface. ETC1-1-13 is a 1:1 RF balun that converts the single-ended RF input to differential signal. RBIAS. Optional bias setting resistor. See the Bias Circuit section to see how to use this feature. Rev. A | Page 24 of 28 Default Condition Not applicable R1, R3, R6 = 0 (0603) C2, C4, C8 = 100 pF (0402) C1, C3, C9 = 0.1 F (0603) C6, C10, C11 = 1000 pF (0402) C7 = open R4, R5, R13 to R16 = 0 (0402) R9 to R12 = open L1, L2 = 33 nH (0603CS-33NX, Coilcraft) R7, R8 = 0 (0402) T2, T3 = TCM9-1, 9:1 (Mini-Circuits) C12, C13 = 0.1 F (0402) T4 = ETC1-1-13, 1:1 (M/A-COM) T1 = ETC1-1-13, 1:1 (M/A-COM) R2 = open ADL5382 07208-062 07208-061 Data Sheet Figure 62. Evaluation Board Top Layer Silkscreen Figure 61. Evaluation Board Top Layer Rev. A | Page 25 of 28 Data Sheet Figure 63. Evaluation Board Bottom Layer 07208-064 07208-063 ADL5382 Figure 64. Evaluation Board Bottom Layer Silkscreen Rev. A | Page 26 of 28 Data Sheet ADL5382 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 18 3.75 BSC SQ 1 0.50 BSC 2.45 2.30 SQ 2.15 EXPOSED PAD 6 13 TOP VIEW 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 7 12 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-09-2012-A PIN 1 INDICATOR PIN 1 INDICATOR 24 19 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5382ACPZ-R7 ADL5382ACPZ-WP ADL5382-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead LFCSP_VQ, 7" Tape and Reel 24-Lead LFCSP_VQ, Waffle Pack Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 27 of 28 Package Option CP-24-2 CP-24-2 Ordering Quantity 1,500 64 ADL5382 Data Sheet NOTES (c)2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07208-0-5/12(A) Rev. A | Page 28 of 28