CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
Small Outline, 5 Lead, High
CMR, High Speed, Logic Gate
Optocouplers
Technical Data HCPL-M600
HCPL-M601
HCPL-M611
Description
These small outline high CMR,
high speed, logic gate optocoup-
lers are single channel devices in
a five lead miniature footprint.
They are electrically equivalent to
the following Agilent
optocouplers (except there is no
output enable feature):
SO-5 Package Standard DIP SO-8 Package
HCPL-M600 6N137 HCPL-0600
HCPL-M601 HCPL-2601 HCPL-0601
HCPL-M611 HCPL-2611 HCPL-0611
The SO-5 JEDEC registered (MO-
155) package outline does not
require “through holes” in a PCB.
This package occupies
approximately one fourth the
footprint area of the standard
dual-in-line package. The lead
profile is designed to be com-
patible with standard surface
mount processes.
The HCPL-M600/01/11 optically
coupled gates combine a GaAsP
light emitting diode and an
integrated high gain photon
detector. The output of the
detector I.C. is an Open-collector
Schottky-clamped transistor. The
internal shield provides a
guaranteed common mode
transient immunity specification of
5,000 V/µs for the HCPL-M601,
and 10,000 V/µs for the HCPL-
M611.
This unique design provides
maximum ac and dc circuit
isolation while achieving TTL
compatibility. The optocoupler ac
and dc operational parameters are
guaranteed from -40°C to 85°C
allowing trouble free system
performance.
Features
• Surface Mountable
• Very Small, Low Profile
JEDEC Registered Package
Outline
• Compatible with Infrared
Vapor Phase Reflow and
Wave Soldering Processes
• Internal Shield for High
Common Mode Rejection
(CMR)
HCPL-M601: 10,000 V/µs at
VCM = 50 V
HCPL-M611: 15,000 V/µs at
VCM = 1000 V
• High Speed: 10 Mbd
• LSTTL/TTL Compatible
• Low Input Current
Capability: 5 mA
• Guaranteed ac and dc
Performance over
Temperature: -40°C to 85°C
• Recognized under the
Component Program of U.L.
(File No. E55361) for
Dielectric Withstand Proof
Test Voltage of 2500 Vac, 1
Minute
2
The HCPL-M600/01/11 are
suitable for high speed logic
interfacing, input/output
buffering, as line receivers in
environments that conventional
line receivers cannot tolerate, and
are recommended for use in
extremely high ground or induced
noise environments.
Outline Drawing (JEDEC MO-155)
Applications
• Isolated Line Receiver
• Simplex/Multiplex Data
Transmission
• Computer-Peripheral
Interface
• Microprocessor System
Interface
• Digital Isolation for A/D, D/A
Conversion
• Switching Power Supply
• Instrument Input/Output
Isolation
• Ground Loop Elimination
• Pulse Transformer
Replacement
Pin Location (for reference only) Schematic
7.2
(0.28)
0.9
(0.04)
2.5
(0.10)
1.3
(0.05)
0.3
(0.01)
0.5
(0.02)
4.4
(0.17)
HCPL-M601/11 SHIELD
6
5
4
1
3
USE OF A 0.1 µF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN PINS
6 AND 4 (SEE NOTE 1).
I
F
I
CC
V
CC
V
O
GND
I
O
+
–
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
MXXX
XXX
6
5
43
1
7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
V
CC
V
OUT
GNDCATHODE
ANODE
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)
BSG
0.15 ± 0.025
(0.006 ± 0.001)
0.71
(0.028)MIN.
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
"Agilent" IS MARKED ON THE 
UNDERSIDE OF THE PACKAGE
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
3
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Input Current, Low Level IFL* 0 250 µA
Input Current, High Level IFH 515mA
Supply Voltage, Output V
CC 4.5 5.5 V
Fan Out (RL = 1 kΩ) N 5 TTL
Loads
Output Pull-Up Resistor RL330 4,000 Ω
Operating Temperature T
A-40 85 °C
* The off condition can also be guaranteed by ensuring that VF(off) ≤ 0.8 volts.
Absolute Maximum Ratings
(No Derating Required up to 85°C)
Storage Temperature .................................................... -55°C to +125°C
Operating Temperature .................................................. -40°C to +85°C
Forward Input Current - IF (see Note 2) ....................................... 20 mA
Reverse Input Voltage - VR................................................................. 5 V
Supply Voltage - VCC (1 Minute Maximum) ........................................ 7 V
Output Collector Current - IO........................................................ 50 mA
Output Collector Power Dissipation ............................................ 85 mW
Output Collector Voltage - VO............................................................ 7 V
(Selection for higher output voltages up to 20 V is available)
Infrared and Vapor Phase Reflow Temperature ....................... see below
Maximum Solder Reflow Thermal Profile.
(Note: Use of Non-Chlorine Activated Fluxes is Recommended.)
240
∆T = 115°C, 0.3°C/SEC
0
∆T = 100°C, 1.5°C/SEC
∆T = 145°C, 1°C/SEC
TIME – MINUTES
TEMPERATURE – °C
220
200
180
160
140
120
100
80
60
40
20
0
260
123456789101112
4
Electrical Specifications
Over recommended temperature (T
A = -40°C to 85°C) unless otherwise specified. (See note 1.)
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Input Threshold ITH 25mAV
CC = 5.5 V, IO ≥13 mA, 13
Current VO = 0.6 V
High Level Output IOH 5.5 100 µAV
CC = 5.5 V, VO = 5.5 V 1
Current IF = 250 µA
Low Level Output VOL 0.4 0.6 V VCC = 5.5 V, IF = 5 mA, 2, 4,
Voltage IOL (Sinking) = 13 mA 5, 13
High Level Supply ICCH 4 7.5 mA VCC = 5.5 V, IF = 0 mA,
Current
Low Level Supply ICCL 6 10.5 VCC = 5.5 V, IF = 10 mA,
Current
Input Forward VF1.4 1.75 V T
A = 25°C3
Voltage 1.5
1.3 1.85 IF = 10 mA
Input Reverse BVR5I
R
= 10 µA
Breakdown Voltage
Input Capacitance CIN 60 pF VF = 0V, f = 1 MHz
Input Diode ∆VF/∆TA-1.6 mV/°C I
F
= 10 mA 12
Temperature
Coefficient
Input-Output VISO 2500 VRMS RH ≤ 50%, t = 1 min. 3, 4
Insulation
Resistance RI-O 1012 ΩVI-O = 500 V 3
(Input-Output)
Capacitance CI-O 0.6 pF f = 1 MHz 3
(Input-Output)
*All typicals at T
A = 25°C, VCC = 5 V.
Insulation Related Specifications
Parameter Symbol Value Units Conditions
Min. External Air Gap L(IO1) ≥5 mm Measured from input terminals
(Clearance) to output terminals
Min. External Tracking Path L(IO2) ≥5 mm Measured from input terminals
(Creepage) to output terminals
Min. Internal Plastic Gap 0.08 mm Through insulation distance
(Clearance) conductor to conductor
Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109
5
Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
Device
Parameter Symbol HCPL- Min. Typ.* Max. Unit Test Conditions Fig. Note
Propagation tPLH 20 48 75 ns TA = 25°C 6, 7 5
Delay Time
to High 100 8
Output Level
Propagation tPHL 25 50 75 TA = 25°C 6, 7 6
Delay Time
to Low 100 RL = 350 Ω8
Output Level
Propagation tPSK 40 10,
Delay Skew 11
Pulse Width |tPHL - tPLH| 3.5 35 CL = 15 pF 9 10
Distortion
Output Rise trise 24
Time 10
(10%-90%)
Output Fall tfall 10
Time 10
(10%-90%)
Common |CMH| M600 10,000 V/µsV
CM = 10 V VO(min) = 2 V 11 7, 9
M601 5,000 10,000 VCM = 50 V
M611 10,000 15,000 VCM = 1000 V
Common |CMH| M600 10,000 VCM = 10 V VO(max) = 0.8 V 11 8, 9
M601 5,000 10,000 VCM = 50 V
M611 10,000 15,000 VCM = 1000 V
*All typicals at TA = 25°C, VCC = 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. The total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥3000 VRMS for 1 second
(Leakage detection current limit, II-O ≤ 5 µA).
5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., V
OUT > 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., V
OUT > 0.8 V).
9. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p).
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the worst case operating condition range.
Mode
Transient
Immunity at
High Output
Level
Mode
Transient
Immunity at
Low Output
Level
RL = 350 Ω
IF = 7.5 mA
TA = 25°C
RL = 350 Ω
IF = 0 mA
TA = 25°C
6
Figure 5. Low Level Output Current
vs. Temperature.
Figure 4. Output Voltage vs.
Forward Input current.
Figure 1. High Level Output
Current vs. Temperature. Figure 2. Low Level Output Voltage
vs. Temperature. Figure 3. Input Diode Forward
Characteristic.
Figure 6. Test Circuit for tPHL and tPLH.
I
OH
– HIGH LEVEL OUTPUT CURRENT – µA
-60
0
T
A
– TEMPERATURE – °C
100
10
15
-20
5
20
V
CC
= 5.5 V
V
O
= 5.5 V
I
F
= 250 µA
60
-40 0 40 80
V
CC
= 5.5 V
I
F
= 5.0 mA
0.5
0.4
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
0.3
80400-40
0.1
V
OL
– LOW LEVEL OUTPUT VOLTAGE – V
0.2
I
O
= 16 mA
I
O
= 12.8 mA
I
O
= 9.6 mA
I
O
= 6.4 mA
V
F
– FORWARD VOLTAGE – VOLTS
10
0.1
0.01
1.10 1.20 1.30 1.40
I
F
– FORWARD CURRENT – mA
1.601.50
1.0
0.001
100
I
F
V
F
+
T
A
= 25°C
–
1
6
2
3
4
5
123456
I
F
– FORWARD INPUT CURRENT – mA
R
L
= 350 Ω
R
L
= 1 KΩ
R
L
= 4 KΩ
00
V
CC
= 5 V
T
A
= 25 °C
V
O
– OUTPUT VOLTAGE – V
I
OL
– LOW LEVEL OUTPUT CURRENT – mA
-60
0
T
A
– TEMPERATURE – °C
100
60
80
-20
20
20
V
CC
= 5.0 V
V
OL
= 0.6 V
60-40 0 40 80
40
I
F
= 10 mA, 15 mA
I
F
= 5.0 mA
OUTPUT V
O
MONITORING 
NODE
1.5 V
t
PLH
t
PHL
I
F
INPUT
V
O
OUTPUT
I
F
= 7.5 mA
I
F
= 3.75 mA
+5 V
I
F
R
L
R
M
0.1µF
BYPASS
*C
L
*C
L
IS APPROXIMATELY 15 pF WHICH INCLUDES 
PROBE AND STRAY WIRING CAPACITANCE.
INPUT
MONITORING
NODE
PULSE GEN.
Z
O
= 50 Ω
t
f
= t
r
= 5 ns
V
CC
GND
1
3
6
5
4
7
Figure 12. Temperature Coefficient
for Forward Voltage vs. Input
Current.
Figure 10. Rise and Fall Time vs.
Temperature.
Figure 9. Pulse Width Distortion vs.
Temperature.
Figure 8. Propagation Delay vs.
Pulse Input Current.
Figure 7. Propagation Delay vs.
Temperature.
Figure 11. Test Circuit for Common
Mode Transient Immunity and
Typical Waveforms.
V
CC
= 5.0 V
I
F
= 7.5 mA
100
80
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
60
80400-40
0
t
P
– PROPAGATION DELAY – ns
40
20
t
PLH
, R
L
= 4 KΩ
t
PLH
, R
L
= 1 KΩ
t
PLH
, R
L
= 350 Ω
t
PHL
, R
L
= 350 Ω
1 KΩ
4 KΩ
V
CC
= 5.0 V
T
A
= 25°C
105
90
5913
I
F
– PULSE INPUT CURRENT – mA
75
15117
30
t
P
– PROPAGATION DELAY – ns
60
45
t
PLH
, R
L
= 4 KΩ
t
PLH
, R
L
= 1 KΩ
t
PLH
, R
L
= 350 Ω
t
PHL
, R
L
= 350 Ω
1 KΩ
4 KΩ
V
CC
= 5.0 V
I
F
= 7.5 mA
40
30
-20 20 60 100
T
A
– TEMPERATURE – °C
20
80400-40
PWD – PULSE WIDTH DISTORTION – ns
10 R
L
= 350 kΩ
R
L
= 1 kΩ
R
L
= 4 kΩ
0
-60
-10
t
r
, t
f
– RISE, FALL TIME – ns
-60
0
T
A
– TEMPERATURE – °C
100
300
-20
40
20 60-40 0 40 80
60
290
20
V
CC
= 5.0 V
I
F
= 7.5 mA
R
L
= 4 kΩ
R
L
= 1 kΩ
R
L
= 350 Ω, 1 kΩ, 4 kΩ
t
RISE
t
FALL
R
L
= 350 Ω
dVF/
dT
– FORWARD VOLTAGE 
TEMPERATURE COEFFICIENT – mV/°C
0.1 1 10 100
I
F
– PULSE INPUT CURRENT – mA
-1.4
-2.2
-2.0
-1.8
-1.6
-1.2
-2.4
V
O
0.5 V
V
O
(MIN.)
5 V
0 V SWITCH AT A: I
F
= 0 mA
SWITCH AT B: I
F
= 7.5 mA
V
CM
CM
H
CM
L
V
O
(MAX.)
V
CM
(PEAK)
V
O
+5 V
0.1 µF
BYPASS
+_
350 Ω
V
FF
1
3
6
5
4
B
AOUTPUT V
O
MONITORING 
NODE
IF
PULSE
GENERATOR
Z
O
= 50 Ω
V
CC
GND
8
Propagation Delay, Pulse-
Width Distortion and
Propagation Delay Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (tPLH)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low (see
Figure 7).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ in
value. PWD is defined as the
difference between tPLH and tPHL
and often determines the maxi-
mum data rate capability of a
transmission system. PWD can
be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically, PWD
on the order of 20-30% of the
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-1, etc.).
Propagation delay skew, tPSK, is
an important parameter to
consider in parallel data appli-
cations where synchronization of
signals on parallel data lines is a
concern. If the parallel data is
being sent through a group of
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of the
optocouplers at different times. If
this difference in propagation
delays is large enough, it will
determine the maximum rate at
which parallel data can be sent
through the optocouplers.
Propagation delay skew is defined
as the difference between the
minimum and maximum
propagation delays, either tPLH or
tPHL, for any given group of
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
operating temperature). As
illustrated in Figure 15, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, tPSK is the
difference between the shortest
propagation delay, either tPLH or
tPHL, and the longest propagation
delay, either tPLH or tPHL.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 11
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
Propagation delay skew
represents the uncertainty of
where an edge might be after
being sent through an
optocoupler. Figure 16 shows
that there will be uncertainty in
both the data and the clock lines.
It is important that these two
areas of uncertainty not overlap,
otherwise the clock signal might
arrive before all of the data
outputs have settled, or some of
the data outputs may start to
change before the clock signal
has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice tPSK. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
The tPSK specified optocouplers
offer the advantages of
guaranteed specifications for
propagation delays, pulse-width
distortion and propagation delay
skew over the recommended
temperature, and input current,
and power supply ranges.
9
Figure 15. Illustration of
Propagation Delay Skew – tPSK.
Figure 13. Input Threshold Current
vs. Temperature. Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
Figure 16. Parallel Data Transmission Example.
I
TH
– INPUT THRESHOLD CURRENT – mA
-60
0
T
A
– TEMPERATURE – °C
100
4
5
-20
2
20 60-40 0 40 80
3
V
CC
= 5.0 V
V
O
= 0.6 V
1R
L
= 4 kΩ
R
L
= 1 kΩR
L
= 350 Ω
6
V
CC
1
GND 1
470
SHIELD
* DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED
FOR UNITS WITH OPEN COLLECTOR OUTPUT.
6
5
4
390 Ω
0.1 µF
BYPASS
GND 2
V
CC
2
1
3
*D1
5 V
5 V
I
F
V
F
2
1
50%
1.5 V
I
F
V
O
50%I
F
V
O
t
PSK
1.5 V
DATA
tPSK
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
tPSK
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5091-9635E (10/93)
5966-4942E (11/99)