Low Power, 18 MHz Variable Gain Amplifier
Data Sheet
AD8338
Rev. A Document Feedback
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FEATURES
Voltage controlled gain range of 0 dB to 80 dB
3 mA supply current at gain of 40 dB
Low frequency (LF) to 18 MHz operation
Supply range: 3.0 V to 5.0 V
Low noise: 4.5 nV/
√
Hz at 80 dB gain
Fully differential signal path
Offset correction (offset null) feature
Internal 1.5 V reference
16-lead LFCSP
Automatic gain control feature
Wide gain range for high dynamic range signals
APPLICATIONS
Front end for inductive telemetry systems
Ultrasonic signal receivers
Signal compression for driving an ADC
AGC amplifiers
GENERAL DESCRIPTION
The AD8338 is a variable gain amplifier (VGA) for applications
that require a fully differential signal path, low power, low noise,
and a well-defined gain over frequency. While the inputs are
differential, the device can also be driven with a single-ended
source if required.
The basic gain function is linear-in-dB and is controlled by the
voltage applied to Pin GAIN. The nominal gain range spans
from 0 dB to 80 dB for control voltages between 0.1 V to 1.1 V
with a slope of 12.5 mV/dB. The nominal gain range can be
shifted up or down via direct access to Pin INPD and Pin INMD,
the current inputs of the VGA. For example, driving the INPD
and INMD pins with 50 Ω resistors shifts the gain range up by
20 dB, that is, 20 dB to 100 dB, and lowers the input referred
noise of the device to 1.5 nV/√Hz. Additionally, the gain slope
can be inverted via logic Pin MODE.
The AD8338 includes additional circuit blocks to enable input
offset correction and automatic gain control (AGC). DC offset
voltages are removed by the offset correction circuit, which
behaves like a high-pass filter whose corner is set with an
external capacitor. The AGC function varies the gain of the
AD8338 to maintain a constant RMS output voltage. An
externally applied voltage to Pin VAGC with respect to the
voltage at Pin VREF sets the output RMS amplitude. A
capacitor from Pin DETO to ground sets the response time
of the AGC circuit.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Figure 2. Gain vs. Frequency
The AD8338 offers additional versatility by providing access to
the internal summing nodes of the VGA core and the output
amplifiers. With the addition of a few external passive
components, users can customize the gain, bandwidth, input
impedance, and noise profile of the part to fit their application.
The AD8338 uses a single supply voltage of 3.0 V to 5.0 V and
is very power efficient, consuming as little as 3 mA quiescent
current at mid gain. The AD8338 is available in a 3 mm ×
3 mm, RoHS compliant, 16-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
INPR
INPD
INMD
INMR
MODECOMM GAIN
FBKM
OUTP
OUTM
DETO VAGC
FBKP
+
–
+
–
VREF
VG A CORE
0dB TO 80dB
OFFSET NULL
OUTPUT
STAGE
0dB
OFSN VREF
VBAT
AUTOMATIC
GAIN
CONTROL
GAIN INTE RFACE
AD8338
11279-001
100
–40
–20
0
20
40
60
80
10k 100M10M1M100k
GAIN (dB)
FRE QUENCY (Hz)
VGAIN = 0.1V
VGAIN = 0.2V
VGAIN = 0.3V
VGAIN = 0.4V
VGAIN = 0.5V
VGAIN = 0.6V
VGAIN = 0.7V
VGAIN = 0.8V
VGAIN = 0.9V
VGAIN = 1.0V
VGAIN = 1.1V
11279-005
AD8338 Data Sheet
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Specifications .......................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 12
Introduction ................................................................................ 12
Explanation of the Gain Function ............................................ 16
Adjusting The Output Common Mode .................................. 17
Applications Information .............................................................. 18
Simple On-Off Keyed (OOK) Receiver ................................... 18
Interfacing the AD8338 to an ADC ......................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
11/13—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and General
Descriptions Section ........................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Pin 13 and Pin 14 Descriptions .................................. 5
Added Conditions to Typical Performance Characteristics;
Changes to Figure 4 and Figure 5; Changes to Figure 6, Figure 7,
Figure 8 Captions .............................................................................. 6
Changes to Figure 12 and Figure 13............................................... 7
Changes to Figure 18 and Figure 19............................................... 8
Changes to Figure 22 ........................................................................ 9
Changes to Figure 35 and Figure 36............................................. 11
Replaced Theory of Operation Section ....................................... 12
Changes to Figure 50 ...................................................................... 18
Changes to Ordering Guide .......................................................... 20
4/13—Revision 0: Initial Version
Data Sheet AD8338
Rev. A | Page 3 of 20
SPECIFICATIONS
AC SPECIFICATIONS
VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation,
unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT INTERFACE INPD, INMD, INPR, INMR pins
Input Voltage Range 3 V p-p
−3 dB Bandwidth 18 MHz
Input Resistance Standard configuration using the INPR and
INMR inputs
0.8 1 1.2 kΩ
Input Capacitance 2 pF
OUTPUT INTERFACE OUTP and OUTM pins
Small Signal Bandwidth VGAIN = 0.6 V 18 MHz
Peak Slew Rate VGAIN = 0.6 V 50 V/µs
Peak-to-Peak Output Swing Differential output 2.8 V p-p
Common-Mode Voltage 1.5 V
Input-Referred Voltage Noise
Using Internal Resistors VGAIN = 1.1 V 4.5 nV/√Hz
VGAIN = 0.6 V 15 nV/√Hz
VGAIN = 0.1 V 150 nV/√Hz
Using External 47 Ω Resistors VGAIN = 1.1 V 1.5 nV/√Hz
Offset Voltage
RTO, V
GAIN
= 0.1 V, offset null enabled
−10
+10
mV
RTO, VGAIN = 0.6 V, offset null enabled −10 +10 mV
RTO, VGAIN = 0.1 V, offset null disabled −50 +50 mV
RTO, VGAIN = 0.6 V, offset null disabled −200 +200 mV
POWER SUPPLY
VBAT
3.0
5.0
V
IVBAT Min gain, VGAIN = 0.1 V 6.0 8.0 mA
Mid gain, VGAIN = 0.6 V 3.0 3.8 mA
Max gain, VGAIN = 1.1 V 4.5 6.0 mA
GAIN CONTROL
Gain Range Standard configuration using the INPR and
INMR inputs
0 80 dB
Gain Span 80 dB
Gain Voltage VGAIN relative to COMM 0.1 1.1 V
Gain Slope
77
80
83
dB/V
12 12.5 13 mV/dB
Gain Accuracy Standard configuration using the INPR and
INMR inputs; 0.1 V < VGAIN < 1.1 V
−2 +0.5 +2 dB
VREF REFERENCE OUTPUT
Output Voltage 1.5 V
Output Current 5 mA
Accuracy 2 %
DETO OUTPUT CURRENT ±10 µA
MODE INPUT
Logic High 2.5 VBAT V
Logic Low COMM 0.6 V
AGC CONTROL MODE = 0 V
Maximum Target Amplitude Expected rms output value for target =
VAGC − VREF = 1.0 V
1.0 V rms
AD8338 Data Sheet
Rev. A | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VBAT to COMM −0.3 V to +5.5 V
INPR, INPD, INMD, INMR, MODE, GAIN,
FBKM, FBKP, OUTM, OUTP, VAGC,
VREF, OFSN
COMM to VBAT
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 3. Thermal Resistance
Package Type θJA Unit
16-Lead LFCSP 48.75 °C/W
ESD CAUTION
Data Sheet AD8338
Rev. A | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
0
EPAD
Exposed Pad. The exposed pad should be tied to a quiet analog ground.
1 INPR Positive 500 Ω Resistor Input for Voltage Input Applications.
2 INPD Positive Input for Current Input Applications.
3 INMD Negative Input for Current Input Applications.
4 INMR Negative 500 Ω Resistor Input for Voltage Input Applications.
5 COMM Ground.
6 MODE Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the
gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is
tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin.
7 GAIN Gain Control Input, 12.5 mV/dB or 80 dB/V.
8 DETO Detector Output Terminal, ±10 µA. If the AGC feature is not used, tie DETO to COMM.
9 FBKM Negative Feedback Node. For more information, see the FBKP, FBKM, OUTP, and OUTM Pins section.
10 OUTM Negative Output.
11 OUTP Positive Output.
12 FBKP Positive Feedback Node. For more information, see the FBKP, FBKM, OUTP, and OUTM Pins section.
13 VAGC Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit.
For more information, see the AGC Circuit, VAGC Pin section. If the AGC feature is not used, tie VAGC to VREF.
14
OFSN
Offset Null Terminal. For more information, see the Offset Correction Circuit, OFSN Pin section. If the offset null
feature is not used, tie OFSN to ground; otherwise, a capacitor to VREF is used to set the offset null high-pass
corner.
15 VBAT Positive Supply Voltage.
16 VREF Internal 1.5 V Voltage Reference.
1INPR
2INPD 3INMD 4INMR
11 OUTP
12 FBKP
10 OUTM
9FBKM
5COMM
6MODE 7GAIN 8DETO
15 VBAT
16 VREF
14 OFSN
13 VAGC
AD8338
TOP VI EW
(No t t o Scale)
NOTES
1. THE EXPOSED PAD SHOULD BE TIED
TO A QUIET ANALOG GROUND.
11279-002
AD8338 Data Sheet
Rev. A | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation;
unless otherwise noted.
Figure 4. Gain vs. VGAIN
Figure 5. Gain Slope Histogram
Figure 6. Gain vs. Frequency, 8 dB Steps
Figure 7. Gain vs. Frequency, RIN = 50 Ω, 20 dB Steps
Figure 8. Gain vs. Frequency, RIN = 5 kΩ, 20 dB Steps
Figure 9. Gain Error vs. VGAIN over Temperature
80
0
10
20
30
40
50
60
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
GAIN (dB)
V
GAIN
(V)
MODE PIN LOW MODE PIN HIGH
11279-003
80
0
10
20
30
40
50
60
70
NUMBER OF HITS
GAIN SLOPE (dB/V)
78.0 78.3 78.6 78.9 79.2 79.5 79.8 80.1 80.4
11279-105
N = 962
100
–40
–20
0
20
40
60
80
10k 100M10M1M100k
GAIN (dB)
FRE QUENCY (Hz)
VGAIN = 0. 1V
VGAIN = 0. 2V
VGAIN = 0. 3V
VGAIN = 0. 4V
VGAIN = 0. 5V
VGAIN = 0. 6V
VGAIN = 0. 7V
VGAIN = 0. 8V
VGAIN = 0. 9V
VGAIN = 1. 0V
VGAIN = 1. 1V
11279-106
80
–60
–40
–20
0
20
40
60
100k 1M 10M 100M
GAIN (dB)
FRE QUENCY (Hz)
VGAIN = 100mV
VGAIN = 350mV
VGAIN = 600mV
11279-109
80
–80
–60
–40
–20
0
20
40
60
100k 1M 10M 100M
GAIN (dB)
FRE QUENCY (Hz)
VGAIN = 100mV
VGAIN = 350mV
VGAIN = 600mV
VGAIN = 850mV
VGAIN = 1100mV
11279-107
5
–5
–4
–3
–2
–1
0
1
2
3
4
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
GAIN ERROR (dB)
V
GAIN
(V)
–40°C
+25°C
+85°C
+105°C
V
S
= 3V
f = 1MHz
11279-006
Data Sheet AD8338
Rev. A | Page 7 of 20
Figure 10. Gain Error vs. VGAIN over Frequency
Figure 11. Group Delay vs. Frequency
Figure 12. Differential Offset Voltage Histogram
Figure 13. Differential Offset Voltage vs. VGAIN, Offset Null On
Figure 14. Output Impedance vs. Frequency
Figure 15. Output Balance Error vs. Frequency
1.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
GAIN ERROR (dB)
V
GAIN
(V)
10kHz
100kHz
1MHz
2MHz
4MHz
8MHz
10MHz
12MHz
14MHz
11279-007
30
0
5
10
15
20
25
100k 1M 10M 100M
DEL AY ( ns)
FRE QUENCY (Hz)
11279-110
0
10
20
30
40
50
60
NUMBER OF HITS
DIFFERENTIAL OFFSET VOLTAGE (mV)
–3 –2 –1 012
11279-111
OFFSET NULL ENABLED
RELATIVE TO OUTPUT
VGAIN = 0. 6V
N = 962
5
–5
–4
–3
–2
–1
0
1
2
3
4
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
OFFSET VOLTAGE (mV)
REF E RRE D TO OUTPUT
VGAIN (V)
–40°C
+25°C
+85°C
+105°C
11279-012
350
300
0
50
100
150
200
250
100k 1M 10M 100M
IMPEDANCE (Ω)
FRE QUENCY (Hz)
SINGLE-ENDED
DIFFERENTIAL
11279-112
20
–120
–100
–80
–60
–40
–20
0
100k 1M 10M 100M
BALANCE E RROR (dB)
FRE QUENCY (Hz)
11279-015
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
AD8338 Data Sheet
Rev. A | Page 8 of 20
Figure 16. CMRR vs. Frequency over Gain, Offset Null On,
Referred to Input
Figure 17. Output Referred Noise vs. VGAIN
Figure 18. Input Referred Noise vs. VGAIN
Figure 19. Input Referred Noise vs. Frequency
Figure 20. Harmonic Distortion vs. Frequency
Figure 21. Harmonic Distortion vs. Output Amplitude
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10k 100k 1M 10M
CMRR (dB)
FRE QUENCY (Hz)
0dB
20dB
40dB
60dB
80dB
11279-115
100k
10k
1k
100 00.4 0.8 1.20.3 0.7 1.10.2 0.6 1.00.1 0.5 0.9
NOISE (nV/ Hz)
V
GAIN
(V)
11279-017
+85°C
–40°C
+25°C
1k
1
10
100
01.21.11.00.90.80.70.60.50.40.30.20.1
NOISE (nV/ Hz)
V
GAIN
(V)
11279-119
+85°C
–40°C
+25°C
1k
0.1
1
10
100
10k 100k 1M 100M10M
NOISE (nV/ Hz)
FRE QUENCY (Hz)
11279-117
GAIN = 1, O FSN DIS ABLED
GAIN = 10, O FSN DIS ABLED
GAIN = 100, O FSN DIS ABLED
GAIN = 1000, O FSN ENABL E D
GAIN = 10000, O FSN ENABL E D
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
50k 500k 5M
HARMO NIC DIST ORTI ON (dBc)
FRE QUENCY (Hz)
HD2, 1kΩ
HD3, 1kΩ
HD2, 10kΩ
HD3, 10kΩ
V
OUT
= 0.5V p-p
11279-118
0
–10
–20
–30
–40
–50
–60
–70
–800.5 3.02.52.01.51.0
HARMO NIC DIST ORTI ON (dBc)
V
OUT
(V p-p)
HD2
HD3
11279-120
Data Sheet AD8338
Rev. A | Page 9 of 20
Figure 22. Harmonic Distortion vs. VGAIN
Figure 23. Input and Output 1 dB Compression vs. VGAIN
Figure 24. OIP3 vs. VGAIN
Figure 25. IMD3 Distortion vs. Frequency
Figure 26. Large Signal Pulse Response vs. Time, VGAIN = 0 V
Figure 27. Large Signal Pulse Response vs. Time, VGAIN = 1.0 V
0
–10
–20
–30
–40
–50
–60
–70
–800.1 1.10.90.70.50.3 1.00.80.60.40.2
HARMO NIC DIST ORTI ON (dBc)
V
GAIN
(V)
HD2, M ODE PIN HIGH
11279-123
V
OUT
= 0.5V p-p
HD2, M ODE PIN LOW
HD3, M ODE PIN HIGH
HD3, M ODE PIN LOW
20
10
0
–10
–20
–30
–40
–50
–60
–700.1 0.3 0.5 0.7 0.9 1.1
P1d B COMPRESS ION (dBm)
V
GAIN
(V)
11279-122
OUTPUT
INPUT
25
0
5
10
15
20
0.1 1.10.90.5 0.70.3
OIP3 (dBm)
V
GAIN
(V)
11279-125
100kHz
1MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
20k 20M2M200k
IMD3 DISTORTION (dBc)
FRE QUENCY (Hz)
11279-124
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0100 200 300 400 500 600 700 800
VOUT (V)
TIME (n s)
VOUT = 2V p-p
f = 1MHz
GAIN = 0dB
11279-027
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
00.2 0.4 0.6 0.8
V
OUT
(V)
TIME (µs)
V
OUT
= 2V p-p
f = 1MHz
GAIN = 80dB
11279-028
AD8338 Data Sheet
Rev. A | Page 10 of 20
Figure 28. Large Signal Pulse Response vs. Time, VGAIN = 0.6 V
Figure 29. Small Signal Pulse Response vs. Time (Varying Capacitive Loads)
Figure 30. Gain Step Response vs. Time
Figure 31. Overdrive Recovery vs. Time
Figure 32. Supply Current vs. VGAIN
Figure 33. Offset Null Bandwidth vs. Offset Null Capacitor
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
00.2 0.4 0.6 0.8
V
OUT
(V)
TIME (µs)
V
OUT
= 2V p-p
f = 1MHz
GAIN = 40dB
11279-030
100
–100
–80
–60
–40
–20
0
20
40
60
80
00.2 0.4 0.6 0.8
V
OUT
(mV)
TIME (µs)
C
L
= 0pF
C
L
= 10pF
C
L
= 20pF
C
L
= 47pF
V
OUT
= 100mV p - p
f = 1. 5M Hz
GAIN = 1
11279-031
0.6
0.1
1.0
0
–1.0
0108642 97531
GAIN STEP (V)
TIME (µs)
11279-127
V
GAIN
V
OUT
1.5
0.5
1.0
0
–0.5
–1.5
–1.0
080 160 20060 14040 12020 100 180
OUTPUT VOLTAGE (V)
TIME (µs)
11279-018
f = 100kHz
V
IN
LOW = 2mV
V
IN
HIGH = 20mV
GAIN = 40dB
12
10
8
6
4
2
001.21.11.00.80.60.40.2 0.90.70.50.30.1
I
DD
(mA)
V
GAIN
(V)
–40°C, MODE P IN HIG H
+25° C, MODE P IN HIG H
+85° C, MODE P IN HIG H
–40°C, MODE P IN LO W
+25° C, MODE P IN LO W
+85° C, MODE P IN LO W
11279-131
50
–40
–30
–20
–10
0
10
20
30
40
20 100 1k 10k 100k 1M 10M 100M
GAIN (dB)
FRE QUENCY (Hz)
11279-134
0.01µF
0.1µF
1µF
10µF
OFFSET NULL OFF
GAIN = 100
Data Sheet AD8338
Rev. A | Page 11 of 20
Figure 34. PSRR vs. Frequency
Figure 35. AGC Response vs. Time, No Load, Input 100 mV Differential
Figure 36. AGC Response vs. Time, CL = 0.01 μF, Input 100 mV Differential
Figure 37. Output Common-Mode Voltage vs. RCM to VBAT
Figure 38. Output Common-Mode Voltage vs. RCM to COMM
0
–10
–100
–90
–80
–70
–60
–50
–40
–30
–20
100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
11279-133
0.6
0.1
0
–1.0
1.0
010 30405252015 35
VOLTAGE (V)
TIME (µs)
11279-019
VAGC VOLTAGE
OUTPUT VOLTAGE
0.6
0.1
0
–1.0
1.0
02 6 109815437
VOLTAGE (V)
TIME (ms)
11279-020
VAGC VOLTAGE
OUTPUT VOLTAGE
3.0
0
0.5
1.0
1.5
2.0
2.5
20k 100k
OUTPUT COMMON-MODE VOLTAGE (V)
RESISTANCE (Ω)
V
S
= 3V
V
S
= 5V
11279-135
3.0
0
0.5
1.0
1.5
2.0
2.5
10k 100k
OUTPUT COMMON-MODE VOLTAGE (V)
RESISTANCE (Ω)
V
S
= 3V
11279-136
AD8338 Data Sheet
Rev. A | Page 12 of 20
THEORY OF OPERATION
INTRODUCTION
The AD8338 is a single supply variable gain amplifier (VGA)
with an adjustable gain range of 80 dB. More accurately, the
AD8338 is an input variable gain amplifier (IVGA), which has
been designed to accept a wide range of input amplitudes, and
via its variable gain, compress it to either a narrow range of
output amplitudes or a constant output amplitude (for example,
automatic gain control applications). Like other VGAs from
Analog Devices, Inc., the AD8338 possesses a constant band-
width over the entire gain range. Therefore, with a bandwidth
of 18 MHz, the AD8338 achieves a gain-bandwidth product of
180 GHz at its highest gain setting (gain of 80 dB). Additionally,
the differential output of the AD8338 allows the VGA to
directly drive differential input ADCs without the need of a
single-ended-to-differential converter.
OVERALL STRUCTURE OF THE AD8338
Figure 39 shows a block schematic of the AD8338 depicting the
key sections of the VGA and a general overview of its features.
The AD8338 signal path is comprised by the 500 Ω input
resistors, the VGA core, and the transimpedance output
amplifiers. The gain of the signal path is adjusted by the linear-
in-dB gain interface and the voltage at Pin GAIN with respect
to its local ground, Pin COMM. The automatic gain control
(AGC) circuit block, is a current output RMS detector that can
be used to drive the GAIN pin and configure the AD8338 as
an AGC amplifier with constant RMS output amplitude. This
output amplitude is adjusted by the voltage at Pin VAGC with
respect to the voltage at Pin VREF. The offset null circuit block
allows the AD8338 to auto zero any dc offset voltages. To enable
the offset null functionality, connect a capacitor between the
OFSN and VREF pins. To disable the offset null functionality,
connect Pin OFSN to ground. The INPD, INMD, FBKP, and
FBKM pins provide access to internal nodes in the VGA core
of the AD8338 and output amplifiers allowing the user to adjust
the gain range, output common-mode voltage, and bandwidth
of the device.
Figure 39. Block Schematic
VGA CORE
Figure 40 shows a simplified diagram of the VGA core at the
heart of the AD8338. The key concepts regarding the operation
of this VGA core are as follows: First, the ratio of the collector
currents in the two differential pairs (Q1, Q2 and Q3, Q4) is
identical given that the two differential pairs share the same
base drive. This ratio is represented by the modulation factor,
x, where values of x range from −1 and +1. Second, the input
current signal is forced into the collectors of the input differ-
ential pair (Q1, Q2) by means of the loop amplifier to modulate
the fixed tail current, ID, and set the modulation factor, x. The
value of x in the input differential pair is replicated to the
output differential pair (Q3, Q4) to modulate its fixed tail
current, IN, and generate a differential output current. Third,
the current gain of this cell is exactly G = IN/ID over many
decades of variable bias current.
By varying IN, the overall function of the cell is that of a two-
quadrant analog multiplier, exhibiting a linear relationship to
both the signal modulation factor, x, and this numerator current.
On the other hand, by varying ID, the overall function is that
of a two-quadrant analog divider, having a hyperbolic gain
function with respect to the modulation factor, x, controlled
by this denominator current. Because the AD8338 is an input
VGA, it controls ID to adjust the amplifier’s gain. However,
because a hyperbolic gain function is generally of less value
than one in which the decibel gain is a linear function of a
control input, the AD8338 includes a special interface to provide
either increasing or decreasing exponential control of ID.
Figure 40. Simplified Diagram of the VGA Core
11279-200
INPR
INPD
INMD
INMR
MODECOMM GAIN DETO VAGC
VG A CORE
–26dB TO +54d B
OFFSET NULL
OFSN VREF
VBAT
AUTOMATIC
GAIN
CONTROL
GAIN INTE RFACE
AD8338
9.5kΩ
9.5kΩ
VREF
FBKP
OUTP
OUTM
FBKM
I
OUT
I
IN
500Ω
500Ω
INP UT IS xlD
DENOMINATOR
BIAS CURRE NT
ID
Q1
Q2
Q4
Q3
2
+ –
LOOP
AMPLIFIER
2
NUMERATOR
BIAS CURRE NT IN
OUTPUT IS xlN
G = IN/ID
22
11279-146
(1–x) I D(1–x) ID(1–x) IN(1+x) I N
Data Sheet AD8338
Rev. A | Page 13 of 20
NORMAL OPERATING CONDITIONS
Normal operating conditions for the AD8338 are defined as
follows:
• The input pins, INPR and INMR, are voltage driven (the
source impedance is assumed to be zero).
• The output pins, OUTP and OUTM, are open circuited
(the load impedance is assumed to be infinite).
• Pin COMM is grounded.
• Pin MODE is either tied to a logic high or left uncon-
nected, to set the noninverted gain slope gain mode.
INPR, INMR, INPD, and INMD Pins
The input signal to the AD8338 is accepted at the INPR/INMR
and the INPD/INMD differential input ports. These pins are
internally biased to approximately 1.5 V, the voltage at reference
Pin VREF. The INPR and INMR pins are voltage input pins (see
Figure 41) where the differential input voltage and the internal
input resistors generate current, IIN, the input current for the
VGA core. While the voltage inputs can be driven in either a
single-sided or a differential manner, operation using a differ-
ential drive is preferable, and is assumed in all specifications,
unless otherwise stated. The pin-to-pin input resistance
between the voltage inputs is specified as 1000 Ω ± 20%.
In most cases, the voltage input pins are ac-coupled via
two capacitors chosen to provide adequate low frequency
transmission. This results in the minimum input noise that
increases when a common-mode voltage other than 1.5 V is
forced onto these input pins. The short-circuit (INPR shorted to
INMR) input-referred noise at maximum gain is approximately
4.5 nV/√Hz.
Figure 41. Input Voltage Applied to the INPR and INMR Pins
The INPD and INMD pins are current input pins (see
Figure 42) where the differential input current is directly
applied to the VGA core input. This input current can either
be generated with an external current source like an unbiased
photodiode, or with a voltage source and external coupling
resistors (see Figure 43). The latter method allows the gain
range of the AD8338 to be shifted as explained in the
Explanation of the Gain Function section. When using the
INPD and INMD inputs, the INPR and INMR pins should
be shorted to one another to prevent stability issues.
Figure 42. Input Current Applied to the INPD and INMD Pins
Figure 43. Using External Resistors at the INPD and INMD Pins
FBKP, FBKM, OUTP, and OUTM Pins
Output voltage pins, OUTP and OUTM, have a default
common-mode voltage of 1.5 V, the voltage at the VREF
reference pin. This output common-mode voltage can be
adjusted by injecting common-mode currents into Pin FBKP
and Pin FBKM, the summing nodes of the output amplifiers,
which are also biased at 1.5 V. The output amplifiers of the
AD8338 possess rail-to-rail output stages which allow the
output common mode of the VGA to be shifted from ground
to the positive supply, though the use of such extreme values
leaves only a small range for the differential output signal swing.
Adding feedback capacitors, CFBK, across nodes (OUTP, FBKP
and OUTM, FBKM) reduces bandwidth of the output amplifi-
ers of the AD8338 and the signal path of the VGA. These
capacitors and the feedback resistors of the output amplifiers
form a low-pass filter with a cut-off frequency of approximately:
FBKFBK
CCR
f××
=
π
2
1
(1)
where RFBK are the internal feedback resistors of the output
amplifiers. RFBK is specified as 9800 Ω ± 20%.
Reducing the bandwidth of the AD8338 minimizes output noise
and simplifies the design of the antialiasing filter when using
the VGA to drive an ADC.
INPR
INPD
INMD
INMR
500Ω
500Ω
I
IN
V
IN
0dB TO 80dB
OUTP
OUTM
+V
OUT
/2 + V RE F
–V
OUT
/2 + V RE F
11279-044
1.5V
INPR
INPD
INMD
INMR
500Ω
500Ω
I
IN
l
D
0dB TO 80dB
OUTP
OUTM
+V
OUT
/2 + V RE F
–V
OUT
/2 + V RE F
11279-045
1.5V
INPR
INPD
INMD
INMR
500Ω
500Ω
I
IN
V
IN
20dB TO 80dB
OUTP
OUTM
+V
OUT
/2 + V RE F
–V
OUT
/2 + V RE F
11279-046
1.5V
50Ω
50Ω
AD8338 Data Sheet
Rev. A | Page 14 of 20
Linear-in-dB Gain Control, GAIN Pin
To facilitate the use of an 80 dB gain range, the AD8338 has a
linear-in-dB gain control. The gain is controlled by the voltage
at Pin GAIN with respect to the local ground COMM. In normal
operating conditions, adjusting the voltage at Pin GAIN from
0.1 V to 1.1 V adjusts the gain from its lowest value of 0 dB to
its highest value of 80 dB. The basic gain equation is
( )
dB8
mV5.12 −=
GAIN
V
dBG
(2)
where VGAIN is in volts.
Alternatively, the gain equation can be expressed as a numerical
gain magnitude
mV250
10398.0
GAIN
V
N
G×=
(3)
where VGAIN is in volts.
Inversion of the Gain Slope, MODE Pin
Pin MODE controls the polarity of the gain adjustment. That is,
Pin MODE allows the slope of the gain function to be inverted.
If Pin MODE is tied to VBAT, the gain of the AD8338 increases
exponentially (or linear-in-dB) with an increase in the voltage
at Pin GAIN. If Pin MODE is tied to COMM, the gain of the
AD8338 decreases exponentially (or linear-in-dB) with an
increase in the voltage at Pin GAIN. Figure 44 shows the two
gain control modes when the AD8338 is configured in normal
operating conditions.
Figure 44. Two Gain Control Modes of the AD8338
Offset Correction Circuit, OFSN Pin
The AD8338 includes an internal offset correction circuit
that cancels out any dc offsets that may be present in the
VGA. Connecting a capacitor, COFSN, between Pin OFSN
and Pin VREF enables the offset correction circuit.
The offset correction circuit uses an internal autozero feedback
loop, which introduces small signal high-pass filter characteris-
tics to the signal path. The −3 dB corner frequency is
OFSN
OFSN C
f×Ω×
=4002
1
π
(4)
Even though the AD8338 exhibits a high-pass filter characteris-
tic in its transfer function when the offset correction circuit is
enabled, the latter should not be used as a high-pass filter due
to the narrow voltage range of dc input voltages the circuit can
reject. If signals at frequencies below the band of interest need
to be rejected, for best performance, incorporate a high-pass
filter preceding the AD8338. This can be achieved by ac-
coupling the inputs as shown in Figure 41.
To provide a dc-coupled signal path, the offset correction
circuit can be disabled by connecting Pin OFSN to Pin COMM.
Exercise caution when operating the AD8338 with the offset
correction circuit disabled, because at large gains, dc offsets
will cause large dc errors at the outputs of the VGA.
80
0
10
20
30
40
50
60
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
GAIN (dB)
V
GAIN
(V)
LOW MODE HIGH MODE
11279-103
Data Sheet AD8338
Rev. A | Page 15 of 20
AGC Circuit, VAGC Pin
The AD8338 includes a current output RMS detector that can
be used to configure the AD8338 as an AGC amplifier (see
Figure 46).
In this configuration, the AGC circuit compares the RMS
output amplitude of the VGA with the desired RMS output
amplitude (voltage at Pin VAGC with respect to the voltage at
Pin VREF), and drives Pin GAIN to minimize their difference.
Therefore, in steady state conditions, the circuit forces the RMS
output amplitude of the AD8338 to be the voltage at Pin VAGC
with respect to the voltage at Pin VREF. Because the AGC
circuit uses negative feedback, the gain slope of the AD8338
needs to be inverted by connecting Pin MODE to ground.
The bandwidth of the AGC circuit is dictated by Capacitor
CDETO. Choose this capacitor carefully to ensure that the
bandwidth of the AGC circuit is high enough so that it can
react to fast changes in the input signal’s amplitude, but low
enough to prevent the AGC circuit from distorting the signal
of interest. For example, in an on-off keying (OOK) application
with a carrier frequency of 6.8 MHz and a bit rate of 10 kb/s, it
is recommended to use a 0.01 µF capacitor. This capacitor value
ensures that the gain reacts to the bit energy but does not react
to the carrier signal.
As mentioned previously, the AGC circuit forces the RMS
output amplitude of the AD8338 to be the voltage at Pin VAGC
with respect to the voltage at Pin VREF. Furthermore, the input
to the AGC circuit, Pin VAGC, is symmetrical with respect to
Pin VREF. In other words, the AGC circuit responds to the
absolute value of the difference in voltage between Pin VAGC
and Pin VREF (see Figure 45).
Figure 45. Output RMS Voltage and VGAIN vs. VAGC – VREF
Not all applications require the AGC circuit. Therefore, the
AGC circuit can be disabled by connecting Pin DETO to
ground, and connecting Pin VAGC to Pin VREF.
Internal Reference, Pin VREF
The AD8338 includes an internal 1.5 V voltage reference that is
used to set the quiescent bias voltages of many key nodes in the
VGA. These nodes include inputs pins (INPR, INMR, INPD,
and INMD), output pins (OUTP and OUTM), and feedback
pins (FKBP and FBKM). The output voltage of the internal
reference, Pin VREF, maybe bypassed with a 0.1 µF capacitor
to Pin COMM, but do not force it externally.
Figure 46. AD8338 Configured as an AGC Amplifier
1200
0
200
400
600
800
1000
–1.0 –0.8 –0.6 –0.4 –0.2 00.2 0.4 0.6 0.8 1.0
OUTPUT AMP LIT UDE ( mV rms)
VAGC – VREF (V)
11279-147
1200
0
200
400
600
800
1000
VGAIN (mV)
INPR
INPD
INMD
INMR
MODE
COMM
GAIN
FBKM
OUTP
OUTM
DETO
VAGC
FBKP
VREF
VG A CORE
0dB TO 80dB
OFFSET NULL
OUTPUT
STAGE
0dB
OFSN VREF
VBAT
AUTOMATIC
GAIN
CONTROL
GAIN INTE RFACE
AD8338
AGC SETPOINT
0.01µF
CAGC
11279-148
AD8338 Data Sheet
Rev. A | Page 16 of 20
EXPLANATION OF THE GAIN FUNCTION
The signal chain of the AD8338 can be broken down into
three stages. The first stage is a differential voltage-to-current
converter comprised by the input resistors, RP and RN, of the
VGA. These input resistors may either be the internal 500 Ω
resistors coupled to Pin INPR and Pin INMR, or external
resistors coupled to Pin INPD and Pin INMD. The trans-
resistance of the voltage-to-current converter is RP + RN
such that the current flowing in the resistors is given by:
NP
INMxINPx
IN
R R
VV
I+
−
=
(5)
The current in the input resistors, IIN, is fed to the second
stage of the AD8338, the VGA core. The VGA core is a fully
differential variable gain current amplifier with a gain range
of 80 dB. In the noninverting gain slope setting (Pin MODE
connected to Pin VBAT), the current gain of the VGA core
spans from −26 dB (VGAIN = 0.1 V) to +54 dB (VGAIN = 1.1 V). In
numerical gain magnitude, the gain of the VGA core is given by
mV25020/)3480(
,
1002.010
GAIN
GAIN
V
IN
V
IN
VGAOUT
III ××≈×=
−
(6)
The differential output current of the VGA core is fed to the
third stage of the AD8338, a fully differential current-to-voltage
converter comprised by the output amplifiers and their corre-
sponding feedback resistors, RFBK. The overall transimpedance
of the current to voltage converter is 2RFBK, such that the
differential output voltage of the stage is given by:
FBK
VGAOUTDIFFOUT RIV ××= 2
,,
(7)
Therefore, the overall voltage gain of the AD8338 is:
( )
34
2
log2080 −
+
×
×××=
NP
FBK
GAIN
RR
R
VdBG
(8)
Alternatively, the gain equation can be expressed as a numerical
gain magnitude,
mV250
10
2
02.0
GAIN
V
NP
FBK
N
RR
R
G×
+
×
×=
(9)
Equation 8 and Equation 9 show that the gain range of the
AD8338 can be shifted by using external input resistors, RP and
RN. For example, driving the INPD and INMD pins with an RP
and RN of 50 Ω shifts the gain range of the AD8338 up by 20 dB,
from 20 dB to 100 dB (see Figure 43). Similarly, driving the
INPD and INMD pins with an RP and RN of 5 kΩ, shifts the
gain range down by 20 dB, from −20 dB to +60 dB.
As shown in Figure 43, when using external resistors to drive
the INPD and INMD pins, short the INPR and INMR pins to
one another to prevent stability issues.
Effects of Using External Resistors
When the gain range is shifted through the use of external
resistors, several trade-offs must be considered. External
resistors connected to Pin INPD and Pin INMD load the
current inputs of the VGA core changing the dynamic behavior
of the block and the −3 dB bandwidth of the AD8338. The
−3 dB bandwidth of the AD8338 with external resistors is
Ω
×
+Ω
×Ω
×= 500
1
500
500
MHz18
EXT
EXT
CL
R
R
f
(10)
For example, with 50 Ω external resistors, the input-referred
noise at maximum gain decreases to approximately 1 nV/√Hz
and the gain range shifts up by 20 dB. However, the −3 dB
bandwidth is reduced from 18 MHz to approximately 1.8 MHz.
Data Sheet AD8338
Rev. A | Page 17 of 20
ADJUSTING THE OUTPUT COMMON-MODE
VOLTAGE
The output common-mode voltage of the AD8338 differential
outputs is nominally set to 1.5 V, the voltage at Pin VREF. This
output common-mode voltage can be adjusted by connecting
a resistor from each of the output amplifier’s summing nodes
(Pin FBKP and Pin FBKM) to either Pin COMM or Pin VBAT.
Connecting a resistor from Pin FBKP and Pin FBKM to Pin
VBAT decreases the output common-mode voltage, whereas
connecting a resistor from Pin FBKP and Pin FBKM to Pin
COMM increases the output common-mode voltage (see
Figure 47 and Figure 48).
Figure 47. Decreasing the Output Common-Mode Voltage
Figure 48. Increasing the Output Common-Mode Voltage
Table 5 and Table 6 show suggested values for the external
resistors shown in Figure 47 and Figure 48.
Table 5. Resistor Values for Decreasing the Output
Common-Mode Voltage
VBAT ( V) Target VOCM (V) Resistor Value (Ω) Tied to
5.0 0.9 55,417 VBAT
3.3 0.9 28,500 VBAT
3.0 0.9 23,750 VBAT
Table 6. Resistor Values for Increasing the Output
Common-Mode Voltage
VBAT ( V) Target VOCM (V) Resistor Value (Ω) Tied to
Any 1.8 47,500 COMM
Any 2.0 28,500 COMM
Any 2.5 14,250 COMM
FBKM
OUT P = 1.5V –
OUT M = 1.5V –
FBKP
9.5kΩ
VREF = 1.5V
VBAT
VBAT
(VBAT – 1.5V) × 9.5kΩ
R2
R2
R1
9.5kΩ
(VBAT – 1.5V) × 9.5kΩ
R1 + V
OUT
/2
+ V
OUT
/2
11279-150
l
OUT
FBKM
OUTP = 1.5V –
OUTM = 1.5V –
FBKP
9.5kΩ
VREF = 1.5V
COMM
COMM
(0 – 1.5V) × 9.5kΩ
R2
R2
R1
9.5kΩ
(0 – 1.5V) × 9.5kΩ
R1 + V
OUT
/2
+ V
OUT
/2
11279-151
l
OUT
AD8338 Data Sheet
Rev. A | Page 18 of 20
APPLICATIONS INFORMATION
The excellent performance of the AD8338 results in a flat response
over various gains with rail-to-rail output signal swing, high drive
capability, and a very high dynamic range at a low 12 mW. These
features make the AD8338 an exceptional choice for use in battery-
operated equipment, low frequency and baseband applications,
and many other applications.
SIMPLE ON-OFF KEYED (OOK) RECEIVER
For low complexity, low power data communications, a simple
link built using a modulating carrier tone in an on/off state
provides a fast and cost-effective solution to the designer. Such
designs are used in a variety of applications, including near-
field communications among noninterference mechanical
systems, low data rate sensors, RFID tags, and so on.
The schematic shown in Figure 49 demonstrates a complete
inductive telemetry on-off keyed (OOK) front end. The crystal
is cut for the target receive frequency of interest, creating a very
narrow-band filter, typically around the 6.78 MHz ISM band.
The AD8338 amplifies the signal (the gain is set by an external
controller) and drives a full-wave rectifier bridge. The output of
this bridge is then low-pass filtered into 100 Ω terminations. This
design provides excellent rejection of RF and excellent baseband
information recovery for the decision stage that follows.
The reactive filter components—Capacitors C1 through C4 and
Inductors L1 and L2—set the baseband recovery performance. A
design trade-off exchanges baseband response for RF attenuation.
Table 7 provides typical values for these components at two data
rates. Note that Capacitors C1 through C4 are all of equal value,
and Inductor L2 has the same value as L1.
Table 7. Typical Values for Components in Reactive Filter
Data Rate C1 to C4 L1 and L2
Carrier Attenuation
(f = 6.78 MHz)
19,200 bps 12 nF 240 µH −101 dB
57,600 bps 3.9 nF 82 µH −73 dB
Figure 49. Complete, Low Power OOK Receiver
VREF
MODE
VREF
OUTP
OUTM
COMM
OFSN
CRYSTAL
ANTENNA
C
TUNE
U1
AD8338
C6
0.01µF
GAIN
3.0V
INPR
INMR
DETO
C5
0.1µF
D1 D2
D4 D3
C1
C3
C2
C4
L1
L2
R1
100Ω
R2
100Ω
OOK_P
OOK_M
11279-048
Data Sheet AD8338
Rev. A | Page 19 of 20
INTERFACING THE AD8338 TO AN ADC
The AD8338 is well suited to drive a high speed analog-to-digital
converter (ADC) and is compatible with many ADCs from Analog
Devices. This example illustrates the interfacing of the AD8338 to
the AD7450. The AD7450 is a low power, 3.0 V ADC, which is
also competitively priced for a low cost total solution.
Figure 50 shows the basic connections between the AD8338
and the AD7450. The common-mode voltage provided by the
AD8338 is within the specifications of the AD7450.
The AD8338 can be coupled directly to the AD7450 for full
dc-to-18 MHz operation at the highest level of performance with
low operating power (160 mW typical). The glueless interface
enables a physically small, high performance data acquisition
system that is ideal for many field instruments. A filter before
the VGA provides the antialiasing function and noise limiting.
In applications where the modulated information is not encoded
in the signal amplitude, use the AGC feature of the AD8338 to
reduce any bit errors in the sampled signal.
Figure 50. Basic Connections to the AD7450 ADC
INPR
INMR
FILTER
OUTPUT
VREF
OUTP
OUTM
C1
0.1µF
COMM
DETO
OFSN
C2
0.1µF
MODE
VBAT
3.0V
U1
AD8338
GAIN
GAIN
CONTROL
U2
AD7450
GND
3.0V
C3
0.1µF
3.0V
C4
0.1µF
R1
5.1Ω
VDD
VREF
SCLK
SDATA
CS
TO
MICRO-
CONTROLLER
VIN+
VIN–
C4
0.1µF
11279-149
AD8338 Data Sheet
Rev. A | Page 20 of 20
OUTLINE DIMENSIONS
Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8338ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 Y4K
AD8338ACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 Y4K
AD8338-EVALZ AD8338 Evaluation Board
1 Z = RoHS Compliant Part.
3.10
3.00 SQ
2.90
0.30
0.23
0.18
1.75
1.60 SQ
1.45
08-16-2010-E
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDI
C
ATOR
FOR PROP E R C ONNECTION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIG URATIO N A ND
FUNCTIO N DESCRIP TIO NS
SECTION OF THIS DATA SHEET .
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS M O-220-WEED-6.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11279-0-11/13(A)
