TOSHIBA TC74HC573AP/AF/AFW TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC573AP, TC74HC573AF, TC74HC573AFW (Note) The JEDEC SOP (FW) is not available OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT in Japan. The TC74HC573A is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Its 8- bit D-type latche is controlled by a latch enable input (LE) and a output enable input (OF). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. FEATURES : High Speed---------e-sssecseesesseeeseesees toa = 13ns(typ.) at Voc = 5V e Low Power Dissipation :+:+++++++++++ loc = 4A(Max.) at Ta= 25C High Noise Immunity--+--+-+--+++--++ Vain = Vnit = 28% Voc (Min.) Output Drive Capability ------------- 15 LSTTL Loads e Symmetrical Output Impedance---| lon | = lo. = 6mA(Min.) e Balanced Propagation Delays----toLH=tpHL Wide Operating Voltage Range---- Vcc (opr.) =2V~ 6V e Pin and Function Compatible with 74LS573 P (DIP20-P-300-2.54A) Weight : 1.30g (Typ.) 20 ee 1 1 F (SOP20-P-300-1.27) Weight : 0.22g (Typ.) FW (SOL20-P-300-1.27) Weight : 0.46g (Typ.) PIN ASSIGNMENT OF 1g 20 Do 2g 19 D1 30 18 D2 4[ 17 D3 50D 16 D4 60 15 D5 670 nM 14 D6 68 13 b?7 9f r] 12 GND 10[ r] 11 (TOP VIEW) QO Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE TRUTH TABLE IEC LOGIC SYMBOL INPUTS OUTPUT LE Q x HZ 1 EN C1 OE tp (ui (2) (19) L Qn x (3) pp (18) ot H L D2 (4) (17) Q2 H H H D3 (5) (16) Q3 D4 (6) (15) o4 X: Dont Care (7) (14) HZ: High Impedance DS 8) (3) 2 Qn (Qn) : Q(Q) outputs are latched at the time D6 (9) (12) Q6 when the LE input is taken to a low D7 Q7 logic level. 961001EBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. 1997-08-07 1/6TOSHIBA TC74HC573AP/AF/AFW SYSTEM DIAGRAM DO D1 D2 D3 D4 D5 D6 D7 4 D D D D D D D D Qh Qh Qh Qh Qh Qh Qh Q L L L L L L L L ls ped>l I I I I | I | Q0 Qi Q2 Q3 Q4 Q5 Q6 Q7 961001EBA2" @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1997-08-07 2/6TOSHIBA TC74HC573AP/AF/AFW ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT *500mW in the range of Ta= Supply Voltage Range Vec 0.5~7 V 5a G5 08 C. From Ta= 65C N5~ to 85C a derating factor o DC Input Voltage Vin 0.5~Vec + 0.5 V ~10mW/C shall be applied DC Output Voltage Vout 0.5~Vec + 0.5 Vv until 300mW. Input Diode Current lik +20 mA Output Diode Current lox +20 mA DC Output Current lout +35 mA DC Vec/ Ground Current lee +75 mA Power Dissipation Pp 500 (DIP)* / 180 (SOP) mw Storage Temperature Tstg 65~150 C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Vec 2~6 V Input Voltage Vin O~Vec Vv Output Voltage Vout O~Vec Vv Operating Temperature Topr 40~85 0~ 1000 (Vcc = 2.0V) Input Rise and Fall Time tr, tf O~ 500 (Ve =4.5V) ns O~ 400(Vec =6.0V) DC ELECTRICAL CHARACTERISTICS Ta =25C Ta = -40~85C PARAMETER SYMBOL TEST CONDITION Vee UNIT (V) | MIN. | TYP. | MAX. | MIN. | MAX. : 2.0 | 1.50 _ 1.50 High - Level _ _ _ Input Voltage Mi 60 | 426 | | = | a2} = | * 2.0 _ 0.50 _ 0.50 Low - Level _ _ _ Input Voltage Vit 63 - 130 - 130 v 20uA a3 qa a3 4A SPitVtage | Vox | YiNGry, | _1 20] $8 [eo | [os | = | y P 9 Orin \T > 6 mA 45/ 4.18 | 431 4.13 lou=7.8mA | 6.0 | 5.68 | 5.80 | | 5.63 | lo. = 20uA ae 00 01 01 Low-Level Vo. | Vine one 60; |o0 [01 | - |oi |] y utput Voltage VinorVii 6 mA |45| | 0171 026| | 0.233 loL=7.8mA 6.0 _ 0.18 | 0.26 _ 0.33 3 - State Output VineViporVit _ _ _ Off - State Current loz Vout = Vec or GND 6.0 +0.5 +5.0 Input Leakage Current lin Vin=Vec or GND 60; T+o1! [+10 | A Quiescent Supply Current lec Vin =Vec or GND 6.0 _ _ 4.0 _ 40.0 1997-08-07 3/6TOSHIBA TC74HC573AP/AF/AFW TIMING REQUIREMENTS { Input t, = t = 6ns ) PARAMETER syMBoL| TESTCONDITION py =25 Ta = CJ unit cc : __, 2.0 = 75 95 Minimum ie Width tw) 45 _ 15 19 6.0 - 13 16 Minimum Setup Time t ae _ 0 68 ns ( Data ) 6.0 - 9 11 Minimum Hold Time 2.0 _ > > th 4.5 5 5 ( Data ) 6.0 5 5 AC ELECTRICAL CHARACTERISTICS ( Input t, = t;=6ns) TEST CLT V Ta=25C Ta = 40~85C PARAMETER SYMBOL | CONDITION | (pF) | (Wy | MIN. | TYP. | MAX] iN, | max, [UNIT f 20/ 20 60 75 Output Transition Time ta 50} 45] 6 12 15 THL 6.0 | 5 10 - 13 t 20/ 50 115 = 145 Propagation Delay Time pLH 50 43 15 33 - 28 (LEQ, Q) 20/ - 60 155 = 195 toni 150} 45] 20 31 39 6.0 | 17 26 _ 33 t 20] 42 110 140 Propagation Delay Time pLH 50 | 4.5 - 14 22 - 28 _ 6.0 | 12 19 24 | (D-Q, 0) 20! 57 150 = 190 6.0 | 16 26 32 t 20/ 55 140 = 175 pzL 50/45] 17 28 _ 35 Output Enable time RL=1kO 28 u a = tozH 150} 45] 22 36 45 6.0 | 19 31 38 t 20/ 40 125 = 155 Output Disable time touz RL=1ko 50 45 7 25 31 Input Capacitance Cin _ 5 10 _ 10 Output Capacitance Court _ 10 _ _ _ pF Power Dissipation Capacitance | Cpp (1) _ 51 _ _ _ Note (1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: lee (opr) =Cpp - Vec . fin + lec /8 ( per Latch ) And the total Cpp when n pes. of Latch operate can be gained by the following equation: Cpp(total) =334+18-n 1997-08-07 4/6TOSHIBA TC74HC573AP/AF/AFW DIP 20PIN OUTLINE DRAWING (DIP20-P-300-2.54A) Unit in mm 20 uW 4 Cd = 3 [8 3 Os LILI Cte eT Ct oOo Oo Ca cd : 1 10 25.1 MAX 24.6140.2 0.9540.1_ ' 3 gt il zy zt 2 z | 1.4+0.1 Q.5+0.1 [0.25 Gal 2.54 Weight : 1.30g (Typ.) SOP 20PIN (200mil BODY) OUTLINE DRAWING (SOP20-P-300-1.27) Unit in mm 20 11 - ; uN 3 all = a || & a) R ns HAH HARA BR 3 | 1 10 0.685T YP a 0.43:0.1 [0.25 Gi 1.27 13.3MAX 12.8+0.2 4 Fi = Cor % fH Fell 58 3 10.1 ST oS _ 0.80.2 Weight : 0.22g (Typ.) 1997-08-07 5/6TOSHIBA TC74HC573AP/AF/AFW SOP 20PIN (300mil BODY) OUTLINE DRAWING (SOL20-P-300-1.27) Unit in mm (Note) This package is not available in Japan. Poogagonggq 0.685TYP 12,80.1 45 N x re io x 8 a | e N nN \_ o 0.1 a 2 3 0.90.3 Weight : 0.46g (Typ.) 1997-08-07 6/6