LT1767EMS8-1.8#PBF - ANALOG DEVICES

LT1767/LT1767-1.8/

LT1767-2.5/LT1767-3.3/LT1767-5

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Typical applicaTion

DescripTion

Monolithic 1.5A, 1.25MHz

Step-Down Switching Regulators

L, LT , LT C , LT M , Linear Technology, the Linear logo and Burst Mode are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 6611131, 6498466.

FeaTures

applicaTions

n 1.5A Switch in a Small MSOP Package

n Constant 1.25MHz Switching Frequency

n High Power Exposed Pad (MS8E) Package

n Wide Operating Voltage Range: 3V to 25V

n High Efﬁciency 0.22 Switch

n 1.2V Feedback Reference Voltage

n Fixed Output Voltages of 1.8V, 2.5V, 3.3V, 5V

n 2% Overall Output Tolerance

n Uses Low Proﬁle Surface Mount Components

n Low Shutdown Current: 6µA

n Synchronizable to 2MHz

n Current Mode Loop Control

n Constant Maximum Switch Current Rating at All Duty

Cycles*

The LT

1767 is a 1.25MHz monolithic buck switching

regulator. A high efficiency 1.5A, 0.22Ω switch is included

on the die together with all the control circuitry required

to complete a high frequency, current mode switching

regulator. Current mode control provides fast transient

response and excellent loop stability.

New design techniques achieve high efficiency at high

switching frequencies over a wide operating range. A

low dropout internal regulator maintains consistent per-

formance over a wide range of inputs from 24V systems

to Li-Ion batteries. An operating supply current of 1mA

improves efficiency, especially at lower output currents.

Shutdown reduces quiescent current to 6µA. Maximum

switch current remains constant at all duty cycles. Syn-

chronization allows an external logic level signal to increase

the internal oscillator from 1.5MHz to 2MHz.

The LT1767 is available in an 8-pin MSOP fused lead-frame

package and a low thermal resistance

exposed pad package.

Full cycle-by-cycle current limit and thermal shutdown are

provided. High frequency operation allows the reduction

of input and output filtering components and permits the

use of chip inductors.

n DSL Modems

n Portable Computers

n Wall Adapters

n Battery-Powered Systems

n Distributed Power

Efficiency vs Load Current

12V to 3.3V Step-Down Converter

BOOST

LT1767-3.3

OUTPUT

3.3V

1.2A*

12V

1767 TA01

0.1µF

1.5nF

4.7k

UPS120

10µF

CERAMIC

2.2µF

CERAMIC

CMDSH-3

5µH

FBSHDN

OPEN

HIGH

= ON GND V

SYNC

*MAXIMUM OUTPUT CURRENT IS SUBJECT TO THERMAL DERATING.

LOAD CURRENT (A)

00.2 0.4 0.6 0.8 1 1.2 1.4

EFFICIENCY (%)

1767 TA01a

= 10V

OUT

= 5V

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pin conFiguraTion

absoluTe MaxiMuM raTings

(Note 1)

Input Voltage ........................................................... 25V

BOOST Pin Above SW ............................................. 20V

Max BOOST Pin Voltage ............................................ 35V

SHDN Pin ................................................................. 25V

FB Pin Voltage ........................................................... 6V

FB Pin Current ......................................................... 1mA

SYNC Pin Current ................................................... 1mA

Operating Junction Temperature Range (Note 2)

LT1767E ........................................... –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

BOOST

VIN

GND

SYNC

SHDN

TOP VIEW

MS8 PACKAGE

8-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 110°C/W

GROUND PIN CONNECTED TO LARGE COPPER AREA

BOOST

VIN

GND

SYNC

SHDN

TOP VIEW

MS8E PACKAGE

8-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 40°C/W

GROUND PIN CONNECTED TO LARGE COPPER AREA ON PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LT1767EMS8#PBF LT1767EMS8#TRPBF LTLS 8-Lead Plastic MSOP –40°C to 125°C

LT1767EMS8-1.8#PBF LT1767EMS8-1.8#TRPBF LTW G 8-Lead Plastic MSOP –40°C to 125°C

LT1767EMS8-2.5#PBF LT1767EMS8-2.5#TRPBF LTW D 8-Lead Plastic MSOP –40°C to 125°C

LT1767EMS8-3.3#PBF LT1767EMS8-3.3#TRPBF LTW E 8-Lead Plastic MSOP –40°C to 125°C

LT1767EMS8-5#PBF LT1767EMS8-5#TRPBF LTW F 8-Lead Plastic MSOP –40°C to 125°C

LT1767EMS8E#PBF LT1767EMS8E#TRPBF LTZG 8-Lead Plastic MSOP, Exposed Pad –40°C to 125°C

LT1767EMS8E-1.8#PBF LT1767EMS8E-1.8#TRPBF LTZH 8-Lead Plastic MSOP, Exposed Pad –40°C to 125°C

LT1767EMS8E-2.5#PBF LT1767EMS8E-2.5#TRPBF LTZJ 8-Lead Plastic MSOP, Exposed Pad –40°C to 125°C

LT1767EMS8E-3.3#PBF LT1767EMS8E-3.3#TRPBF LTZK 8-Lead Plastic MSOP, Exposed Pad –40°C to 125°C

LT1767EMS8E-5#PBF LT1767EMS8E-5#TRPBF LTZL 8-Lead Plastic MSOP, Exposed Pad –40°C to 125°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

Consult LT C Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS

Maximum Switch Current Limit TA = 0°C to 125°C

TA = < 0°C

1.5

1.3

2 3

Oscillator Frequency 3.3V < VIN < 25V

1.1

1.25 1.4

1.5

MHz

Switch On Voltage Drop ISW = –1.5A, 0°C ≤ TA ≤ 125°C and –1.3A, TA < 0°C

330 400

500

VIN Undervoltage Lockout (Note 3) l2.47 2.6 2.73 V

VIN Supply Current VFB = VNOM + 17% l1 1.3 mA

Shutdown Supply Current VSHDN = 0V, VIN = 25V, VSW = 0V

6 20

µA

Feedback Voltage 3V < VIN < 25V, 0.4V < VC < 0.9V

(Note 3)

LT1767 (Adj)

1.182

1.176

1.2 1.218

1.224

LT1767-1.8 l1.764 1.8 1.836 V

LT1767-2.5 l2.45 2.5 2.55 V

LT1767-3.3 l3.234 3.3 3.366 V

LT1767-5 l4.9 5 5.1 V

FB Input Current LT1767 (Adj) l–0.25 –0.5 µA

FB Input Resistance LT1767-1.8

LT1767-2.5

LT1767-3.3

LT1767-5

10.5

14.7

27.5

kΩ

Error Amp Voltage Gain 0.4V < VC < 0.9V 150 350

Error Amp Transconductance ∆IVC = ±10µA l500 850 1300 µMho

VC Pin Source Current VFB = VNOM – 17% l80 120 160 µA

VC Pin Sink Current VFB = VNOM + 17% l70 110 180 µA

VC Pin to Switch Current Transconductance 2.5 A/V

VC Pin Minimum Switching Threshold Duty Cycle = 0% 0.35 V

VC Pin 1.5A ISW Threshold 0.9 V

Maximum Switch Duty Cycle VC = 1.2V, ISW = 400mA

90 %

Minimum Boost Voltage Above Switch ISW = –1.5A, 0°C ≤ TA ≤ 125°C and –1.3A, TA < 0°C l1.8 2.7 V

Boost Current ISW = –0.5A (Note 4)

ISW = –1.5A, 0°C ≤ TA ≤ 125°C and –1.3A, TA < 0°C (Note 4)

SHDN Threshold Voltage l1.27 1.33 1.40 V

SHDN Input Current (Shutting Down) SHDN = 60mV Above Threshold l–7 –10 –13 µA

SHDN Threshold Current Hysteresis SHDN = 100mV Below Threshold l4 7 10 µA

SYNC Threshold Voltage 1.5 2.2 V

SYNC Input Frequency 1.5 2 MHz

SYNC Pin Resistance ISYNC = 1mA 20 kΩ

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open

unless otherwise noted.

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TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125

SHDN THRESHOLD (V)

1767 G04

1.40

1.38

1.36

1.34

1.32

1.30

(V)

0 5 10 15 20 25 30

CURRENT (µA)

1767 G05

SHDN = 0V

SHDN IP Current vs Temperature

SHDN Threshold vs Temperature SHDN Supply Current vs VIN

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125

SHDN INPUT (µA)

1767 G06

–12

–10

–8

–6

–4

–2

STARTING UP

SHUTTING DOWN

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125

FB VOLTAGE (V)

1767 G01

1.22

1.21

1.20

1.19

1.18

SWITCH CURRENT (A)

0 0.5 1 1.5

SWITCH VOLTAGE (mV)

1767 G02

400

350

300

250

200

150

100

125°C

25°C

–40°C

FB vs Temperature (Adj) Switch On Voltage Drop Oscillator Frequency

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125

FREQUENCY (MHz)

1767 G03

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

Typical perForMance characTerisTics

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT1767E is guaranteed to meet performance specifications

from 0°C to 125°C. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls.

Note 3: Minimum input voltage is defined as the voltage where the internal

regulator enters lockout. Actual minimum input voltage to maintain a

regulated output will depend on output voltage and load current. See

Applications Information.

Note 4: Current flows into the BOOST pin only during the on period of the

switch cycle.

TA = 25°C, unless otherwise noted.

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Typical perForMance characTerisTics

LOAD CURRENT (mA)

100

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

INPUT VOLTAGE (V)

Minimum Input Voltage, 3.3V Out

1767 G07

BOOST DIODE TIED TO V

OUT

BOOST DIODE TIED TO V

TO START

TO RUN

SHUTDOWN VOLTAGE (V)

00.2 0.4 0.6 0.8 1 1.2 1.4

CURRENT (µA)

1767 G08

300

250

200

150

100

= 15V

INPUT VOLTAGE (V)

0 5 10 15 20 25 30

CURRENT (µA)

1767 G09

1200

1000

800

600

400

200

MINIMUM

INPUT

VOLTAGE

Minimum Input Voltage, 3.3V Out SHDN Supply Current Input Supply Current

FEEDBACK VOLTAGE (V)

0 0.2 0.4 0.6 0.8 1 1.2

SWITCH PEAK CURRENT (A)

1767 G10

2.0

1.5

1.0

0.5

FB INPUT CURRENT (µA)

FB CURRENT

SWITCH CURRENT

1767 G11

INPUT VOLTAGE (V)

0 5 10 15 20 25

OUTPUT CURRENT (A)

1.5

1.3

1.1

0.9

0.7

0.5

L = 4.7µH

L = 2.2µH

L = 1.5µH

INPUT VOLTAGE (V)

0 5 10 15 20 25

OUTPUT CURRENT (A)

1767 G12

1.5

1.3

1.1

0.9

0.7

L = 4.7µH

L = 2.2µH

L = 1.5µH

Current Limit Foldback

Maximum Load Current,

VOUT = 5V

Maximum Load Current,

VOUT = 2.5V

TA = 25°C, unless otherwise noted.

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pin FuncTions

FB: The feedback pin is used to set output voltage using

an external voltage divider that generates 1.2V at the pin

with the desired output voltage. The fixed voltage 1.8V,

2.5V, 3.3V and 5V versions have the divider network in-

cluded internally and the FB pin is connected directly to

the output. If required, the current limit can be reduced

during start up or short-circuit when the FB pin is below

0.5V (see the Current Limit Foldback graph in the Typical

Performance Characteristics section). An impedance of

less than 5kΩ (adjustable part only) at the FB pin is needed

for this feature to operate.

BOOST: The BOOST pin is used to provide a drive voltage,

higher than the input voltage, to the internal bipolar NPN

power switch. Without this added voltage, the typical

switch voltage loss would be about 1.5V. The additional

boost voltage allows the switch to saturate and voltage

loss approximates that of a 0.22Ω FET structure.

VIN: This is the collector of the on-chip power NPN switch.

This pin powers the internal circuitry and internal regu-

lator. At NPN switch on and off, high dI/dt edges occur

on this pin. Keep the external bypass capacitor and catch

diode close to this pin. All trace inductance in this path

will create a voltage spike at switch off, adding to the VCE

voltage across the internal NPN.

GND: The GND pin acts as the reference for the regulated

output, so load regulation will suffer if the “ground” end of

the load is not at the same voltage as the GND pin of the

IC. This condition will occur when load current or other

currents flow through metal paths between the GND pin

and the load ground point. Keep the ground path short

between the GND pin and the load and use a ground plane

when possible. Keep the path between the input bypass

and the GND pin short. The GND pin of the MS8 package

is directly attached to the internal tab. This pin should

be attached to a large copper area to improve thermal

resistance. The exposed pad of the MS8E package is also

connected to GND. This should be soldered to a large

copper area to improve its thermal resistance.

VSW: The switch pin is the emitter of the on-chip power

NPN switch. This pin is driven up to the input pin voltage

during switch on time. Inductor current drives the switch

pin negative during switch off time. Negative voltage must

be clamped with an external catch diode with a VBR <0.8V.

SYNC: The sync pin is used to synchronize the internal

oscillator to an external signal. It is directly logic compat-

ible and can be driven with any signal between 20% and

80% duty cycle. The synchronizing range is equal to

initial

operating frequency, up to 2MHz. See Synchronization in

Applications Information section for details. When not in

use, this pin should be grounded.

SHDN: The shutdown pin is used to turn off the regulator and

to reduce input drain current to a few microamperes. The

1.33V threshold can function as an accurate undervoltage

lockout (UVLO), preventing the regulator from operating

until the input voltage has reached a predetermined level.

Float or pull high to put the regulator in the operating mode.

VC: The VC pin is the output of the error amplifier and the

input of the peak switch current comparator. It is normally

used for frequency compensation, but can do double duty

as a current clamp or control loop override. This pin sits

at about 0.35V for very light loads and 0.9V at maximum

load. It can be driven to ground to shut off the output.

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block DiagraM

then an abrupt 180° shift will occur. The current fed sys-

tem will have 90° phase shift at a much lower frequency,

but will not have the additional 90° shift until well beyond

the LC resonant frequency. This makes it much easier to

frequency compensate the feedback loop and also gives

much quicker transient response.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing switch to be saturated.

This boosted voltage is generated with an external capac-

itor and diode. A comparator connected to the shutdown

pin disables the internal regulator, reducing supply

current.

The LT1767 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

two feedback loops that control the duty cycle of the power

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscillator

pulse which sets the RS flip-flop to turn the switch on. When

switch current reaches a level set by the inverting input of

the comparator, the flip-flop is reset and the switch turns

off. Output voltage control is obtained by using the output

of the error amplifier to set the switch current trip point.

This technique means that the error amplifier commands

current to be delivered to the output rather than voltage.

A voltage fed system will have low phase shift up to the

resonant frequency of the inductor and output capacitor,

Figure 1. Block Diagram

–

∑

2.5V BIAS

REGULATOR

1.25MHz

OSCILLATOR

GND

1767 F01

SLOPE COMP

0.01Ω

INTERNAL

CURRENT

SENSE

AMPLIFIER

VOLTAGE GAIN = 40

SYNC

SHDN

SHUTDOWN

COMPARATOR

CURRENT

COMPARATOR

ERROR

AMPLIFIER

= 850µMho

BOOST

FLIP-FLOP

DRIVER

CIRCUITRY

0.35V

POWER

SWITCH

PARASITIC DIODES

DO NOT

FORWARD BIAS

1.2V

–

1.33V

3µA

7µA

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applicaTions inForMaTion

FB RESISTOR NETWORK

If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required, the

respective fixed option part, -1.8, -2.5, -3.3 or -5, should be

used. The FB pin is tied directly to the output; the necessary

resistive divider is already included on the part. For other

voltage outputs, the adjustable part should be used and an

external resistor divider added. The suggested resistor (R2)

from FB to ground is 10k. This reduces the contribution of

FB input bias current to output voltage to less than 0.25%.

The formula for the resistor (R1) from VOUT to FB is:

R1=R2 VOUT −1.2

( )

1.2−R2(0.25µA)

(~0.4V at maximum load). This leads to a minimum input

voltage of:

IN MIN

( )

OUT

DCMAX

– V

D+VSW

with DCMAX = 0.80 at output current below 0.5A, and

DCMAX = 0.75 at higher loads. The maximum duty cycle

decreases when the LT1767 is synchronized to an external

clock; DCMAX = 1 – 0.25µs • fCLK.

The maximum input voltage is determined by the absolute

maximum ratings of the VIN and BOOST pins and by the

minimum duty cycle DCMIN = 0.16:

IN MAX

( )

OUT

DCMIN

– V

D+VSW

For a 12V input, the lowest practical output voltage is

1.8V. Minimum duty cycle will increase when the LT1767

is synchronized; DCMIN = 0.11µs • fCLK. Note that this is

a restriction on the operating input voltage; the circuit

will tolerate transient inputs up to the absolute maximum

ratings of the VIN and BOOST pins, provided the output

is not shorted.

For wider input voltage range, consult the related parts

table on the last page of this data sheet.

INPUT CAPACITOR

Step-down regulators draw current from the input supply in

pulses. The rise and fall times of these pulses are very fast.

The input capacitor is required to reduce the voltage ripple

this causes at the input of LT1767 and force the switching

current into a tight local loop, thereby minimizing EMI. The

RMS ripple current can be calculated from:

IRIPPLE RMS

( )

=IOUT VOUT VIN −VOUT

( )

VIN2

Higher value, lower cost ceramic capacitors are now available

in smaller case sizes. These are ideal for input bypassing

since their high frequency capacitive nature removes most

ripple current rating and turn-on surge problems. At higher

switching frequency, the energy storage requirement of the

Figure 2. Feedback Network

–

1.2V

GND

1767 F02

10k

OUTPUT

ERROR

AMPLIFIER

LT1767

INPUT VOLTAGE RANGE

The input voltage range for LT1767 applications depends

on the output voltage, the absolute maximum ratings of

the VIN and BOOST pins, and the operating frequency.

The minimum input voltage is determined by either the

LT1767’s minimum operating voltage of 2.73V or by its

maximum duty cycle. The duty cycle is the fraction of

time that the internal switch is on and is determined by

the input and output voltages:

DC =

OUT

– V

where VD is the forward voltage drop of the catch diode

(~0.4V) and VSW is the voltage drop of the internal switch

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applicaTions inForMaTion

INDUCTOR CHOICE AND MAXIMUM OUTPUT

CURRENT

Maximum output current for a buck converter is equal

to the maximum switch rating (IP) minus one half peak

to peak inductor current. In past designs, the maximum

switch current has been reduced by the introduction of

slope compensation. Slope compensation is required at

duty cycles above 50% to prevent an affect called sub-

harmonic oscillation (see Application Note 19 for details).

The LT1767 has a new circuit technique that maintains a

constant switch current rating at all duty cycles.

For most applications, the output inductor will be in the

1µH to 10µH range. Lower values are chosen to reduce

the physical size of the inductor, higher values allow

higher output currents due to reduced peak to peak ripple

current, and reduces the current at which discontinuous

operation occurs. The following formula gives maximum

output current for continuous mode operation, implying

that the peak to peak ripple (2x the term on the right) is

less than the maximum switch current.

input capacitor is reduced so values in the range of 1µF

to 4.7µF are suitable for most applications.

Y5V or similar

type ceramics can be used since the absolute value of ca-

pacitance is less important and has no significant effect on

loop stability. If operation is required close to the minimum

input required by the output of the LT1767, a larger value

may be required. This is to prevent excessive ripple causing

dips below the minimum operating voltage, resulting in

erratic operation.

If tantalum capacitors are used, values in the 22µF to 470µF

range are generally needed to minimize ESR and meet ripple

current and surge ratings. Care should be taken to ensure

the ripple and surge ratings are not exceeded. The AVX TPS

and Kemet T495 series are surge rated. AVX recommends

derating capacitor operating voltage by 2:1 for high surge

applications.

OUTPUT CAPACITOR

Unlike the input capacitor, RMS ripple current in the output

capacitor is normally low enough that ripple current rating

is not an issue. The current waveform is triangular, with

an RMS value given by:

RIPPLE RMS

( )

=0.29 V

OUT

( )

−V

OUT

( )

The LT1767 will operate with both ceramic and tantalum

output capacitors. Ceramic capacitors are generally chosen

for their small size, very low ESR (effective series resistance),

and good high frequency operation, reducing output ripple

voltage. Typical ceramic output capacitors are in the 4.7µF

to 47µF range. Since the absolute value of capacitance

defines the pole frequency of the output stage, an X7R or

X5R type ceramic, which have good temperature stability,

is recommended.

Tantalum capacitors are usually chosen for their bulk capac-

itance properties, useful in high transient load applications.

ESR rather than capacitive value defines output ripple at

1.25MHz. Typical LT1767 applications require a tantalum

capacitor with less than 0.3Ω ESR at 22µF to 500µF.

Figure 3. Output Ripple Voltage Waveform

VOUT USING 47µF, 0.1Ω

TANTALUM CAPACITOR

(10mV/DIV)

0.2µs/DIV

1767 F03

VOUT USING 2.2µF

CERAMIC CAPACITOR

(10mV/DIV)

VSW

(5V/DIV)

Figure 3 shows a comparison of output ripple for a ceramic

and tantalum capacitor at 200mA ripple current.

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applicaTions inForMaTion

especially with smaller inductors and lighter loads, so

don’t omit this step. Powdered iron cores are forgiving

because they saturate softly, whereas ferrite cores

saturate abruptly. Other core materials fall somewhere

in between.

IPEAK =IOUT +VOUT VIN−VOUT

( )

2 L

( )

VIN

( )

VIN = Maximum input voltage

f = Switching frequency, 1.25MHz

3. Decide if the design can tolerate an “open” core ge-

ometry like a rod or barrel, which have high magnetic

field radiation, or whether it needs a closed core like a

toroid to prevent EMI problems. This is a tough decision

because the rods or barrels are temptingly cheap and

small and there are no helpful guidelines to calculate

when the magnetic field radiation will be a problem.

4. After making an initial choice, consider the secondary

things like output voltage ripple, second sourcing, etc.

Use the experts in the Linear Technology’s applications

department if you feel uncertain about the final choice.

They have experience with a wide range of inductor

types and can tell you about the latest developments

in low profile, surface mounting, etc.

Continuous Mode

IOUT MAX

( )

IP−VOUT

( )

VIN −VOUT

( )

2 L

( )

VIN

( )

Discontinuous operation occurs when

IOUT(DIS) =

OUT

)

2(L)(f)

For VIN = 8V, VOUT = 5V and L = 3.3µH,

IOUT MAX

( )

=1.5−5

( )

−

( )

2 3.3 •10−6

( )

1.25 •106

( )

=1.5 −0.23=1.27 A

Note that the worst case (minimum output current avail-

able) condition is at the maximum input voltage. For the

same circuit at 15V, maximum output current would be

only 1.1A.

When choosing an inductor, consider maximum load cur-

rent, core and copper losses, allowable component height,

output voltage ripple, EMI, fault current in the inductor,

saturation, and of course, cost. The following procedure

is suggested as a way of handling these somewhat com-

plicated and conflicting requirements.

1. Choose a value in microhenries from the graphs of

maximum load current. Choosing a small inductor

with lighter loads may result in discontinuous mode

of operation, but the LT1767 is designed to work well

in either mode.

Assume that the average inductor current is equal to

load current and decide whether or not the inductor

must withstand continuous fault conditions. If maxi-

mum load current is 0.5A, for instance, a 0.5A inductor

may not survive a continuous 2A overload condition.

Also, the instantaneous application of input or release

from shutdown, at high input voltages, may cause

saturation of the inductor. In these applications, the

soft-start circuit shown in Figure 10 should be used.

2. Calculate peak inductor current at full load current to

ensure that the inductor will not saturate. Peak cur-

rent can be significantly higher than output current,

Table 1

PART NUMBER VALUE (uH) IS AT (Amps) DCR () HEIGHT (mm)

Coiltronics

TP1-2R2 2.2 1.3 0.188 1.8

TP2-2R2 2.2 1.5 0.111 2.2

TP3-4R7 4.7 1.5 0.181 2.2

TP4- 100 10 1.5 0.146 3.0

Murata

LQH1C1R0M04 1.0 0.51 0.28 1.8

LQH3C1R0M24 1.0 1.0 0.06 2.0

LQH3C2R2M24 2.2 0.79 0.1 2.0

LQH4C1R5M04 1.5 1.0 0.09 2.6

Sumida

CD73- 100 10 1.44 0.080 3.5

CDRH4D18-2R2 2.2 1.32 0.058 1.8

CDRH5D18-6R2 6.2 1.4 0.071 1.8

CDRH5D28-100 10 1.3 0.048 2.8

LT1767/LT1767-1.8/

LT1767-2.5/LT1767-3.3/LT1767-5

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For more information www.linear.com/LT1767

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CATCH DIODE

The suggested catch diode (D1) is a UPS120 Schottky, or

its Motorola equivalent, MBRM120LT I /MBRM130LT I . It is

rated at 2A average forward current and 20V/30V reverse

voltage. Typical forward voltage is 0.5V at 1A. The diode

conducts current only during switch off time. Peak reverse

voltage is equal to regulator input voltage. Average forward

current in normal operation can be calculated from:

ID AVG

( )

=IOUT VIN −VOUT

( )

BOOST PIN

For most applications, the boost components are a 0.1µF

capacitor and a CMDSH-3 diode. The anode is typically

connected to the regulated output voltage to generate

a voltage approximately VOUT above VIN to drive the

output stage. The output driver requires at least 2.7V of

headroom throughout the on period to keep the switch

fully saturated. However, the output stage discharges the

boost capacitor during the on time. If the output voltage is

less than 3.3V, it is recommended that an alternate boost

supply is used. The boost diode can be connected to the

input, although, care must be taken to prevent the 2x VIN

boost voltage from exceeding the BOOST pin absolute

maximum rating. The additional voltage across the switch

driver also increases power loss, reducing efficiency. If

available, an independent supply can be used with a local

bypass capacitor.

A 0.1µF boost capacitor is recommended for most ap-

plications. Almost any type of film or ceramic capacitor

is suitable, but the ESR should be <1Ω to ensure it can

be fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

700ns on-time, 50mA boost current, and 0.7V discharge

ripple. This value is then guard banded by 2x for secondary

factors such as capacitor tolerance, ESR and temperature

effects. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve cir-

cuit operation or efficiency. Under low input voltage and

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start up operation.

SHUTDOWN AND UNDERVOLTAGE LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1767. Typically, UVLO is used in situations where

the input supply is

current limited

, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

load to the source and can cause the source to current limit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

An internal comparator will force the part into shutdown

below the minimum VIN of 2.6V. This feature can be

used to prevent excessive discharge of battery-operated

systems. If an adjustable UVLO threshold is required, the

shutdown pin can be used. The threshold voltage of the

shutdown pin comparator is 1.33V. A 3µA internal current

source defaults the open pin condition to be operating (see

Typical Performance Graphs). Current hysteresis is added

above the SHDN threshold. This can be used to set voltage

hysteresis of the UVLO using the following:

R1=

−V

7µA

R2=1.33V

VH−1.33V

( )

+3µA

VH – Turn-on threshold

VL – Turn-off threshold

1.33V

GND

VSW

VIN

1767 F04

OUTPUT

SHDN

VCC

LT1767

3µA

7µA

Figure 4. Undervoltage Lockout

LT1767/LT1767-1.8/

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Example: switching should not start until the input is

above 4.75V and is to stop if the input falls below 3.75V.

VH = 4.75V

VL = 3.75V

R1=

4.75V −3.75V

7µA=143k

R2=1.33V

4.75V −1.33V

( )

143k

+3µA

=49.4k

Keep the connections from the resistors to the SHDN

pin short and make sure that the interplane or surface

capacitance to the switching nodes are minimized. If high

resistor values are used, the SHDN pin should be bypassed

with a 1nF capacitor to prevent coupling problems from

the switch node.

SYNCHRONIZATION

The SYNC pin, is used to synchronize the internal oscillator

to an external signal. The SYNC input must pass from a

logic level low, through the maximum synchronization

threshold with a duty cycle between 20% and 80%. The

input can be driven directly from a logic level output. The

synchronizing range is equal to

initial

operating frequency

up to 2MHz. This means that

minimum

practical sync

frequency is equal to the worst-case

high

self-oscillating

frequency (1.5MHz), not the typical operating frequency

of 1.25MHz. Caution should be used when synchronizing

above 1.6MHz because at higher sync frequencies the

amplitude of the internal slope compensation used to

prevent subharmonic switching is reduced. This type of

subharmonic switching only occurs at input voltages less

than twice output voltage. Higher inductor values will tend

to eliminate this problem. See Frequency Compensation

section for a discussion of an entirely different cause of

subharmonic switching before assuming that the cause

is insufficient slope compensation. Application Note 19

has more details on the theory of slope compensation.

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maxi-

mum efficiency, switch rise and fall times are typically

in the nanosecond range. To prevent noise both radiated

and conducted, the high speed switching current path,

shown in Figure 5, must be kept as short as possible.

This is implemented in the suggested layout of Figure 6.

Shortening this path will also reduce the parasitic trace

inductance of approximately 25nH/inch. At switch-off, this

parasitic inductance produces a flyback spike across the

LT1767 switch. When operating at higher currents and

input voltages, with poor layout, this spike can generate

voltages across the LT1767 that may exceed its absolute

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

The VC and FB components should be kept as far away as

possible from the switch and boost nodes. The LT1767

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability

or subharmonic like oscillation.

Board layout also has a significant effect on thermal re-

sistance. Soldering the exposed pad to as large a copper

area as possible and placing feedthroughs under the pad

to a ground plane, will reduce die temperature and increase

the power capacity of the LT1767. For the nonexposed

package, Pin 4 is connected directly to the pad inside the

package. Similar treatment of this pin will result in lower

die temperatures.

Figure 5. High Speed Switching Path

1767 F05

LT1767

D1 C1C3

HIGH

FREQUENCY

CIRCULATING

PATH

LOAD

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Figure 6. Typical Application and Suggested Layout (Topside Only Shown)

BOOST

LT1767-2.5

OUTPUT

2.5V

1.2A

12V

1767 F06a

0.1µF

1.5nF

4.7k

UPS120

10µF

CERAMIC

2.2µF

CERAMIC

CMDSH-3

5µH

FBSHDN

OPEN

HIGH

= ON GND V

SYNC

GND

OUT

1767 F06

SYNC

SHDN

KELVIN SENSE

OUT

CONNECT TO

GROUND PLANE

MINIMIZE LT1767,

C3, D1 LOOP

KEEP FB AND V

COMPONENTS

AWAY FROM

HIGH INPUT

COMPONENTS

PLACE FEEDTHROUGHS

AROUND GROUND PIN

AND UNDER GROUND PAD

FOR GOOD THERMAL

CONDUCTIVITY

GND

THERMAL CALCULATIONS

Power dissipation in the LT1767 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current, and input quiescent current. The following

formulas show how to calculate each of these losses.

These formulas assume continuous mode operation, so

they should not be used for calculating efficiency at light

load currents.

Switch loss:

PSW =RSW IOUT

( )

2VOUT

( )

+17ns IOUT

( )

VIN

( )

Boost current loss for VBOOST = VOUT:

PBOOST =VOUT2IOUT / 50

( )

Quiescent current loss:

VIN 0.001

( )

RSW = Switch resistance (≈0.27Ω when hot)

17ns = Equivalent switch current/voltage overlap time

f = Switch frequency

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Example: with VIN = 10V, VOUT = 5V and IOUT = 1A:

PSW =0.27

( )

10 +17 •10−9

( )

1.25 •106

( )

=0.135+0.21=0.34W

PBOOST =5

( )

21/ 50

( )

10 =0.05W

PQ=10 0.001

( )

=0.01W

Total power dissipation is 0.34 + 0.05 + 0.01 = 0.4W.

Thermal resistance for LT1767 package is influenced

by the presence of internal or backside planes. With a

full plane under the package, thermal resistance for the

exposed pad package will be about 40°C/W. No plane

will increase resistance to about 150°C/W. To calculate

die temperature, use the appropriate thermal resistance

number and add in worst-case ambient temperature:

TJ = TA + θJA (PTOT)

When estimating ambient, remember the nearby catch

diode and inductor will also be dissipating power.

DIODE =VF

( )

VIN −VOUT

( )

ILOAD

( )

VF = Forward voltage of diode (assume 0.5V at 1A)

DIODE =0.5

( )

12−5

( )

=0.29W

Notice that the catch diode’s forward voltage contributes

a significant loss in the overall system efficiency. A larger,

lower VF diode can improve efficiency by several percent.

PINDUCTOR = (ILOAD) (LDCR)

LDCR = Inductor DC resistance (assume 0.1Ω)

PINDUCTOR = (1) (0.1) = 0.1W

Typical thermal resistance of the board is 35°C/W. At an

ambient temperature of 65°C,

Tj = 65 + 40 (0.4) + 35 (0.39) = 95°C

If a true die temperature is required, a measurement of the

SYNC to GND pin resistance can be used. The SYNC pin

resistance across temperature must first be calibrated, with

no device power, in an oven. The same measurement can

then be used in operation to indicate the die temperature.

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency

response, the following should be remembered – the worse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits, read the Layout Considerations section first.

Common layout errors that appear as stability problems

are distant placement of input decoupling capacitor and/

or catch diode, and connecting the VC compensation to a

ground track carrying significant switch current. In addition,

the theoretical analysis considers only first order non-ideal

component behavior. For these reasons, it is important

that a final stability check is made with production layout

and components.

The LT1767 uses current mode control to regulate the

output. This simplifies loop compensation. In particular,

the LT1767 does not require the ESR (equivalent series

resistance) of the output capacitor for stability, so you

are free to use ceramic capacitors to achieve low output

ripple and small circuit size. Frequency compensation is

provided by the components tied to the VC pin, as shown

in Figure 7. Generally a capacitor (CC) and a resistor (RC)

in series to ground are used. In addition, there may be

lower value capacitor (CF) in parallel.

Figure 7 also shows an equivalent circuit for the LT1767

control loop. The error amplifier is a transconductance

amplifier with finite output impedance. The power section,

consisting of the modulator, power switch and inductor,

is modeled as a transconductance amplifier generating an

output current proportional to the voltage at the VC pin.

Note that the output capacitor integrates this current, and

that the capacitor on the VC pin (CC) integrates the error

amplifier output current, resulting in two poles in the loop.

In most cases a zero is required and comes from either

the output capacitor ESR or from a resistor RC in series

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with CC. This simple model works well as long as the val-

ue of the inductor is not too high and the loop crossover

frequency is much lower than the switching frequency.

A phase lead capacitor (CPL) across the feedback divider

may improve the transient response. An optional capacitor

(CF) in parallel with the compensation may be included.

This capacitor is not part of the loop compensation, but

instead filters noise at the switching frequency, and is

required only if a phase-lead capacitor is used or if the

output capacitor has high ESR.

For output capacitors with specified ESR greater than

~50mΩ, a single capacitor can be used for compensation.

For ceramic output capacitor, include a zero resistor in

the compensation network. Figure 8 shows the transient

response of the circuit on the front page of the data sheet.

When checking loop stability, the circuit should be operated

over the application’s full voltage, current and tempera-

ture range. Any transient loads should be applied and the

output voltage monitored for a well-damped behavior. See

Application Note 76 for more details.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for exam-

ple, a battery powered device with a wall adapter input,

the output of the LT1767 can be held up by the backup

supply with its input disconnected. In this condition, the

SW pin will source current into the VIN pin. If the SHDN

pin is held at ground, only the shut down current of 6µA

will be pulled via the SW pin from the second supply.

With the SHDN pin floating, the LT1767 will consume its

quiescent operating current of 1mA. The VIN pin will also

source current to any other components connected to the

input line. If this load is greater than 10mA or the input

could be shorted to ground, a series Schottky diode must

be added, as shown in Figure 9. With these safeguards,

the output can be held at voltages up to the VIN absolute

maximum rating.

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 10 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

configuration with the addition of R3, R4, CSS and Q1. As

the output starts to rise, Q1 turns on, regulating switch

current via the VC pin to maintain a constant dv/dt at the

output. Output rise time is controlled by the current through

CSS defined by R4 and Q1’s VBE. Once the output is in

regulation, Q1 turns off and the circuit operates normally.

R3 is transient protection for the base of Q1.

RiseTime =(R4)(CSS )(VOUT )

)

Using the values shown in Figure 10,

RiseTime =(47 •103)(15 •10–9 )(5)

0.7

=5ms

Figure 7. Model for Loop Response

–

1.2V

LT1767

GND

1767 F07

OUTPUT

ESR

500k

ERROR

AMPLIFIER

R2 C1

CURRENT MODE

POWER STAGE

= 2.5mho

850µmho

CERAMICTANTALUM

Figure 8. Oscillograph Shows the Output Voltage

Response to a Load Current Transient from 0.3A to 1A.

The Compensation Network Results in Fast, Damped

Response. (Front Page Schematic, 12V in to 3.3V out)

10µs/DIV

OUT

100mV/DIV

1767 F08

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The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

output current is unchanged. Variants of this circuit can

be used for sequencing multiple regulator outputs.

Dual Output SEPIC Converter

The circuit in Figure 11 generates both positive and negative

5V outputs with a single piece of magnetics. The two in-

ductors shown are actually just two windings on a standard

B H Electronics inductor. The topology for the 5V output

is a standard buck converter. The – 5V topology would be

a simple flyback winding coupled to the buck converter

if C4 were not present. C4 creates a SEPIC (single-ended

primary inductance converter) topology which improves

regulation and reduces ripple current in L1. Without C4,

the voltage swing on L1B compared to L1A would vary

due to relative loading and coupling losses. C4 provides a

low impedance path to maintain an equal voltage swing in

L1B, improving regulation. In a flyback converter, during

switch on time, all the converter’s energy is stored in L1A

only, since no current flows in L1B. At switch off, energy

is transferred by magnetic coupling into L1B, powering

the –5V rail. C4 pulls L1B positive during switch on time,

causing current to flow, and energy to build in L1B and

C4. At switch off, the energy stored in both L1B and C4

supply the –5V rail. This reduces the current in L1A and

changes L1B current waveform from square to triangular.

For details on this circuit, including maximum output

currents, see Design Note 100.

3.3V, 1A

* ONLY REQUIRED IF INPUT CAN SINK >10mA

REMOVABLE

INPUT

0.1µF

1.5nF

83k

UPS120

1767 F09

2.2µF

UPS120*

CMDSH-3

5µH

10µF

BOOST

LT1767-3.3

FBSHDN

GND V

SYNC

ALTERNATE

SUPPLY

28.5k

4.7k

Figure 10. Buck Converter with Adjustable Soft-Start

BOOST

LT1767-5

VIN

OUTPUT

VIN

12V

1767 F10

0.1µF

100µF

CSS

15nF

330pF

2.2µF

CMDSH-3

5µH

VSW

SHDN

GND VC

SYNC

47k

D1: UPS120

Q1: 2N3904

OUTPUT

–5V

†

* L1 IS A SINGLE CORE WITH TWO WINDINGS

BH ELECTRONICS #511-1013

†

IF LOAD CAN GO TO ZERO,

AN OPTIONAL PRELOAD OF 1k TO 5k

MAY BE USED TO IMPROVE LOAD REGULATION

D1, D3: UPS120

TO 15V

GND

1767 F11

0.1µF

330pF D1

100µF

10V TANT

100µF

10V TANT

2.2µF

16V

CERAMIC

2.2µF

16V

CERAMIC

CMDSH-3

L1A*

9µH

L1B*

BOOST

LT1767-5

FBSHDN

GND V

SYNC

Figure 11. Dual Output SEPIC Converter

Figure 9. Dual Source Supply with 6µA Reverse Leakage

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package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MS8) 0213 REV G

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.86

(.034)

REF

0.65

(.0256)

BSC

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

1 2 34

4.90 ±0.152

(.193 ±.006)

8765

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.52

(.0205)

REF

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.038

(.0165 ±.0015)

TYP

0.65

(.0256)

BSC

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev G)

LT1767/LT1767-1.8/

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Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MS8E) 0213 REV K

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.65

(.0256)

BSC

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

1 2 34

4.90 ±0.152

(.193 ±.006)

BOTTOM VIEW OF

EXPOSED PAD OPTION

765

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.52

(.0205)

REF

1.68

(.066)

1.88

(.074)

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004) 0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.65

(.0256)

BSC

0.42 ±0.038

(.0165 ±.0015)

TYP

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MS8E Package

8-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1662 Rev K)

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation

that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

B 11/14 Clarified Schematic and Graph

Clarified Ordering Information

Clarified Note 1

Clarified Minimum Input Voltage for 3.3VOUT Graph

Added Input Voltage Range Section

Clarified Figure 5

Clarified Frequency Compensation Description

Clarified Related Parts Section

(Revision history begins at Rev B)

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Linear Technology Corporation

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 LINEAR TECHNOLOGY CORPORATION 1999

LT 1114 REV B • PRINTED IN USA

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT1767

Typical applicaTion

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LT1936 36V, 1.5A, 500kHz, Step-Down Regulator 90% Efficiency, VIN = 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.8mA,

ISC<1µA, MSOP-8E

LT3505 36V, 1.2A, 3MHz, Step-Down Regulator 90% Efficiency, VIN = 3.6V to 36V, VOUT(MIN) = 0.78V, IQ = 2mA,

ISC<2µA, 3mm×3mm DFN-8, MSOP-8E

LTC3600 15V, 1.5A, 4MHz, Synchronous Rail-to-Rail Single Resistor

Step-Down Regulator

95% Efficiency, VIN = 4V to 15V, VOUT(MIN) = 0V, IQ = 700µA,

ISC<1µA, 3mm×3mm DFN-12, MSOP-12E

LTC3621/

LTC3621-2

17V, 1.5A, 1/2.25MHz, Synchronous Step-Down Regulator 95% Efficiency, VIN = 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 3.5µA,

ISC<1µA, 2mm×3mm DFN-6, MSOP-8E

LTC3624/

LTC3624-2

17V, 2A, 1/2.25MHz, Synchronous Step-Down Regulator 95% Efficiency, VIN = 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 3.5µA,

ISC<1µA, 3mm×3mm DFN-8

LTC3622/

LTC3622-2

17V, Dual 1A (IOUT), 1/2.25MHz, Synchronous Step-Down

DC/DC Converter

95% Efficiency, VIN = 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 5µA,

ISC<1µA, 3mm×4mm DFN-14

LTC3646/

LTC3646-1

340V, 1A (IOUT), 4MHz, Synchronous

Step-Down DC/DC Converter

95% Efficiency, VIN = 4V to 40V, VOUT(MIN) = 0.6V, IQ = 140µA,

ISC<8µA, 3mm×4mm DFN-14, MSOP16E

LT3685 36V (60V Transients), 2A (IOUT), 2.44MHz,

Step-Down DC/DC Converter

90% Efficiency, VIN = 3.6V to 36V, VOUT(MIN) = 0.79V, IQ = 0.9mA,

ISC<14µA, 3mm×3mm DFN-10, MSOP-10E

LT3508 36V, Dual 1.4A, 2.5MHz, Step-Down Regulator 90% Efficiency, VIN = 3.7V to 36V, VOUT(MIN) = 0.8V, IQ = 2mA,

ISC<1µA, 4mm×4mm QFN-24, TSSOP-16E

BOOST

LT1767-3.3

VIN

OUTPUT

3.3V

1.2A*

VIN

12V

1767 TA01

0.1µF

1.5nF

4.7k

UPS120

10µF

CERAMIC

2.2µF

CERAMIC

CMDSH-3

5µH

VSW

FBSHDN

OPEN

HIGH

= ON GND VC

SYNC

*MAXIMUM OUTPUT CURRENT IS SUBJECT TO THERMAL DERATING.

12V to 3.3V Step-Down Converter