MC33580BAPNAR2 - Freescale Semiconductor / Motorola

Document Number: MC33580

Rev. 6.0, 4/2007

Freescale Semiconductor

Advance Information

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Quad High-Side Switch

(Quad 15 mΩ)

The 33580 is one in a family of devices designed for low-voltage

automotive and industrial lighting and motor control applications. Its

four low RDS(ON) MOSFETs (four 15 mΩ) can control the high sides of

four separate resistive or inductive loads.

Programming, control, and diagnostics are accomplished using a

16-bit SPI interface. Additionally, each output has its own parallel input

for pulse-width modulation (PWM) control if desired. The 33580 allows

the user to program via the SPI the fault current trip levels and duration

of acceptable lamp inrush or motor stall intervals. Such

programmability allows tight control of fault currents and can protect

wiring harnesses and circuit boards as well as loads.

The 33580 is packaged in a power-enhanced 12 x 12 nonleaded

Power QFN package with exposed tabs.

Features

•Quad 15 mΩ High-Side Switches (at 25°C)

• Operating Voltage Range of 6.0 V to 27 V with Standby Current

< 5.0 µA

• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking

Time, Output OFF Open Load Detection, Output ON / OFF

Control, Watchdog Timeout, Slew Rates, and Fault Status

Reporting

• SPI Status Reporting of Overcurrent, Open and Shorted Loads,

Overtemperature, Undervoltage and Overvoltage Shutdown,

Fail-Safe Pin Status, and Program Status

• Analog Current Feedback with Selectable Ratio

• Analog Board Temperature Feedback

• Enhanced -16 V Reverse Polarity VPWR Protection

• Pb-Free Packaging Designated by Suffix Code PNA

Figure 1. 33580 Simplified Application Diagram

HIGH-SIDE SWITCH

PNA SUFFIX (Pb-FREE)

98ART10510D

24-PIN PQFN (12 x 12)

33580

ORDERING INFORMATION

Device Temperature

Range (TA)Package

MC33580BAPNA/R2 - 40°C to 125°C 24 PQFN

VDD

SCLK

I/O

VPWR

WAKE

SCLK

RST

IN0

IN1

IN2

IN3

GND

HS0

HS1

GND

LOAD 0

33580

MCU

VDD

VDD VPWR

A/D

GND

CSNS

TEMP

FSI

VPWR

LOAD 1

LOAD 2

LOAD 3

HS2

HS3

Analog Integrated Circuit Device Data

2Freescale Semiconductor

33580

BLOCK DIAGRAM

Figure 2. 33580 Simplified Internal Block Diagram

GND

Programmable

Watchdog

279 ms–2250 ms

Overtemperature

Detection

Logic

SPI

3.0 MHz

Selectable Over-

HS[0:3]: 4.8 A–18.2 A

Selectable Overcurrent

Internal

Regulator

Selectable Slew

Rate Gate Drive

Over/Undervoltage

Protection

HS0

VPWRVDD

SCLK

RST

WAKE

IN0

FSI

IN3

HS1

HS0

HS1

HS2

HS3

HS2

HS3

IN1

IN2

current Low Detection

HS[0:3]: 70 A or 100 A

Selectable Output Current

HS[0:3]: 1/13000 or 1/38000

CSNS

Recopy (Analog MUX)

VIC

IDWN

IUP

IDWN

RDWN

Open Load

Detection

High Detection

Selectable Over-

current Low Detection

0.15 ms–155 ms

Blanking Time

Temperature

Feedback

TEMP

VIC

Analog Integrated Circuit Device Data

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33580

PIN CONNECTIONS

Figure 3. 33580 Pin Connections

Table 1. 33580 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

Number Pin Name Pin

Function Formal Name Definition

1 CSNS Output Output Current

Monitoring

The Current Sense pin sources a current proportional to the designated

HS0 : HS3 output.

IN0

IN1

IN2

IN3

Input Serial Inputs The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 high-

side output pins, respectively.

4 TEMP Output Temperature

Feedback

This pin reports an analog value proportional to the temperature of the GND

flag (pins 14, 17, 23). It is used by the MCU to monitor board temperature.

7FS Output Fault Status

(Active Low)

This pin is an open drain configured output requiring an external pullup resistor

to VDD for fault reporting.

8 WAKE Input Wake This input pin controls the device mode and watchdog timeout feature if

enabled.

9RST Input Reset This input pin is used to initialize the device configuration and fault registers,

as well as place the device in a low-current sleep mode.

10 CS Input Chip Select

(Active Low)

This input pin is connected to a chip select output of a master microcontroller

(MCU).

11 SCLK Input Serial Clock This input pin is connected to the MCU providing the required bit shift clock for

SPI communication.

12 SI Input Serial Input This pin is a command data input pin connected to the SPI Serial Data Output

of the MCU or to the SO pin of the previous device of a daisy-chain of devices.

Transparent Top View of Package

12 1098 7654 32111

19 20 21

GND

HS3

HS1 NC HS0

HS2

GND

FSI

VDD

SCLK

RST

WAKE

IN3

IN2

TEMP

IN1

IN0

CSNS

GND

VPWR

Analog Integrated Circuit Device Data

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33580

PIN CONNECTIONS

13 VDD Power Digital Drain Voltage

(Power)

This pin is an external voltage input pin used to supply power to the SPI circuit.

14, 17, 23 GND Ground Ground These pins are the ground for the logic and analog circuitry of the device.

15 VPWR Power Positive Power Supply This pin connects to the positive power supply and is the source of operational

power for the device.

16 SO Output Serial Output This output pin is connected to the SPI Serial Data Input pin of the MCU or to

the SI pin of the next device of a daisy-chain of devices.

HS3

HS1

HS0

HS2

Output High-Side Outputs Protected 15 mΩ high-side power output pins to the load.

20 NC N/A No Connect This pin may not be connected.

24 FSI Input Fail-Safe Input The value of the resistance connected between this pin and ground

determines the state of the outputs after a Watchdog timeout occurs.

Table 1. 33580 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

Number Pin Name Pin

Function Formal Name Definition

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33580

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Operating Voltage Range

Steady-State

VPWR(SS)

-16 to 41

VDD Supply Voltage VDD -0.3 to 5.5 V

Input / Output Voltage (1) See note (1) - 0.3 to 7.0 V

SO Output Voltage (1) VSO - 0.3 to VDD

+ 0.3 V

WAKE Input Clamp Current ICL(WAKE) 2.5 mA

CSNS Input Clamp Current ICL(CSNS) 10 mA

HS [0:3] Voltage

Positive

Negative

VHS

-16

Output Current (2) IHS[0:3] 22.8 A

Output Clamp Energy (3) ECL [0:3] 0.2 J

ESD Voltage (4)

Human Body Model (HBM)

Charge Device Model (CDM)

Corner Pins (1, 13, 19, 21)

All Other Pins (2-12, 14-18, 20, 22-24)

VESD1

VESD2

± 2000

± 750

± 500

THERMAL RATINGS

Operating Temperature

Ambient

Junction

- 40 to 125

- 40 to 150

°C

Storage Temperature TSTG - 55 to 150 °C

Thermal Resistance (5)

Junction to Case

Junction to Ambient

RθJC

RθJA

<1.0

°C/ W

Peak Pin Reflow Temperature During Solder Mounting (6) TSOLDER 245 °C

Notes

1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, TEMP, SI, SO, SCLK, CS, or FS pins may cause a malfunction or permanent

damage to the device.

2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

3. Active clamp energy using single-pulse method (L = 2 mH, RL = 0 Ω, VPWR = 14 V, TJ = 150°C initial).

4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)

(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).

5. Device mounted on a 2s2p test board per JEDEC JESD51-2.

6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

Analog Integrated Circuit Device Data

6Freescale Semiconductor

33580

ELECTRICAL CHARACTERISTICS

STATIC ELECTICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER INPUT (VPWR, VDD)

Battery Supply Voltage Range

Fully Operational

VPWR

6.0 – 27

VPWR Operating Supply Current

Outputs ON, HS[0 : 3] open

IPWR(ON)

––20

VPWR Supply Current

Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,

RST = VLOGIC HIGH

IPWR(SBY)

––5.0

Sleep State Supply Current (VPWR = 14 V, RST < 0.5 V, WAKE < 0.5 V)

TA = 25°C

TA = 85°C

IPWR(SLEEP)

–

1.0

–

µA

VDD Supply Voltage VDD(ON) 4.5 5.0 5.5 V

VDD Supply Current

No SPI Communication

3.0 MHz SPI Communication(8)

IDD(ON)

–

1.0

5.0

VDD Sleep State Current IDDSLEEP ––5.0µA

Overvoltage Shutdown Threshold VOV 28 32 36 V

Overvoltage Shutdown Hysteresis VOVHYS 0.2 0.8 1.5 V

Undervoltage Shutdown Threshold (7) VUV 4.75 5.25 5.75 V

Undervoltage Hysteresis (9) VUVHYS –0.25– V

Undervoltage Power-ON Reset VUVPOR – – 4.75 V

Notes

7. The undervoltage fault condition is reported to SPI register as long as the external VDD supply is within specification and the VRWR

voltage level does not go below the undervoltage Power-ON Reset threshold.

8. Not guaranteed in production.

9. This applies when the undervoltage fault is not latched (IN[0:3] = 0).

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ELECTRICAL CHARACTERISTICS

STATIC ELECTICAL CHARACTERISTICS

OUTPUTS (HS0, HS1, HS2, HS3)

Output Drain-to-Source ON Resistance (IHS = 10 A, TA = 25°C)

VPWR = 6.0 V

VPWR = 10 V

VPWR = 13 V

RDS(ON)

–

mΩ

Output Drain-to-Source ON Resistance (IHS = 10 A, TA = 150°C)

VPWR = 6.0 V

VPWR = 10 V

VPWR = 13 V

RDS(ON)

–

25.5

mΩ

Output Source-to-Drain ON Resistance (10)

IHS = 5.0 A, TA = 25°C, VPWR = -12 V

RSD(ON)

––30

mΩ

Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)

SOCH = 0 (11)

SOCH = 1

IOCH0

IOCH1

100

120

Overcurrent Low Detection Levels (9.0 V < VPWR < 16 V)

SOCL[2:0] : 000

SOCL[2:0] : 001

SOCL[2:0] : 010

SOCL[2:0] : 011

SOCL[2:0] : 100

SOCL[2:0] : 101

SOCL[2:0] : 110

SOCL[2:0] : 111

IOCL0

IOCL1

IOCL2

IOCL3

IOCL4

IOCL5

IOCL6

IOCL7

14.6

11.5

8.4

6.9

5.4

3.8

18.2

16.3

14.4

12.5

10.5

8.6

6.7

4.8

22.8

20.4

15.7

13.2

10.8

8.4

6.0

Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)

DICR D2 = 0

DICR D2 = 1

CSR0

CSR1

–

1/13000

1/38000

–

Current Sense Ratio (CSR0) Accuracy

Output Current

2.0 to 10 A

CSR0_ACC

- 15 – 15

Current Sense Ratio (CSR1) Accuracy

Output Current

10 A to 20 A

CSR1_ACC

- 19 – 19

Current Sense Clamp Voltage

CSNS Open; IHS[0:3] = 22 A

VCL(CSNS)

4.5 6.0 7.0

Open Load Detection Current (12) IOLDC 30 – 100 µA

Notes

10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.

11. Guaranteed by process monitoring.

12. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of

an open load condition when the specific output is commanded OFF.

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

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33580

ELECTRICAL CHARACTERISTICS

STATIC ELECTICAL CHARACTERISTICS

OUTPUTS (HS0, HS1, HS2, HS3) (continued)

Output Fault Detection Threshold

Output Programmed OFF

VOFD(THRES)

2.0 3.0 4.0

Output Negative Clamp Voltage

0.5 A < IHS[0:3] < 2.0 A, Output OFF

VCL

- 20 – -16

Overtemperature Shutdown (13) TSD 155 175 190 °C

Overtemperature Shutdown Hysteresis (13) TSD(HYS) 5.0 – 20 °C

CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI)

Input Logic High Voltage (14) VIH 0.7 VDD – – V

Input Logic Low Voltage (14) VIL – – 0.2 VDD V

Input Logic Voltage Hysteresis (15) VIN(HYS) 100 850 1200 mV

Input Logic Pulldown Current (SCLK, SI, IN[0:3], VIN>0.2 VDD) IDWN 5.0 –20 µA

RST Input Voltage Range VRST 4.5 5.0 5.5 V

SO, FS Tri-State Capacitance (15) CSO – – 20 pF

Input Logic Pulldown Resistor (RST) and WAKE RDWN 100 200 400 kΩ

Input Capacitance (15) CIN –4.0 12 pF

Wake Input Clamp Voltage (16)

ICL(WAKE) < 2.5 mA

VCL(WAKE)

7.0 –14

Wake Input Forward Voltage

ICL(WAKE) = -2.5 mA

VF(WAKE)

- 2.0 –- 0.3

SO High-State Output Voltage

IOH = 1.0 mA

VSOH

0.8 VDD – –

FS, SO Low-State Output Voltage

IOL = -1.6 mA

VSOL

–0.2 0.4

SO Tri-State Leakage Current

CS>=0.7VDD, 0<VSO<VDD

ISO(LEAK)

- 5.0 05.0

µA

Input Logic Pullup Current (CS) (17)

Vin < 0.7 VDD

IUP

5.0 –20

µA

Notes

13. Guaranteed by process monitoring. Not production tested.

14. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST

signals may be supplied by a derived voltage referenced to VPWR.

15. Ads Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production

tested.

16. The current must be limited by a series resistance when using voltages > 7.0 V.

17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD.

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

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33580

ELECTRICAL CHARACTERISTICS

STATIC ELECTICAL CHARACTERISTICS

CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI) (continued)

FSI Input pin External Pulldown Resistance (18)

FSI Disabled, HS[0:3] state according to direct inputs state and SPI

INx_SPI bits and A/O_s bit

FSI Enabled, HS[0:3] OFF

FSI Enabled, HS0 ON, HS[1:3] OFF

FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF

RFS

–

6.0

6.5

Infinite

1.0

7.0

–

kohms

Temperature Feedback

TA = 25°C

TFeed

3.8 3.9 4.0

Temperature Feedback Derating DTFeed -7.2 -7.5 -7.8 mV/°C

Notes

18. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the

resistance value will always be within the desired (specified) range.

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

33580

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING (HS0, HS1, HS2, HS3)

Output Rising Slow Slew Rate A (DICR D3 = 0) (19)

9.0 V < VPWR < 16 V

SRRA_SLOW

0.2 0.6 1.5

V/µs

Output Rising Slow Slew Rate B (DICR D3 = 0) (20)

9.0 V < VPWR < 16 V

SRRB_SLOW

0.025 0.1 0.225

V/µs

Output Rising Fast Slew Rate A (DICR D3 = 1) (19)

9.0 V < VPWR < 16 V

SRRA_FAST

0.06 0.2 4.0

V/µs

Output Rising Fast Slew Rate B (DICR D3 = 1) (20)

9.0 V < VPWR < 16 V

SRRB_FAST

0.025 0.3 1.1

V/µs

Output Falling Slow Slew Rate A (DICR D3 = 0) (19)

9.0 V < VPWR < 16 V

SRFA_SLOW

0.2 0.6 1.5

V/µs

Output Falling Slow Slew Rate B (DICR D3 = 0) (20)

9.0 V < VPWR < 16 V

SRFB_SLOW

0.025 0.1 0.225

V/µs

Output Falling Fast Slew Rate A (DICR D3 = 1) (19)

9.0 V < VPWR < 16 V

SRFA_FAST

1.2 3.5 5.0

V/µs

Output Falling Fast Slew Rate B (DICR D3 = 1) (20)

9.0 V < VPWR < 16 V

SRFB_FAST

0.025 0.7 1.1

V/µs

Direct Input Switching Frequency (DICR D3 = 0) fPWM -300 -Hz

Notes

19. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR

- 3.5 V (see Figure 4, page 13).

These parameters are guaranteed by process monitoring.

20. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR

- 3.5 V (see Figure 4). These

parameters are guaranteed by process monitoring.

Analog Integrated Circuit Device Data

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33580

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)

Output Turn-ON Delay Time in Slow Slew Rate (21)

DICR = 0

DLY_SLOW(ON)

2.0 10 130

µs

Output Turn-ON Delay Time in Fast Slew Rate (21)

DICR = 1

DLY_FAST(ON)

1.0 3.0 60

µs

Output Turn-OFF Delay Time in Slow Slew Rate Mode (22)

DICR = 0

DLY_SLOW(OFF)

20 100 400

µs

Output Turn-OFF Delay Time in Fast Slew Rate Mode (22)

DICR = 1

DLY_FAST(OFF)

5.0 20 100

µs

Overcurrent Low Detection Blanking Time

OCLT[1:0] : 00

OCLT[1:0] : 01 (23)

OCLT[1:0] : 10

OCLT[1:0] : 11

OCL0

OCL1

OCL2

OCL3

108

–

0.08

155

–

0.15

202

–

0.3

Overcurrent High Detection Blanking Time tOCH 1.0 520 µs

CS to CSNS Valid Time (24) t

CNSVAL – – 10 µs

Watchdog Timeout (25)

WD[1:0] : 00

WD[1:0] : 01

WD[1:0] : 10

WD[1:0] : 11

WDTO0

WDTO1

WDTO2

WDTO3

446

223

1800

900

558

279

2250

1125

725

363

2925

1463

Notes

21. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output ON to VHS[0 : 3] = 0.5 V with

RL = 5.0 Ω resistive load.

22. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output OFF to VHS[0 : 3] = VPWR -

0.5 V with RL = 5.0 Ω resistive load.

23. This logical bit is not defined. Do not use.

24. Time necessary for the CSNS to be with ±5% of the targeted value.

25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output

driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t

WDTO is consistent for all configured

watchdog time-outs.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

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ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

SPI INTERFACE CHARACTERISTICS

Maximum Frequency of SPI Operation f

SPI – – 3.0 MHz

Required Low State Duration for RST (26) t

WRST –50 350 ns

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27) t

CS – – 300 ns

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (27) t

ENBL – – 5.0 µs

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (27) t

LEAD –50 167 ns

Required High State Duration of SCLK (Required Setup Time) (27) t

WSCLKh – – 167 ns

Required Low State Duration of SCLK (Required Setup Time) (27) t

WSCLKl – – 167 ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (27) t

LAG –50 167 ns

SI to Falling Edge of SCLK (Required Setup Time) (28) t

SI (SU) –25 83 ns

Falling Edge of SCLK to SI (Required Setup Time) (28) t

SI (HOLD) –25 83 ns

SO Rise Time

CL = 200 pF

RSO

–25 50

SO Fall Time

CL = 200 pF

FSO

–25 50

SI, CS, SCLK, Incoming Signal Rise Time (28) t

RSI – – 50 ns

SI, CS, SCLK, Incoming Signal Fall Time (28) t

FSI – – 50 ns

Time from Falling Edge of CS to SO Low Impedance (29) t

SO(EN) – – 145 ns

Time from Rising Edge of CS to SO High Impedance (30) t

SO(DIS) –65 145 ns

Time from Rising Edge of SCLK to SO Data Valid (31)

0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF

VALID

–65 105

Notes

26. RST low duration measured with outputs enabled and going to OFF or disabled condition.

27. Maximum setup time required for the 33580 is the minimum guaranteed time needed from the microcontroller.

28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

29. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.

30. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.

31. Time required to obtain valid data out from SO following the rise of SCLK.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

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33580

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 4. Output Slew Rate and Time Delays

Figure 5. Overcurrent Shutdown

VPWR

VPWR - 0.5V

VPWR - 3V

0.5V

VPWR

PWR-0.5 V

PWR-3.5 V

0.5 V

tDLY_SLOW(OFF)

tDLY_FAST(OFF)

SRRB_SLOW

SRRB

SRFB_SLOW

SRFB_FAST

SRFA_SLOW

SRFA_FAST

SRRA_SLOW

SRRA_FAST

DLY(ON)

Load

Current

IOCHx

IOCLx

tOCLx

Time

tOCH

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

33580

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 6. Overcurrent Low and High Detection

Figure 7. Input Timing Switching Characteristics

IOCH0

OCL0

OCL2

OCL3

OCH

Time

Load

Current

IOCH1

IOCL0

IOCL2

IOCL3

IOCL4

IOCL5

IOCL6

IOCL7

IOCL1

RSTB

CSB

SCLK

Don’t Care Don’t Care Don’t Care

Valid Valid

VIH

VIL

VIH

VIL

TwRSTB

Tlead TwSCLKh TrSI

Tlag

TSIsu TwSCLKl

TSI(hold) TfSI

0.7 VDD

0.2 VDD

0.7VDD

0.2VDD

0.7VDD

TCSB

TENBL

RST

SCLK

0.2 VDD

tWRST tENBL

0.2 VDD

tLEAD

tWSCLKh

tRSI

0.7 VDD

0.2 VDD

0.7 VDD

0.2 VDD

tSI(SU)

WSCLKl

tSI(HOLD) tFSI

0.7 VDD

tCS

tLAG

VIH

VIL

VIH

VIL

VIH

Analog Integrated Circuit Device Data

Freescale Semiconductor 15

33580

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 8. SCLK Waveform and Valid SO Data Delay Time

SCLK

VOH

VOL

VOH

VOL

VOH

VOL

TfSI

TdlyLH

TdlyHL

TVALID

TrSO

TfSO

3.5V

50%

TrSI

High-to-Low

1.0V

0.7 VDD

0.2VDD

0.2 VDD

0.7 VDD

Low-to-High

tRSI tFSI

0.7 VDD

SCLK

VOH

VOL

VOH

VOL

VOH

VOL

1.0 V

0.2 VDD

0.7 VDD

tRSO

tFSO

0.2 VDD

tSO(EN)

tSO(DIS)

3.5 V

Low to High

High to Low

tVALID

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

33580

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33580 is one in a family of devices designed for low-

voltage automotive and industrial lighting and motor control

applications. Its four low RDS(ON) MOSFETs (15 mΩ) can

control the high sides of four separate resistive or inductive

loads.

Programming, control, and diagnostics are accomplished

using a 16-bit SPI interface. Additionally, each output has its

own parallel input for PWM control if desired. The 33580

allows the user to program via the SPI the fault current trip

levels and duration of acceptable lamp inrush or motor stall

intervals. Such programmability allows tight control of fault

currents and can protect wiring harnesses and circuit boards

as well as loads.

The 33580 is packaged in a power-enhanced 12 x 12

nonleaded PQFN package with exposed tabs.

FUNCTIONAL PIN DESCRIPTION

OUTPUT CURRENT MONITORING (CSNS)

The Current Sense pin sources a current proportional to

the designated HS0 : HS3 output. That current is fed into a

ground-referenced resistor and its voltage is monitored by an

MCU's A/D. The output to be monitored is selected via the

SPI. This pin can be tri-stated through SPI.

SERIAL INPUTS (IN0, IN1, IN2, IN3)

The IN0 : IN3 high-side input pins are used to directly

control HS0 : HS3 high-side output pins, respectively. An SPI

logic state is OR ed or AND ed with the SPI instruction. These

pins are to be driven with 5.0 V CMOS levels, and they have

an active internal pulldown current source.

TEMPERATURE FEEDBACK (TEMP)

This pin reports an analog voltage value proportional to the

temperature of the GND. It is used by the MCU to monitor

board temperature.

FAULT STATUS (FS)

This pin is an open drain configured output requiring an

external pullup resistor to VDD for fault reporting. If a device

fault condition is detected, this pin is active LOW. Specific

device diagnostic faults are reported via the SPI SO pin.

WAKE (WAKE)

This input pin controls the device mode and watchdog

timeout feature if enabled. An internal clamp protects this pin

from high damaging voltages when the output is current

limited with an external resistor. This input has a passive

internal pulldown.

RESET (RST)

This input pin is used to initialize the device configuration

and fault registers, as well as place the device in a low-

current sleep mode. The pin also starts the watchdog timer

when transitioning from logic [0] to logic [1]. This pin should

not be allowed to be logic [1] until VDD is in regulation. This

pin has a passive internal pulldown.

CHIP SELECT (CS)

The CS pin enables communication with the master

microcontroller (MCU). When this pin is in a logic [0] state,

the device is capable of transferring information to, and

receiving information from, the MCU. The 33580 latches in

data from the Input Shift registers to the addressed registers

on the rising edge of CS. The device transfers status

information from the power output to the Shift register on the

falling edge of CS. The SO output driver is enabled when CS

is logic [0]. CS should transition from a logic [1] to a logic [0]

state only when SCLK is a logic [0]. CS has an active internal

pullup, IUP.

SERIAL CLOCK (SCLK)

The SCLK pin clocks the internal shift registers of the

33580 device. The serial input (SI) pin accepts data into the

input shift register on the falling edge of the SCLK signal

while the serial output (SO) pin shifts data information out of

the SO line driver on the rising edge of the SCLK signal. It is

important the SCLK pin be in a logic low state whenever CS

makes any transition. For this reason, it is recommended the

SCLK pin be in a logic [0] whenever the device is not

accessed (CS logic [1] state). SCLK has an active internal

pulldown. When CS is logic [1], signals at the SCLK and SI

pins are ignored and SO is tri-stated (high impedance) (see

Figure 9, page 18).

SERIAL INPUT (SI)

This is a serial interface (SI) command data input pin.

Each SI bit is read on the falling edge of SCLK. A 16-bit

stream of serial data is required on the SI pin, starting with

D15 to D0. The internal registers of the 33580 are configured

and controlled using a 5-bit addressing scheme described in

Table 8, page 22. Register addressing and configuration are

described in Table 9, page 22. The SI input has an active

internal pulldown, IDWN.

DIGITAL DRAIN VOLTAGE (VDD)

This pin is an external voltage input pin used to supply

power to the SPI circuit. In the event VDD is lost, an internal

Analog Integrated Circuit Device Data

Freescale Semiconductor 17

33580

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

supply provides power to a portion of the logic, ensuring

limited functionality of the device.

GROUND (GND)

This pin is the ground for the device.

POSITIVE POWER SUPPLY (VPWR)

This pin connects to the positive power supply and is the

source of operational power for the device. The VPWR contact

is the backside surface mount tab of the package.

SERIAL OUTPUT (SO)

The SO data pin is a tri-stateable output from the shift

the CS pin is put into a logic [0] state. The SO data is capable

of reporting the status of the output, the device configuration,

and the state of the key inputs. The SO pin changes state on

the rising edge of SCLK and reads out on the falling edge of

SCLK. Fault and input status descriptions are provided in

Table 16, page 26.

HIGH-SIDE OUTPUTS (HS3, HS1, HS0, HS2)

Protected 15 mΩ high-side power output pins to the load.

FAIL-SAFE INPUT (FSI)

The value of the resistance connected between this pin

and ground determines the state of the outputs after a

Watchdog timeout occurs. Depending on the resistance

value, either all outputs are OFF or the output HSO only is

ON. If the FSI pin is left to float up to a logic [1] level, then the

outputs HS0 and HS2 will turn ON when in the Fail-Safe

state. When the FSI pin is connected to GND, the Watchdog

circuit and Fail-Safe operation are disabled. This pin

incorporates an active internal pullup current source.

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

33580

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

SPI PROTOCOL DESCRIPTION

The SPI interface has a full duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),

and Chip Select (CS).

The SI / SO pins of the 33580 follow a first-in first-out (D15

to D0) protocol, with both input and output words transferring

the most significant bit (MSB) first. All inputs are compatible

with 5.0 V CMOS logic levels.

Figure 9. Single 16-Bit Word SPI Communication

OPERATIONAL MODES

The 33580 has four operating modes: Sleep, Normal,

Fault, and Fail-Safe. Table 5 summarizes details contained in

succeeding paragraphs.

SLEEP MODE

The Default mode of the 33580 is the Sleep mode. This is

the state of the device after first applying battery voltage

(VPWR) prior to any I/O transitions. This is also the state of the

device when the WAKE and RST are both logic [0]. In the

Sleep mode, the output and all unused internal circuitry, such

as the internal 5.0 V regulator, are off to minimize current

draw. In addition, all SPI-configurable features of the device

are as if set to logic [0]. The 33580 will transition to the

Normal or Fail-Safe operating modes based on the WAKE

and RST inputs as defined in Table 5.

NORMAL MODE

The 33580 is in Normal mode when:

•V

PWR and VDD are within the normal voltage range.

•RST pin is logic [1].

• No fault has occurred.

FAIL-SAFE MODE

Fail-Safe Mode and Watchdog

If the FSI input is not grounded, the watchdog timeout

detection is active when either the WAKE or RST input pin

transitions from logic [0] to logic [1]. The WAKE input is

capable of being pulled up to VPWR with a series of limiting

CSB

SCLK

D15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D13 D12 D11 D10

OD12

OD13 OD14 OD15 OD6OD7OD8OD9OD10OD11 OD1 OD2 OD3 OD4OD5

1. RSTB is in a logic H state during the above operation.

2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

NOTES:

OD0

device.

RST

is a logic [1] state during the above operation.

2. D15

D0 relate to the most recent ordered entry of data into the device.

3. OD15

OD0 relate to the first 16 bits of ordered fault and status data out of the device.

Notes

Table 5. Fail-Safe Operation and Transitions to Other

33580 Modes

Mode FS Wake RST WDTO Comments

Sleep x 0 0 x Device is in Sleep mode. All

outputs are OFF

Normal 1 x 1 No Normal mode. Watchdog is

active if enabled.

Fault 0 1 1 No Device is currently in fault

mode. The faulted output(s)

is (are) OFF.

0 1 0

0 0 1

Fail-

Safe

1 0 1

Yes

Watchdog has timed out and

the device is in Fail-Safe

Mode. The outputs are as

configured with the RFS

resistor connected to FSI.

RST and WAKE must go

from logic [1] to logic [0]

simultaneously to bring the

device out of the Fail-safe

mode or momentarily tied the

FSI pin to ground.

1 1 1

1 1 0

x = Don’t care.

Analog Integrated Circuit Device Data

Freescale Semiconductor 19

33580

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

resistance limiting the internal clamp current according to the

specification.

The Watchdog timeout is a multiple of an internal oscillator

and is specified in the Table 15, page 24. As long as the WD

bit (D15) of an incoming SPI message is toggled within the

minimum watchdog timeout period (WDTO), based on the

programmed value of the WDR, the device will operate

normally. If an internal watchdog timeout occurs before the

WD bit, the device will revert to a Fail-Safe mode until the

device is reinitialized.

During the Fail-Safe mode, the outputs will be ON or OFF

depending upon the resistor RFS connected to the FSI pin,

regardless of the state of the various direct inputs and modes

(Table 6).

In the Fail-Safe mode, the SPI register content is retained

except for overcurrent high and low detection levels, timing

and latched overtemperature which are reset to their default

value (SOCL, SOCH, OCTL and OT_latch_[0:3] bits). Then the

watchdog, overvoltage, overtemperature, and overcurrent

circuitry (with default value) are fully operational.

The Fail-Safe mode can be detected by monitoring the

WDTO bit D2 of the WD register. This bit is logic [1] when the

device is in Fail-Safe mode. The device can be brought out of

the Fail-Safe mode by transitioning the WAKE and RST pins

from logic [1] to logic [0] or forcing the FSI pin to logic [0].

Table 5 summarizes the various methods for resetting the

device from the latched Fail-Safe mode.

If the FSI pin is tied to GND, the Watchdog fail-safe

operation is disabled.

Loss of VDD

If the external 5.0 V supply is not within specification, or

even disconnected, all register content is reset. The outputs

can still be driven by the direct inputs IN0 : IN3. The 33580

uses the battery input to power the output MOSFET-related

current sense circuitry and any other internal logic providing

fail-safe device operation with no VDD supplied. In this state,

the watchdog, undervoltage, overvoltage, overtemperature

(latched), and overcurrent circuitry are fully operational with

default values.

FAULT MODE

This 33580 indicates the faults below as they occur by

driving the FS pin to logic [0]:

• Overtemperature fault

• Overvoltage and undervoltage fault

• Open load fault

• Overcurrent fault (high and low)

The FS pin will automatically return to logic [1] when the

fault condition is removed, except for overcurrent,

overtemperature (in case of latching configuration) and in

some cases of undervoltage.

The FS pin reports all faults. For latched faults, this pin is

reset by a new Switch ON command (via SPI or direct input

IN).

Fault information is retained in the fault register and is

available (and reset) via the SO pin during the first valid SPI

communication (refer to Table 17, page 26).

PROTECTION AND DIAGNOSTIC FEATURES

OVERTEMPERATURE FAULT (LATCHING OR

NON-LATCHING)

The 33580 incorporates overtemperature detection and

shutdown circuitry for each output structure.

The overtemperature is latched per default and can be

unlatched through SPI with OT_latch_[0:3] bits.

An overtemperature fault condition results in turning OFF

the corresponding output. To remove the fault and be able to

turn ON again the outputs, the failure must be removed and:

• in Normal Mode: the corresponding output must be

commanded OFF and ON again in case of

overtemperature latched (OT_latch bit = 0).

• in Normal Mode: the corresponding output turns ON

automatically if the temperature is below TSD-TSD(HYS)

in case of unlatched overtemperature (OT_latch bit = 1).

• in Fail-Safe Mode: the FSI input must be grounded and

then set to its nominal voltage to switch ON the outputs.

The overtemperature fault (one for each output) is

reported by SPI. If the overtemperature is latched, the SPI

reports OTF_s = [1] and OCLF_s = [1]. In case of non-

latched, OTF_s = [1] only is reported.

The fault bits will be cleared in the status register after

either a valid SPI read command or a power on reset of the

device.

Table 6. Output State During Fail-Safe Mode

RFS (kΩ)High-Side State

0 (shorted to ground) Fail-Safe Mode Disabled

6.0 All HS OFF

15 HS0 ON

HS1 : HS3 OFF

30 (open) HS0 and HS2 ON

HS1 and HS3 OFF

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

33580

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

OVERCURRENT FAULT (LATCHING)

The 33580 has eight programmable overcurrent low

detection levels (IOCL) and two programmable overcurrent

high detection levels (IOCH) for maximum device protection.

The two selectable, simultaneously active overcurrent

detection levels, defined by IOCH and IOCL, are illustrated in

Figure 6, page 14. The eight different overcurrent low detect

levels (IOCL0 : IOCL7) are illustrated in Figure 6.

If the load current level ever reaches the selected

overcurrent low detection level and the overcurrent condition

exceeds the programmed overcurrent time period (tOCx), the

device will latch the output OFF.

If at any time the current reaches the selected IOCH level,

then the device will immediately latch the fault and turn OFF

the output, regardless of the selected toch driver.

For both cases, the device output will stay off indefinitely

until the device is commanded OFF and then ON again.

OVERVOLTAGE FAULT (NON-LATCHING)

The 33580 shuts down the output during an overvoltage

fault (OVF) condition on the VPWR pin. The output remains in

the OFF state until the overvoltage condition is removed.

When experiencing this fault, the OVF fault bit is set in the bit

D1 and cleared after either a valid SPI read or a power reset

of the device.

The overvoltage protection can be disabled through SPI

(bit OV_DIS). When disabled, the returned SO bit OD13 still

reflects any overvoltage condition (overvoltage warning).

UNDERVOLTAGE SHUTDOWN (LATCHING OR

NON-LATCHING)

The output(s) will latch off at some battery voltage below

6.0 V. As long as the VDD level stays within the normal

specified range, the internal logic states within the device will

be sustained.

In the case where battery voltage drops below the

undervoltage threshold (VPWRUV) output will turn off, FS will

go to logic 0, and the fault register UVF bit will be set to 1.

Two cases need to be considered when the battery level

recovers :

• If outputs command are low, FS will go to logic 1 but the

UVF bit will remain set to 1 until the next read operation

(warning report).

• If the output command is ON, then FS will remain at

logic 0. The output must be turned OFF and ON again

to re-enable the state of output and release FS. The

UVF bit will remain set to 1 until the next read operation.

The undervoltage protection can be disabled through SPI

(bit UV_dis = 1). In this case, the FS does not report any

undervoltage fault condition, UVF bit is set to 1, and the

output state is not changed as long as the battery voltage

does not drop any lower than 2.5 V.

In case of VPWR is missing, the daisy chain feature is

available under VDD in nominal conditions.

Analog Integrated Circuit Device Data

Freescale Semiconductor 21

33580

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

OPEN LOAD FAULT (NON-LATCHING)

The 33580 incorporates open load detection circuitry on

the output. Output open load fault (OLF) is detected and

reported as a fault condition when the output is disabled

(OFF). The open load fault is detected and latched into the

status register after the internal gate voltage is pulled low

enough to turn OFF the output. The OLF fault bit is set in the

status register. If the open load fault is removed, the status

The open load protection can be disabled through SPI (bit

OL_DIS). It is recommended to disable the open load

detection circuitry in case of permanent disconnected

load.

REVERSE BATTERY

The output survives the application of reverse voltage as

low as -16 V. Under these conditions, the output’s gate is

enhanced to keep the junction temperature less than 150°C.

The ON resistance of the output is fairly similar to that in the

Normal mode. No additional passive components are

required except on VDD.

GROUND DISCONNECT PROTECTION

In the event the 33580 ground is disconnected from load

ground, the device protects itself and safely turns OFF the

output regardless of the state of the output at the time of

disconnection. A 10K resistor needs to be added between the

wake pin and the rest of the circuitry in order to ensure that

the device turns off in case of ground disconnect and to

prevent this pin to exceed its maximum ratings.

Current limit resistors in the digital input lines protect the

digital supply against excessive current (1 kohm typical).

Table 7. Device Behavior in Case of Undervoltage

Quad High-Side

Switch

(VPWR Battery

Voltage) ∗∗

State

UV Enable

IN[0:3]=0

(Falling VPWR)

UV Enable

IN[0:3]=0

(Falling or

Rising VPWR)

UV Enable

IN_x***=1

(Falling VPWR)

UV Enable

IN_x***=1

(Rising VPWR)

UV Disable

IN[0:3]=0

(Falling or

Rising VPWR)

UV Disable

IN_x***=1

(Falling or

Rising VPWR)

VPWR > VPWRUV Output State OFF OFF ON OFF OFF ON

FS State 1 1 1 0 1 1

SPI Fault Register

UVF Bit

01 until next read 0 1 0 (falling)

1 until next read

(rising)

0 (falling)

1 until next read

(rising)

VPWRUV > VPWR

> UVPOR

Output State OFF OFF OFF OFF OFF ON

FS State 0 0 0 0 1 1

SPI Fault Register

UVF Bit

1 1 1 1 1 1

UVPOR > VPWR >

2.5 V ∗

Output State OFF OFF OFF OFF OFF ON

FS State 1 1 1 1 1 1

SPI Fault Register

UVF Bit

1 until next read 11 until next read 1 until next read 1 until next read 1 until next read

2.5 V > VPWR > 0V Output State OFF OFF OFF OFF OFF OFF

FS State 1 1 1 1 1 1

SPI Fault Register

UVF Bit

1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read

Comments UV fault is

not latched

UV fault is

not latched

UV fault

is latched

∗ = Typical value; not guaranteed.

∗∗ = While VDD remains within specified range.

∗∗∗ = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

33580

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SERIAL INPUT COMMUNICATION

SPI communication is accomplished using 16-bit

messages. A message is transmitted by the MCU starting

with the MSB D15 and ending with the LSB, D0 (Table 8).

Each incoming command message on the SI pin can be

interpreted using the following bit assignments: the MSB,

D15, is the watchdog bit. In some cases, output selection is

done with bits D12 : D11. The next three bits, D10 : D8, are

used to select the command register. The remaining five bits,

D4 : D0, are used to configure and control the outputs and

their protection features.

Multiple messages can be transmitted in succession to

accommodate those applications where daisy-chaining is

desirable, or to confirm transmitted data, as long as the

messages are all multiples of 16 bits. Any attempt made to

latch in a message that is not 16 bits will be ignored.

The 33580 has defined registers, which are used to

configure the device and to control the state of the outputs.

Table 9, page 22, summarizes the SI registers.

Table 8. SI Message Bit Assignment

Bit Sig SI Msg Bit Message Bit Description

MSB D15 Watchdog in: toggled to satisfy watchdog requirements.

D14 : D15 Not used.

D12 : D11 Register address bits used in some cases for output selection.

D10 : D8 Register address bits.

D7 : D5 Not used.

D4 : D1 Used to configure the inputs, outputs, and the device protection features and SO status content.

LSB D0 Used to configure the inputs, outputs, and the device protection features and SO status content.

Table 9. Serial Input Address and Configuration Bit Map

SI Register

SI Data

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

STATR_s WDIN 0 0 0 0 0 0 0 0 0 0 SOA4 SOA3 SOA2 SOA1 SOA0

OCR0 WDIN 0 0 0 0 0 0 1 0 0 0 0 IN3_SPI IN2_SPI IN1_SPI IN0_SPI

OCR1 WDIN 0 0 0 1 0 0 1 0 0 0 0 CSNS3 EN CSNS2 EN CSNS1 EN CSNS0 EN

SOCHLR_s WDIN 0 0 A1A00 1 0 0 0 0 0 SOCH_s SOCL2_s SOCL1_s SOCL0_s

CDTOLR_s WDIN 0 0 A1A00 1 1 0 0 0 0 OL_DIS_s OCL_DIS_s OCLT1_s OCLT0_s

DICR_s WDIN 0 0 A1A01 0 0 0 0 0 0 FAST_SR_s CSNS_high_s DIR_DIS_s A/O_s

UOVR WDIN 0 0 0 0 1 0 1 0 0 0 0 OT_latch-1 OT_latch_0 UV_DIS OV_DIS

WDR WDIN 0 0 0 1 1 0 1 0 0 0 0 OT_latch_3 OT_latch_2 WD1 WD0

NAR WDIN 0 0 0 0 1 1 0 0 0 0 0 No Action (Allow Toggling of D15- WDIN)

RESET 0 0 0 X X X X X 0 0 0 0 0 0 0 0

x = Don’t care.

s = Output selection with the bits A1A0 as defined in Table 10.

D15 is used to toggle watchdog event (WDIN).

Analog Integrated Circuit Device Data

Freescale Semiconductor 23

33580

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DEVICE REGISTER ADDRESSING

The following section describes the possible register

addresses and their impact on device operation.

ADDRESS 00000 — STATUS REGISTER (STATR_S)

The STATR register is used to read the device status and

the various configuration register contents without disrupting

the device operation or the register contents. The register bits

D[4:0] determine the content of the first sixteen bits of SO

data. In addition to the device status, this feature provides the

ability to read the content of the OCR0, OCR1, SOCHLR,

CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to

the section entitled Serial Output Communication (Device

Status Return Data) beginning on page 25.)

ADDRESS 00001— OUTPUT CONTROL REGISTER

(OCR0)

The OCR0 register allows the MCU to control the ON / OFF

state of four outputs through the SPI. Incoming message bit

D3 : D0 reflects the desired states of the four high-side

outputs (INx_SPI), respectively. A logic [1] enables the

corresponding output switch and a logic [0] turns it OFF.

ADDRESS 01001— OUTPUT CONTROL REGISTER

(OCR1)

Incoming message bits D3 : D0 reflect the desired output

that will be mirrored on the Current Sense (CSNS) pin. A

logic [1] on message bits D3 : D0 enables the CSNS pin for

outputs HS3 : HS0, respectively. In the event the current

sense is enabled for multiple outputs, the current will be

summed. In the event that bits D3 : D0 are all logic [0], the

output CSNS will be tri-stated. This is useful when several

CSNS pins of several devices share the same A /D converter.

ADDRESS A1A0010 — SELECT OVERCURRENT

HIGH AND LOW REGISTER (SOCHLR_S)

The SOCHLR_s register allows the MCU to configure the

output overcurrent low and high detection levels,

respectively. Each output “s” is independently selected for

configuration based on the state of the D12 : D11 bits

(Table 10).

Each output can be configured to different levels. In

addition to protecting the device, this slow blow fuse

emulation feature can be used to optimize the load

requirements matching system characteristics. Bits D2 : D0

set the overcurrent low detection level to one of eight possible

levels, as shown in Table 11, page 23. Bit D3 sets the

overcurrent high detection level to one of two levels, as

outlined in Table 12, page 23.

ADDRESS A1A0011 — CURRENT DETECTION TIME

AND OPEN LOAD REGISTER (CDTOLR)

The CDTOLR register is used by the MCU to determine

the amount of time the device will allow an overcurrent low

condition before an output latches OFF. Each output is

independently selected for configuration based on A1A0 ,

which are the state of the D12 : D11 bits (refer to Table 10,

page 23).

Table 10. Output Selection

A1 (D12) A0 (D11) HS_s

0 0 HS0

0 1 HS1

1 0 HS2

1 1 HS3

Table 11. Overcurrent Low Detection Levels

SOCL2_s*

(D2)

SOCL1_s*

(D1)

SOCL0_s*

(D0)

Overcurrent Low

Detection (Amperes)

HS0 to HS3

000 18.2

001 16.3

010 14.4

011 12.5

100 10.5

101 8.6

110 6.7

111 4.8

* “_s” refers to the output, which is selected through bits D12 : D11;

refer to Table 10, page 23.

Table 12. Overcurrent High Detection Levels

SOCH_s* (D3)

Overcurrent High Detection (Amperes)

HS0 to HS3

0100

170

* “_s” refers to the output, which is selected through bits D12 : D11;

refer to Table 10, page 23.

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

33580

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Bits D1 : D0 (OCLT1_s : OCLT0_s) allow the MCU to select

one of three overcurrent fault blanking times defined in

Table 13. Note that these time-outs apply only to the

overcurrent low detection levels. If the selected overcurrent

high level is reached, the device will latch off within 20 µs.

A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent

low detection feature. When disabled, there is no timeout for

the selected output and the overcurrent low detection feature

is disabled.

A logic [1] on bit D3 (OL_DIS_s) disables the open load

(OL) detection feature for the output corresponding to the

state of bits D12 : D11.

ADDRESS A1A0100 — DIRECT INPUT CONTROL

The DICR register is used by the MCU to enable, disable,

or configure the direct IN pin control of each output. Each

output is independently selected for configuration based on

the state bits D12 : D11 (refer to Table 10, page 23).

For the selected output, a logic [0] on bit D1 (DIR_DIS_s)

will enable the output for direct control. A logic [1] on bit D1

will disable the output from direct control.

While addressing this register, if the Input was enabled for

direct control, a logic [1] for the D0 (A/O_s) bit will result in a

Boolean AND of the IN pin with its corresponding IN_SPI

D[4:0] message bit when addressing OCR0. Similarly, a logic

[0] on the D0 pin results in a Boolean OR of the IN pin to the

corresponding message bits when addressing the OCR0.

This register is especially useful if several loads are required

to be independently PWM controlled. For example, the IN

pins of several devices can be configured to operate all of the

outputs with one PWM output from the MCU. If each output

is then configured to be Boolean ANDed to its respective IN

pin, each output can be individually turned OFF by SPI while

controlling all of the outputs, commanded on with the single

PWM output.

A logic [1] on bit D2 (CSNS_high_s) is used to select the

high ratio on the CSNS pin for the selected output. The

default value [0] is used to select the low ratio (Table 14).

A logic [1] on bit D3 (FAST_SR_s) is used to select the

high speed slew rate for the selected output, the default value

[0] corresponds to the low speed slew rate.

ADDRESS 00101 — UNDERVOLTAGE /

OVERVOLTAGE AND HS[0,1]

OVERTEMPERATURE REGISTER (UOVR)

The UOVR register disables the undervoltage (D1) and/or

overvoltage (D0) protection. When these two bits are [0], the

under- and overvoltage are active (default value).

The UOVR register allows the overtemperature detection

latching on the HS0 and HS1. To latch the overtemperature,

the bits (OT_latch_1 and OT_latch_0) must be set to [0]

which is the default value. To disable the latching, both bits

must be set to [1].

ADDRESS 01101 — WATCHDOG AND HS[2,3]

OVERTEMPERATURE REGISTER (WDR)

The WDR register is used by the MCU to configure the

Watchdog timeout. The Watchdog timeout is configured

using bits D1 and D0. When D1 and D0 bits are programmed

for the desired watchdog timeout period (Table 15), the

WDSPI bit should be toggled as well, ensuring the new

timeout period is programmed at the beginning of a new

count sequence.

The WDR register allows the overtemperature detection

latching on the HS2 and HS3. To latch the overtemperature,

the bits (OT_latch_3 and OT_latch_2) must be set to [0]

which is the default value. To disable the latching, both bits

must be set to [1].

Table 13. Overcurrent Low Detection Blanking Time

OCLT[1:0]_s*Timing

00 155 ms

01 Do not use

10 75 ms

11 150 µs

* “_s” refers to the output, which is selected through bits D12 : D11.

Table 14. Current Sense Ratio

CSNS_high_s* (D2)

Current Sense Ratio

HS0 to HS3

01/13000

11/38000

* “_s” refers to the output, which is selected through bits D12 : D11;

refer to Table 10, page 23.

Table 15. Watchdog Timeout

WD[1:0] (D1, D0) Timing (ms)

00 558

01 279

10 2250

11 1125

Analog Integrated Circuit Device Data

Freescale Semiconductor 25

33580

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

ADDRESS 00110 — NO ACTION REGISTER (NAR)

The NAR register can be used to no-operation fill SPI data

packets in a daisy-chain SPI configuration. This would allow

devices to be unaffected by commands being clocked over a

daisy-chained SPI configuration. By toggling the WD bit

(D15) the watchdog circuitry would continue to be reset while

no programming or data read back functions are being

requested from the device.

SERIAL OUTPUT COMMUNICATION (DEVICE

STATUS RETURN DATA)

When the CS pin is pulled low, the output register is

loaded. Meanwhile, the data is clocked out MSB- (OD15-)

first as the new message data is clocked into the SI pin. The

first sixteen bits of data clocking out of the SO, and following

a CS transition, is dependent upon the previously written SPI

word.

Any bits clocked out of the Serial Output (SO) pin after the

first 16 bits will be representative of the initial message bits

clocked into the SI pin since the CS pin first transitioned to a

logic [0]. This feature is useful for daisy-chaining devices as

well as message verification.

A valid message length is determined following a CS

transition of [0] to [1]. If there is a valid message length, the

data is latched into the appropriate registers. A valid

message length is a multiple of 16 bits. At this time, the SO

pin is tri-stated and the fault status register is now able to

accept new fault status information.

SO data will represent information ranging from fault

status to register contents, user selected by writing to the

STATR bits OD4, OD3, OD2, OD1, and OD0. The value of

the previous bits SOA4 and SOA3 will determine which

output the SO information applies to for the registers which

are output specific; viz., Fault, SOCHLR, CDTOLR, and

DICR registers.

Note that the SO data will continue to reflect the

information for each output (depending on the previous OD4,

OD3 state) that was selected during the most recent STATR

write until changed with an updated STATR write.

The output status register correctly reflects the status of

the STATR-selected register data at the time that the CS is

pulled to a logic [0] during SPI communication, and/or for the

period of time since the last valid SPI communication, with

the following exceptions:

• The previous SPI communication was determined to be

invalid. In this case, the status will be reported as

though the invalid SPI communication never occurred.

• Battery transients below 6.0 V resulting in an under-

voltage shutdown of the outputs may result in incorrect

data loaded into the status register. The SO data

transmitted to the MCU during the first SPI

communication following an undervoltage VPWR

condition should be ignored.

• The RST pin transition from a logic [0] to [1] while the

WAKE pin is at logic [0] may result in incorrect data

loaded into the Status register. The SO data transmitted

to the MCU during the first SPI communication following

this condition should be ignored.

SERIAL OUTPUT BIT ASSIGNMENT

The 16 bits of serial output data depend on the previous

serial input message, as explained in the following

paragraphs. Table 16, page 26, summarizes SO returned

data for bits OD15 : OD0.

• Bit OD15 is the MSB; it reflects the state of the

Watchdog bit from the previously clocked-in message.

• Bit OD14 remains logic [0] except when an

undervoltage condition occurred.

• Bit OD13 remains logic [0] except when an overvoltage

condition occurred.

•Bits OD12 : OD8 reflect the state of the bits

SOA4 : SOA0 from the previously clocked in message.

• Bits OD7 : OD4 give the fault status flag of the outputs

HS3 : HS0, respectively.

• The contents of bits OD3 : OD0 depend on bits D4 : D0

from the most recent STATR command SOA4 : SOA0

as explained in the paragraphs following Table 16.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

33580

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000

Bits OD3 : OD0 reflect the current state of the Fault register

(FLTR) corresponding to the output previously selected with

the bits A1A0 (Table 17).

Note The FS pin reports all faults. For latched faults, this

pin is reset by a new Switch OFF command (via SPI or direct

input IN).

PREVIOUS ADDRESS SOA4 : SOA0 = 00001

Data in bits OD3 : OD0 contains IN3_SPI : IN0_SPI

programmed bits for outputs HS3 : HS0, respectively.

PREVIOUS ADDRESS SOA4 : SOA0 = 01001

Data in bits OD3 : OD0 contains the programmed

CSNS3 EN : CSNS0 EN bits for outputs HS3 : HS0,

respectively.

PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010

Data returned in bits OD3 : OD0 are programmed current

values for the overcurrent high detection level (refer to

Table 12, page 23) and the overcurrent low detection level

(refer to Table 11, page 23), corresponding to the output

previously selected with A1A0.

PREVIOUS ADDRESS SOA4 : SOA0= A1A0011

The returned data contains the programmed values in the

CDTOLR register for the output selected with A1A0.

PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100

The returned data contains the programmed values in the

DICR register for the output selected with A1A0.

PREVIOUS ADDRESS SOA4 : SOA0 = 00101

The returned data contains the programmed values in the

UOVR register.

PREVIOUS ADDRESS SOA4 : SOA0 = 01101

The returned data contains the programmed values in the

WDR register. Bit OD2 (WDTO) reflects the status of the

watchdog circuitry. If WDTO bit is logic [1], the watchdog has

timed out and the device is in Fail-Safe mode. IF WDTO is a

logic [0], the device is in Normal mode (assuming the device

Table 16. Serial Output Bit Map Description

Previous STATR SO Returned Data

10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

STATRs A1A0000WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OTF_s OCHF_s OCLF_s OLF_s

OCR0 00001WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 IN3_SPI IN2_SPI IN1_SPI IN0_SPI

OCR1 01001WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 CSNS3 EN CSNS2 EN CSNS1 EN CSNS0 EN

SOCHL

R_s A1A0010WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 SOCH_s SOCL2_s SOCL1_s SOCL0_s

CDTOL

R_s A1A0011WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OL_DIS_s OCL_DIS_s OCLT1_s OCLT0_s

DICR_s A1A0100WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 Fast_SR_s CSNS_high_s DIR_DIS_s A/O_s

UOVR 00101WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OT_latch_1 OT_latch_0 UV_DIS OV_DIS

WDR 01101WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 0WDTO WD1 WD0

PINR0 00110WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 HS2_failsafe HS0_failsafe WD_en WAKE

PINR1 01110WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 IN3 IN2 IN1 IN0

PINR2 01111WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OT_latch_3 OT_latch_2 X X

Reset N/A N/A N/A N/A N/A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

s = Output selection with the bits A1A0 as defined in Table 10, page 23.

Table 17. Output-Specific Fault Register

OD3 OD2 OD1 OD0

OTF_s OCHF_s OCLF_s OLF_s

s = Selection of the output.

Analog Integrated Circuit Device Data

Freescale Semiconductor 27

33580

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

is powered and not in the Sleep mode), with the watchdog

either enabled or disabled.

PREVIOUS ADDRESS SOA4 : SOA0 = 00110

The returned data OD3 and OD2 contain the state of the

outputs HS2 and HS0, respectively, in case of Fail-Safe

state. This information is stated with the external resistance

placed at the FSI pin. OD1 indicates if the watchdog is

enabled or not. OD0 returns the state of the WAKE pin.

PREVIOUS ADDRESS SOA4 : SOA0 = 01110

The returned data OD3 : OD0 reflects the state of the direct

pins IN3 : IN0, respectively.

PREVIOUS ADDRESS SOA4 : SOA0 = 01111

The returned data OD3 -OD2 reports the overtemperature

bits configuration of the outputs [3, 2] set through the WDR

SPI register.

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

33580

TYPICAL APPLICATIONS

INTRODUCTION

TYPICAL APPLICATIONS

INTRODUCTION

The 33580 can be configured in several applications. The figure below shows the 33580 in a typical lighting application.

33580

I/O

PWR

GND

Microcontroller

Voltage regulator

PWR

100nF

HS2

HS0

HS1

HS3

VPWR

VDD

WAKE

IN0

IN2

IN3

SCLK

TEMP

FSI

RST

IN1

10µF

100nF

I/O

SCLK

A/D

10k 10k

10 k

1k R1

10 k

LOAD 0

LOAD 1

LOAD 2

LOAD 3

CSNS

A/D

PWR

Automotive lamps do not tolerate high voltages very well. Tests of a few lamps indicate that failures can occur

when 18V is applied for a few seconds. Consequently, PWM switching reduces the effective RMS voltage in

order to drive bulbs safety.

For example, to maintain the power dissipation associated with a 13V battery at 100% duty cycle, the duty

cycle would be adjusted to (13/18)², or 52%, when the battery is at 18V.

The loads must be chosen in order to guarantee the device normal operating condition for junction tempera-

ture from -40 to 150 °C. In case of permanent short-circuit conditions, the duration and number of activation

cycles must be limited with a dedicated MCU fault management using the fault reporting through the SPI.

55W

Analog Integrated Circuit Device Data

Freescale Semiconductor 29

33580

TYPICAL APPLICATIONS

STANDALONE MODE

This section consists of evaluating the MC33580

standalone capability.

CONFIGURATION WITHOUT MCU

The standalone mode is intended for customers who

desire to plug the device and then immediately “play” with it,

without having to connect it to a microcontroller. It also

provides an easy way to evaluate the main electrical features.

Without the Microcontroller to select programmable

parameters and get full diagnosis via the SPI, the MC33580

runs with all parameters set to default.

The input SPI pin pins and VDD must be connected to

ground. Fail safe mode and watchdog timeout must be

disabled by connecting the FSI to GND.

All protection functions are available without SPI

communication. Nevertheless, any configuration is possible

without an MCU to communicate by SPI. Some functions still

enable, but diagnosis is reduced. Available functions and

default parameters are detailed next.

FUNCTIONING WITHOUT MCU

Without an MCU, SPI communication is not possible. Fail

safe mode and watchdog timeout are not useful functions

without an MCU, but still enable. Wake/Sleep mode is used

to minimize current consumption during sleep mode. IN pins

control the corresponding outputs and FS output is active (at

0 V) when a default occurs.

Table 18 illustrates the available functions without SPI and

default parameters.

Table 19 illustrates default parameters after resetting or

applying supply voltage to the MC33580. Levels and timings

are typical values.

Table 18. Available Functions

Function With SPI Without SPI

Wake/Sleep mode Available Available

Output ON/OFF control Via SPI or IN pin Only with IN pin

Over temperature protection Available, can be unlatched Available

Over voltage protection Available, can be disabled Available, always enable

Under voltage protection Available, can be disabled Available, always enable

Over current protection Available, configurable (with 8 low levels and

2 high levels), can be disabled

Available, always enable with default values

Open load, battery disconnect, reverse

battery, ground disconnect protections

Available Available

Fault diagnosis Full diagnosis with report by SPI and fault

status pin (/FS)

Limited fault diagnosis with Fault status pin

only

Current sense Available, 2 configurable ratios Not available

Watchdog timeout Available, 4 configurable timings Available, default value

Configurable slew rate 2 slew rate modes Default slew rate mode

Analog temperature feedback Available Available

Table 19. Default SPI-Configurable Parameters

Configulable Parameter Default Typical Value

Over voltage protection Enable

Under voltage protection Enable

Over current protection Enable

Over current low level OCLO0

Over current high level OCHI0

Over current detect blanking time tOCLO0

Current sense Disable

Watchdog time timeout TWDTO0

Slew rate mode Slow mode

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

33580

TYPICAL APPLICATIONS

STANDALONE MODE

DIAGNOSIS WITHOUT MCU

When any fault appears (over current, open load…), a full

diagnosis can be reported via the SPI. Without an MCU, the

fault status pin allows reduced diagnosis, as illustrated in

Table 20.

We can note that it is not possible to distinguish over

temperature, over current, under voltage, and over voltage.

Nevertheless, Open load and short circuit to VPWR fault can

be singled out. All protections are reported to Fault status pin

(FS), Open load and short circuit to VPWR are reported only if

the Output is OFF. If the fault is latched, the output must be

turned OFF then ON to disable the fault.

CONCLUSION

Although the MC33580 is not fully functional without a

microcontroller to control and program it, standalone

functioning is safe because all protections are available.

Diagnosis is limited, but the fault status pin will report any

malfunction.

This is a good way to evaluate the main electrical

MC33580 features. Some simplified applications can also

use the MC33580 switch without an MCU to drive a high

power load with full protection.

Table 20. Diagnosis without SPI

IN[x] Level HS[x] Level FS Level Latched

Normal operation HHHN/A

L L H

Over temperature LLLYES

H L L

Under voltage LLLYES

H L L

Over voltage L L H NO

H L L

Over current L L H YES

H L L

Short circuit to VPWR L H L NO

HHH

Open load L Z L NO

HHH

H : High Level, L : Low Level, Z : High impedance, potential depends on the external circuit.

Analog Integrated Circuit Device Data

Freescale Semiconductor 31

33580

PACKAGING

SOLDERING INFORMATION

PACKAGING

SOLDERING INFORMATION

The 33580 is not designed for immersion soldering. The maximum peak temperature during the soldering process should not

exceed 245°C. Terminal soldering limit is for 10 seconds maximum duration. Exceeding these limits may cause malfunction or

permanent damage to the device.

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.comand perform a keyword search using the 98ART10510D listed below.

PNA SUFFIX (Pb-FREE)

24-PIN PQFN

NON-LEADED PACKAGE

98ART10511D

ISSUE 0

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

33580

PACKAGING

PACKAGE DIMENSIONS

Analog Integrated Circuit Device Data

Freescale Semiconductor 33

33580

PACKAGING

PACKAGE DIMENSIONS

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

33580

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

Introduction

This thermal addendum is provided as a supplement to the MC33580 technical

datasheet. The addendum provides thermal performance information that may be

critical in the design and development of system applications. All electrical,

application, and packaging information is provided in the datasheet.

Packaging and Thermal Considerations

This package is a dual die package. There are two heat sources in the package

independently heating with P1 and P2. This results in two junction temperatures,

TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.

For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference

temperature while only heat source 1 is heating with P1.

For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the

reference temperature while heat source 2 is heating with P2. This applies to

RθJ21 and RθJ22, respectively.

The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.

This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated

values were obtained by measurement and simulation according to the standards listed below.

HIGH-SIDE SWITCH

33580PNA

PNA SUFFIX

98ART10510D

24-PIN PQFN (12 x 12)

Note For package dimensions, refer to the

33580 device datasheet.

TJ1

TJ2 =

RθJA11

RθJA21

RθJA12

RθJA22

.P1

Standards

Figure 10. Surface mount for power PQFN

with exposed pads

Table 21. Thermal Performance Comparison

Thermal

Resistance

1 = Power Chip, 2 = Logic Chip [°C/W]

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

RθJAmn (1), (2) 20 16 39

RθJBmn (2), (3) 62.026

RθJAmn (1), (4) 53 40 73

RθJCmn (5) <0.5 0.0 1.0

Notes:

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

2. 2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

Note: Recommended via diameter is 0.5 mm. PTH (plated throug

hole) via must be plugged / filled with epoxy or solder mask in orde

to minimize void formation and to avoid any solder wicking into th

via.

1.0

0.2

Analog Integrated Circuit Device Data

Freescale Semiconductor 35

33580

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

Figure 12. Thermal Test Board

Device on Thermal Test Board

RθJA is the thermal resistance between die junction and

ambient air.

This device is a dual die package. Index m indicates the

die that is heated. Index n refers to the number of the die

where the junction temperature is sensed.

A =

300sqmm

76.2 mm

114.3 mm

A =

300sqmm

A =

300sqmm

76.2 mm

114.3 mm

A =

300sqmm

MC33580 Pin Connections

24-Pin PQFN (12 x 12)

0.9 mm Pitch

12.0 mm x 12.0 mm Body

12 1098 7654 32111

19 20 21

GND

HS3

HS1 NC HS0

HS2

GND

FSI

VDD

SCLK

RST

WAKE

IN3

IN2

TEMP

IN1

IN0

CSNS

GND

VPWR

Transparent Top View

Material: Single layer printed circuit board

FR4, 1.6 mm thickness

Cu traces, 0.07 mm thickness

Outline: 80 mm x 100 mm board area,

including edge connector for thermal

testing

Area A: Cu heat-spreading areas on board

surface

Ambient Conditions: Natural convection, still air

Table 22. Thermal Resistance Performance

Thermal

Resistance

Area A

(mm2)

1 = Power Chip, 2 = Logic Chip (°C/W)

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

RθJAmn

051 38 60

300 43 32 55

600 41 30 55

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

33580

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

Figure 13. Stead State Thermal Resistance

Figure 14. Transient Thermal Resistance

25.000

30.000

35.000

40.000

45.000

50.000

55.000

60.000

65.000

0 100 200 300 400 500 600

RJA 11 RJA 12=RJA 21 RJA 22

RθJA11 RθJA11= RθJA21 RθJA22

RθJA11 RθJA22

RθJA11=RθJA11

0.1

100

1.00E-06 1.00E-04 1.00E-02 1.00E+00 1.00E+02 1.00E+04

RJA11 RJA12=RJA21 RJA22

Analog Integrated Circuit Device Data

Freescale Semiconductor 37

33580

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

2.0 02/2006 • Implemented Revision History page

• Converted to Freescale format

• Added Thermal Addendum

3.0 05/2006 • Added B to the part number ordering information.

• Minor drawing correction to Figure 1

• Number changes to Selectable Output Current and Programmable Watchdog in

Figure 2

• Changed Temperature Feedback Min, Typ, & Max in the StatiC Electical Characteristics

• Changed max limit on Overcurrent Low Detection Blanking Time for OCLT[1:0] : 11 in

the Dynamic Electrical characteristics

• Minor corrections in Figure 7, Input Timing Switching Characteristics

• Added the sentence “It is recommended to disable the open load detection circuitry in

case of permanent disconnected load.“ to Open Load Fault (Non-Latching)

• Changed resistor value for the SPI inputs from 1 k to 10 k in the Typical Applications

• Updated the drawings and version on Package Dimensions

• Made correction to the 33580 Simplified Internal Block Diagram on the HSO MOSFET.

4.0 6/2006 • Changed Note 11 from Guaranteed by design to Guaranteed by process monitoring

• Modified Output Turn ON Delay Times on page 11

5.0 9/2006 • Adjusted numbers on See Output Rising Fast Slew Rate A (DICR D3 = 1) (19) on page

10 and See Output Falling Slow Slew Rate A (DICR D3 = 0) (19) on page 10

• Made additions and corrections to See Typical Applications on page 28

• Made changes to Thermal Addendum (rev 3.0) relating to Figure 12, Table 22, Thermal

Resistance Performance, Figure 13, and Figure 14

6.0 4/2007 • Changed the package type from 98ARL10596D to 98ART10510D

• Removed PC33580BPNA/R2, and added MC33580BAPNA/R2

MC33580

Rev. 6.0

4/2007

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