Freescale Semiconductor Advance Information Document Number: MC33580 Rev. 6.0, 4/2007 Quad High-Side Switch (Quad 15 m) 33580 The 33580 is one in a family of devices designed for low-voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (four 15 m) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for pulse-width modulation (PWM) control if desired. The 33580 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33580 is packaged in a power-enhanced 12 x 12 nonleaded Power QFN package with exposed tabs. HIGH-SIDE SWITCH Features * Quad 15 m High-Side Switches (at 25C) * Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 A * SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output OFF Open Load Detection, Output ON / OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting * SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status * Analog Current Feedback with Selectable Ratio * Analog Board Temperature Feedback * Enhanced -16 V Reverse Polarity VPWR Protection * Pb-Free Packaging Designated by Suffix Code PNA VDD VDD VPWR VDD PNA SUFFIX (Pb-FREE) 98ART10510D 24-PIN PQFN (12 x 12) ORDERING INFORMATION Device Temperature Range (TA) Package MC33580BAPNA/R2 - 40C to 125C 24 PQFN VPWR 33580 SO SCLK CS SI I/O MCU I/O I/O I/O I/O I/O A/D A/D GND VDD WAKE SI SCLK CS SO RST FS IN0 IN1 IN2 IN3 CSNS TEMP FSI VPWR HS0 GND LOAD 0 HS1 LOAD 1 HS2 LOAD 2 HS3 LOAD 3 GND Figure 1. 33580 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. BLOCK DIAGRAM BLOCK DIAGRAM VDD VPWR VIC Internal Regulator IUP CS SCLK Selectable Slew Rate Gate Drive VIC SPI 3.0 MHz IDWN Over/Undervoltage Protection Selectable Overcurrent High Detection HS[0:3]: 70 A or 100 A SO SI RST WAKE FS IN0 Logic IN1 IN2 Selectable Overcurrent Low Detection Blanking Time 0.15 ms-155 ms HS0 Selectable Overcurrent Low Detection HS[0:3]: 4.8 A-18.2 A Open Load Detection IN3 Overtemperature Detection RDWN HS0 IDWN HS1 Programmable Watchdog 279 ms-2250 ms HS1 VIC HS2 HS2 FSI HS3 HS3 TEMP Temperature Feedback Selectable Output Current Recopy (Analog MUX) HS[0:3]: 1/13000 or 1/38000 GND CSNS Figure 2. 33580 Simplified Internal Block Diagram 33580 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS RST WAKE FS IN3 IN2 TEMP IN1 IN0 CSNS 9 8 7 6 5 4 3 2 1 SI SO 16 GND 17 HS3 18 SCLK 13 12 11 10 VDD CS Transparent Top View of Package 14 GND 24 FSI 23 GND 22 HS2 15 VPWR 19 20 21 HS1 NC HS0 Figure 3. 33580 Pin Connections Table 1. 33580 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 16. Pin Number Pin Name Pin Function 1 CSNS Output Output Current Monitoring 2 3 5 6 IN0 IN1 IN2 IN3 Input Serial Inputs The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 highside output pins, respectively. 4 TEMP Output Temperature Feedback This pin reports an analog value proportional to the temperature of the GND flag (pins 14, 17, 23). It is used by the MCU to monitor board temperature. 7 FS Output Fault Status (Active Low) This pin is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. 8 WAKE Input Wake This input pin controls the device mode and watchdog timeout feature if enabled. 9 RST Input Reset This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. 10 CS Input Chip Select (Active Low) This input pin is connected to a chip select output of a master microcontroller (MCU). 11 SCLK Input Serial Clock This input pin is connected to the MCU providing the required bit shift clock for SPI communication. 12 SI Input Serial Input This pin is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy-chain of devices. Formal Name Definition The Current Sense pin sources a current proportional to the designated HS0 : HS3 output. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33580 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 16. Pin Number Pin Name Pin Function 13 VDD 14, 17, 23 Formal Name Definition Power Digital Drain Voltage (Power) This pin is an external voltage input pin used to supply power to the SPI circuit. GND Ground Ground 15 VPWR Power Positive Power Supply This pin connects to the positive power supply and is the source of operational power for the device. 16 SO Output Serial Output This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy-chain of devices. 18 19 21 22 HS3 HS1 HS0 HS2 Output High-Side Outputs 20 NC N/A No Connect 24 FSI Input Fail-Safe Input These pins are the ground for the logic and analog circuitry of the device. Protected 15 m high-side power output pins to the load. This pin may not be connected. The value of the resistance connected between this pin and ground determines the state of the outputs after a Watchdog timeout occurs. 33580 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Operating Voltage Range V VPWR(SS) Steady-State -16 to 41 VDD Supply Voltage VDD Input / Output Voltage (1) See note SO Output Voltage (1) (1) -0.3 to 5.5 V - 0.3 to 7.0 V VSO - 0.3 to VDD + 0.3 V WAKE Input Clamp Current ICL(WAKE) 2.5 mA CSNS Input Clamp Current ICL(CSNS) 10 mA HS [0:3] Voltage V VHS Positive 41 Negative -16 Output Current (2) IHS[0:3] 22.8 A ECL [0:3] 0.2 J Human Body Model (HBM) VESD1 2000 Charge Device Model (CDM) VESD2 Output Clamp Energy ESD Voltage (3) (4) V Corner Pins (1, 13, 19, 21) 750 All Other Pins (2-12, 14-18, 20, 22-24) 500 THERMAL RATINGS C Operating Temperature Ambient TA - 40 to 125 Junction TJ - 40 to 150 TSTG - 55 to 150 RJC <1.0 RJA 30 TSOLDER 245 Storage Temperature Thermal Resistance (5) C/ W Junction to Case Junction to Ambient Peak Pin Reflow Temperature During Solder Mounting C (6) C Notes 1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, TEMP, SI, SO, SCLK, CS, or FS pins may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 2 mH, RL = 0 , VPWR = 14 V, TJ = 150C initial). 4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 5. 6. Device mounted on a 2s2p test board per JEDEC JESD51-2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTICAL CHARACTERISTICS STATIC ELECTICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT (VPWR, VDD) Battery Supply Voltage Range V VPWR Fully Operational VPWR Operating Supply Current 6.0 - 27 - - 20 mA IPWR(ON) Outputs ON, HS[0 : 3] open VPWR Supply Current IPWR(SBY) Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR = 14 V, RST < 0.5 V, WAKE < 0.5 V) mA - - 5.0 A IPWR(SLEEP) TA = 25C - 1.0 10 TA = 85C - - 50 4.5 5.0 5.5 VDD Supply Voltage VDD(ON) VDD Supply Current IDD(ON) V mA No SPI Communication - - 1.0 3.0 MHz SPI Communication(8) - - 5.0 IDDSLEEP - - 5.0 A VOV 28 32 36 V VOVHYS 0.2 0.8 1.5 V VUV 4.75 5.25 5.75 V VUVHYS - 0.25 - V VUVPOR - - 4.75 V VDD Sleep State Current Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage Shutdown Threshold Undervoltage Hysteresis (9) Undervoltage Power-ON Reset (7) Notes 7. The undervoltage fault condition is reported to SPI register as long as the external VDD supply is within specification and the VRWR voltage level does not go below the undervoltage Power-ON Reset threshold. 8. Not guaranteed in production. 9. This applies when the undervoltage fault is not latched (IN[0:3] = 0). 33580 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max VPWR = 6.0 V - - 23 VPWR = 10 V - - 15 VPWR = 13 V - - 15 Unit OUTPUTS (HS0, HS1, HS2, HS3) Output Drain-to-Source ON Resistance (IHS = 10 A, TA = 25C) Output Drain-to-Source ON Resistance (IHS = 10 A, TA = 150C) RDS(ON) m RDS(ON) m VPWR = 6.0 V - - 38 VPWR = 10 V - - 25.5 VPWR = 13 V - - 25.5 - - 30 Output Source-to-Drain ON Resistance (10) IHS = 5.0 A, TA = 25C, VPWR = -12 V m RSD(ON) Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) A SOCH = 0 (11) IOCH0 80 100 120 SOCH = 1 IOCH1 56 70 84 14.6 18.2 22.8 Overcurrent Low Detection Levels (9.0 V < VPWR < 16 V) A SOCL[2:0] : 000 IOCL0 SOCL[2:0] : 001 IOCL1 13 16.3 20.4 IOCL2 11.5 14.4 18 IOCL3 10 12.5 15.7 SOCL[2:0] : 101 IOCL4 8.4 10.5 13.2 SOCL[2:0] : 110 IOCL5 6.9 8.6 10.8 SOCL[2:0] : 111 IOCL6 5.4 6.7 8.4 3.8 4.8 6.0 SOCL[2:0] : 010 SOCL[2:0] : 011 SOCL[2:0] : 100 IOCL7 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) - DICR D2 = 0 CSR0 - 1/13000 - DICR D2 = 1 CSR1 - 1/38000 - Current Sense Ratio (CSR0) Accuracy CSR0_ACC % Output Current 2.0 to 10 A Current Sense Ratio (CSR1) Accuracy - 15 - 15 CSR1_ACC % Output Current 10 A to 20 A Current Sense Clamp Voltage - 19 4.5 6.0 7.0 30 - 100 V VCL(CSNS) CSNS Open; IHS[0:3] = 22 A Open Load Detection Current (12) - 19 IOLDC A Notes 10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 11. 12. Guaranteed by process monitoring. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit 2.0 3.0 4.0 - 20 - -16 TSD 155 175 190 C TSD(HYS) 5.0 - 20 C VIH 0.7 VDD - - V VIL - - 0.2 VDD V VIN(HYS) 100 850 1200 mV Input Logic Pulldown Current (SCLK, SI, IN[0:3], VIN>0.2 VDD) IDWN 5.0 - 20 A RST Input Voltage Range VRST 4.5 5.0 5.5 V CSO - - 20 pF RDWN 100 200 400 k CIN - 4.0 12 pF 7.0 - 14 - 2.0 - - 0.3 0.8 VDD - - OUTPUTS (HS0, HS1, HS2, HS3) (continued) Output Fault Detection Threshold Output Negative Clamp Voltage V VCL 0.5 A < IHS[0:3] < 2.0 A, Output OFF Overtemperature Shutdown (13) Overtemperature Shutdown Hysteresis V VOFD(THRES) Output Programmed OFF (13) CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI) Input Logic High Voltage (14) Input Logic Low Voltage (14) Input Logic Voltage Hysteresis SO, FS Tri-State Capacitance (15) (15) Input Logic Pulldown Resistor (RST) and WAKE Input Capacitance (15) Wake Input Clamp Voltage (16) VCL(WAKE) ICL(WAKE) < 2.5 mA Wake Input Forward Voltage VF(WAKE) ICL(WAKE) = -2.5 mA SO High-State Output Voltage Vin < 0.7 VDD V - 0.2 0.4 - 5.0 0 5.0 5.0 - 20 A ISO(LEAK) CS>=0.7VDD, 0<VSO<VDD Input Logic Pullup Current (CS) (17) V VSOL IOL = -1.6 mA SO Tri-State Leakage Current V VSOH IOH = 1.0 mA FS, SO Low-State Output Voltage V A IUP Notes 13. Guaranteed by process monitoring. Not production tested. 14. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 15. 16. 17. Ads Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0 V. Pullup current is with CS OPEN. CS has an active internal pullup to VDD. 33580 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI) (continued) FSI Input pin External Pulldown Resistance (18) RFS FSI Disabled, HS[0:3] state according to direct inputs state and SPI INx_SPI bits and A/O_s bit FSI Enabled, HS[0:3] OFF FSI Enabled, HS0 ON, HS[1:3] OFF FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF Temperature Feedback TA = 25C Temperature Feedback Derating kohms - 0 1.0 6.0 6.5 7.0 15 17 19 40 Infinite - 3.8 3.9 4.0 -7.2 -7.5 -7.8 TFeed DTFeed V mV/C Notes 18. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be within the desired (specified) range. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max 0.2 0.6 1.5 Unit POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) Output Rising Slow Slew Rate A (DICR D3 = 0) (19) SRRA_SLOW 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (20) SRRB_SLOW 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (19) 0.2 4.0 0.025 0.3 1.1 0.2 0.6 1.5 0.025 0.1 0.225 1.2 3.5 5.0 0.025 0.7 1.1 - 300 - V/s V/s V/s V/s V/s SRFB_FAST 9.0 V < VPWR < 16 V Direct Input Switching Frequency (DICR D3 = 0) 0.06 SRFA_FAST 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (20) 0.225 SRFB_SLOW 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (19) 0.1 SRFA_SLOW 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (20) 0.025 SRRB_FAST 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (19) V/s SRRA_FAST 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate B (DICR D3 = 1) (20) V/s fPWM V/s Hz Notes 19. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V (see Figure 4, page 13). These parameters are guaranteed by process monitoring. 20. Rise and Fall Slew Rates B measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V (see Figure 4). These parameters are guaranteed by process monitoring. 33580 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max 2.0 10 130 1.0 3.0 60 Unit POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued) Output Turn-ON Delay Time in Slow Slew Rate (21) Output Turn-ON Delay Time in Fast Slew Rate (21) t DLY_SLOW(OFF) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (22) s t DLY_FAST(ON) DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode (22) s t DLY_SLOW(ON) DICR = 0 s 20 100 400 5.0 20 100 108 155 202 - - - t DLY_FAST(OFF) DICR = 1 s Overcurrent Low Detection Blanking Time OCLT[1:0] : 00 OCLT[1:0] : 01 (23) OCLT[1:0] : 10 OCLT[1:0] : 11 Overcurrent High Detection Blanking Time CS to CSNS Valid Time Watchdog Timeout (24) ms t OCL0 t OCL1 t OCL2 t OCL3 55 75 95 0.08 0.15 0.3 tOCH 1.0 5 20 s t CNSVAL - - 10 s t WDTO0 t WDTO1 t WDTO2 t WDTO3 446 558 725 223 279 363 1800 2250 2925 900 1125 1463 (25) WD[1:0] : 00 WD[1:0] : 01 WD[1:0] : 10 WD[1:0] : 11 ms Notes 21. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output ON to VHS[0 : 3] = 0.5 V with RL = 5.0 resistive load. 22. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output OFF to VHS[0 : 3] = VPWR 0.5 V with RL = 5.0 resistive load. 23. 24. 25. This logical bit is not defined. Do not use. Time necessary for the CSNS to be with 5% of the targeted value. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured watchdog time-outs. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit f SPI - - 3.0 MHz t WRST - 50 350 ns t CS - - 300 ns t ENBL - - 5.0 s t LEAD - 50 167 ns t WSCLKh - - 167 ns t WSCLKl - - 167 ns SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation Required Low State Duration for RST (26) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (27) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Required High State Duration of SCLK (Required Setup Time) (27) Required Low State Duration of SCLK (Required Setup Time) (27) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (27) (27) t LAG - 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (28) t SI (SU) - 25 83 ns Falling Edge of SCLK to SI (Required Setup Time) (28) t SI (HOLD) - 25 83 ns - 25 50 - 25 50 t RSI - - 50 ns SO Rise Time t RSO CL = 200 pF SO Fall Time t FSO CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (28) SI, CS, SCLK, Incoming Signal Fall Time ns (28) ns t FSI - - 50 ns Time from Falling Edge of CS to SO Low Impedance (29) t SO(EN) - - 145 ns Time from Rising Edge of CS to SO High Impedance (30) t SO(DIS) - 65 145 ns - 65 105 Time from Rising Edge of SCLK to SO Data Valid (31) t VALID 0.2 VDD SO 0.8 VDD, CL = 200 pF Notes 26. 27. 28. 29. 30. 31. ns RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33580 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k on pullup on CS. Time required for output status data to be terminated at SO. 1.0 k on pullup on CS. Time required to obtain valid data out from SO following the rise of SCLK. 33580 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS VPWR V PWR VPWR - 0.5V VPWR -0.5 V VPWR - 3V -3.5 V VPWR SRFB_SLOW & SRFB_FAST SRRB_SLOW & SRRB SRFA_SLOW & SRFA_FAST SRRA_SLOW & SRRA_FAST t 0.5V 0.5 V t DLY_SLOW(OFF) & t DLY_FAST(OFF) tDLY(ON) Figure 4. Output Slew Rate and Time Delays IOCHx Load Current t OCH IOCLx t OCLx Time Figure 5. Overcurrent Shutdown 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS IOCH0 IOCH1 IOCL0 IOCL1 IOCL2 Load Current IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 Time t OCH t OCL3 t OCL2 t OCL0 Figure 6. Overcurrent Low and High Detection VIH VIH RSTB RST 0.2 VDD 0.2 VDD tWRST TwRSTB tENBL VIL VIL tTCSB CS TENBL VIH VIH 0.7 VDD 0.7VDD CS CSB 0.2 VDD 0.7VDD tTlead LEAD VIL VIL t RSI t WSCLKh TwSCLKh TrSI t LAG Tlag 0.70.7VDD VDD SCLK SCLK VIH VIH 0.2 VDD 0.2VDD t TSIsu SI(SU) VIL VIL t WSCLKl TwSCLKl t SI(HOLD) TSI(hold) SI SI Don't Care 0.7 0.7 V VDD DD 0.2VDD 0.2 VDD Valid tTfSI FSI Don't Care Valid Don't Care VIH VIH VIH VIL Figure 7. Input Timing Switching Characteristics 33580 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS tFSI tRSI TrSI TfSI VOH VOH 3.5 V 3.5V 50% SCLK SCLK 1.0VV 1.0 VOL VOL t SO(EN) TdlyLH SO SO 0.7 V VDD DD 0.20.2 VDD VDD Low-to-High Low to High TrSO t RSO VOH VOH VOL VOL VALID tTVALID SO TfSO t FSO SO VOH VOH VDD VDD High to Low 0.70.7 High-to-Low 0.2VDD 0.2 VDD TdlyHL VOL VOL t SO(DIS) Figure 8. SCLK Waveform and Valid SO Data Delay Time 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33580 is one in a family of devices designed for lowvoltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (15 m) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33580 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33580 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) CHIP SELECT (CS) The Current Sense pin sources a current proportional to the designated HS0 : HS3 output. That current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The output to be monitored is selected via the SPI. This pin can be tri-stated through SPI. The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33580 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pullup, IUP. SERIAL INPUTS (IN0, IN1, IN2, IN3) The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 high-side output pins, respectively. An SPI register determines if each input is activated or if the input logic state is OR ed or AND ed with the SPI instruction. These pins are to be driven with 5.0 V CMOS levels, and they have an active internal pulldown current source. SERIAL CLOCK (SCLK) This pin is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. The SCLK pin clocks the internal shift registers of the 33580 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pulldown. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance) (see Figure 9, page 18). WAKE (WAKE) SERIAL INPUT (SI) This input pin controls the device mode and watchdog timeout feature if enabled. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown. This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. The internal registers of the 33580 are configured and controlled using a 5-bit addressing scheme described in Table 8, page 22. Register addressing and configuration are described in Table 9, page 22. The SI input has an active internal pulldown, IDWN. TEMPERATURE FEEDBACK (TEMP) This pin reports an analog voltage value proportional to the temperature of the GND. It is used by the MCU to monitor board temperature. FAULT STATUS (FS) RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a lowcurrent sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin should not be allowed to be logic [1] until VDD is in regulation. This pin has a passive internal pulldown. DIGITAL DRAIN VOLTAGE (VDD) This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal 33580 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION supply provides power to a portion of the logic, ensuring limited functionality of the device. GROUND (GND) This pin is the ground for the device. the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 16, page 26. HIGH-SIDE OUTPUTS (HS3, HS1, HS0, HS2) Protected 15 m high-side power output pins to the load. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes state on FAIL-SAFE INPUT (FSI) The value of the resistance connected between this pin and ground determines the state of the outputs after a Watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF or the output HSO only is ON. If the FSI pin is left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-Safe state. When the FSI pin is connected to GND, the Watchdog circuit and Fail-Safe operation are disabled. This pin incorporates an active internal pullup current source. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION SPI PROTOCOL DESCRIPTION The SI / SO pins of the 33580 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). CSB CS CS SCLK SI D15 SO D14 D13 D12 D11 D10 D9 OD15 OD14 OD13 OD12 OD11 OD10 OD9 D8 OD8 D7 D6 OD7 OD6 D5 OD5 D4 D3 OD4 OD3 D2 OD2 D1 D0 OD1 OD0 Notes 1. RST is a logic [1] state during the above operation. D15is: D0 to the most ordered entry of data into the device. NOTES: 1. 2.RSTB in arelate logic H state during therecent above operation. OD15 : OD0 relate thetofirst 16 bits ofordered ordered fault and status data out IC of the device. device. 2. 3.DO, D1, D2, ... , and D15to relate the most recent entry of program data into the LUX Figure 9. Single 16-Bit Word SPI Communication OPERATIONAL MODES The 33580 has four operating modes: Sleep, Normal, Fault, and Fail-Safe. Table 5 summarizes details contained in succeeding paragraphs. Table 5. Fail-Safe Operation and Transitions to Other 33580 Modes Mode FS Sleep x 0 0 x Device is in Sleep mode. All outputs are OFF Normal 1 x 1 No Normal mode. Watchdog is active if enabled. Fault 0 1 1 No 0 1 0 Device is currently in fault mode. The faulted output(s) is (are) OFF. 0 0 1 1 0 1 1 1 1 1 1 0 FailSafe x = Don't care. Wake RST WDTO Yes Comments Watchdog has timed out and the device is in Fail-Safe Mode. The outputs are as configured with the RFS resistor connected to FSI. RST and WAKE must go from logic [1] to logic [0] simultaneously to bring the device out of the Fail-safe mode or momentarily tied the FSI pin to ground. SLEEP MODE The Default mode of the 33580 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to logic [0]. The 33580 will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 5. NORMAL MODE The 33580 is in Normal mode when: * VPWR and VDD are within the normal voltage range. * RST pin is logic [1]. * No fault has occurred. FAIL-SAFE MODE Fail-Safe Mode and Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting 33580 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator and is specified in the Table 15, page 24. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR, the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 6). Table 6. Output State During Fail-Safe Mode RFS (k) High-Side State 0 (shorted to ground) Fail-Safe Mode Disabled 6.0 All HS OFF 15 HS0 ON HS1 : HS3 OFF 30 (open) HS0 and HS2 ON HS1 and HS3 OFF In the Fail-Safe mode, the SPI register content is retained except for overcurrent high and low detection levels, timing and latched overtemperature which are reset to their default value (SOCL, SOCH, OCTL and OT_latch_[0:3] bits). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0]. Table 5 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog fail-safe operation is disabled. Loss of VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The outputs can still be driven by the direct inputs IN0 : IN3. The 33580 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing fail-safe device operation with no VDD supplied. In this state, the watchdog, undervoltage, overvoltage, overtemperature (latched), and overcurrent circuitry are fully operational with default values. FAULT MODE This 33580 indicates the faults below as they occur by driving the FS pin to logic [0]: * Overtemperature fault * Overvoltage and undervoltage fault * Open load fault * Overcurrent fault (high and low) The FS pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, overtemperature (in case of latching configuration) and in some cases of undervoltage. The FS pin reports all faults. For latched faults, this pin is reset by a new Switch ON command (via SPI or direct input IN). Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 17, page 26). PROTECTION AND DIAGNOSTIC FEATURES OVERTEMPERATURE FAULT (LATCHING OR NON-LATCHING) The 33580 incorporates overtemperature detection and shutdown circuitry for each output structure. The overtemperature is latched per default and can be unlatched through SPI with OT_latch_[0:3] bits. An overtemperature fault condition results in turning OFF the corresponding output. To remove the fault and be able to turn ON again the outputs, the failure must be removed and: * in Normal Mode: the corresponding output must be commanded OFF and ON again in case of overtemperature latched (OT_latch bit = 0). * in Normal Mode: the corresponding output turns ON automatically if the temperature is below TSD-TSD(HYS) in case of unlatched overtemperature (OT_latch bit = 1). * in Fail-Safe Mode: the FSI input must be grounded and then set to its nominal voltage to switch ON the outputs. The overtemperature fault (one for each output) is reported by SPI. If the overtemperature is latched, the SPI reports OTF_s = [1] and OCLF_s = [1]. In case of nonlatched, OTF_s = [1] only is reported. The fault bits will be cleared in the status register after either a valid SPI read command or a power on reset of the device. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES OVERCURRENT FAULT (LATCHING) The 33580 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 6, page 14. The eight different overcurrent low detect levels (IOCL0 : IOCL7) are illustrated in Figure 6. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected toch driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again. OVERVOLTAGE FAULT (NON-LATCHING) The 33580 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit D1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection can be disabled through SPI (bit OV_DIS). When disabled, the returned SO bit OD13 still reflects any overvoltage condition (overvoltage warning). UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING) The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to logic 0, and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers : * If outputs command are low, FS will go to logic 1 but the UVF bit will remain set to 1 until the next read operation (warning report). * If the output command is ON, then FS will remain at logic 0. The output must be turned OFF and ON again to re-enable the state of output and release FS. The UVF bit will remain set to 1 until the next read operation. The undervoltage protection can be disabled through SPI (bit UV_dis = 1). In this case, the FS does not report any undervoltage fault condition, UVF bit is set to 1, and the output state is not changed as long as the battery voltage does not drop any lower than 2.5 V. In case of VPWR is missing, the daisy chain feature is available under VDD in nominal conditions. 33580 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES Table 7. Device Behavior in Case of Undervoltage Quad High-Side Switch (VPWR Battery Voltage) VPWR > VPWRUV VPWRUV > VPWR > UVPOR UVPOR > VPWR > 2.5 V State Output State UV Enable IN[0:3]=0 (Falling VPWR) UV Enable UV Disable UV Disable UV Enable UV Enable IN[0:3]=0 IN[0:3]=0 IN_x***=1 IN_x***=1 IN_x***=1 (Falling or (Falling or (Falling or (Falling VPWR) (Rising VPWR) Rising VPWR) Rising VPWR) Rising VPWR) OFF OFF ON OFF OFF ON FS State 1 1 1 0 1 1 SPI Fault Register UVF Bit 0 1 until next read 0 1 0 (falling) 1 until next read (rising) 0 (falling) 1 until next read (rising) OFF OFF OFF OFF OFF ON FS State 0 0 0 0 1 1 SPI Fault Register UVF Bit 1 1 1 1 1 1 OFF OFF OFF OFF OFF ON 1 1 1 1 1 1 Output State Output State FS State SPI Fault Register 1 until next read UVF Bit 2.5 V > VPWR > 0V Output State FS State 1 1 until next read 1 until next read 1 until next read 1 until next read OFF OFF OFF OFF OFF OFF 1 1 1 1 1 1 SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read UVF Bit Comments UV fault is not latched UV fault is not latched UV fault is latched = Typical value; not guaranteed. = While VDD remains within specified range. = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input. OPEN LOAD FAULT (NON-LATCHING) The 33580 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled through SPI (bit OL_DIS). It is recommended to disable the open load detection circuitry in case of permanent disconnected load. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required except on VDD. GROUND DISCONNECT PROTECTION In the event the 33580 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection. A 10K resistor needs to be added between the wake pin and the rest of the circuitry in order to ensure that the device turns off in case of ground disconnect and to prevent this pin to exceed its maximum ratings. Current limit resistors in the digital input lines protect the digital supply against excessive current (1 kohm typical). REVERSE BATTERY The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output's gate is enhanced to keep the junction temperature less than 150C. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS SERIAL INPUT COMMUNICATION Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 33580 has defined registers, which are used to configure the device and to control the state of the outputs. Table 9, page 22, summarizes the SI registers. SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 8). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit. In some cases, output selection is done with bits D12 : D11. The next three bits, D10 : D8, are used to select the command register. The remaining five bits, D4 : D0, are used to configure and control the outputs and their protection features. Table 8. SI Message Bit Assignment Bit Sig SI Msg Bit MSB D15 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. D14 : D15 Not used. D12 : D11 Register address bits used in some cases for output selection. D10 : D8 Register address bits. D7 : D5 Not used. D4 : D1 Used to configure the inputs, outputs, and the device protection features and SO status content. D0 Used to configure the inputs, outputs, and the device protection features and SO status content. LSB Table 9. Serial Input Address and Configuration Bit Map SI Data SI Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 STATR_s WDIN 0 0 0 0 0 0 0 0 0 0 SOA4 SOA3 SOA2 SOA1 SOA0 OCR0 WDIN 0 0 0 0 0 0 1 0 0 0 0 IN3_SPI IN2_SPI IN1_SPI IN0_SPI OCR1 WDIN 0 0 0 1 0 0 1 0 0 0 0 CSNS3 EN CSNS2 EN CSNS1 EN CSNS0 EN SOCHLR_s WDIN 0 0 A1 A0 0 1 0 0 0 0 0 SOCH_s SOCL2_s SOCL1_s SOCL0_s CDTOLR_s WDIN 0 0 A1 A0 0 1 1 0 0 0 0 OL_DIS_s OCL_DIS_s OCLT1_s OCLT0_s DICR_s WDIN 0 0 A1 A0 1 0 0 0 0 0 0 FAST_SR_s CSNS_high_s DIR_DIS_s A/O_s UOVR WDIN 0 0 0 0 1 0 1 0 0 0 0 OT_latch-1 OT_latch_0 UV_DIS OV_DIS WDR WDIN 0 0 0 1 1 0 1 0 0 0 0 OT_latch_3 OT_latch_2 WD1 WD0 NAR WDIN 0 0 0 0 1 1 0 0 0 0 0 RESET 0 0 0 X X X X X 0 0 0 0 No Action (Allow Toggling of D15- WDIN) 0 0 0 0 x = Don't care. s = Output selection with the bits A1A0 as defined in Table 10. D15 is used to toggle watchdog event (WDIN). 33580 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS DEVICE REGISTER ADDRESSING The following section describes the possible register addresses and their impact on device operation. ADDRESS 00000 -- STATUS REGISTER (STATR_S) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR0, OCR1, SOCHLR, CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 25.) ADDRESS 00001-- OUTPUT CONTROL REGISTER (OCR0) The OCR0 register allows the MCU to control the ON / OFF state of four outputs through the SPI. Incoming message bit D3 : D0 reflects the desired states of the four high-side outputs (INx_SPI), respectively. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF. ADDRESS 01001-- OUTPUT CONTROL REGISTER (OCR1) Incoming message bits D3 : D0 reflect the desired output that will be mirrored on the Current Sense (CSNS) pin. A logic [1] on message bits D3 : D0 enables the CSNS pin for outputs HS3 : HS0, respectively. In the event the current sense is enabled for multiple outputs, the current will be summed. In the event that bits D3 : D0 are all logic [0], the output CSNS will be tri-stated. This is useful when several CSNS pins of several devices share the same A /D converter. ADDRESS A1A0010 -- SELECT OVERCURRENT HIGH AND LOW REGISTER (SOCHLR_S) The SOCHLR_s register allows the MCU to configure the output overcurrent low and high detection levels, respectively. Each output "s" is independently selected for configuration based on the state of the D12 : D11 bits (Table 10). Table 10. Output Selection A1 (D12) A0 (D11) HS_s 0 0 HS0 0 1 HS1 1 0 HS2 1 1 HS3 Each output can be configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements matching system characteristics. Bits D2 : D0 set the overcurrent low detection level to one of eight possible levels, as shown in Table 11, page 23. Bit D3 sets the overcurrent high detection level to one of two levels, as outlined in Table 12, page 23. Table 11. Overcurrent Low Detection Levels SOCL2_s* SOCL1_s* SOCL0_s* (D2) (D1) (D0) Overcurrent Low Detection (Amperes) HS0 to HS3 0 0 0 18.2 0 0 1 16.3 0 1 0 14.4 0 1 1 12.5 1 0 0 10.5 1 0 1 8.6 1 1 0 6.7 1 1 1 4.8 * "_s" refers to the output, which is selected through bits D12 : D11; refer to Table 10, page 23. Table 12. Overcurrent High Detection Levels SOCH_s* (D3) Overcurrent High Detection (Amperes) HS0 to HS3 0 100 1 70 * "_s" refers to the output, which is selected through bits D12 : D11; refer to Table 10, page 23. ADDRESS A1A0011 -- CURRENT DETECTION TIME AND OPEN LOAD REGISTER (CDTOLR) The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before an output latches OFF. Each output is independently selected for configuration based on A1A0 , which are the state of the D12 : D11 bits (refer to Table 10, page 23). 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Bits D1 : D0 (OCLT1_s : OCLT0_s) allow the MCU to select one of three overcurrent fault blanking times defined in Table 13. Note that these time-outs apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s. Table 13. Overcurrent Low Detection Blanking Time OCLT[1:0]_s* Timing 00 155 ms 01 Do not use 10 75 ms 11 150 s * "_s" refers to the output, which is selected through bits D12 : D11. A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent low detection feature. When disabled, there is no timeout for the selected output and the overcurrent low detection feature is disabled. A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL) detection feature for the output corresponding to the state of bits D12 : D11. ADDRESS A1A0100 -- DIRECT INPUT CONTROL REGISTER (DICR) The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of each output. Each output is independently selected for configuration based on the state bits D12 : D11 (refer to Table 10, page 23). For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the Input was enabled for direct control, a logic [1] for the D0 (A/O_s) bit will result in a Boolean AND of the IN pin with its corresponding IN_SPI D[4:0] message bit when addressing OCR0. Similarly, a logic [0] on the D0 pin results in a Boolean OR of the IN pin to the corresponding message bits when addressing the OCR0. This register is especially useful if several loads are required to be independently PWM controlled. For example, the IN pins of several devices can be configured to operate all of the outputs with one PWM output from the MCU. If each output is then configured to be Boolean ANDed to its respective IN pin, each output can be individually turned OFF by SPI while controlling all of the outputs, commanded on with the single PWM output. A logic [1] on bit D2 (CSNS_high_s) is used to select the high ratio on the CSNS pin for the selected output. The default value [0] is used to select the low ratio (Table 14). Table 14. Current Sense Ratio CSNS_high_s* (D2) Current Sense Ratio HS0 to HS3 0 1/13000 1 1/38000 * "_s" refers to the output, which is selected through bits D12 : D11; refer to Table 10, page 23. A logic [1] on bit D3 (FAST_SR_s) is used to select the high speed slew rate for the selected output, the default value [0] corresponds to the low speed slew rate. ADDRESS 00101 -- UNDERVOLTAGE / OVERVOLTAGE AND HS[0,1] OVERTEMPERATURE REGISTER (UOVR) The UOVR register disables the undervoltage (D1) and/or overvoltage (D0) protection. When these two bits are [0], the under- and overvoltage are active (default value). The UOVR register allows the overtemperature detection latching on the HS0 and HS1. To latch the overtemperature, the bits (OT_latch_1 and OT_latch_0) must be set to [0] which is the default value. To disable the latching, both bits must be set to [1]. ADDRESS 01101 -- WATCHDOG AND HS[2,3] OVERTEMPERATURE REGISTER (WDR) The WDR register is used by the MCU to configure the Watchdog timeout. The Watchdog timeout is configured using bits D1 and D0. When D1 and D0 bits are programmed for the desired watchdog timeout period (Table 15), the WDSPI bit should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. The WDR register allows the overtemperature detection latching on the HS2 and HS3. To latch the overtemperature, the bits (OT_latch_3 and OT_latch_2) must be set to [0] which is the default value. To disable the latching, both bits must be set to [1]. Table 15. Watchdog Timeout WD[1:0] (D1, D0) Timing (ms) 00 558 01 279 10 2250 11 1125 33580 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS ADDRESS 00110 -- NO ACTION REGISTER (NAR) The NAR register can be used to no-operation fill SPI data packets in a daisy-chain SPI configuration. This would allow devices to be unaffected by commands being clocked over a daisy-chained SPI configuration. By toggling the WD bit (D15) the watchdog circuitry would continue to be reset while no programming or data read back functions are being requested from the device. SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA) When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CS transition, is dependent upon the previously written SPI word. Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification. A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, SOCHLR, CDTOLR, and DICR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous OD4, OD3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored. * The RST pin transition from a logic [0] to [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. SERIAL OUTPUT BIT ASSIGNMENT The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16, page 26, summarizes SO returned data for bits OD15 : OD0. * Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. * Bit OD14 remains logic [0] except when an undervoltage condition occurred. * Bit OD13 remains logic [0] except when an overvoltage condition occurred. * Bits OD12 : OD8 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message. * Bits OD7 : OD4 give the fault status flag of the outputs HS3 : HS0, respectively. * The contents of bits OD3 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 16. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 16. Serial Output Bit Map Description Previous STATR SO Returned Data SO SO SO SO SO OD A4 A3 A2 A1 A0 15 STATRs A1 A0 OD 14 OD 13 OD 12 OD 11 OD OD9 OD8 OD7 OD6 OD5 OD4 10 OD3 OD2 OD1 OD0 0 0 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OTF_s OCHF_s OCLF_s OLF_s IN1_SPI IN0_SPI OCR0 0 0 0 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 IN3_SPI IN2_SPI OCR1 0 1 0 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 CSNS3 EN CSNS2 EN CSNS1 EN CSNS0 EN SOCHL A1 A0 R_s 0 1 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 SOCH_s SOCL2_s SOCL1_s SOCL0_s CDTOL A1 A0 R_s 0 1 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OL_DIS_s OCL_DIS_s OCLT1_s OCLT0_s DICR_s A1 A0 1 0 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 Fast_SR_s CSNS_high_s DIR_DIS_s UOVR 0 0 1 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OT_latch_1 OT_latch_0 WDR 0 1 1 0 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 PINR0 0 0 1 1 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 HS2_failsafe HS0_failsafe PINR1 0 1 1 1 0 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 PINR2 0 1 1 1 1 WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 OT_latch_3 OT_latch_2 0 0 Reset N/A N/A N/A N/A N/A 0 0 0 0 0 0 0 0 0 0 0 IN3 0 WDTO IN2 0 A/O_s UV_DIS OV_DIS WD1 WD0 WD_en WAKE IN1 IN0 X X 0 0 s = Output selection with the bits A1A0 as defined in Table 10, page 23. PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000 PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010 Bits OD3 : OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits A1A0 (Table 17). Data returned in bits OD3 : OD0 are programmed current values for the overcurrent high detection level (refer to Table 12, page 23) and the overcurrent low detection level (refer to Table 11, page 23), corresponding to the output previously selected with A1A0. Table 17. Output-Specific Fault Register OD3 OD2 OD1 OD0 OTF_s OCHF_s OCLF_s OLF_s s = Selection of the output. Note The FS pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (via SPI or direct input IN). PREVIOUS ADDRESS SOA4 : SOA0 = 00001 Data in bits OD3 : OD0 contains IN3_SPI : IN0_SPI programmed bits for outputs HS3 : HS0, respectively. PREVIOUS ADDRESS SOA4 : SOA0 = 01001 Data in bits OD3 : OD0 contains the programmed CSNS3 EN : CSNS0 EN bits for outputs HS3 : HS0, respectively. PREVIOUS ADDRESS SOA4 : SOA0= A1A0011 The returned data contains the programmed values in the CDTOLR register for the output selected with A1A0. PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100 The returned data contains the programmed values in the DICR register for the output selected with A1A0. PREVIOUS ADDRESS SOA4 : SOA0 = 00101 The returned data contains the programmed values in the UOVR register. PREVIOUS ADDRESS SOA4 : SOA0 = 01101 The returned data contains the programmed values in the WDR register. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-Safe mode. IF WDTO is a logic [0], the device is in Normal mode (assuming the device 33580 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS is powered and not in the Sleep mode), with the watchdog either enabled or disabled. PREVIOUS ADDRESS SOA4 : SOA0 = 00110 The returned data OD3 and OD2 contain the state of the outputs HS2 and HS0, respectively, in case of Fail-Safe state. This information is stated with the external resistance placed at the FSI pin. OD1 indicates if the watchdog is enabled or not. OD0 returns the state of the WAKE pin. PREVIOUS ADDRESS SOA4 : SOA0 = 01110 The returned data OD3 : OD0 reflects the state of the direct pins IN3 : IN0, respectively. PREVIOUS ADDRESS SOA4 : SOA0 = 01111 The returned data OD3 -OD2 reports the overtemperature bits configuration of the outputs [3, 2] set through the WDR SPI register. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 27 TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION The 33580 can be configured in several applications. The figure below shows the 33580 in a typical lighting application. VPWR VDD Voltage regulator VDD VPWR VDD VPWR 33580 VDD VPWR VDD 10k 10k 100nF 10F VDD NC WAKE I/O I/O I/O I/O I/O 10 k 10 k 10 k 10 k SCLK CS I/O SO SI 10 k 10 k 10 k 10 k Microcontroller LOAD 0 55W SCLK CS RST SI SO TEMP CSNS FSI 1k HS0 FS IN0 IN1 IN2 IN3 A/D A/D 100nF HS1 LOAD 1 55W HS2 LOAD 2 55W HS3 GND LOAD 3 55W R1 Automotive lamps do not tolerate high voltages very well. Tests of a few lamps indicate that failures can occur when 18V is applied for a few seconds. Consequently, PWM switching reduces the effective RMS voltage in order to drive bulbs safety. For example, to maintain the power dissipation associated with a 13V battery at 100% duty cycle, the duty cycle would be adjusted to (13/18), or 52%, when the battery is at 18V. The loads must be chosen in order to guarantee the device normal operating condition for junction temperature from -40 to 150 C. In case of permanent short-circuit conditions, the duration and number of activation cycles must be limited with a dedicated MCU fault management using the fault reporting through the SPI. 33580 28 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS STANDALONE MODE STANDALONE MODE without an MCU to communicate by SPI. Some functions still enable, but diagnosis is reduced. Available functions and default parameters are detailed next. This section consists of evaluating the MC33580 standalone capability. CONFIGURATION WITHOUT MCU The standalone mode is intended for customers who desire to plug the device and then immediately "play" with it, without having to connect it to a microcontroller. It also provides an easy way to evaluate the main electrical features. Without the Microcontroller to select programmable parameters and get full diagnosis via the SPI, the MC33580 runs with all parameters set to default. FUNCTIONING WITHOUT MCU Without an MCU, SPI communication is not possible. Fail safe mode and watchdog timeout are not useful functions without an MCU, but still enable. Wake/Sleep mode is used to minimize current consumption during sleep mode. IN pins control the corresponding outputs and FS output is active (at 0 V) when a default occurs. Table 18 illustrates the available functions without SPI and default parameters. The input SPI pin pins and VDD must be connected to ground. Fail safe mode and watchdog timeout must be disabled by connecting the FSI to GND. All protection functions are available without SPI communication. Nevertheless, any configuration is possible Table 19 illustrates default parameters after resetting or applying supply voltage to the MC33580. Levels and timings are typical values. Table 18. Available Functions Function With SPI Without SPI Wake/Sleep mode Available Available Output ON/OFF control Via SPI or IN pin Only with IN pin Over temperature protection Available, can be unlatched Available Over voltage protection Available, can be disabled Available, always enable Under voltage protection Available, can be disabled Available, always enable Over current protection Available, configurable (with 8 low levels and 2 high levels), can be disabled Available, always enable with default values Open load, battery disconnect, reverse battery, ground disconnect protections Available Available Fault diagnosis Full diagnosis with report by SPI and fault status pin (/FS) Limited fault diagnosis with Fault status pin only Current sense Available, 2 configurable ratios Not available Watchdog timeout Available, 4 configurable timings Available, default value Configurable slew rate 2 slew rate modes Default slew rate mode Analog temperature feedback Available Available Table 19. Default SPI-Configurable Parameters Configulable Parameter Default Typical Value Over voltage protection Enable Under voltage protection Enable Over current protection Enable Over current low level OCLO0 Over current high level OCHI0 Over current detect blanking time tOCLO0 Current sense Disable Watchdog time timeout TWDTO0 Slew rate mode Slow mode 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 29 TYPICAL APPLICATIONS STANDALONE MODE DIAGNOSIS WITHOUT MCU When any fault appears (over current, open load...), a full diagnosis can be reported via the SPI. Without an MCU, the fault status pin allows reduced diagnosis, as illustrated in Table 20. Table 20. Diagnosis without SPI Normal operation Over temperature Under voltage Over voltage Over current Short circuit to VPWR Open load IN[x] Level HS[x] Level FS Level H H H L L H L L L H L L L L L H L L L L H H L L L L H H L L L H L H H H L Z L H H H Latched N/A YES YES NO YES NO NO H : High Level, L : Low Level, Z : High impedance, potential depends on the external circuit. We can note that it is not possible to distinguish over temperature, over current, under voltage, and over voltage. Nevertheless, Open load and short circuit to VPWR fault can be singled out. All protections are reported to Fault status pin (FS), Open load and short circuit to VPWR are reported only if the Output is OFF. If the fault is latched, the output must be turned OFF then ON to disable the fault. functioning is safe because all protections are available. Diagnosis is limited, but the fault status pin will report any malfunction. This is a good way to evaluate the main electrical MC33580 features. Some simplified applications can also use the MC33580 switch without an MCU to drive a high power load with full protection. CONCLUSION Although the MC33580 is not fully functional without a microcontroller to control and program it, standalone 33580 30 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION The 33580 is not designed for immersion soldering. The maximum peak temperature during the soldering process should not exceed 245C. Terminal soldering limit is for 10 seconds maximum duration. Exceeding these limits may cause malfunction or permanent damage to the device. PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.comand perform a keyword search using the 98ART10510D listed below. PNA SUFFIX (Pb-FREE) 24-PIN PQFN NON-LEADED PACKAGE 98ART10511D ISSUE 0 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 31 PACKAGING PACKAGE DIMENSIONS 33580 32 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 33 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) ADDITIONAL DOCUMENTATION 33580PNA THERMAL ADDENDUM (REV 3.0) Introduction This thermal addendum is provided as a supplement to the MC33580 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. HIGH-SIDE SWITCH Packaging and Thermal Considerations This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2 = RJA11 RJA12 RJA21 RJA22 . PNA SUFFIX 98ART10510D 24-PIN PQFN (12 x 12) Note For package dimensions, refer to the 33580 device datasheet. P1 P2 The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 21. Thermal Performance Comparison 1 = Power Chip, 2 = Logic Chip [C/W] Thermal Resistance RJAmn (1), (2) RJBmn (2), (3) RJAmn (1), (4) RJCmn (5) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 20 16 39 6 2.0 26 53 40 73 <0.5 0.0 1.0 Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad. 1.0 0.2 1.0 0.2 Note: Recommended via diameter is 0.5 mm. PTH (plated through hole) via must be plugged / filled with epoxy or solder mask in orde to minimize void formation and to avoid any solder wicking into the via. Figure 10. Surface mount for power PQFN with exposed pads 33580 34 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) WAKE FS IN3 IN2 TEMP IN1 IN0 CSNS 7 6 5 4 3 2 1 SO 16 GND 17 HS3 18 14 GND 76.2 mm 24 FSI 23 GND 22 HS2 A= 300sqmm 15 VPWR 19 20 HS1 NC 114.3 mm RST 8 SCLK 9 SI 13 12 11 10 VDD CS Transparent Top View A= 300sqmm 21 HS0 MC33580 Pin Connections 24-Pin PQFN (12 x 12) 0.9 mm Pitch 12.0 mm x 12.0 mm Body Figure 12. Thermal Test Board Device on Thermal Test Board Material: Outline: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Area A: Cu heat-spreading areas on board surface Ambient Conditions: Natural convection, still air Table 22. Thermal Resistance Performance Thermal Resistance RJAmn Area A 1 = Power Chip, 2 = Logic Chip (C/W) (mm2) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 0 51 38 60 300 43 32 55 600 41 30 55 RJA is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 35 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) 65.000 60.000 55.000 50.000 45.000 40.000 35.000 30.000 25.000 0 100 200 RRJA11 JA11 300 400 RJA21 RJA11= RJA12=RJA21 500 600 RRJA22 JA22 Figure 13. Stead State Thermal Resistance 100 10 1 0.1 1.00E-06 1.00E-04 1.00E-02 RRJA11 JA11 1.00E+00 RRJA12=RJA21 JA11= RJA11 1.00E+02 1.00E+04 RRJA22 JA22 Figure 14. Transient Thermal Resistance 33580 36 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE 2.0 02/2006 3.0 05/2006 DESCRIPTION OF CHANGES * * * * * * * * * * 4.0 6/2006 5.0 9/2006 * * * * * * * * 6.0 4/2007 * * Implemented Revision History page Converted to Freescale format Added Thermal Addendum Added B to the part number ordering information. Minor drawing correction to Figure 1 Number changes to Selectable Output Current and Programmable Watchdog in Figure 2 Changed Temperature Feedback Min, Typ, & Max in the StatiC Electical Characteristics Changed max limit on Overcurrent Low Detection Blanking Time for OCLT[1:0] : 11 in the Dynamic Electrical characteristics Minor corrections in Figure 7, Input Timing Switching Characteristics Added the sentence "It is recommended to disable the open load detection circuitry in case of permanent disconnected load." to Open Load Fault (Non-Latching) Changed resistor value for the SPI inputs from 1 k to 10 k in the Typical Applications Updated the drawings and version on Package Dimensions Made correction to the 33580 Simplified Internal Block Diagram on the HSO MOSFET. Changed Note 11 from Guaranteed by design to Guaranteed by process monitoring Modified Output Turn ON Delay Times on page 11 Adjusted numbers on See Output Rising Fast Slew Rate A (DICR D3 = 1) (19) on page 10 and See Output Falling Slow Slew Rate A (DICR D3 = 0) (19) on page 10 Made additions and corrections to See Typical Applications on page 28 Made changes to Thermal Addendum (rev 3.0) relating to Figure 12, Table 22, Thermal Resistance Performance, Figure 13, and Figure 14 Changed the package type from 98ARL10596D to 98ART10510D Removed PC33580BPNA/R2, and added MC33580BAPNA/R2 33580 Analog Integrated Circuit Device Data Freescale Semiconductor 37 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC33580 Rev. 6.0 4/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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