APL5315-BI-TRL - Anpec Electronics Corporation

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and

advise customers to obtain the latest version of relevant information to verify before placing orders.

Selectable Adjustable/Fixed Low dropout 300mA Linear Regulator

Features

•Wide Operating Voltage: 2.7~6V

•Low Dropout Voltage:

230mV(typical) @ 300mA

•Guaranteed 300mA Output Current

•Two Modes for Setting Output Voltage

- Fixed Output Voltage: 1~5V

- Adjustable Output Voltage: 0.8~5.5V

•Current Limit Protection with Foldback Current

•Internal Soft-Start

•Over Temperature Protection

•Stable with Low ESR Ceriamic Capacitor

•SOT-23-5 Package

•Lead Free Available (RoHS Compliant)

Applications

General Description

The APL5315 is a P-channel low dropout linear regulator

which needs only one input voltage from 2.7~6V, and

delivers current up to 300mA to set output voltage. It also

can work with low ESR ceramic capacitors and is ideal for

using in the battery-powered applications such as note-

book computers, cellular phones. Typical dropout voltage

is only 230mV at 300mA loading.

The APL5315 provides two kinds of output voltage

operation modes for setting the output voltage. Fixed

output voltage mode senses the output voltage on

VOUT, adjustable output voltage mode needs two

resistors as a voltage divider. Current limit with current

foldback and thermal shutdown functions protect the

device against current over-loads and over temperature.

The APL5315 is available in a SOT-23-5 package.

•Cellular Phones

•Portable and Battery-powered Equipment

•Notebook and Personal Computers

Simplified Application Circuit

Ordering and Marking Information

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully

compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-

free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.

VIN

SHDNGND

VOUT

SET

CIN 1

3 4

APL5315 VOUT

COUT

VIN

Temperature Range

Package Code

Voltage Code

APL5315

Handling Code

Lead Free Code

Package Code

B : SOT- 23-5

Operating Junction Temperature Range

I : -40 to 85 C

Handling Code

TR : Tape & Reel

Voltage Code

12 : 1.2V Blank: Adjustable

Lead Free Code

L : Lead Free Device

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw2

Pin Configuration

Symbol Parameter Rating Unit

VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 6.5 V

VSHND SHND Input Voltage (SHND to GND) -0.3 ~ 6.5 V

PD Power Dissipation Internally Limited W

TJ Junction Temperature -40 ~ 150 °C

TSTG Storage Temperature -65 ~ 150 °C

TSDR Soldering Temperature, 10 Seconds 260 °C

Absolute Maximum Ratings

VIN 3 4 VOUT

SHDN 1

GND 2 5 SET

SOT-23-5

Product Name

Marking Product Name

Marking Product Name Marking

APL5315 35RX APL5315-12 355X APL5315-15 359X

APL5315-18 35CX APL5315-25 35JX APL5315- 33 35RX (Note2)

Note1 : Other voltage version please contact ANPEC for detail.

Note2 : Because APL5315 and APL5315-33 are identical, the marking of APL5315 is same as APL5315-33.

Thermal Characteristics

Symbol Parameter Typical Value Unit

θJA Thermal Resistance-Junction to Ambient (Note 3) 240 oC/W

Note3 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Recommended Operating Conditions

Symbol Parameter Range Unit

VIN VIN Supply Voltage 2.7 ~ 6 V

VOUT Output Voltage 0.8 ~ 5.5 V

IOUT VOUT Output Current 0 ~ 300 mA

COUT Output Capacitor 1.5 ~ 33 µF

TJ Junction Temperature -40 ~ 125 oC

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw3

Electrical Characteristics

Unless otherwise specified, these specifications apply over VIN = VOUT+1V (min VIN=2.7V), IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF,

TA = -40 to 85oC. Typical values are at TA = 25oC.

APL5315

Symbol

Parameter Test Condition Min. Typ. Max.

Unit

VIN Input Voltage

2.7 --- 6 V

VOUT Output Voltage Range 0.8 --- 5.5 V

UVLO Threshold 1.5 2.3 2.6 V

UVLO Hysteresis --- 0.8 --- V

IQ Quiescent Current IOUT =10mA ~300mA --- 120 160 µA

VREF Reference Voltage Measured on SET, VIN=2.7V, IOUT=10mA 0.784

0.8 0.816

Output Voltage Accuracy Fixed output voltage, IOUT=10mA -2 --- +2 %

REGLINE

Line Regulation ΔVOUT%/ΔVIN, IOUT=10mA -0.06

--- +0.06

%/V

REGLOAD

Load Regulation ΔVOUT%/ΔIOUT -0.2 --- +0.2 %/A

VOUT = 2.5V, IOUT = 300mA --- 230 360

VDROP

Dropout Voltage VOUT = 3.3V, IOUT = 300mA --- 170 300 mV

PSRR

Power Supply Ripple Rejection

Ratio f = 10kHz, IOUT = 300mA --- 45 --- dB

Noise f = 80Hz to 100KHz, IOUT = 300mA --- 160 --- µVRMS

ILIMIT Current Limit 400 500 650 mA

ISHORT

Foldback Current VOUT = 0V --- 80 --- mA

SHDN Input Voltage High 1.6 --- ---

SHDN Input Voltage Low --- --- 0.4 V

Shutdown VIN Supply Current

SHDN = Low, VIN = 6V --- 0.1 1 µA

SHDN Pull Low Resistance --- 3 --- MΩ

VOUT Discharge MOSFET

RDS(ON) SHDN = Low --- 60 --- Ω

Over Temperature Threshold --- 160 --- °

Over Temperature Hysteresis --- 40 --- °

SET Input Threshold for

Fixed/Adjustable Output Voltage

Mode --- 100 --- mV

SET input bias current VSET=0.8V -100 --- 100 nA

TSS Soft-Start Interval 60 80 100 µs

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw4

Typical Operating Characteristics

Quiescent Current vs. Supply VoltageQuiescent Current vs. Junction Temperature

Quiescent Current vs. Output CurrentPSRR vs. Frequency

Dropout Voltage vs. Output CurrentDropout Voltage vs. Output Current

1000 10000 100000 1000000

PSRR (dB)

Frequency (Hz)

-60

-50

-40

-30

-20

-10

0VIN=3.3V, VOUT=1.2V

CIN=1µF, COUT=2.2µF

IOUT=300mA

Output Current, IOUT (mA)

Dropout Voltage, VDROP (mV)

100

150

200

250

300

0100 200 300

VOUT=2.5V

TJ=-50°C

TJ=75°C

TJ=25°C

TJ=0°C

TJ=125°C

Dropout Voltage, VDROP (mV)

Output Current, IOUT (mA)

VOUT=3.3V

0100 200 300

100

150

200

250

TJ=-50°C

TJ=0°C

TJ=25°C

TJ=125°C

TJ=75°C

Supply Voltage, VIN (V)

Quiescent Current, IQ (µA)

100

120

140

160

0 1 2 3 4 5 6 7

IOUT= 0mV

Junction Temperature, TJ (°C)

Quiescent Current, IQ (µA)

102

104

106

108

110

112

114

-50 -25 0 25 50 75 100 125

100

120

140

160

180

050 100 150 200 250 300

Output Current, IOUT (mA)

Quiescent Current, IQ (µA)

VIN=5.5V

VIN=4.5V

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw5

Typical Operating Characteristics (Cont.)

Loop Gain vs. Frequency Phase vs. Frequency

Current Limit vs. Junction Temperature

Junction Temperature, TJ (°C)

Current Limit, ILIMIT (mA)

VIN=5V

400

450

500

550

600

-50 -25 025 50 75 100 125

Loop Gain (dB)

Frequency (Hz)

IOUT=100mA

IOUT=300mA

VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF

-40

-30

-20

-10

1000 10000 100000 1000000 1000 10000 100000 1000000

Frequency (Hz)

Phase (degree)

IOUT=100mA

IOUT=300mA

VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF

100

120

140

160

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw6

Operating Waveforms

Load TransientLine Transient

CH1 : VOUT, 50mV/div, AC

CH2 : IOUT, 100mA/div, DC

Time : 100µs/div

CH1 : VIN, 1V/div, DC

CH2 : VOUT, 20mV/div, AC

Time : 100µs/div

EnableShutdown

CH1 : VOUT, 500mV/div

CH2 : VSHDN, 5V/div

CH3 : IOUT, 200mA/div

Time : 50µs/div

CH1 : VOUT, 500mV/Div

CH2 : VSHDN, 5V/Div

CH3 : IOUT, 200mA/Div DC

Time : 10µs/Div

VOUT

OUT

VIN=3.3V, CIN=1µF, COUT=2.2µF, TR=1µsCIN=1µF, COUT=2.2µF, TR=10µs, IOUT=10mA

VIN

OUT

VOUT

VSHDN

I OUT

VOUT

VSHDN

I OUT

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw7

Operating Waveforms (Cont.)

Power on Power off

CH1 : VIN, 2V/div

CH2 : VOUT, 500mV/div

CH3 : IOUT, 100mA/div

Time : 200µs/Div

CH1 : VIN, 2V/div

CH2 : VOUT,, 500mV/div,

CH3 : IOUT, 100mA/div

Time : 50ms/Div

Pin Descriptions

No NAME I/O FUNCTION

1 SHDN

I Shutdown control pin, logic high: enable; logic low: shutdown

2 GND Ground pin

3 VIN I Voltage supply input pin

4 VOUT O Regulator output pin

5 SET I Connect this pin to ground for fixed output voltage operation. Connect this pin to an

external resistor divider for adjustable output voltage mode operation.

VIN

VOUT

OUT

VIN

VOUT

OUT

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw8

Block Diagram

Typical Application Circuits

1. Fixed Output Voltage Mode

Thermal

Shutdown

GND

SHDN

VOUT

SET

VIN

UVLO &

Shutdown

Logic Foldback

current

limit

100mVVREF

3MΩLow

High

VIN

SHDN

GND

VOUT

SET

CIN 1

3 4

APL5315 VOUT

VIN

2.2µF

1µF

Enable

Shutdown

COUT

2.2µF/GRM155R60J225M Murata

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw9

Typical Application Circuits (Cont.)

2. Adjustable Output Voltage Mode

Functional Descriptions

Internal Soft-Start

An internal soft-start function controls rising rate of the

output voltage to limit the surge current at start-up. The

typical soft-start interval is about 80µs.

Under-Voltage Lock Out (UVLO)

The APL5315 monitors the input voltage to prevent

wrong logic control. The UVLO function initiates a soft-

start process after input voltage exceeds its rising

UVLO threshold during power on. The UVLO function

also shuts off the output when the input voltage falls

below it’s falling threshold. Typical UVLO hysteresis

voltage is 0.8V.











+⋅=R2

10.8 VOUT

Where R1 is connected from VOUT to SET with Kelvin

sensing and R2 is connected from SET to GND. The

recommended value of R2 is in the range of 100~100KΩ.

An error amplifier working with a temperature compen-

sated 0.8V reference and an output PMOS regulates the

output to the presetting voltage. The error amplifier

designed with high bandwidth and DC gain provides

very fast transient response and less load regulation.

It compares the reference with the feedback voltage and

amplifies the difference to drive the output PMOS which

provides load current from VIN to VOUT.











+⋅=R2

10.8 VOUT

Thermal Shutdown

A thermal shutdown circuit limits the junction tempera-

ture of APL5315. When the junction temperature exceeds

+160οC, a thermal sensor turns off the output PMOS,

allowing the device to cool down. The regulator regu-

lates the output again through initiation of a new soft-

start cycle after the junction temperature cools by 40οC.

The thermal shutdown designed with a 40οC hysteresis

lowers the average junction temperature during continu-

ous thermal overload conditions, extending life time of

the device.

For normal operation, device power dissipation should

be externally limited so that junction temperature will not

exceed 125οC.

Output Voltage Regulation

The APL5315 can works in either fixed or adjustable mode

by connecting the SET to GND or a resistor-divider which

receives the feedback voltage of the regulator. The output

voltage set by the resistor-divider is determined by:

Shutdown Control

The APL5315 has an active-low shutdown function. Force

SHDN high (>1.6V) enables the VOUT; force SHDN low

(<0.4V) disables the VOUT. SHDN is internally pulled low

by a resistor (3MΩ typical). If it is not used, connect to VIN

for normal operation.

VIN

SHDN

GND

VOUT

SET

CIN 1

3 4

APL5315 VOUT

COUT

VIN

2.2µF

1µF

Enable

Shutdown

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw10

Application Information

Input Capacitor

The APL5315 requires proper input capacitors to supply

surge current during stepping load transients to prevent

the input rail from dropping . Because the parasitic induc-

tor from the voltage sources or other bulk capacitors to

the VIN limit the slew rate of the surge current. Place the

Input capacitors near VIN as close as possible. Input

capacitors should be larger than 1µF and a minimum

ceramic capacitor of 1µF is necessary.

Output Capacitor

The APL5315 needs a proper output capacitor to main-

tain circuit stability and to improve transient response over

temperature and current. In order to insure the circuit

stability, the proper output capacitor value should be larger

than 2.2µF. With X5R and X7R dielectrics, 2.2µF is suffi-

cient at all operating temperatures. Large output capaci-

tor value can reduce noise and improve load-transient

response and PSRR, however it also affects power on

issue. Equation (1) shows the relationship between the

maximum COUT value and VOUT.

)1........(..........

0.1155

-0.5587COUT

OUT(max) 













⋅=

Where the unit of COUT is µF and VOUT is V. Figure 1 shows

the curve of maximum output capacitor over the output

voltage. The output voltage range is from 0.8 to 5.5V and

the output capacitor value should be under the line. Out-

put capacitors must be placed at the load and ground pin

as close as possible and the impedance of the layout

must be minimized.

0 1 2 3 4 5 6

Output Capacitor (uF)

Output voltage (V)

Figure 1

Operation Region and Power dissipation

The APL5315 maximum power dissipation depends

on the thermal resistance and temperature difference

between the die junction and ambient air. The power dis-

sipation PD across the device is:

PD = (TJ - TA) / θJA

where (TJ-TA) is the temperature difference between the

junction and ambient air. θJA is the thermal resistance

between Junction and ambient air. Assuming the

TA=25oC and maximum TJ=160oC (typical thermal limit

threshold), the maximum power dissipation is calcu-

lated as:

PD(max)=(160-25)/240

= 0.56(W)

For normal operation, do not exceed the maximum junc-

tion temperature rating of TJ = 125 oC. The calculated power

dissipation should less than:

PD =(125-25)/240

= 0.41(W)

The GND provides an electrical connection to ground and

channels heat away. Connect the GND to ground by

using a large pad or ground plane.

Layout Considerations

Figure 2 illustrates the layout. Below is a checklist for

yours layout:

1. Please place the input capacitors close to the VIN.

2. Ceramic capacitors for load must be placed near

the load as close as possible.

3. To place APL5315 and output capacitors near the

load is good for performance.

4. Large current paths, the bold lines in figure 2,

must have wide tracks.

5. Divider resistor R1 and R2 must be placed near

the SET as close as possible.

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw11

Application Information (Cont.)

PCB Layout Consideration( Cont.)

Figure 2

VIN

GND

VOUT

APL5315

VOUT

COUT

SET

LOAD

CIN

VIN

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw12

Package Information

SOT23-5

MAX.

0.057

0.051

0.024

0.006

0.009

0.0200.012

L0.30

0.08

0.30

0.60 0.012

2.80 BSC

0.95 BSC

1.90 BSC

1.60 BSC

0.22

0.50

2.90 BSC

0.110 BSC

0.037 BSC

0.075 BSC

0.063 BSC

0.114 BSC

0.003

MIN.

MILLIMETERS

0.00

0.90

SOT23-5

MAX.

1.45

0.15

1.30

MIN.

0.000

0.035

INCHES

VIEW A

0.25

GAUGE PLANE

SEATING PLANE

A2A1

SEE

VIEW A

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw13

Carrier Tape & Reel Dimensions

Application Carrier Width Cover Tape Width Devices Per Reel

SOT23-5 8 5.3 3000

Cover Tape Dimensions

(mm)

Po P

Application

A B C J T1 T2 W P E

178 ±1

72 ± 1.0

13.0 + 0.2

2.5 ± 0.15

8.4 ± 2

1.5 ± 0.3

8.0 ± 0.3

4 ± 0.1

1.75± 0.1

F D D1 Po P1 Ao Bo Ko t

SOT-23-5

3.5 ± 0.05

1.5± 0.1

4.0 ± 0.1

2.0 ± 0.1

3.15 ± 0.1

3.2± 0.1

1.4± 0.1

0.2±0.033

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw14

Terminal Material Solder-Plated Copper (Solder Material: 90/10 or 63/37 SnPb), 100%Sn

Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.

Physical Specifications

Reflow Condition (IR/Convection or VPR Reflow)

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average ramp-up rate

(TL to TP) 3°C/second max. 3°C/second max.

Preheat

- Temperature Min (Tsmin)

- Temperature Max (Tsmax)

- Time (min to max) (ts)

100°C

150°C

60-120 seconds

150°C

200°C

60-180 seconds

Time maintained above:

- Temperature (TL)

- Time (tL) 183°C

60-150 seconds 217°C

60-150 seconds

Peak/Classification Temperature (Tp) See table 1 See table 2

Time within 5°C of actual

Peak Temperature (tp) 10-30 seconds 20-40 seconds

Ramp-down Rate 6°C/second max. 6°C/second max.

Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.

Notes: All temperatures refer to topside of the package. Measured on the body surface.

t 25 C to Peak

Ramp-up

Ramp-down

Preheat

Tsmax

Tsmin

Temperature

Time

Critical Zone

TL to TP

Rev. A.2 - Mar., 2007

APL5315

www.anpec.com.tw15

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

7F, No. 137, Lane 235, Pao Chiao Rd.,

Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.

Tel : 886-2-89191368

Fax : 886-2-89191369

Test item Method Description

SOLDERABILITY MIL-STD-883D-2003 245°C, 5 SEC

HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C

PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C

TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles

ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V

Latch-Up JESD 78 10ms, 1tr > 100mA

Reliability Test Program

Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 240 +0/-5°C 225 +0/-5°C

≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Table 2. Pb-free Process – Package Classification Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*

1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*

≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*

* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated

classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL

level.

Classification Reflow Profiles (Cont.)