1
Data sheet acquired from Harris Semiconductor
SCHS142F
September 1997 - Revised October 2003
Features
• Overriding Reset Terminates Output Pulse
• Triggering From the Leading or Trailing Edge
• Q and Q Buffered Outputs
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on Both A and B Inputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are
dual monostable multivibrators with resets. They are all
retriggerable and differ only in that the 123 types can be
triggered by a negative to positive reset pulse; whereas the
423 types do not have this feature. An external resistor (RX)
and an external capacitor (CX) control the timing and the
accuracy for the circuit. Adjustment of Rx and CXprovides a
wide range of output pulse widths from the Q and Q
terminals. Pulse triggering on the A and B inputs occur at a
particular voltage level and is not related to the rise and fall
times of the trigger pulses.
Once triggered, the output pulse width may be extended by
retriggering inputs A and B. The output pulse can be
terminated by a LOW level on the Reset (R) pin. Trailing
edge triggering (A) and leading edge triggering (B) inputs
are provided for triggering from either edge of the input
pulse. If either Mono is not used each input on the unused
device (A, B, and R) must be terminated high or low.
The minimum value of external resistance, Rx is typically
5kΩ. The minimum value external capacitance, CX, is 0pF.
The calculation for the pulse width is t
W
= 0.45 R
X
C
X
at
V
CC
= 5V.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD54HC123F3A -55 to 125 16 Ld CERDIP
CD54HCT123F3A -55 to 125 16 Ld CERDIP
CD74HC123E -55 to 125 16 Ld PDIP
CD74HC123M -55 to 125 16 Ld SOIC
CD74HC123MT -55 to 125 16 Ld SOIC
CD74HC123M96 -55 to 125 16 Ld SOIC
CD74HC123NSR -55 to 125 16 Ld SOP
CD74HC123PW -55 to 125 16 Ld TSSOP
CD74HC123PWR -55 to 125 16 Ld TSSOP
CD74HC123PWT -55 to 125 16 Ld TSSOP
CD74HC423E -55 to 125 16 Ld PDIP
CD74HC423M -55 to 125 16 Ld SOIC
CD74HC423MT -55 to 125 16 Ld SOIC
CD74HC423M96 -55 to 125 16 Ld SOIC
CD74HC423NSR -55 to 125 16 Ld SOP
CD74HCT123E -55 to 125 16 Ld PDIP
CD74HCT123M -55 to 125 16 Ld SOIC
CD74HCT123MT -55 to 125 16 Ld SOIC
CD74HCT123M96 -55 to 125 16 Ld SOIC
CD74HCT423E -55 to 125 16 Ld PDIP
CD74HCT423MT -55 to 125 16 Ld SOIC
CD74HCT423M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54/74HC123, CD54/74HCT123,
CD74HC423, CD74HCT423
High-Speed CMOS Logic Dual Retriggerable
Monostable Multivibrators with Resets
[ /Title
(CD74
HC123
,
CD74
HCT12
3,
CD74
HC423
,
CD74
HCT42
3)
/Sub-
ject
(High
Speed
2
Pinout
CD54HC123, CD54HCT123
(CERDIP)
CD74HC123
(PDIP, SOIC, SOP, TSSOP)
CD74HC423
(PDIP, SOIC, SOP)
CD74HCT123, CD74HCT423
(PDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1A
1B
1R
1Q
2Q
2CX
GND
2RXCX
VCC
1CX
1Q
2Q
2R
2B
2A
1RXCX2R 11
2A 9
10
5
12 2Q
2Q
2B MONO 2
VCC
67
2Cx 2RxCx
1R 3
1A
2
1
13
41Q
1Q
1B
MONO 1
VCC
14 15
1Cx 1RxCx
1Cx 1Rx
2Cx 2Rx
TRUTH TABLE
INPUTS OUTPUTS
ABRQQ
CD74HC/HCT123
HXHLH
XLHLH
L↑H
↓HH
XXLLH
LH↑
CD74HC/HCT423
HXHLH
XLHLH
L↑H
↓HH
XXLLH
H = High Voltage Level, L = Low Voltage Level,
X = Don’t Care.
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
4
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
All 0.35
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.
360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
Minimum Input,
Pulse Width tWL
A 2 100 - - 125 - - 150 - - ns
4.5 20 - - 25 - - 30 - - ns
617- -21- -26--ns
Bt
WH 2 100 - - 125 - - 150 - - ns
4.5 20 - - 25 - - 30 - - ns
617- -21- -26--ns
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
5
Rt
WL 2 100 - - 125 - - 150 - 150 ns
4.5 20 - - 25 - - 30 - 30 ns
6 17 - - 21 - - 26 - 26 ns
A and B Hold Time tH2 50 - - 65 - - 75 - 75 ns
4.5 10 - - 13 - - 15 - 15 ns
6 9 - - 11 - - 13 - 13 ns
Reset Removal Time tREM 2 50 - - 65 - - 75 - 75 ns
4.5 10 - - 13 - - 15 - 15 ns
6 9 - - 11 - - 13 - 13 ns
Retrigger Time Number trT 5---------ns
RX = 10KΩ, CX = 0 - 50 - - 63 - - 76 - ns
Output Pulse Width tW5
Q or Q
RX= 10KΩ,C
X= 10nF 40 - 50 38.7 - 51.3 38.2 - 51.8 µs
HCT TYPES
Minimum Input,
Pulse Width tWL 5-
A20--25--30--ns
Bt
WH 20 - - 25 - - 30 - - ns
Rt
WL 20 - - 25 - - 30 - - ns
A and B Hold Time tH510- -13- -15--ns
Reset Removal Time tREM 510- -13- -15 -ns
Retrigger Time Number
(Note 3)
RX = 10KΩ, CX = 0 trT 5 - 50 - - 63 - - 76 - ns
Output Pulse Width Q or Q tW5 40 - 50 38.7 - 51.3 38.2 - 51.8 µs
RX= 10KΩ,C
X= 10nF
NOTE:
3. Time to trigger depends on the values of RX and CX. The output pulse width can only be extended when the time between the active-
going edges of the trigger input pulses meet the minimum retrigger time requirement.
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
6
Switching Specifications Input tr, tf= 6ns, RX = 10KΩ, CX = 0
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oCUNIT
SMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Trigger Propagation Delay tPLH CL = 50pF
A, B, R to Q 2 - - 300 - 375 - 450 ns
4.5 - - 60 - 75 - 90 ns
CL = 15pF 5 - 25 - - - - - ns
CL = 50pF 6 - - 51 - 64 - 76 ns
A, B, R to Qt
PHL CL = 50pF 2 - - 320 - 400 - 480 ns
4.5 - - 64 - 80 - 96 ns
CL = 15pF 5 - 26 - - - - - ns
CL = 50pF 6 - - 54 - 68 - 82 ns
Reset Propagation Delay tPHL,t
PLH CL = 50pF 2 - - 215 - 270 - 325 ns
R to Q or Q 4.5 - - 43 - 54 - 65 ns
6 - - 37 - 46 - 55 ns
Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Output Pulse Width
RX = 10KΩ, CX = 10nF - - 5 - 45 - - - - - µs
Pulse Width Match Between
Circuits In the Same Package
RX = 10KΩ, CX = 10pF
--5-±2- - - - - %
PowerDissipationCapacitance
(Note 4) CPD CL = 15pF 5 - - - - - - - pF
Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF
HCT TYPES
Trigger Propagation Delay
A, B, R to QtPLH CL = 50pF 4.5 - - 60 - 75 - 90 ns
CL = 15pF 5 - 25 - - - - - ns
A, B, R to Qt
PHL CL = 50pF 4.5 - - 68 - 85 - 102 ns
CL =15pF 5 - 27 - - - - - ns
Reset Propagation Delay
R to Q or QtPHL,t
PLH CL = 50pF 4.5 - - 48 - 60 - 72 ns
Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns
Output Pulse Width
RX = 10KΩ, CX = 10nF - - 5 - 45 - - - - - µs
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
7
Switching Specifications Input tr, tf= 6ns, RX = 10KΩ, CX = 0 (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oCUNIT
SMIN TYP MAX MIN MAX MIN MAX
Pulse Width Match Between
Circuits In the Same Package
RX = 10KΩ, CX = 10pF
--5 ±2- - - - - %
Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF
NOTE:
4. CPD is used to determine the dynamic power consumption, per multivibrator.
PD = (CPD + CX) VCC2 fi∑(CL VCC2 fO)
Where
fi = input frequency
fO = Output Frequency
CL = Output Load Capacitance
CX = External Capacitance
VCC = Supply Voltage,
assuming fi « I
tW
-
--
---
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
8
Test Circuits and Waveforms
FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT
(R) PULSE FOR 123 FIGURE 2. OUTPUT PULSE CONTROL USING RESET INPUT
(R) FOR 423
FIGURE 3. TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD tW
FIGURE 4. TYPICAL OUTPUT PULSE WIDTH AS A FUNCTION
OF CX FOR RX = 10kΩ AND 100kΩFIGURE 5. TYPICAL “K” FACTOR AS A FUNCTION OF VCC
B = LOW
A = HIGH
tWtW
VS
VS
Q
R
B
A
tWtW
A
B
R
B = LOW
A = HIGH
Q
tW
VS
VS
tWtW
A
B
B
A
Q
trT
(R = HIGH)
tWtW
tW
tW
N
OTE: Output pulse control using retrigger pulse for 123 and 423.
VS
OUTPUT PULSE WIDTH (µs)
2
4
6
8
103
102
101
2
4
6
8
2
4
6
8
2
4
6
8
EXTERNAL CAPACITANCE (CX) - pF
2468
1031042 4 68 2 4 68 2 4 68
105106107
RX = 100kΩ
RX = 10kΩ
DC SUPPLY VOLTAGE (VCC) = 5V
AMBIENT TEMPERATURE (TA) = 25oC
EXTERNAL CAPACITANCE (CX) = 10nF
EXTERNAL RESISTANCE (RX) = 10kΩ TO 100kΩ
AMBIENT TEMPERATURE (TA) = 25oC
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1 1234 567891011
“K” FACTOR
HCT
DC SUPPLY VOLTAGE (VCC) - VOLTS
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8684701EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-8970001EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
CD54HC123F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC123F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT123F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC123E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC123EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC123M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74HC123PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC123PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC423EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC423M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74HC423NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC423NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT123EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT123M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT123MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT423E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT423EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT423M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT423M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT423M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74HCT423MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT423MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT423MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC123, CD54HCT123, CD74HC123, CD74HCT123 :
•Catalog: CD74HC123, CD74HCT123
•Military: CD54HC123, CD54HCT123
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 5
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC123NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC123PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC123PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC423M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC423NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HCT123M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT423M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC123NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC123PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC123PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HC423M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC423NSR SO NS 16 2000 367.0 367.0 38.0
CD74HCT123M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT423M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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