74HC/HCT533 MSI OCTAL D-TYPE TRANSPARENT LATCH; 3-STATE; INVERTING FEATURES @ 3state i ti 3s ate inver ing ourputs for | TYPICAL 5 oriented applications SYMBOL | PARAMETER CONDITIONS UNIT @ Common 3-state output enable input I HC HCT Output capability: bus driver Icc category: MSI PHL! | Ded, delay Cy = 15 pF a | 16 [ns PLH | LE top Veo =5V 1g | 19 J ns GENERAL DESCRIPTION | The 74HC/HCT533 are high-speed 1 input capacitance 38 | 35 | PF Sane with Tow power Schottky Cep power cissiPatiOn on notes tand2 | 34 | 34 | pF TTL (LSTTLI, They are specified in capacitance per late _| compliance with JEDEC standard no. 7A. The 74HC/HCT533 are octal D-type transparent latches f eaturing separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to ail latches. The 533 consists of eight D-type transparent latches with 3-state inverting outputs. When LE is HIGH, data at the Dp inputs enter the latches. In this condition the latches are transparent, i.e. a latch output wiil change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the O-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OF F-state. Operation of the OE input does not affect the state of the latches. The 533 is functionally identical to the "373", "563" and 573, but the 373" and 573" have non-inverted outputs and the 563 and "573" have a different pin arrangement. GND = 0 V; Tamp = 25C; ty = ty = 6 ns Notes 1. Cpo is used to determine the dynamic power dissipation (Pp in nW): Po = Cpp x Vec* x f+ (CL x VCC? x fo) where: fj = input frequency in MHz Ci = - = _~ output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V Z(CL x Voc? x fy) = sum of outouts 2. For HC the condition is V| = GND to Vcc For HCT the condition is V} = GND to Vcc 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION [ PIN NO. | SYMBOL NAME AND FUNCTION Fr | OE d-state output enable input (active LOW) 15 4 e ?, Gg to G7 3-state latch outputs 3, 4, 7, 8, 13, . 14, 17. &. 3 Oo to D7 data inputs 10 GND ground (0 V) 11 LE latch enable input {active HIGH) 20 Vec positive supply voltage et] VU [ave Go (2 13] 8 00 ra o> ae ios a,[6 6] G S| Gl, S a, (4 is] Bs nO] = 23 fe] 13] 04 a] fia] Se GND ]10 [jue 7290988 Fig. 1 Pin configuration. {a LE I-{Oq dg p 2 so, 4, ps 1-0, QP 6 e407 po wo, Of 0s5 Os p 15 17 40g Og fo 16 16-07 0, 19 OE t 729098) 72908601 Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. December 1990 65774HC/HCT533 MSI 2/0 |_| Sol 4s = pois 2182 216 3]23 Sle lo LATCH [7] 3-STATE ar 4 ays Vto8 | ouTPuTs fpS be 14/5 WESTER 120s L [Gels D 6 1ayP7 | Jz t8 ANGE | Le 7z90987.t {OE 7zZ90086 Fig. 4 Functional diagram. Fig. 5 Logic diagram (one latch}. FUNCTION TABLE INPUTS OUTPUTS |orerarine MODES aes ' BE) LE| Dy Qq to G7 enable and read ;L JH [Lt L H register L H |H H L i H = HIGH voltage level ee mode} h = HIGH yoltage level one set-up prior to \ L H the HIGH-to-LOW LE transition lroaewr read C ; c h H L L = LOW voltage level I t | = LOW voltage level ont set-up prior to iNatch register and HIXIX x Zz the HIGH-to-LOW LE transition [disble outputs H | xX |X x z X = dont care Z = high impedance OF F-state a9 Oy 0, Dy D4 Ds Dg D> Y. ab Oo aMe o an 0 Qry o Q 3 aR 0 Q 0 qa LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH 1 2 3 4 5 6 ? 8 TE Le i Le tE ue cE LE t .e te le Eve LE ve Lt mn qT LT | LI Li | e Dold. | | | | l $ ? do a, a> ay a, as a a 1290988 Fig. 6 Logic diagram. 658 March 1988Octal D-type transparent latch; 3-state; inverting 74HC/HCT533 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver toc category: MSI AC CHARACTERISTICS FOR 74HC GND =O V;t, =t=6ns;C, = 50 pF [ Tamb (C) TEST CONDITIONS 74HC | SYMBOL | PARAMETER UNIT | Voc | WAVEFORMS +25 40 to +85 | 40 to +125 Vv min. | typ. | max. | min. | max. | min. | max. ; 47 | 150 190 225 2.0 tPHL/ _| propagation delay 17 | 30 38 45 | ns 45 | Fig.7 'PLH On to On 14 | 26 33 38 60 . 58 | 175 220 265 2.0 teyL/ propagation delay 21 135 44 53 ns 45 Fig. 8 'PLH LE to On 17 130 37 45 6.0 tpzH/ 3-state output enable time te xO ee 228 ns ze Fig. 9 1PZL DE to Oy 13 | 26 33 38 6.0 tpyz/ 3-state output disable time O . 328 ns ae Fig. 9 PLZ OE to Q, 14 | 26 33 38 6.0 erat / 14 | 60 75 90 2.0 | CHEN output transition time ; 6 ie ns eo Fig. 7 . go | 14 100 120 2.0 tw LE pulse width 16 |S 20 24 ns | 4.5 | Fig. 8 HIGH 14 | 4 17 20 6.0 set-up time 50 |3 65 78 2.0 et-u 7 t 10 | 1 13 16 ns 45 Fig. 10 su Dn to LE 9 1 "1 13 6.0 . 35 {3 45 55 2.0 th si 7 |1 9 1 ns 4.5 | Fig. 10 nto 6 |1 8 9 6.0 March 1988 65974HC/HCT533 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver lec category: MSI Note to HCT types The value of additional quiescent supply current (Alcc) for a unit load of 1 is given in the family specifications. To determine Alec per input, muitiply this vatue by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT Dn 0.18 LE 0.30 GE | 0.55 AC CHARACTERISTICS FOR 74HCT GND =O Vt, = t = 6 ns; CL = 50 pF | Tamb (C) TEST CONDITIONS | 74HCT SYMBOL | PARAMETER t UNIT | V WAVEFORMS | cc i +25 40 to +85 | 40to +125 1 ov | min. typ. | max, | min.| max. | min. | max. teHL/ | propagation delay . IPLH | Dp to Gn 19 34 43 51 ns 4.5 Fig. 7 teHL/ propagation delay | . tPLH i" LE to Gp 22 | 38 48 57 ns 45 Fig. 8 tpzH/ | 3-state output enable time : tP2L | OE to Gy, 19 | 35 44 53 ns 45 Fig. 9 tpHz/ |: 3-state output disable time . tPLz OE to On 18 | 30 38 45 ns 45 Fig. 9 THL/ | output transition time 5 | 12 15 18 | ns 45 | Fig.7 tTLH ty LE ule width 16 | 5 20 24 ns 6145 | Fig. 8 ! set-up time . tsu D, to LE 10 | 3 13 15 ns 4.5 | Fig. 10 hold time . th Dp to LE 8 2 10 12 ns 4.5 Fig. 10 660 March 1988Octal D-type transparent latch; 3-state; inverting | 74HC/HCT533 MSI AC WAVEFORMS r v / , LE (INPUT / vu D,, INPUT Via Me le Tp Le! G, ouTeuT @,, OUTPUT 1Ze7ae8 4 ae OTHE wel ee OT LH rza7eay trHy ol i Fig. 8 Waveforms showing the latch enable input Fig. 7 Waveforms showing the data input (D,) (LE) pulse width, the latch enable input to to output (O,) propagation delays and the output (Gp) Propagation delays and the output transition times. output transition times. 0, INPUT O INPUT Gd, OUTPUT LOW-ta-OFF LE INPUT OFF -10-LOW TZ87866 le paz oy hae TRZH es . - 4 . Fig. 10 Waveforms showing the data set-up and a, OUTPUT ! + . . WIGH-10- OFF hold times for Dp input to LE input. OFF -to- HIGH | OUTDUTS ele UT DUS le OUTS: 7296101 enapied disabled anadied Note to Fig. 10 The shaded areas indicate when the input is Fig. 9 Waveforms showing the 3-state enable permitted to change for predictable output and disable times, performance. Note to AC waveforms (1) HC: Vy = 50%; V) = GND to Voc. HCT: Vy = 1.3. V; V) = GND to 3Vv. January 1986 661