MC74HC244A Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver High-Performance Silicon-Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two active-low output enables. The HC244A is similar in function to the HC240A. http://onsemi.com MARKING DIAGRAMS 20 PDIP-20 N SUFFIX CASE 738 1 Features * * * * * * * * * 20 MC74HC244AN AWLYYWWG 1 20 Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 136 FETs or 34 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant SOIC-20 DW SUFFIX CASE 751D 20 1 HC244A AWLYYWWG 1 20 HC 244A ALYWG G TSSOP-20 DT SUFFIX CASE 948E 20 1 1 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (*Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. (c) Semiconductor Components Industries, LLC, 2012 July, 2012 - Rev. 14 1 Publication Order Number: MC74HC244A/D MC74HC244A PIN ASSIGNMENT ENABLE A 1 20 VCC A1 2 19 ENABLE B YB4 3 18 YA1 A2 4 17 B4 YB3 5 16 YA2 A3 6 15 B3 YB2 7 14 YA3 A4 8 13 B2 YB1 9 12 YA4 GND 10 11 B1 LOGIC DIAGRAM A1 A2 A3 A4 DATA INPUTS B1 B2 B3 FUNCTION TABLE Inputs Enable A, Enable B A, B B4 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 YA1 YA2 YA3 YA4 YB1 NONINVERTING OUTPUTS YB2 YB3 YB4 Outputs YA, YB L L L H H X Z = high impedance L H Z OUTPUT ENABLES 1 ENABLE A 19 ENABLE B PIN 20 = VCC PIN 10 = GND ORDERING INFORMATION Package Shipping PDIP-20 (Pb-Free) 18 Units / Rail MC74HC244ADWG SOIC-20 WIDE (Pb-Free) 38 Units / Rail MC74HC244ADWR2G SOIC-20 WIDE (Pb-Free) 1000 / Tape & Reel MC74HC244ADTG TSSOP-20 (Pb-Free) 75 Units / Rail MC74HC244ADTR2G TSSOP-20 (Pb-Free) 2500 / Tape & Reel NLV74HC244ADWR2G* SOIC-20 WIDE (Pb-Free) 1000 / Tape & Reel NLV74HC244ADTR2G* TSSOP-20 (Pb-Free) 2500 / Tape & Reel Device MC74HC244ANG For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable http://onsemi.com 2 MC74HC244A MAXIMUM RATINGS Symbol Parameter Value Unit - 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 35 mA ICC DC Supply Current, VCC and GND Pins 75 mA IIK Input Clamp Current (VI < 0 or VI > VCC) 20 mA IOK Output Clamp Current (VO < 0 or VO > VCC) 20 mA PD Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types - 55 + 125 _C tr, tf Input Rise and Fall Time VCC = 2.0 V (Figure 1) VCC = 4.5 V VCC = 6.0 V 0 0 0 1000 500 400 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Test Conditions VCC V - 55 to 25_C Symbol Parameter v 85_C v 125_C Unit VIH Minimum High-Level Input Voltage Vout = VCC - 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High-Level Output Voltage Vin = VIH |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin = VIH |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 http://onsemi.com 3 MC74HC244A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VOL VCC V - 55 to 25_C v 85_C v 125_C Unit Vin = VIL |Iout| v 20 mA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Parameter Test Conditions Maximum Low-Level Output Voltage Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 mA IOZ Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 0.5 5.0 10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C v85_C v125_C Unit tPLH, tPHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) 2.0 3.0 4.5 6.0 96 50 18 15 115 60 23 20 135 70 27 23 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 60 22 19 140 70 28 24 165 80 33 28 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 60 22 19 140 70 28 24 165 80 33 28 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns Cin Maximum Input Capacitance - 10 10 10 pF Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) - 15 15 15 pF Typical @ 25C, VCC = 5.0 V CPD 34 Power Dissipation Capacitance (Per Buffer)* * Used to determine the no-load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC . http://onsemi.com 4 pF MC74HC244A SWITCHING WAVEFORMS tr tf DATA INPUT A OR B VCC VCC 90% 50% 10% ENABLE A OR B GND tPLH 50% GND tPHL 90% 50% 10% OUTPUT YA OR YB tPLZ tPZL OUTPUT Y tPZH tTLH tTHL HIGH IMPEDANCE 50% OUTPUT Y tPHZ 10% VOL 90% VOH 50% Figure 1. HIGH IMPEDANCE Figure 2. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit PIN DESCRIPTIONS INPUTS function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state. A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17) OUTPUTS Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled. YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3) Device outputs. Depending upon the state of the output-enable pins, these outputs are either noninverting outputs or high-impedance outputs. CONTROLS Enable A, Enable B (Pins 1, 19) Output enables (active-low). When a low level is applied to these pins, the outputs are enabled and the devices http://onsemi.com 5 MC74HC244A LOGIC DETAIL TO THREE OTHER A OR B INVERTERS ONE OF 8 INVERTERS VCC DATA INPUT A OR B YA OR YB ENABLE A OR ENABLE B http://onsemi.com 6 MC74HC244A PACKAGE DIMENSIONS PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. -A- 20 11 1 10 B L C -T- K SEATING PLANE M N E G F J D 20 PL 20 PL 0.25 (0.010) 0.25 (0.010) M T A M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 M SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G A 20 11 X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HC244A PACKAGE DIMENSIONS TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V IIII IIII IIII K K1 S J J1 11 B -U- PIN 1 IDENT 1 SECTION N-N 0.25 (0.010) N 10 M 0.15 (0.006) T U S N A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. F DETAIL E -W- C G D 0.100 (0.004) -T- SEATING H DETAIL E SOLDERING FOOTPRINT PLANE DIM A B C D F G H J J1 K K1 L M 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC244A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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