MX25L1606E MX25L1606E 3V, 16M-BIT [x 1/x 2] CMOS SERIAL FLASH MEMORY Key Features * Hold Feature * Low Power Consumption * Auto Erase and Auto Program Algorithms * Additional 512 bit secured OTP for unique identifier P/N: PM1548 1 Rev. 1.9, November 13, 2017 MX25L1606E Contents FEATURES................................................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 6 PIN CONFIGURATIONS .............................................................................................................................................. 7 PIN DESCRIPTION....................................................................................................................................................... 8 BLOCK DIAGRAM........................................................................................................................................................ 9 MEMORY ORGANIZATION........................................................................................................................................ 10 Table 1. Memory Organization............................................................................................................................ 10 DEVICE OPERATION................................................................................................................................................. 11 Figure 1. Serial Modes Supported....................................................................................................................... 11 DATA PROTECTION................................................................................................................................................... 12 Table 2. Protected Area Sizes............................................................................................................................. 13 Table 3. 512 bit Secured OTP Definition............................................................................................................. 14 HOLD FEATURE......................................................................................................................................................... 15 Figure 2. Hold Condition Operation .................................................................................................................... 15 COMMAND DESCRIPTION........................................................................................................................................ 16 Table 4. COMMAND DEFINITION...................................................................................................................... 16 (1) Write Enable (WREN).................................................................................................................................... 17 (2) Write Disable (WRDI)..................................................................................................................................... 17 (3) Read Status Register (RDSR)....................................................................................................................... 17 Table 5. Status Register...................................................................................................................................... 18 (4) Write Status Register (WRSR)....................................................................................................................... 18 Table 6. Protection Modes................................................................................................................................... 19 (5) Read Data Bytes (READ).............................................................................................................................. 20 (6) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 20 (7) Dual Output Mode (DREAD).......................................................................................................................... 20 (8) Sector Erase (SE).......................................................................................................................................... 20 (9) Block Erase (BE)............................................................................................................................................ 21 (10) Chip Erase (CE)........................................................................................................................................... 21 (11) Page Program (PP)...................................................................................................................................... 21 (12) Deep Power-down (DP)............................................................................................................................... 22 (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .............................................. 22 (14) Read Identification (RDID)........................................................................................................................... 23 (15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................... 23 Table 7. ID DEFINITIONS .................................................................................................................................. 23 (16) Enter Secured OTP (ENSO)........................................................................................................................ 23 (17) Exit Secured OTP (EXSO)........................................................................................................................... 24 (18) Read Security Register (RDSCUR)............................................................................................................. 24 Table 8. SECURITY REGISTER DEFINITION.................................................................................................... 24 (19) Write Security Register (WRSCUR)............................................................................................................. 24 P/N: PM1548 2 Rev. 1.9, November 13, 2017 MX25L1606E (20) Read SFDP Mode (RDSFDP)...................................................................................................................... 25 Figure 3. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence...................................................... 25 Table 9. Signature and Parameter Identification Data Values ............................................................................ 26 Table 10. Parameter Table (0): JEDEC Flash Parameter Tables........................................................................ 27 Table 11. Parameter Table (1): Macronix Flash Parameter Tables...................................................................... 29 POWER-ON STATE.................................................................................................................................................... 31 ELECTRICAL SPECIFICATIONS............................................................................................................................... 32 ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 32 Figure 4. Maximum Negative Overshoot Waveform........................................................................................... 32 CAPACITANCE TA = 25C, f = 1.0 MHz.............................................................................................................. 32 Figure 5. Maximum Positive Overshoot Waveform............................................................................................. 32 Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................... 33 Figure 7. OUTPUT LOADING............................................................................................................................ 33 Figure 8. SCLK TIMING DEFINITION................................................................................................................. 33 Table 12. DC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V - 3.6V).... 34 Table 13. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V - 3.6V).... 35 Timing Analysis......................................................................................................................................................... 36 Figure 9. Serial Input Timing............................................................................................................................... 36 Figure 10. Output Timing..................................................................................................................................... 36 Figure 11. Hold Timing........................................................................................................................................ 37 Figure 12. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 37 Figure 13. Write Enable (WREN) Sequence (Command 06h)............................................................................ 38 Figure 14. Write Disable (WRDI) Sequence (Command 04h)............................................................................. 38 Figure 15. Read Status Register (RDSR) Sequence (Command 05h)............................................................... 39 Figure 16. Write Status Register (WRSR) Sequence (Command 01h).............................................................. 39 Figure 17. Read Data Bytes (READ) Sequence (Command 03h)..................................................................... 39 Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0Bh).................................................. 40 Figure 19. Dual Output Read Mode Sequence (Command 3Bh)........................................................................ 41 Figure 20. Sector Erase (SE) Sequence (Command 20h)................................................................................. 41 Figure 21. Block Erase (BE) Sequence (Command 52h or D8h)....................................................................... 41 Figure 22. Chip Erase (CE) Sequence (Command 60h or C7h)........................................................................ 42 Figure 23. Page Program (PP) Sequence (Command 02h)............................................................................... 42 Figure 24. Deep Power-down (DP) Sequence (Command B9h) ....................................................................... 43 Figure 25. Release from Deep Power-down (RDP) Sequence (Command ABh).............................................. 43 Figure 26. Read Electronic Signature (RES) Sequence (Command ABh)......................................................... 43 Figure 27. Read Identification (RDID) Sequence (Command 9Fh)..................................................................... 44 Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90h)............................. 44 Figure 29. Read Security Register (RDSCUR) Sequence (Command 2Bh)....................................................... 45 Figure 30. Write Security Register (WRSCUR) Sequence (Command 2Fh)...................................................... 45 Figure 31. Power-up Timing................................................................................................................................ 46 Table 14. Power-Up Timing ................................................................................................................................ 46 P/N: PM1548 3 Rev. 1.9, November 13, 2017 MX25L1606E OPERATING CONDITIONS........................................................................................................................................ 47 Figure 32. AC Timing at Device Power-Up.......................................................................................................... 47 Figure 33. Power-Down Sequence..................................................................................................................... 48 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 49 DATA RETENTION..................................................................................................................................................... 49 LATCH-UP CHARACTERISTICS............................................................................................................................... 49 ORDERING INFORMATION....................................................................................................................................... 50 PART NAME DESCRIPTION...................................................................................................................................... 51 PACKAGE INFORMATION......................................................................................................................................... 52 16-PIN SOP (300mil)........................................................................................................................................... 52 8-PIN SOP (150mil)............................................................................................................................................. 53 8-PIN SOP (200mil)............................................................................................................................................. 54 8-PIN PDIP (300mil)............................................................................................................................................ 55 8-LAND WSON (6x5mm).................................................................................................................................... 56 8-LAND USON (4x4mm)..................................................................................................................................... 57 24-BALL BGA...................................................................................................................................................... 58 REVISION HISTORY .................................................................................................................................................. 59 P/N: PM1548 4 Rev. 1.9, November 13, 2017 MX25L1606E 16M-BIT [x 1 / x 2] CMOS SERIAL FLASH FEATURES GENERAL * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Supports Serial Peripheral Interface -- Mode 0 and Mode 3 * 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure * 512 Equal Sectors with 4K byte each - Any Sector can be erased individually * 32 Equal Blocks with 64K byte each - Any Block can be erased individually * Program Capability - Byte base - Page base (256 bytes) * Latch-up protected to 100mA from -1V to Vcc +1V SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Advanced Security Features - Block lock protection The BP3-BP0 status bit defines the size of the area to be software protection against program and erase instructions - Additional 512 bit secured OTP for unique identifier * Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) * Status Register Feature * Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS commands for 1-byte manufacturer ID and 1-byte device ID * Support Serial Flash Discoverable Parameters (SFDP) mode PERFORMANCE * High Performance - Fast access time: 86MHz serial clock - Serial clock of Dual Output mode : 80MHz - Fast program time: 0.6ms(typ.) and 3ms(max.)/page - Byte program time: 9us (typ.) - Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block * Low Power Consumption - Low active read current: 25mA(max.) at 86MHz - Low active programming current: 15mA (typ.) - Low active sector erase current: 9mA (typ.) - Low standby current: 15uA (typ.) HARDWARE FEATURES * PACKAGE - 16-pin SOP (300mil) - 8-pin SOP (150mil) - 8-pin SOP (200mil) - 8-pin PDIP (300mil) - 8-land WSON (6x5mm) - 8-land USON (4x4mm) - 24-Ball BGA - All devices are RoHS Compliant and Halogenfree - Deep power-down mode 2uA (typ.) * Typical 100,000 erase/program cycles * 20 years of data retention P/N: PM1548 5 Rev. 1.9, November 13, 2017 MX25L1606E GENERAL DESCRIPTION The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output. The device provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis. Erase command is executed on sector, or block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. P/N: PM1548 6 Rev. 1.9, November 13, 2017 MX25L1606E PIN CONFIGURATIONS 16-PIN SOP (300mil) HOLD# VCC NC NC NC NC CS# SO/SIO1 8-PIN SOP (200mil, 150mil) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI/SIO0 NC NC NC NC GND WP# CS# SO/SIO1 WP# GND 1 2 3 4 8 7 6 5 8 7 6 5 VCC HOLD# SCLK SI/SIO0 8-PIN PDIP (300mil) 8-LAND WSON (6x5mm), USON (4x4mm) CS# SO/SIO1 WP# GND 1 2 3 4 VCC HOLD# SCLK SI/SIO0 CS# SO/SIO1 WP# GND 1 2 3 4 8 7 6 5 VCC HOLD# SCLK SI/SIO0 24-BALL BGA 5 4 3 NC NC NC NC NC NC VCC WP# HOLD# NC NC GND NC SI/SIO0 NC NC SCLK CS# SO/SIO1 NC NC NC NC NC B C D E 2 1 A P/N: PM1548 7 Rev. 1.9, November 13, 2017 MX25L1606E PIN DESCRIPTION SYMBOL CS# DESCRIPTION Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for Dual Output mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Output (for Dual Output mode) SCLK Clock Input WP# Write protection HOLD# Hold, to pause the device without deselecting the device VCC + 3.3V Power Supply GND Ground P/N: PM1548 8 Rev. 1.9, November 13, 2017 MX25L1606E BLOCK DIAGRAM X-Decoder Address Generator SI/SIO0 SO/SIO1 SIO2 * SIO3 * WP# * HOLD# * RESET# * CS# SCLK Memory Array Y-Decoder Data Register Sense Amplifier SRAM Buffer Mode Logic State Machine HV Generator Clock Generator Output Buffer * Depends on part number options. P/N: PM1548 9 Rev. 1.9, November 13, 2017 MX25L1606E MEMORY ORGANIZATION Table 1. Memory Organization Block 31 30 Sector 511 : 496 495 : 480 Address Range 1FF000h 1FFFFFh : : 1F0000h 1F0FFFh 1EF000h 1EFFFFh : : 1E0000h 1E0FFFh : : : : : : : : 0 15 : 3 2 1 0 00F000h : 003000h 002000h 001000h 000000h 00FFFFh : 003FFFh 002FFFh 001FFFh 000FFFh P/N: PM1548 10 Rev. 1.9, November 13, 2017 MX25L1606E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. The CS# falling time needs to follow tCHCL spec. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. The CS# rising time needs to follow tCLCH spec. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown in "Figure 1. Serial Modes Supported". 5. For the following instructions:RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, DREAD, RES, and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1548 11 Rev. 1.9, November 13, 2017 MX25L1606E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. * Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. * Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion * Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). * Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. P/N: PM1548 12 Rev. 1.9, November 13, 2017 MX25L1606E I. Block lock protection - The Software Protected Mode (SPM): MX25L1606E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to "Table 2. Protected Area Sizes". - The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L1606E: BP3-BP0 bits and SRWD bit. Table 2. Protected Area Sizes Status bit Protect Level BP3 BP2 BP1 BP0 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 31st) 0 0 1 0 2 (2blocks, block 30th-31st) 0 0 1 1 3 (4blocks, block 28th-31st) 0 1 0 0 4 (8blocks, block 24th-31st) 0 1 0 1 5 (16blocks, block 16th-31st) 0 1 1 0 6 (32blocks, all) 0 1 1 1 7 (32blocks, all) 1 0 0 0 8 (32blocks, all) 1 0 0 1 9 (32blocks, all) 1 0 1 0 10 (16blocks, block 0th-15th) 1 0 1 1 11 (24blocks, block 0th-23rd) 1 1 0 0 12 (28blocks, block 0th-27th) 1 1 1 1 0 1 1 0 13 (30blocks, block 0th-29th) 14 (31blocks, block 0th-30th) 1 1 1 1 15 (32blocks, all) P/N: PM1548 MX25L1606E 13 Rev. 1.9, November 13, 2017 MX25L1606E II. Additional 512 bit secured OTP for unique identifier: to provide 512 bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 512 bit Secured OTP Definition". - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 512 bit secured OTP by entering 512 bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 512 bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 8. SECURITY REGISTER DEFINITION" for security register bit definition and "Table 3. 512 bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512 bit secured OTP mode, array access is not allowed. Table 3. 512 bit Secured OTP Definition Address range Size Standard Factory Lock xxxx00-xxxx0F 128-bit ESN (electrical serial number) xxxx10-xxxx3F 384-bit N/A P/N: PM1548 14 Customer Lock Determined by customer Rev. 1.9, November 13, 2017 MX25L1606E HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low). SI/SIO0 SO/SIO1 (internal) SO/SIO1 (External) Don't care Valid Data Valid Data High_Z Bit 6 Bit 5 Bit 6 SO/SIO1 (internal) SO/SIO1 (External) High_Z Bit 7 Bit 5 SI/SIO0 HOLD# SCLK Valid Data Bit 6 Bit 7 CS# Don't care Bit 7 HOLD# SCLK CS# Figure 2. Hold Condition Operation Don't care Valid Data Bit 7 Bit 7 Valid Data Bit 6 High_Z Don't care Bit 5 Bit 6 Bit 5 Valid Data Bit 4 High_Z Bit 3 Bit 4 Bit 3 During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1548 15 Rev. 1.9, November 13, 2017 MX25L1606E COMMAND DESCRIPTION Table 4. COMMAND DEFINITION WRSR RDID RDSR FAST READ Command WREN WRDI READ (write status (read identific- (read status (fast read (byte) (write enable) (write disable) (read data) register) ation) register) data) 1st byte 06 (hex) 04 (hex) 01 (hex) 9F (hex) 05 (hex) 03 (hex) 0B (hex) 2nd byte AD1 AD1 3rd byte AD2 AD2 4th byte AD3 AD3 th 5 byte Dummy sets the (WEL) resets the to write new outputs to read out n bytes read n bytes read write enable (WEL) write values to the JEDEC the values out until CS# out until CS# latch bit enable latch status register ID: 1-byte of the status goes high goes high Action bit Manufact-urer register ID & 2-byte Device ID REMS (read DREAD RES electronic (Double SE BE CE (read manufacturer Output Mode (sector erase) (block erase) (chip erase) electronic ID) & device ID) command) 5A (hex) AB (hex) 90 (hex) 3B (hex) 20 (hex) 52 or D8 (hex) 60 or C7 (hex) AD1 x x AD1 AD1 AD1 AD2 x x AD2 AD2 AD2 AD3 x ADD(Note 1) AD3 AD3 AD3 Dummy Dummy Read SFDP to read out output the n bytes read to erase the to erase the to erase mode 1-byte Device Manufacturer out by Dual selected selected whole chip ID ID & Device Output until sector block ID CS# goes high Command RDSFDP (byte) (Read SFDP) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action Command (byte) PP (page program) 1st byte 2nd byte 3rd byte 4th byte 5th byte 02 (hex) AD1 AD2 AD3 Action RDSCUR WRSCUR RDP (Release ENSO (enter EXSO (exit DP (Deep (read security (write security from deep secured OTP) secured OTP) power down) register) register) power down) 2B (hex) 2F (hex) B1 (hex) C1 (hex) B9 (hex) AB (hex) to program to read value to set the to enter to exit the 512 enters deep the selected of security lock-down bit the 512 bit bit secured power down page register as "1" (once secured OTP OTP mode mode lock-down, mode cannot be updated) release from deep power down mode Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. P/N: PM1548 16 Rev. 1.9, November 13, 2017 MX25L1606E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low sending WREN instruction code CS# goes high. The sequence is shown as "Figure 13. Write Enable (WREN) Sequence (Command 06h)". (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low sending WRDI instruction code CS# goes high. The sequence is shown as "Figure 14. Write Disable (WRDI) Sequence (Command 04h)". The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low sending RDSR instruction code Status Register data out on SO. The sequence is shown as "Figure 15. Read Status Register (RDSR) Sequence (Command 05h)". The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. P/N: PM1548 17 Rev. 1.9, November 13, 2017 MX25L1606E BP3, BP2, BP1, BP0 bits. The Block Protect (BP3-BP0) bits, non-volatile bits, indicate the protected area(as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3-BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3-BP0) are read only. The SRWD bit defaults to be "0". Table 5. Status Register bit7 bit6 SRWD (status register write protect) 1=status register write disabled 0=status register write enabled 0 0 bit5 BP3 (level of protected block) (note 1) bit4 BP2 (level of protected block) (note 1) Non-volatile Non-volatile bit bit Note 1: Please refer to "Table 2. Protected Area Sizes". Non-volatile bit 0 bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write operation enable 0=not write 0=not in write enable operation volatile bit volatile bit (4) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3-BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal (Please refer to "Figure 12. WP# Disable Setup and Hold Timing during WRSR when SRWD=1"). The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The WRSR instruction has no effect on b6, b1, b0 of the status register. The sequence of issuing WRSR instruction is: CS# goes low sending WRSR instruction code Status Register data on SI CS# goes high. The sequence is shown as "Figure 16. Write Status Register (WRSR) Sequence (Command 01h)". The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. P/N: PM1548 18 Rev. 1.9, November 13, 2017 MX25L1606E Table 6. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP3-BP0 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP3-BP0 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3-BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes". As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3-BP0. The protected area, which is defined by BP3-BP0 is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3-BP0. The protected area, which is defined by BP3-BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3-BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3-BP0. P/N: PM1548 19 Rev. 1.9, November 13, 2017 MX25L1606E (5) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low sending READ instruction code3-byte address on SI data out on SO to end READ operation can use CS# to high at any time during data out. The sequence is shown as "Figure 17. Read Data Bytes (READ) Sequence (Command 03h)". (6) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low sending FAST_READ instruction code 3-byte address on SI1-dummy byte (default) address on SI data out on SO to end FAST_READ operation can use CS# to high at any time during data out. The sequence is shown as "Figure 18. Read at Higher Speed (FAST_ READ) Sequence (Command 0Bh)". While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (7) Dual Output Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low sending DREAD instruction 3-byte address on SI 8-bit dummy cycle data out interleave on SIO1 & SIO0 to end DREAD operation can use CS# to high at any time during data out. The sequence is shown as "Figure 19. Dual Output Read Mode Sequence (Command 3Bh)". While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD throughputs. (8) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before P/N: PM1548 20 Rev. 1.9, November 13, 2017 MX25L1606E sending the Sector Erase (SE). Any address of the sector (see "Table 1. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low sending SE instruction code 3-byte address on SI CS# goes high. The sequence is shown as "Figure 20. Sector Erase (SE) Sequence (Command 20h)". The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP3-BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (9) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte sector erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see "Table 1. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low sending BE instruction code 3-byte address on SI CS# goes high. The sequence is shown as "Figure 21. Block Erase (BE) Sequence (Command 52h or D8h)". The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP3-BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (10) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see "Table 1. Memory Organization") is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low sending CE instruction code CS# goes high. The sequence is shown as "Figure 22. Chip Erase (CE) Sequence (Command 60h or C7h)". The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is protected by BP3-BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3BP0 all set to "0". (11) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. The last address byte (the eight least significant address P/N: PM1548 21 Rev. 1.9, November 13, 2017 MX25L1606E bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the requested page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low sending PP instruction code 3-byte address on SI at least 1-byte on data on SI CS# goes high. The sequence is shown as "Figure 23. Page Program (PP) Sequence (Command 02h)". The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP3-BP0 bits, the Page Program (PP) instruction will not be executed. (12) Deep Power-down (DP) The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Powerdown mode, in which the quiescent current is reduced from ISB1 to ISB2. The sequence of issuing DP instruction: CS# goes low send DP instruction code CS# goes high. The CS# must go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the instruction will not be executed. The sequence is shown as "Figure 24. Deep Power-down (DP) Sequence (Command B9h)". After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be ignored except Release from Deep Power-down (RDP). The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep Powerdown (RDP) instruction, power-cycle, or reset. (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select (CS#) must remain High for at least tRES1(max), as specified in "Table 13. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V - 3.6V)". Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7. ID DEFINITIONS". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/ erase/write cycle in progress. The sequence is shown in "Figure 25. Release from Deep Power-down (RDP) Sequence (Command ABh)" and "Figure 26. Read Electronic Signature (RES) Sequence (Command ABh)". The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in P/N: PM1548 22 Rev. 1.9, November 13, 2017 MX25L1606E Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. (14) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 7. ID DEFINITIONS". The sequence of issuing RDID instruction is: CS# goes low sending RDID instruction code 24-bits ID data out on SO to end RDID operation can use CS# to high at any time during data out. The sequence is shown as "Figure 27. Read Identification (RDID) Sequence (Command 9Fh)". While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. (15) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table 7. ID DEFINITIONS". The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first as shown in "Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90h)". If the address byte is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 7. ID DEFINITIONS Command Type RDID Command manufacturer ID C2 RES Command REMS manufacturer ID C2 MX25L1606E memory type 20 electronic ID 14 device ID 14 memory density 15 (16) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 512 bit secured OTP mode. While the device is in 512 bit secured OTP mode, array access is not available. The additional 512 bit secured OTP is independent from main array, and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low sending ENSO instruction to enter Secured OTP mode CS# goes high. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. P/N: PM1548 23 Rev. 1.9, November 13, 2017 MX25L1606E (17) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 512 bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low sending EXSO instruction to exit Secured OTP mode CS# goes high. (18) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low sending RDSCUR instruction Security Register data out on SO CS# goes high. The sequence is shown as "Figure 29. Read Security Register (RDSCUR) Sequence (Command 2Bh)". The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the Secured OTP area is locked by factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512 bit Secured OTP area cannot be updated any more. Table 8. SECURITY REGISTER DEFINITION bit7 bit6 bit5 bit4 x x x x bit3 bit2 x x bit1 LDSO (indicate if lock-down) reserved reserved reserved reserved reserved reserved 0 = not lockdown 1 = lock-down (cannot program/erase OTP) volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit bit0 Secured OTP indicator bit 0 = nonfactory lock 1 = factory lock non-volatile bit (19) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 512 bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing WRSCUR instruction is :CS# goes low sending WRSCUR instruction CS# goes high. The sequence is shown as "Figure 30. Write Security Register (WRSCUR) Sequence (Command 2Fh)". P/N: PM1548 24 Rev. 1.9, November 13, 2017 MX25L1606E (20) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes lowsend RDSFDP instruction (5Ah)send 3 address bytes on SI pinsend 1 dummy byte on SI pinread SFDP code on SOto end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Figure 3. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1548 4 25 6 5 4 3 2 1 0 7 MSB Rev. 1.9, November 13, 2017 MX25L1606E Table 9. Signature and Parameter Identification Data Values SFDP Table below is for MX25L1606EM2I-12G, MX25L1606EM1I-12G, MX25L1606EMI-12G, MX25L1606EPI12G, MX25L1606EZNI-12G, MX25L1606EZUI-12G and MX25L1606EXCI-12G Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1548 26 Rev. 1.9, November 13, 2017 MX25L1606E Table 10. Parameter Table (0): JEDEC Flash Parameter Tables SFDP Table below is for MX25L1606EM2I-12G, MX25L1606EM1I-12G, MX25L1606EMI-12G, MX25L1606EPI12G, MX25L1606EZNI-12G, MX25L1606EZUI-12G and MX25L1606EXCI-12G Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01b 02 1b 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 01:00 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 0b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 0b (1-1-4) Fast Read 0=not support 1=support 22 0b 23 1b 33h 31:24 FFh 37h:34h 31:00 00FF FFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1548 27 04:00 0 0000b 07:05 000b 15:08 FFh 20:16 0 0000b 23:21 000b 31:24 FFh 81h FFh 00h FFh 00h FFh Rev. 1.9, November 13, 2017 MX25L1606E SFDP Table below is for MX25L1606EM2I-12G, MX25L1606EM1I-12G, MX25L1606EMI-12G, MX25L1606EPI12G, MX25L1606EZNI-12G, MX25L1606EZUI-12G and MX25L1606EXCI-12G Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits (1-1-2) Fast Read Opcode Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0000b 23:21 000b 31:24 FFh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 00h FFh EEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 0000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 10h 10h 4Fh 31:24 D8h D8h 50h 07:00 00h 00h 51h 15:08 FFh FFh 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1548 28 00h Rev. 1.9, November 13, 2017 MX25L1606E Table 11. Parameter Table (1): Macronix Flash Parameter Tables SFDP Table below is for MX25L1606EM2I-12G, MX25L1606EM1I-12G, MX25L1606EMI-12G, MX25L1606EPI12G, MX25L1606EZNI-12G, MX25L1606EZUI-12G and MX25L1606EXCI-12G Description Vcc Supply Maximum Voltage Vcc Supply Minimum Voltage Comment 2000h=2.000V 2700h=2.700V 3600h=3.600V 1650h=1.650V, 1750h=1.750V 2250h=2.250V, 2350h=2.350V 2650h=2.650V, 2700h=2.700V Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) 61h:60h 07:00 15:08 00h 36h 00h 36h 63h:62h 23:16 31:24 00h 27h 00h 27h H/W Reset# pin 0=not support 1=support 00 0b H/W Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b S/W Reset 0=not support 1=support 03 0b S/W Reset Opcode Reset Enable (66h) should be issued before Reset Opcode Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 0b 66h 23:16 FFh FFh 67h 31:24 FFh FFh 65h:64h Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 11:04 1111 1111b 4FF6h (FFh) Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 0b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 1b 09:02 1111 1111b (FFh) 10 1b 11 1b Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh Unused 6Bh:68h 6Fh:6Ch CFFEh MX25L1606EM2I-12G-SFDP_2014-10-14 P/N: PM1548 29 Rev. 1.9, November 13, 2017 MX25L1606E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix. P/N: PM1548 30 Rev. 1.9, November 13, 2017 MX25L1606E POWER-ON STATE The device is at the following states after power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to "Figure 31. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1548 31 Rev. 1.9, November 13, 2017 MX25L1606E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40C to 85C Storage Temperature -55C to 125C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see "Figure 4. Maximum Negative Overshoot Waveform" and "Figure 5. Maximum Positive Overshoot Waveform". Figure 4. Maximum Negative Overshoot Waveform 20ns Figure 5. Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25C, f = 1.0 MHz Symbol CIN COUT P/N: PM1548 Parameter Input Capacitance Output Capacitance Min. Typ. 32 Max. 6 8 Unit pF pF Conditions VIN = 0V VOUT = 0V Rev. 1.9, November 13, 2017 MX25L1606E Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.2VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 7. OUTPUT LOADING DEVICE UNDER TEST 2.7K ohm CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30pF/15pF Including jig capacitance Figure 8. SCLK TIMING DEFINITION tCLCH tCHCL VIH (Min.) 0.5VCC VIL (Max.) tCL tCH 1/fSCLK P/N: PM1548 33 Rev. 1.9, November 13, 2017 MX25L1606E Table 12. DC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V - 3.6V) Symbol Parameter Notes Min. Typ. Max. Units Test Conditions ILI Input Load Current 1 2 uA VCC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 2 uA VCC = VCC Max, VOUT = VCC or GND ISB1 VCC Standby Current 1 15 25 uA ISB2 Deep Power-down Current 2 20 uA 1 25 mA 1 20 mA 1 10 mA ICC1 VCC Read ICC2 VCC Program Current (PP) 1 15 20 mA ICC3 VCC Write Status Register (WRSR) Current 1 3 20 mA ICC4 VCC Sector Erase Current (SE) 1 9 20 mA ICC5 VCC Chip Erase Current (CE) 1 15 20 mA VIN = VCC or GND, CS# = VCC VIN = VCC or GND, CS# = VCC f=86MHz fT=80MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz, SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz, SCLK=0.1VCC/0.9VCC, SO=Open Program in Progress, CS# = VCC Program status register in progress, CS#=VCC Erase in Progress, CS#=VCC Erase in Progress, CS#=VCC VIL Input Low Voltage -0.5 0.3VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage 0.4 V IOL = 1.6mA VOH Output High Voltage V IOH = -100uA VCC-0.2 Notes: 1. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Not 100% tested. P/N: PM1548 34 Rev. 1.9, November 13, 2017 MX25L1606E Table 13. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V - 3.6V) Symbol Alt. Parameter Clock Frequency for the following instructions: fSCLK fC FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR fRSCLK fR Clock Frequency for READ instructions fTSCLK fT Clock Frequency for DREAD instructions fC=86MHz tCH(1) tCLH Clock High Time fR=33MHz fC=86MHz (1) tCL tCLL Clock Low Time fR=33MHz tCLCH(2) Clock Rise Time(3) (peak to peak) tCHCL(2) Clock Fall Time(3) (peak to peak) tSLCH tCSS CS# Active Setup Time (relative to SCLK) tCHSL CS# Not Active Hold Time (relative to SCLK) tDVCH tDSU Data In Setup Time tCHDX tDH Data In Hold Time tCHSH CS# Active Hold Time (relative to SCLK) tSHCH CS# Not Active Setup Time (relative to SCLK) Read tSHSL tCSH CS# Deselect Time Write tSHQZ(2) tDIS Output Disable Time tCLQV tV Clock Low to Output Valid, Loading 30pF/15pF tCLQX tHO Output Hold Time tHLCH HOLD# Setup Time (relative to SCLK) tCHHH HOLD# Hold Time (relative to SCLK) tHHCH HOLD Setup Time (relative to SCLK) tCHHL HOLD Hold Time (relative to SCLK) (2) tHHQX tLZ HOLD to Output Low-Z tHLQZ(2) tHZ HOLD# to Output High-Z tWHSL(4) Write Protect Setup Time tSHWL(4) Write Protect Hold Time tDP(2) CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature tRES1(2) Read CS# High to Standby Mode with Electronic Signature (2) tRES2 Read tW Write Status Register Cycle Time tBP Byte-Program tPP Page Program Cycle Time tSE Sector Erase Cycle Time tBE Block Erase Cycle Time tCE Chip Erase Cycle Time Min. Typ. Max. Unit DC 86 MHz DC DC 5.5 13 5.5 13 0.1 0.1 5 5 2 5 5 5 15 40 33 80 10 MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us 8.8 us 8.8 us 40 50 3 200 2 20 ms us ms ms s s 6 8/6 0 5 5 5 5 6 6 20 100 5 9 0.6 40 0.4 6.5 Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5. 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as "Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" & "Figure 7. OUTPUT LOADING". 6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec. P/N: PM1548 35 Rev. 1.9, November 13, 2017 MX25L1606E Timing Analysis Figure 9. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 10. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM1548 tSHQZ ADDR.LSB IN 36 Rev. 1.9, November 13, 2017 MX25L1606E Figure 11. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# * SI is "don't care" during HOLD operation. Figure 12. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO P/N: PM1548 High-Z 37 Rev. 1.9, November 13, 2017 MX25L1606E Figure 13. Write Enable (WREN) Sequence (Command 06h) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO Figure 14. Write Disable (WRDI) Sequence (Command 04h) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO P/N: PM1548 04 High-Z 38 Rev. 1.9, November 13, 2017 MX25L1606E Figure 15. Read Status Register (RDSR) Sequence (Command 05h) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 16. Write Status Register (WRSR) Sequence (Command 01h) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI Status Register In 01 7 5 4 3 2 0 1 MSB High-Z SO 6 Figure 17. Read Data Bytes (READ) Sequence (Command 03h) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1548 39 Rev. 1.9, November 13, 2017 MX25L1606E Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0Bh) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1548 4 40 6 5 4 3 2 1 0 7 MSB Rev. 1.9, November 13, 2017 MX25L1606E Figure 19. Dual Output Read Mode Sequence (Command 3Bh) CS# 0 1 2 3 4 5 6 7 8 9 10 11 39 40 41 42 43 30 31 32 SCLK 8 Bit Instruction SO/SIO1 address bit23, bit22, bit21...bit0 3B(hex) SI/SIO0 8 dummy cycle 24 BIT Address dummy High Impedance Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... Figure 20. Sector Erase (SE) Sequence (Command 20h) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB Note: SE command is 20(hex). Figure 21. Block Erase (BE) Sequence (Command 52h or D8h) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52 or D8 2 1 0 MSB Note: BE command is 52 or D8(hex). P/N: PM1548 41 Rev. 1.9, November 13, 2017 MX25L1606E Figure 22. Chip Erase (CE) Sequence (Command 60h or C7h) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). Figure 23. Page Program (PP) Sequence (Command 02h) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02 SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# SCLK Data Byte 2 SI 7 6 MSB P/N: PM1548 5 4 3 2 Data Byte 3 1 0 7 6 5 4 MSB 3 2 Data Byte 256 1 0 7 6 5 4 3 2 MSB 42 Rev. 1.9, November 13, 2017 MX25L1606E Figure 24. Deep Power-down (DP) Sequence (Command B9h) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Deep Power-down Mode Stand-by Mode Figure 25. Release from Deep Power-down (RDP) Sequence (Command ABh) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI AB High-Z SO Deep Power-down Mode Stand-by Mode Figure 26. Read Electronic Signature (RES) Sequence (Command ABh) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI AB tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1548 43 Stand-by Mode Rev. 1.9, November 13, 2017 MX25L1606E Figure 27. Read Identification (RDID) Sequence (Command 9Fh) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO 7 6 5 3 2 1 MSB Device Identification 0 15 14 13 3 2 1 0 MSB Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90h) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 MSB MSB 2 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Instruction is 90(hex). P/N: PM1548 44 Rev. 1.9, November 13, 2017 MX25L1606E Figure 29. Read Security Register (RDSCUR) Sequence (Command 2Bh) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 2B SI SO Security Register Out High-Z 7 6 5 4 3 2 1 Security Register Out 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 30. Write Security Register (WRSCUR) Sequence (Command 2Fh) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO P/N: PM1548 2F High-Z 45 Rev. 1.9, November 13, 2017 MX25L1606E Figure 31. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) Device is fully accessible tVSL time Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 14. Power-Up Timing Symbol (1) tVSL Parameter Min. VCC(min) to CS# low 200 Max. Unit us Note: 1. The parameter is characterized only. P/N: PM1548 46 Rev. 1.9, November 13, 2017 MX25L1606E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in "Figure 32. AC Timing at Device Power-Up" and "Figure 33. Power-Down Sequence" are the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power down, CS# need to follow the voltage applied on VCC to keep the device not be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 32. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX tCLCH LSB IN MSB IN SI High Impedance SO Symbol Parameter tVR VCC Rise Time Notes 1 Min. Max. Unit 500000 us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 13. AC CHARACTERISTICS (Temperature = -40C to 85C for Industrial grade, VCC = 2.7V - 3.6V)". P/N: PM1548 47 Rev. 1.9, November 13, 2017 MX25L1606E Figure 33. Power-Down Sequence During power down, CS# need to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1548 48 Rev. 1.9, November 13, 2017 MX25L1606E ERASE AND PROGRAMMING PERFORMANCE Typ.(1) Max.(2) Unit Write Status Register Time 5 40 ms Sector Erase Time 40 200 ms Block Erase Time 0.4 2 s Chip Erase Time 6.5 20 s 9 50 us 0.6 3 ms Parameter Min. Byte Program Time (via page program command) Page Program Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25C, 3.3V, and checkerboard pattern. 2. Under worst conditions of 85C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. Erase/Program cycles comply with JEDEC: JESD-47 & JESD22-A117 standard. DATA RETENTION Parameter Condition Min. Data retention 55C 20 Max. Unit years LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1548 49 Rev. 1.9, November 13, 2017 MX25L1606E ORDERING INFORMATION Please contact Macronix regional sales for the latest product selection and available form factors. CLOCK PART NO. Temperature PACKAGE (MHz) 16-SOP MX25L1606EMI-12G 86 -40C to 85C (300mil) 8-SOP MX25L1606EM1I-12G 86 -40C to 85C (150mil) 8-SOP MX25L1606EM2I-12G 86 -40C to 85C (200mil) 8-PDIP MX25L1606EPI-12G 86 -40C to 85C (300mil) 8-WSON MX25L1606EZNI-12G 86 -40C to 85C (6x5mm) 8-USON MX25L1606EZUI-12G 86 -40C to 85C (4x4mm) MX25L1606EXCI-12G P/N: PM1548 86 -40C to 85C 50 24-Ball BGA Remark RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant Rev. 1.9, November 13, 2017 MX25L1606E PART NAME DESCRIPTION MX 25 L 1606E ZN I 12 G OPTION: G: RoHS Compliant and Halogen-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40C to 85C) PACKAGE: ZN: WSON (0.8mm package height) ZU: USON (0.6mm package height) M: 300mil 16-SOP M1: 150mil 8-SOP M2: 200mil 8-SOP P: 300mil 8-PDIP XC: 24-Ball BGA DENSITY & MODE: 1606E: 16Mb TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1548 51 Rev. 1.9, November 13, 2017 MX25L1606E PACKAGE INFORMATION 16-PIN SOP (300mil) P/N: PM1548 52 Rev. 1.9, November 13, 2017 MX25L1606E 8-PIN SOP (150mil) P/N: PM1548 53 Rev. 1.9, November 13, 2017 MX25L1606E 8-PIN SOP (200mil) P/N: PM1548 54 Rev. 1.9, November 13, 2017 MX25L1606E 8-PIN PDIP (300mil) P/N: PM1548 55 Rev. 1.9, November 13, 2017 MX25L1606E 8-LAND WSON (6x5mm) P/N: PM1548 56 Rev. 1.9, November 13, 2017 MX25L1606E 8-LAND USON (4x4mm) P/N: PM1548 57 Rev. 1.9, November 13, 2017 MX25L1606E 24-BALL BGA P/N: PM1548 58 Rev. 1.9, November 13, 2017 MX25L1606E REVISION HISTORY Revision No. Description Page Date 0.01 1. Document status: changed from Advanced Information to Preliminary P5JAN/28/2010 2. Table 2. Protected Area Sizes: Modified content P12 3. DATA PROTECTION-Block Lock Protection: Revised description P11 4. Table 4. COMMAND DESCRIPTION: Modified RDDMC P15 5. PERFORMANCE: Revised Low Power Consumption (low active read P5,31 current and low standby current) 1.0 1. Removed "Preliminary" P5 MAR/30/2010 2. GENERAL DESCRIPTION: Revision P6 3. COMMAND DESCRIPTION: DMC Parameter ID Table (2) revision P26 4. Changed ISB1(MAX.) from 50uA to 25uA P5,30,45 5. Modified Figure 28. AC Timing at Device Power-Up P42 6. Added Figure 29 P43 7. Modified "Dual Output Mode (DREAD)" description P19 8. Modified fC, fR, fT/(Min.) from 10KHz to DC P31 9. Revised DMC description P24 1.1 1. Modified Figure 19. Block Erase (BE) Sequence P37 MAY/19/2010 2. Modified REMS description P22,40 3. Modified Figure 8. Output Timing P32 4. Revised Vcc Supply Minimum Voltage Address Bits P25 5. Revised Note 4 of Erase And Programming Performance table P44 6. Changed wording from DMC to SFDP P6,10,15,24 7. Revised SFDP sequence description P24 1.2 1. Removed SFDP sequence description & content table P6,10,15, JUL/02/2010 P24 1.3 1. Added RDSCUR & WRSCUR diagram form P38 SEP/01/2011 2. Added CS# rising and falling time description P10,28 3. Modified tW from 40(typ.)/100(max.) to 5(typ.)/40(max.) P28,42 4. Modified description for RoHS compliance P6,43,44 5. Removed MX25L8006E content (to a separated datasheet) 1.4 1. Added Read SFDP (RDSFDP) Mode P6,11,16, FEB/23/2012 P25~30,35 2. Added 24-ball BGA package information P6,7,50,51, P58 1.5 1. Updated parameters for DC/AC Characteristics P5,34,35 NOV/06/2013 2. Updated Erase and Programming Performance P5,49 1.6 1. Modified Hold figure and description 2. Modified notes for SFDP table P15 OCT/22/2014 P29 1.7 1. Updated BLOCK DIAGRAM 2. Updated Package outline diagram for WSON 8L P9 MAY/14/2015 P56 1.8 1. Revised HOLD Feature descriptions 2. Modified Copyright years P15 JUN/04/2015 P60 P/N: PM1548 59 Rev. 1.9, November 13, 2017 MX25L1606E Revision No. Description Page Date 1.9 1. Updated tVR descriptions P47 NOV/13/2017 2. Modified SRWD bit descriptions P18 3. Updated the descriptions of REMS command P23 4. Added "Figure 8. SCLK TIMING DEFINITION" P33 5. Added a statement for product ordering information P50 6. Updated "8-LAND WSON (6x5mm)" in Min./Max. D1, E1 and L values. P56 7. Updated "(12) Deep Power-down (DP)" descriptions P22 8. Content correction P22, 24 9. Format modification P52-58 P/N: PM1548 60 Rev. 1.9, November 13, 2017 MX25L1606E Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it's suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright(c) Macronix International Co., Ltd. 2013-2017. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, HybridXFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Book, Rich TV, OctaRAM, OctaBus, OctaFlash and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix's Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. P/N: PM1548 61 Rev. 1.9, November 13, 2017