To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 Mitsubishi microcomputers Rev.1.1 M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Description The M16C/62N (80-pin version) group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, low voltage (2.4V(mask ROM version is 2.2V) to 3.6V), they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other highspeed processing applications. The M16C/62N (80-pin version) group includes a wide range of products with different internal memory types and sizes and various package types. Features * Memory capacity .................................. ROM (See Figure 1.1.3. ROM Expansion) RAM 10K to 20K bytes * Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait) * Supply voltage ..................................... 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) 2.4V to 3.6V (f(XIN)=7MHZ, without software wait) 2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait) :mask ROM version * Low power consumption ...................... 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait) * Interrupts .............................................. 25 internal and 5 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) * Multifunction 16-bit timer ...................... 5 output timers + 6 input timers (3 for timer function only) * Serial I/O .............................................. 5 channels (2 for UART or clock synchronous, 1 for UART, 2 for clock synchronous) * DMAC .................................................. 2 channels (trigger: 25 sources) * A-D converter ....................................... 10 bits X 8 channels (Expandable up to 18 channels) * D-A converter ....................................... 8 bits X 2 channels * CRC calculation circuit ......................... 1 circuit * Watchdog timer .................................... 1 line * Programmable I/O ............................... 70 lines _______ * Input port .............................................. 1 line (P85 shared with NMI pin) * Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Note: Memory expansion mode and microprocessor mode are not supported. Applications Audio, cameras, office equipment, communications equipment, portable equipment ------Table of Contents-----About the M16C/62N (80-pin version) group .. 7 Central Processing Unit (CPU) ..................... 11 Reset ............................................................. 14 Processor Mode ............................................ 21 Clock Generating Circuit ............................... 26 Protection ...................................................... 35 Interrupts ....................................................... 36 Watchdog Timer ............................................ 56 DMAC ........................................................... 58 Timer ............................................................. 68 Serial I/O ....................................................... 86 A-D Converter ............................................. 127 D-A Converter ............................................. 137 CRC Calculation Circuit .............................. 139 Programmable I/O Ports ............................. 141 Electric Characteristics ............................... 151 Flash memory version ................................. 158 1 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Pin Configuration Figures 1.1.1 show the pin configurations (top view). P33 P34 P35 P36 P37 P40 P41 P42 P22 P23 P24 P25 P26 P27 P30 P31 P32 P07/AN07 P20 P21 PIN CONFIGURATION (top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P06/AN06 P05/AN05 P04/AN04 P03/AN03 P02/AN02 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 61 40 P43 62 39 P50 63 38 64 37 65 36 66 35 67 34 68 33 P51 P52 P53 P54 P55 P56 P57/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 32 69 M16C/62N Group (80-pin version) 70 71 31 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 22 80 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P90/TB0IN/CLK3 CNVss(BYTE) P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN P80/TA4OUT P77/TA3IN 1 P70/TxD2/SDA/TA0OUT (Note) P71/RxD2/SCL/TA0IN/TB5IN (Note) P76/TA3OUT Note : P70 and P71 are N channel open-drain output pin. Package: 80P6S-A Figure 1.1.1. Pin configuration (top view) 2 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Block Diagram Figure 1.1.2 is a block diagram of the M16C/62N (80-pin version) group. 8 I/O ports Port P0 Port P2 8 4 Port P3 8 8 Port P4 Port P5 Port P6 UART/clock synchronous SI/O Clock synchronous SI/O (8 bits X 3 channels)(Note 3) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) M16C/60 series16-bit CPU core Registers (15 bits) Stack pointer ISP USP Flag register FLG RAM (Note 2) Multiplier 8 SB PC Vector table INTB ROM (Note 1) Port P10 D-A converter (8 bits X 2 channels) Program counter Memory 7 DMAC (2 channels) R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAA AAAA Port P9 Watchdog timer (8 bits X 2 channels) 7 Expandable up to 18channels) 4 Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) System clock generator XIN-XOUT XCIN-XCOUT A-D converter Port P85 (10 bits X 8 channels Port P8 Timer Port P7 Internal peripheral functions 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Note 3: One of three channels is used for UART and IIC mode. Figure 1.1.2. Block diagram of M16C/62N (80-pin version) group 3 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Performance Outline Table 1.1.1 is a performance outline of M16C/62N (80-pin version) group. Table 1.1.1. Performance outline of M16C/62N (80-pin version) group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait) Memory ROM (See the figure 1.1.3. ROM Expansion) capacity RAM 10K to 20K bytes I/O port P0 to P10 (except P85) 8 bits x 6, 7 bits x 2, 4 bits x 2 Input port P85 1 bit x 1 Multifunction TA0, TA3, TA4 16 bits x 3 (timer mode, internal/external event count, timer one-shot timer mode and pulse width measurement mode) TB0, TB2, TB3, TB4, TB5 16 bits x 5 (timer mode, internal/external event count and pulse period/pulse width measurement mode) TA1, TA2 16 bits x 2 (timer mode, internal event count and a trigger through one-shot timer mode occurs.) TB1 16 bits x 1 (timer mode and internal event count) Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 2, UART x 1(UART2) SI/O3, SI/O4 (Clock synchronous) x 2 (SI/O3 is output only) A-D converter 10 bits x (8 x 2 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 25 sources) CRC calculation circuit CRC-CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt 25 internal and 5 external sources, 4 software sources, 7 levels Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) 2.4V to 3.6V (f(XIN)=7MHZ, without software wait) 2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait) :mask ROM version Power consumption 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait) I/O I/O withstand voltage 3.3V characteristics Output current 1mA Device configuration CMOS high performance silicon gate Package 80-pin plastic mold QFP Note : M16C/62N (80-pin version) group does not support memory expansion or microprocessor mode. 4 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Mitsubishi plans to release the following products in the M16C/62N (80-pin version) group: (1) Support for mask ROM version and flash memory version (2) ROM capacity (3) Package 80P6S-A : Plastic molded QFP (mask ROM and flash memory versions) ROM Size (Byte) External ROM 256K M30625MGN-XXXGP M30625FGNGP 128K M30621MCN-XXXGP M30621FCNGP 96K 80K 64K 32K Mask ROM version Flash memory version Figure 1.1.3. ROM expansion The M16C/62N (80-pin version) group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/62N (80-pin version) group Type No M30621MCN-XXXGP ** M30625MGN-XXXGP ** M30621FCNGP ** M30625FGNGP ROM capacity 128 Kbytes RAM capacity As of May 2002 Package type 10 Kbytes 80P6S-A 256 Kbytes 20 Kbytes 80P6S-A 128 Kbytes 10 Kbytes 80P6S-A 256 Kbytes 20 Kbytes 80P6S-A Remarks Mask ROM version Flash memory version **: Under development 5 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Type No. M30621 M C N- XXX GP Package type: GP : Package 80P6S-A ROM No. Omitted for flash memory version ROM capacity: C : 128K bytes G: 256K bytes Memory type: M : Mask ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/62 Group M16C Family Figure 1.1.4. Type No., memory size, and package 6 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description About the M16C/62N (80-pin version) group The M16C/62N (80-pin version) group is packaged in a 80-pin plastic mold package. The number of pins in comparison with the 100-pin package products is decreased. So be careful about the following. (a) The M16C/62N (80-pin version) group supports single chip mode alone. It supports neither memory expansion mode nor microprocessor mode. (b) The input/output ports given below are absent from the M16C/62N (80-pin version) group. To stabilize the internal state, set to output mode the direction register of each input/output port. Failing in setting to output mode involves an increase in current consumption. <Pins absent from the 80-pin version> P10 to P17, P44 to P47, P72 to P75, P91 ________ ________ ________ (c) INT3 to INT5 allocated to P15 to P17 cannot be used. Keep the INT3 interrupt control register ________ ________ disabled for interrupts. The INT4 interrupt control register and the INT5 interrupt control register are shared with SI/O3 and SI/O4. When the user don't use them as SI/O3 and SI/O4, set them disabled for interrupts. (d) The output pins of timers A1 and A2 - TA1IN, TA1OUT, TA2IN and TA2OUT - allocated to P72 to P75 cannot be used. In connection with this, the gate function and pulse outputting function of timers A1 and A2 cannot be used. Use timer mode and internal event count, or use as trigger signal generation in one-shot timer mode. _________ ________ (e) The UART2 input/output pins - CLK2 and CTS2/RTS2 - allocated to P72 and P73 cannot be used. In connection with this, UART2 solely as UART of the internal clock can be used. And UART2 must ________ ________ be used by setting the CTS/ RTS disable bit (bit 4 at address 037C16) to "1". (f) The input pin TB1IN of timer B1 allocated to P91 cannot be used. With timer B1 under this state, use only timer mode or the internal event count. (g) The input pin SIN3 of serial I/O3 allocated to P91 cannot be used. In connection with this, use serial I/O3 as a serial I/O exclusive to transmission. (h) The output pins for three-phase motor control allocated to P72 to P75 cannot be used. So set to 0 (ordinary mode) the mode select bit (bit 2) of three-phase PWM control register 0. (i) The registers given below are reserved registers. Do not access these registers for read or write. Address Register Address Register 000816 Chip select control register (CSR) 034B16 Thrree-phase output buffer register 1(IDB1) 000B16 Data bank register (DBR) 034C16 Dead time timer(DTT) 034916 Three-phase PWM control register 1(INVC1) 034D16 Timer B2 interrupt occurrence frequency set counter(ICTB2) 034A16 Thrree-phase output buffer register 0(IDB0) 03FF16 Port control register (PCR) 7 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Pin name Signal name Function Supply 2.2V to 3.6 V (mask ROM version), 2.4V to 3.6 V (flash memory version) to the VCC pin. Supply 0 V to the VSS pin. VCC, VSS Power supply input CNVSS CNVSS I This pin switches between processor modes. Connect it to the VSS pin. (BYTE) External data bus width select input I This pin is connected to CNVss in microcomputer. Connect this pin to VSS. RESET Reset input I An "L" on this input resets the microcomputer. XIN Clock input I XOUT Clock output O These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. AVCC Analog power supply input This pin is a power supply input for the A-D converter. Connect this pin to VCC. AVSS Analog power supply input This pin is a power supply input for the A-D converter. Connect this pin to VSS. VREF Reference voltage input P00 to P07 I/O port P0 I/O This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. P0 also function as A-D converter extended input pins as selected by software. P20 to P27 I/O port P2 I/O This is an 8-bit I/O port equivalent to P0. P30 to P37 I/O port P3 I/O This is an 8-bit I/O port equivalent to P0. P40 to P43 I/O port P4 I/O This is a 4-bit I/O port equivalent to P0. P50 to P57 I/O port P5 I/O This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. P60 to P67 I/O port P6 I/O This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. P70, P71, P76, P77 I/O port P7 I/O This is a 4-bit I/O port equivalent to P0 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0-A3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, I/O port P8 I/O P80 to P84, P86, and P87 are I/O ports with the same functions as P0. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from "H" to "L". The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. P85 I I/O P86,P87, 8 I/O I/O port P85 I This pin is a reference voltage input for the A-D converter. Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Pin name Signal name I/O Function P90, P92 to P97 I/O port P9 I/O This is an 7-bit I/O port equivalent to P0. Pins in this port also function as SI/O3, 4 I/O pins, Timer B0-B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. P100 to P107 I/O port P10 I/O This is an 8-bit I/O port equivalent to P0. Pins in this port also function as A-D converter input pins. Furthermore, P104-P107 also function as input pins for the key input interrupt function. Note: Memory expansion mode and microprocessor mode are not be supported. 9 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Operation of Functional Blocks The M16C/62N (80-pin version) group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/ logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. Memory Figure 1.4.1 is a memory map of the M16C/62N (80-pin version) group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30621MCNXXXGP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts _______ such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30621MCN-XXXGP, 10K bytes of internal RAM is mapped to the space from 0040016 to 02BFF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.7.1 to 1.7.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. 0000016 SFR area For details, see Figures 1.7.1 to 1.7.3 FFE0016 0040016 Internal RAM area RAM size Address XXXXX16 10K bytes 02BFF16 20K bytes 053FF16 Special page vector table XXXXX16 Reserved area ROM size Address YYYYY16 128K bytes E000016 256K bytes C000016 FFFDC16 Undefined instruction FFFFF16 BRK instruction Address match Single step Watchdog timer DBC NMI Reset Overflow YYYYY16 Internal ROM area FFFFF16 Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 1.4.1. Memory map 10 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA b15 R0(Note) b8 b7 b15 R1(Note) b15 R3(Note) b15 A0(Note) b15 FB(Note) b19 b0 L Program counter Data registers b19 INTB b0 Interrupt table register L H b15 b0 b0 User stack pointer USP b15 b0 b0 b0 PC b0 AAAAAAA AAAAAAA AAAAAAA b15 A1(Note) b8 b7 H b15 R2(Note) b0 L H b0 Interrupt stack pointer ISP Address registers b15 b0 Static base register SB b15 b0 Frame base registers b0 FLG Flag register A AAAAAAA AA A AA A AA AA AA A AAAAAAAAAAAAAA A AAAAAA IPL U I O B S Z D C Note: These registers consist of two register banks. Figure 1.5.1. Central processing unit register (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 11 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag: * Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged. 12 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU * Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. * Bits 8 to 11: Reserved area * Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. AA AAAAAAA AA AA A AA AA AA A AA AAAAAAAAAAAAAA AA AA AA A AA b15 b0 IPL U I O B S Z D C Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.5.2. Flag register (FLG) 13 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. The RAM is undefined at power on. The initial values must therfore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence. 3V 2.4V VCC RESET 0V 3V VCC RESET 0.48V 0V More than 20 cycles of XIN are needed. Example when VCC = 3V. Figure 1.6.1. Example reset circuit XIN More than 20 cycles are needed Single chip mode RESET BCLK 28cycles BCLK FFFFC16 Address Figure 1.6.2. Reset sequence 14 Content of reset vector FFFFE16 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset ____________ Table 1.6.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 1.6.1. Pin status when RESET pin level is "L" Pin name Status CNVSS = VSS P0, P2, P3, P40 to P43, P5, P6, P70, P71, P76, P77, P80 to P84, Input port (floating) P86, P87, P90, P92 to P97, P10 15 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset (1) Processor mode register 0 (000416)*** (2) Processor mode register 1 (000516)*** 0 0 0 0 0 0 (3) System clock control register 0 0016 (28) UART0 receive interrupt control register (29) UART1 transmit interrupt control register (005216)*** ? 0 0 0 (005316)*** ? 0 0 0 (000616)*** 0 1 0 0 1 0 0 0 (30) UART1 receive interrupt control register (005416)*** ? 0 0 0 0 (000716)*** 0 0 1 0 0 0 0 0 (31) Timer A0 interrupt control register (005516)*** ? 0 0 0 (5) Chip select control register (000816)*** 0 0 0 0 0 0 0 1 (32) Timer A1 interrupt control register (005616)*** ? 0 0 0 (6) Address match interrupt enable register (7) Protect register (000916)*** 0 0 (33) Timer A2 interrupt control register (005716)*** ? 0 0 0 (000A16)*** 0 0 0 (34) Timer A3 interrupt control register (005816)*** ? 0 0 0 (8) Data bank register (000B16)*** (35) Timer A4 interrupt control register (005916)*** ? 0 0 0 (9) Watchdog timer control register (000F16)*** 0 0 0 ? ? ? ? ? (36) Timer B0 interrupt control register (005A16)*** ? 0 0 0 (10) Address match interrupt register 0 (001016)*** 0016 (37) Timer B1 interrupt control register (005B16)*** ? 0 0 0 (001116)*** 0016 (38) Timer B2 interrupt control register (005C16)*** ? 0 0 0 (4) System clock control register 1 (39) INT0 interrupt control register (005D16)*** 0 0 ? 0 0 0 (001416)*** 0016 (40) INT1 interrupt control register (005E16)*** 0 0 ? 0 0 0 (001516)*** 0016 (41) INT2 interrupt control register (005F16)*** 0 0 ? 0 0 0 (42) Timer B3,4,5 count start flag (034016)*** 0 0 0 (034816)*** (001216)*** (11) Address match interrupt register 1 0016 (001616)*** 0 0 0 0 0 0 0 0 (12) DMA0 control register (002C16)*** 0 0 0 0 0 ? 0 0 (43) Three-phase PWM control register 0 (13) DMA1 control register (003C16)*** 0 0 0 0 0 ? 0 0 (44) Three-phase PWM control register 1 (034916)*** 0016 (14) INT3 interrupt control register (004416)*** 0 0 ? 0 0 0 (45) Three-phase output buffer register 0 (034A16)*** 0016 (15) Timer B5 interrupt control register (004516)*** ? 0 0 0 (46) Three-phase output buffer register 1 (034B16)*** 0016 (16) Timer B4 interrupt control register (004616)*** ? 0 0 0 (47) Timer B3 mode register (035B16)*** 0 0 ? ? 0 0 0 0 (17) Timer B3 interrupt control register (004716)*** ? 0 0 0 (48) Timer B4 mode register (035C16)*** 0 0 ? 0 0 0 0 (18) SI/O4 interrupt control register (004816)*** 0 0 ? 0 0 0 (49) Timer B5 mode register (035D16)*** 0 0 ? 0 0 0 0 (19) SI/O3 interrupt control register (004916)*** 0 0 ? 0 0 0 (50)Interrupt cause select register (035F16)*** 0016 0016 (20) Bus collision detection interrupt control register (004A16)*** ? 0 0 0 (51) SI/O3 control register (036216)*** 4016 (21) DMA0 interrupt control register (004B16)*** ? 0 0 0 (52) SI/O4 control register (036616)*** 4016 (22) DMA1 interrupt control register (004C16)*** ? 0 0 0 (53) UART2 special mode register 3 (037516)*** 0016 (23) Key input interrupt control register (004D16)*** ? 0 0 0 (54) UART2 special mode register 2 (037616)*** 0016 (24) A-D conversion interrupt control register (004E16)*** ? 0 0 0 (55) UART2 special mode register (037716)*** 8016 (25) UART2 transmit interrupt control register (004F16)*** ? 0 0 0 (56) UART2 transmit/receive mode register (037816)*** 0016 (26) UART2 receive interrupt control register (27) UART0 transmit interrupt control register (005016)*** ? 0 0 0 (57) UART2 transmit/receive control register 0 (037C16)*** 0 0 0 0 1 0 0 0 (005116)*** ? 0 0 0 (58)UART2 transmit/receive control register 1 (037D16)*** 0 0 0 0 0 0 1 0 x : Nothing is mapped to this bit ? : Undefined The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set. The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Figure 1.6.3. Device's internal status after a reset is cleared 16 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset (85) A-D control register 1 (03D716)*** 0016 (038116)*** 0 (86) D-A control register (03DC16)*** 0016 (61) One-shot start flag (038216)*** 0 0 0 0 0 0 0 (87) Port P0 direction register (03E216)*** 0016 (62) Trigger select flag (038316)*** 0016 (88) Port P1 direction register (03E316)*** 0016 (63) Up-down flag (038416)*** 0016 (89) Port P2 direction register (03E616)*** 0016 (64) Timer A0 mode register (039616)*** 0016 (90) Port P3 direction register (03E716)*** 0016 (65) Timer A1 mode register (039716)*** 0016 (91) Port P4 direction register (03EA16)*** 0016 (66) Timer A2 mode register (039816)*** 0016 (92) Port P5 direction register (03EB16)*** 0016 (67) Timer A3 mode register (039916)*** 0016 (93) Port P6 direction register (03EE16)*** 0016 (68) Timer A4 mode register (039A16)*** 0016 (94) Port P7 direction register (03EF16)*** 0016 (69) Timer B0 mode register (039B16)*** 0 0 ? ? 0 0 0 0 (95) Port P8 direction register (03F216)*** 0 0 0 0 0 0 0 (70) Timer B1 mode register (039C16)*** 0 0 ? 0 0 0 0 (96) Port P9 direction register (03F316)*** 0016 (71) Timer B2 mode register (039D16)*** 0 0 ? 0 0 0 0 (97) Port P10 direction register (03F616)*** 0016 (72) UART0 transmit/receive mode register (03A016)*** (98) Pull-up control register 0 (03FC16)*** 0016 (73) UART0 transmit/receive control register 0 (03A416)*** 0 0 0 0 1 0 0 0 (99) Pull-up control register 1 (03FD16)*** 0016 (74) UART0 transmit/receive control register 1 (03A516)*** 0 0 0 0 0 0 1 0 (100) Pull-up control register 2 (03FE16)*** 0016 (03A816)*** (101) Port control register (03FF16)*** (59) Count start flag (038016)*** (60) Clock prescaler reset flag (75) UART1 transmit/receive mode register 0016 0016 0016 0016 (76) UART1 transmit/receive control register 0 (03AC16)*** 0 0 0 0 1 0 0 0 (102) Data registers (R0/R1/R2/R3) 000016 (77) UART1 transmit/receive control register 1 (03AD16)*** 0 0 0 0 0 0 1 0 (103) Address registers (A0/A1) 000016 (78) UART transmit/receive control register 2 (03B016)*** (104) Frame base register (FB) 000016 (79) Flash identification register (Note) (03B416)*** (105) Interrupt table register (INTB) 0000016 (106) User stack pointer (USP) 000016 000016 (80) Flash memory control register 0 (Note) (03B716)*** 0 0 0 0 0 0 0 0016 0 0 0 0 0 1 (81) DMA0 cause select register (03B816)*** 0016 (107) Interrupt stack pointer (ISP) (82) DMA1 cause select register (03BA16)*** 0016 (108) Static base register (SB) 000016 (83) A-D control register 2 (03D416)*** 0 0 0 0 (109) Flag register (FLG) 000016 (84) A-D control register 0 (03D616)*** 0 0 0 0 0 ? ? ? 0 x : Nothing is mapped to this bit ? : Undefined The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set. The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Note: This register is only exist in flash memory version. Figure 1.6.4. Device's internal status after a reset is cleared 17 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR 000016 004016 000116 004116 000216 004216 000316 004316 004416 000716 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) 000816 Chip select control register (CSR) 004816 000916 000A16 Address match interrupt enable register (AIER) Protect register (PRCR) 004916 000B16 Data bank register (DBR) 000416 000516 000616 004516 004616 004716 INT3 interrupt control register (INT3IC)* Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC)* SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC)* 000C16 004A16 Bus collision detection interrupt control register (BCNIC) 000D16 004B16 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) 000E16 000F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) 001016 001116 004C16 004D16 004E16 Address match interrupt register 0 (RMAD0) 004F16 001216 005016 001316 005116 001416 001516 005216 Address match interrupt register 1 (RMAD1) 005316 001616 005416 001716 005516 001816 005616 001916 005716 001A16 005816 001B16 005916 001C16 005A16 001D16 005B16 001E16 005C16 001F16 005D16 005E16 002016 002116 DMA0 source pointer (SAR0) 005F16 002216 006016 002316 006116 DMA0 destination pointer (DAR0) 006316 002616 006416 002716 006516 002816 002916 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) 006216 002416 002516 UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) DMA0 transfer counter (TCR0) 002A16 002B16 002C16 DMA0 control register (DM0CON) 032A16 002D16 032B16 002E16 032C16 002F16 032D16 032E16 003016 003116 DMA1 source pointer (SAR1) 032F16 003216 033016 003316 033116 033216 003416 003516 DMA1 destination pointer (DAR1) 033316 003616 033416 003716 033516 003816 003916 DMA1 transfer counter (TCR1) 033716 033816 003A16 033916 003B16 003C16 033616 DMA1 control register (DM1CON) 033A16 003D16 033B16 003E16 033C16 003F16 033D16 033E16 033F16 Note 1: M16C/62N (80-pin version) group is not provided with the functions, in whole or in part, of the registers marked with an *. But the relevant registers need to be dealt with as given on page 7. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.7.1. Location of peripheral unit control registers (1) 18 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR 034016 Timer B3, 4, 5 count start flag (TBSR) 034216 034316 034416 034516 034616 034716 038016 038116 034116 Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) 038216 038316 038416 038516 038616 038716 038816 034C16 Three-phase PWM control register 0(INVC0)* Three-phase PWM control register 1(INVC1) Thrree-phase output buffer register 0(IDB0) Thrree-phase output buffer register 1(IDB1) Dead time timer(DTT) 034D16 Timer B2 interrupt occurrence frequency set counter(ICTB2) 038D16 034816 034916 034A16 034B16 038916 038A16 038B16 038C16 034E16 038E16 034F16 038F16 035016 039016 035116 035216 035316 035416 035516 Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) 039116 039216 039316 039416 039516 035616 039616 035716 039716 035816 039816 035916 039916 039A16 035A16 035B16 035C16 035D16 Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) 036016 Interrupt cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) 036116 036216 036316 036416 SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) 036716 039C16 039D16 Timer A1 register (TA1) Timer A2 register (TA2) Timer A3 register (TA3) Timer A4 register (TA4) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) 039F16 03A016 UART0 transmit/receive mode register (U0MR) 03A116 UART0 bit rate generator (U0BRG) 03A216 03A316 03A416 03A516 036516 036616 039B16 Timer A0 register (TA0) 039E16 035E16 035F16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) 03A616 03A716 UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) 036816 03A816 UART1 transmit/receive mode register (U1MR) 036916 03A916 UART1 bit rate generator (U1BRG) 036A16 03AA16 036B16 03AB16 036C16 03AC16 036D16 03AD16 036E16 03AE16 036F16 03AF16 037016 03B016 037116 03B116 037216 03B216 037316 03B316 03B416 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 UART2 special mode register 3 (U2SMR3) UART2 special mode register 2 (U2SMR2) UART2 special mode register (U2SMR) 03B516 UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) 03B816 UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0)* UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) Flash identification register (FIDR) (Note1) 03B616 03B716 Flash memory control register 0 (FMR0) (Note1) DMA0 request cause select register (DM0SL) 03B916 03BA16 DMA1 request cause select register (DM1SL) 03BB16 03BC16 03BD16 03BE16 CRC data register (CRCD) CRC input register (CRCIN) 03BF16 Note 1 : This register is only exist in flash memory version. Note 2 : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Note 3 : M16C/62N (80-pin version) group is not provided with the functions, in whole or in part, of the registers marked with an *. But the relevant registers need to be dealt with as given on page 7. Figure 1.7.2. Location of peripheral unit control registers (2) 19 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) 03D016 03D116 03D216 03D316 03D416 A-D control register 2 (ADCON2) 03D516 03D616 03D716 03D816 A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) 03D916 03DA16 D-A register 1 (DA1) 03DB16 03DC16 D-A control register (DACON) 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 Port P0 register (P0) Port P1 register (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 register (P2) Port P3 register (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 register (P4) Port P5 register (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 register (P6) Port P7 register (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 register (P8) Port P9 register (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 register (P10) * * * * * * * * 03F516 03F616 Port P10 direction register (PD10) 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Note 1: M16C/62N (80-pin version) group is not provided with the functions, in whole or in part, of the registers marked with an *. But the relevant registers need to be dealt with as given on page 7. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.7.3. Location of peripheral unit control registers (3) 20 Mitsubishi microcomputers M16C / 62N Group (80-pin) Software Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Reset Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode Single-chip mode M16C/62N (80-pin version) group support single-chip mode only. In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. Figure 1.8.1 shows the processor mode registers 0 and 1. Figure 1.8.2 shows the memory map. 21 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor Mode Processor mode register 0 (Note) b7 b6 b5 b4 0 0 0 0 b3 b2 b1 b0 0 Symbol PM0 Address 000416 Bit symbol PM00 Bit name Processor mode bit PM01 Function b1 b0 0 0: Single-chip mode 0 1: Must not be set 1 0: Must not be set 1 1: Must not be set Must always be set to "0" Reserved bit PM03 When reset 0016 Software reset bit Reserved bit AAAA AAAA AAAA R W The device is reset when this bit is set to "1". The value of this bit is "0" when read. Must always be set to "0" Note: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Processor mode register 1 (Note 1) b7 b6 b5 b4 0 0 0 b3 b2 b1 b0 0 Symbol PM1 Address 000516 Bit symbol Bit name Reserved bit When reset 000000X02 Function Must always be set to "0" Nothing is assigned. AA AA AA AA AA AA R W In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. PM12 PM13 Watchdog timer function select bit 0 : Interrupt 1 : Reset (Note 3) Internal reserved area expansion bit (Note 2) 0 : The internal RAM area is 15 kbytes or less and the internal ROM area is 192 kbytes or less 1 : Expands the internal RAM area and internal ROM area to over 15 kbytes and to over 192 kbytes respectively. (Note 2) Reserved bit PM17 Must always be set to "0" Wait bit 0 : No wait state 1 : Wait state inserted (Note 3) Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: When the reset is revoked, this bit is set to "0". To expand the internal area, set this bit to "1" in user program. And the top of user program must be allocated to D000016 or subsequent address. Note 3: This bit can only be set to "1". Figure 1.8.1. Processor mode registers 0 and 1 22 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor Mode Single-chip mode 0000016 SFR area 0040016 Internal RAM area XXXXX16 Reserved area RAM size Address XXXXX16 10K bytes 02BFF16 128K bytes E000016 20K bytes 053FF16 256K bytes C000016 ROM size Address YYYYY16 YYYYY16 Internal ROM area FFFFF16 Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 1.8.2. Memory map Internal Reserved Area Expansion Bit (PM13) This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In M30625MGN, for example, to set this bit to "1" expands the internal RAM area and the internal ROM area to 20 Kbytes and 256 Kbytes respectively. When the reset is revoked, this bit is set to "0". To expand the internal area, set this bit to "1" in user program. And the top of user program must be allocated to D000016 or subsequent address. In the case of the product in which the internal ROM is 192 Kbytes or less and the internal RAM is 15 Kbytes or less, set this bit to "0". The internal area is not expanded and any action is not affected, even if this bit is set to "1". 23 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Wait Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note). A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit. Table 1.8.1 shows the software wait and bus cycles. Figure 1.8.3 shows example bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to "1". Table 1.8.1. Software waits and bus cycles Wait bit SFR Invalid 2 BCLK cycles 0 1 BCLK cycle 1 2 BCLK cycles Internal ROM/RAM 24 Bus cycle Area Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Wait < No wait > Bus cycle (Note1) BCLK Write signal Read signal Output Data bus Address bus (Note2) Address Input Address Chip select (Note2) < With wait > Bus cycle (Note1) BCLK Write signal Read signal Data bus Address bus (Note2) Input Output Address Address Chip select (Note2) Note 1 : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Note 2 : The address bus and chip select may be extended depending on the CPU status such as that of the instruction queue buffer. Note 3 : This figure shows microcomputer internal state. Figure 1.8.3. Typical bus timings using software wait 25 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.9.1. Main clock and sub clock generating circuits Use of clock Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other Main clock generating circuit Sub clock generating circuit * CPU's operating clock source * CPU's operating clock source * Internal peripheral units' * Timer A/B's count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input Example of oscillator circuit Figure 1.9.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.9.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.9.1 and 1.9.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XIN XIN XOUT XOUT Open (Note) Rd Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.9.1. Examples of main clock Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XCIN XCOUT XCIN XCOUT Open (Note) RCd Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.9.2. Examples of sub clock 26 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Control Figure 1.9.3 shows the block diagram of the clock generating circuit. XCIN XCOUT fC32 1/32 f1 CM04 f1SIO2 fAD fC f8SIO2 f8 Sub clock f32SIO2 CM10 "1" Write signal f32 S Q XIN XOUT a RESET Software reset Main clock CM02 CM05 NMI Interrupt request level judgment output AAA AAA b R c Divider d CM07=0 BCLK fC CM07=1 S Q WAIT instruction R c b a 1/2 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 Details of divider Figure 1.9.3. Clock generating circuit 27 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to "1" when the port XC select bit (bit 4 at address 000616) is set to "0" , shifting to stop mode and at a reset. When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. (3) BCLK The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0 (bit 6 at address 000616) changes to "1" when shifting from highspeed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. 28 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Figure 1.9.4 shows the system clock control registers 0 and 1. System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 Bit symbol When reset 4816 Bit name Function b1 b0 AA AA AA AA AA AA AA AA AA RW Clock output function select bit (Valid only in single-chip mode) 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output CM02 WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) CM03 XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH CM04 Port XC select bit (Note 10) 0 : I/O port 1 : XCIN-XCOUT generation (Note 9) CM05 Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) 0 : On 1 : Off CM06 Main clock division select bit 0 (Note 7) 0 : CM16 and CM17 valid 1 : Division by 8 mode CM07 System clock select bit (Note 6) 0 : XIN, XOUT 1 : XCIN, XCOUT CM00 CM01 Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when the port XC select bit (CM04) is set to "0", shiffing to stop mode and at a reset. Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock oscillation is stable, set system clock select bit (CM07) to "1" before setting this bit to "1". The main clock division select bit 0 (CM06) and the XIN-XOUT drive capacity select bit (CM15) change to "1" when this bit is set to "1". Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT ("H") via the feedback resistor. Note 6: Set port XC select bit (CM04) to "1" and stabilize the sub-clock oscillating before setting this bit from "0" to "1". Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the main clock oscillating before setting this bit from "1" to "0". Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. Note 8: fC32 is not included. Do not set to "1" when using low-speed or low power dissipation mode. Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. Note10: The XCIN-XCOUT drive capacity select bit changes to "1" when this bit is set to "0". System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 0 0 0 0 b0 Symbol CM1 Address 000716 Bit symbol CM10 When reset 2016 Bit name All clock stop control bit (Note4) Function 0 : Clock on 1 : All clocks off (stop mode) Reserved bit Must always be set to "0" Reserved bit Must always be set to "0" Reserved bit Must always be set to "0" Reserved bit Must always be set to "0" CM15 XIN-XOUT drive capacity select bit (Note 2) CM16 Main clock division select bit 1 (Note 3) 0 : LOW 1 : HIGH b7 b6 CM17 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode AAA A AA AA AA AA AA AA RW Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state. Figure 1.9.4. Clock control registers 0 and 1 29 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed. Stop Mode Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4 functions provided an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a _______ hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. The main clock division select bit 0 (bit 6 at address 000616) changes to "1" when shifting from high-speed/ medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. Table 1.9.2. Port status during stop mode Pin Port CLKOUT 30 When fc selected When f8, f32 selected Single-chip mode Retains status before stop mode "H" Retains status before stop mode Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Wait Mode Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to "1". Table 1.9.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware _______ reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift to wait mode. Table 1.9.3. Port status during wait mode Pin Port CLKOUT Single-chip mode Retains status before wait mode When fC selected Does not stop When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is retained. 31 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition of BCLK Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.9.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address 000616) and the XIN-XOUT drive capacity select bit (bit 5 at address 000716) change to "1" when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.9.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 CM1i : bit i of the address 000716 CM0i : bit i of the address 000616 32 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode Mitsubishi microcomputers M16C / 62N Group (80-pin) Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode * High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. * Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fC clock is supplied by the sub-clock. Each peripheral function operates according to its assigned clock. * Low power dissipation mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the sub-clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.9.5 is the state transition diagram of the above modes. 33 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control Transition of stop mode, wait mode Reset All oscillators stopped CM10 = "1" Stop mode Interrupt CM07 = "0" CM06 = "1" CM05 = "0" CM10 = "1" (Note) Medium-speed mode (divided-by-8 mode) WAIT instruction CPU operation stopped Wait mode Interrupt Interrupt All oscillators stopped Stop mode High-speed/mediumspeed mode CM10 = "1" Low power dissipation mode Stop mode Low-speed/low power dissipation mode Interrupt CPU operation stopped Wait mode Interrupt Low-speed mode All oscillators stopped CM10 = "1" WAIT instruction WAIT instruction CPU operation stopped Wait mode Interrupt Normal mode (Refer to the following for the transition of normal mode.) Note : To CM0, CM1 registers, do a simultaneous write by word access. Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = "1" BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" Main clock is oscillating CM04 = "0" Sub clock is oscillating CM07 = "0" (Note 1) CM06 = "1" CM04 = "0" CM04 = "1" (Notes 1, 3) High-speed mode Medium-speed mode (divided-by-2 mode) BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-8 mode) Medium-speed mode (divided-by-4 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0" BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1" Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = "0" (Note 1, 3) BCLK : f(XCIN) CM07 = "1" CM07 = "1" (Note 2) CM05 = "0" CM04 = "0" CM06 = "0" (Notes 1,3) Main clock is oscillating Sub clock is stopped CM04 = "1" High-speed mode Medium-speed mode (divided-by-2 mode) BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-4 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0" BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1" Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = "1" (Note 2) CM05 = "1" BCLK : f(XCIN) CM07 = "1" CM06 = "1" CM15 = "1" CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM04 = "1" CM03 = "1" Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 1.9.5. State transition diagram of Power control mode 34 CM05 = "1" Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.9.6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316), SI/O3 control register (address 036216), and SI/O4 control register (address 036616) can only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs can be allocated to port P9. If, after "1" (write-enabled) has been written to the port P9 direction register and SI/Oi control register (i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0". Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol Address 000A16 When reset XXXXX0002 Bit name Function PRC0 Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) PRC1 Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) PRC2 Enables writing to port P9 direction register (address 03F316) and SI/Oi control registers (i=3,4) (addresses 036216 and 036616) (Note) 0 : Write-inhibited 1 : Write-enabled A A A AA A AA AA R W Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note: Writing a value to an address after "1" is written to this bit returns the bit to "0" . Other bits do not automatically return to "0" and they must therefore be reset by the program. Figure 1.9.6. Protect register 35 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of Interrupt Type of Interrupts Figure 1.10.1 lists the types of interrupts. Hardware Special Peripheral I/O (Note) Interrupt Software Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched _______ Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.10.1. Classification of interrupts * Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. 36 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to "1". The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK interrupt A BRK interrupt occurs when executing the BRK instruction. * INT instruction interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. 37 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. * Reset ____________ Reset occurs if an "L" is input to the RESET pin. _______ * NMI interrupt _______ _______ An NMI interrupt occurs if an "L" is input to the NMI pin. ________ * DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. * Watchdog timer interrupt Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). * Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed. * Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. * Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. * DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. * Key-input interrupt ___ A key-input interrupt occurs if an "L" is input to the KI pin. * A-D conversion interrupt This is an interrupt that the A-D converter generates. * UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. * UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. * Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates * Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. ________ ________ * INT0 interrupt through INT2 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin. 38 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.10.2 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA MSB LSB Vector address + 0 Low address Vector address + 1 Mid address Vector address + 2 0000 High address Vector address + 3 0000 0000 Figure 1.10.2. Format for specifying interrupt vector addresses * Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.10.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.10.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. 39 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Variable vector tables The addresses in the variable vector table can be modified, according to the user's settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.10.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.10.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Vector table address Interrupt source Address (L) to address (H) Software interrupt number 0 +0 to +3 (Note 1) BRK instruction Software interrupt number 4 +16 to +19 (Note 1) INT3 (Note 4) Software interrupt number 5 +20 to +23 (Note 1) Timer B5 Software interrupt number 6 +24 to +27 (Note 1) Timer B4 Software interrupt number 7 +28 to +31 (Note 1) Timer B3 Software interrupt number 8 +32 to +35 (Note 1) SI/O4/INT5 (Note 3, 4) Software interrupt number 9 +36 to +39 (Note 1) SI/O3/INT4 (Note 3, 4) Software interrupt number 10 +40 to +43 (Note 1) Bus collision detection Software interrupt number 11 +44 to +47 (Note 1) DMA0 Software interrupt number 12 +48 to +51 (Note 1) DMA1 Software interrupt number 13 +52 to +55 (Note 1) Key input interrupt Software interrupt number 14 +56 to +59 (Note 1) A-D Software interrupt number 15 +60 to +63 (Note 1) UART2 transmit/NACK (Note 2) Software interrupt number 16 +64 to +67 (Note 1) UART2 receive/ACK (Note 2) Software interrupt number 17 +68 to +71 (Note 1) UART0 transmit Software interrupt number 18 +72 to +75 (Note 1) UART0 receive Software interrupt number 19 +76 to +79 (Note 1) UART1 transmit Software interrupt number 20 +80 to +83 (Note 1) UART1 receive Software interrupt number 21 +84 to +87 (Note 1) Timer A0 Software interrupt number 22 +88 to +91 (Note 1) Timer A1 Software interrupt number 23 +92 to +95 (Note 1) Timer A2 Software interrupt number 24 +96 to +99 (Note 1) Timer A3 Software interrupt number 25 +100 to +103 (Note 1) Timer A4 Software interrupt number 26 +104 to +107 (Note 1) Timer B0 Software interrupt number 27 +108 to +111 (Note 1) Timer B1 Software interrupt number 28 +112 to +115 (Note 1) Timer B2 Software interrupt number 29 +116 to +119 (Note 1) INT0 Software interrupt number 30 +120 to +123 (Note 1) INT1 Software interrupt number 31 +124 to +127 (Note 1) INT2 Software interrupt number 32 +128 to +131 (Note 1) to Software interrupt number 63 to +252 to +255 (Note 1) Software interrupt Remarks Cannot be masked I flag Cannot be masked I flag Note 1: Address relative to address in interrupt table register (INTB). Note 2: When IIC mode is selected, NACK and ACK interrupts are selected. Note 3: It is selected by interrupt request cause select bits (bits 6, 7 in address 035F16 ). Note 4: P15/INT3 to P17/INT5 do not connect to outside. INT3 to INT5 interrupt cannot be used in M16C/62N (80-pin version) group. 40 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.10.3 shows the interrupt control registers. 41 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register (Note 2) AAA b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Bit symbol ILVL0 Address 004516 to 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 Bit name Interrupt priority level select bit ILVL2 IR Function b2 b1 b0 000: 001: 010: 011: 100: 101: 110: 111: ILVL1 Interrupt request bit When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 AA A AA A AA A AA A AA A R W Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 : Interrupt not requested 1 : Interrupt requested Nothing is assigned. (Note 1) In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. AA b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol Address INTiIC(i=3) 004416 SiIC/INTjIC (i=4, 3) 004816, 004916 (j=5, 4) 004816, 004916 INTiIC(i=0 to 2) 005D16 to 005F16 Bit symbol ILVL0 Bit name Interrupt priority level select bit ILVL1 ILVL2 IR POL When reset XX00X0002 XX00X0002 XX00X0002 XX00X0002 Interrupt request bit Polarity select bit Reserved bit Nothing is assigned. Function b2 b1 b0 AA A AA A AA A AA A AA A AA A AA A AA A AA A R W 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to "0" (Note 1) In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. Note 3: INT3 to INT5 interrupts cannot be used. However, must set INT3IC to "0016". INT4IC and INT5IC are shared with S3IC and S4IC respectively. When not using as S3IC and S4IC, must set INT3IC and INT4IC to "0016". Figure 1.10.3. Interrupt control registers 42 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: * interrupt enable flag (I flag) = 1 * interrupt request bit = 1 * interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.10.3. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Table 1.10.4. Interrupt levels enabled according to the contents of the IPL Priority order b2 b1 b0 IPL Enabled interrupt priority levels IPL2 IPL1 IPL0 0 0 0 Level 0 (interrupt disabled) 0 0 1 Level 1 0 1 0 0 1 1 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Interrupt levels 2 and above are enabled Level 2 0 1 0 Interrupt levels 3 and above are enabled 1 Level 3 0 1 1 Interrupt levels 4 and above are enabled 0 0 Level 4 1 0 0 Interrupt levels 5 and above are enabled 1 0 1 Level 5 1 0 1 Interrupt levels 6 and above are enabled 1 1 0 Level 6 1 1 0 Interrupt levels 7 and above are enabled 1 1 1 Level 7 1 1 1 All maskable interrupts are disabled Low High 43 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When changing an interrupt control register in a sate of interrupts being disabled, please read the following precautions on instructions used before changing the register. Changing a non-interrupt request bit If an interrupt request for an interrupt control register is generated during an instruction to rewrite the register is being executed, there is a case that the interrupt request bit is not set and consequently the interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV 44 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.10.4 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence Instruction in interrupt routine (b) Interrupt response time (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.10.4. Interrupt response time 45 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.10.5. Table 1.10.5. Time required for executing the interrupt sequence Interrupt vector address Stack pointer (SP) value 16-Bit bus, without wait 8-Bit bus, without wait Even Even 18 cycles (Note 1) 20 cycles (Note 1) Even Odd 19 cycles (Note 1) 20 cycles (Note 1) Odd (Note 2) Even 19 cycles (Note 1) 20 cycles (Note 1) Odd (Note 2) Odd 20 cycles (Note 1) 20 cycles (Note 1) ________ Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BCLK Address bus Address 0000 Interrupt information Data bus R Indeterminate Indeterminate SP-2 SP-4 SP-2 contents SP-4 contents vec vec+2 vec contents PC vec+2 contents Indeterminate W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Figure 1.10.5. Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.10.6 is set in the IPL. Table 1.10.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL _______ Watchdog timer, NMI 7 Reset 0 Other 46 Not changed Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.10.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address MSB Stack area Address MSB LSB Stack area LSB m-4 m-4 Program counter (PCL) m-3 m-3 Program counter (PCM) m-2 m-2 Flag register (FLGL) m-1 m-1 m Content of previous stack m+1 Content of previous stack Stack status before interrupt request is acknowledged [SP] Stack pointer value before interrupt occurs Flag register (FLGH) [SP] New stack pointer value Program counter (PCH) m Content of previous stack m+1 Content of previous stack Stack status after interrupt request is acknowledged Figure 1.10.6. State of stack before and after acceptance of interrupt request 47 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.10.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP). (1) Stack pointer (SP) contains even number Address Stack area Sequence in which order registers are saved [SP] - 5 (Odd) [SP] - 4 (Even) Program counter (PCL) [SP] - 3(Odd) Program counter (PCM) [SP] - 2 (Even) Flag register (FLGL) [SP] - 1(Odd) [SP] Flag register (FLGH) Program counter (PCH) (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits (Even) Finished saving registers in two operations. (2) Stack pointer (SP) contains odd number Address Stack area Sequence in which order registers are saved [SP] - 5 (Even) [SP] - 4(Odd) Program counter (PCL) (3) [SP] - 3 (Even) Program counter (PCM) (4) [SP] - 2(Odd) Flag register (FLGL) [SP] - 1 (Even) [SP] Flag register (FLGH) Program counter (PCH) Saved simultaneously, all 8 bits (1) (2) (Odd) Finished saving registers in four operations. Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 1.10.7. Operation of saving registers 48 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.10.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.10.8. Hardware interrupts priorities Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.10.9 shows the circuit that judges the interrupt priority level. 49 Mitsubishi microcomputers M16C / 62N Group (80-pin) Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt INT1 Level 0 (initial value) High Timer B2 Timer B0 Timer A3 Timer A1 Timer B4 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception Priority of peripheral I/O interrupts (if priority levels are same) UART2 reception/ACK A-D conversion DMA1 Bus collision detection Serial I/O4 Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 Low Serial I/O3 Processor interrupt priority level (IPL) Interrupt request level judgment output to clock generating circuit (Fig.1.9.3) Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Figure 1.10.9. Maskable interrupts priorities (peripheral I/O interrupts) 50 Interrupt request accepted Mitsubishi microcomputers M16C / 62N Group (80-pin) ______ INT Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ______ INT Interrupt ________ _______ INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0"). Figure 1.10.10 shows the Interrupt request cause select register. AA A AA AA AAAA AAA Interrupt request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit symbol Address 035F16 When reset 0016 Bit name Function IFSR0 INT0 interrupt polarity switching bit 0 : One edge 1 : Two edges IFSR1 INT1 interrupt polarity switching bit 0 : One edge 1 : Two edges IFSR2 INT2 interrupt polarity switching bit 0 : One edge 1 : Two edges IFSR3 INT3 interrupt polarity switching bit (Note) 0 : One edge 1 : Two edges IFSR4 INT4 interrupt polarity switching bit (Note) 0 : One edge 1 : Two edges IFSR5 INT5 interrupt polarity switching bit (Note) 0 : One edge 1 : Two edges IFSR6 Interrupt request cause select bit (Note) 0 : SIO3 1 : INT4 IFSR7 Interrupt request cause select bit (Note) 0 : SIO4 1 : INT5 AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A R W Note : INT3 to INT5 interrupts cannot be used in M16C/62N (80-pin version) group. Thus, set this bit to "0". Figure 1.10.10. Interrupt request cause select register 51 Mitsubishi microcomputers M16C / 62N Group (80-pin) ________ NMI Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ______ NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 1.10.11 shows the block diagram of the key input interrupt. Note that if an "L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Port P104-P107 pull-up select bit Pull-up transistor Key input interrupt control register Port P107 direction register (address 004D16) Port P107 direction register P107/KI3 Pull-up transistor Port P106 direction register Interrupt control circuit P106/KI2 Pull-up transistor Port P105 direction register P105/KI1 Pull-up transistor Port P104 direction register P104/KI0 Figure 1.10.11. Block diagram of key input interrupt 52 Key input interrupt request Mitsubishi microcomputers M16C / 62N Group (80-pin) Address Match Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value of the program counter (PC) that is saved to the stack area varies depending on the instruction being executed. Figure 1.10.12 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 000916 When reset XXXXXX002 AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA AAAAAAAAAAAAAA Bit symbol Bit name Function AIER0 Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 Function Address setting register for address match interrupt When reset X0000016 X0000016 AA A AAA Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Figure 1.10.12. Address match interrupt-related registers 53 Mitsubishi microcomputers M16C / 62N Group (80-pin) Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 * When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Even if the address 0000016 is read out by software, "0" is set to the enabled highest priority interrupt source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur. Do not read address 0000016 by software. (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any _______ interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ _______ * The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused. Be sure to work on it. _______ * The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ * Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to the _______ NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down. _______ * Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to _______ the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ * Signals input to the NMI pin require "L" level and "H" level of 2 clock +300ns or more, from the operation clock of the CPU. (4) External interrupt ________ * Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 to _______ INT2 regardless of the CPU operation clock. ________ _______ * When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 1.10.13 shows the procedure for ______ changing the INT interrupt generate factor. Clear the interrupt enable flag to "0" (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit NOP X 2 Clear the interrupt request bit to "0" Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to "1" (Enable interrupt) Note: Execute the setting above individually. Don't execute two or more settings at once(by one instruction). ______ Figure 1.10.13. Switching condition of INT interrupt request 54 Mitsubishi microcomputers M16C / 62N Group (80-pin) Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Watchdog timer interrupt * Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). (6) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When changing an interrupt control register in a sate of interrupts being disabled, please read the following precautions on instructions used before changing the register. Changing a non-interrupt request bit If an interrupt request for an interrupt control register is generated during an instruction to rewrite the register is being executed, there is a case that the interrupt request bit is not set and consequently the interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV 55 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. When the watchdog timer interrupt is selected, write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). Watchdog timer interrupt is selected when bit 2 (PM12) of the processor mode register 1 (address 000516) is "0" and reset is selected when PM12 is "1". No value other than "1" can be written in PM12. Once when reset is selected (PM12="1"), watchdog timer interrupt cannot be selected by software. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. With XIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 32.8 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Also PM12 is initialized only when reset. The watchdog timer interrupt is selected after reset is cancelled. Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timerrelated registers. 56 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Prescaler "CM07 = 0" "WDC7 = 0" 1/16 1/128 BCLK "PM12 = 0" Watchdog timer interrupt request "CM07 = 0" "WDC7 = 1" Watchdog timer Reset "PM12 = 1" "CM07 = 1" 1/2 Write to the watchdog timer start register (address 000E16) Set to "7FFF16" RESET Figure 1.11.1. Block diagram of watchdog timer Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol WDC Bit symbol Address 000F16 When reset 000XXXXX2 Function Bit name High-order bit of watchdog timer Reserved bit Must always be set to "0" Reserved bit Must always be set to "0" WDC7 Prescaler select bit 0 : Divided by 16 1 : Divided by 128 AA AA A AA A AA A R W Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written. A R W Figure 1.11.2. Watchdog timer control and start registers 57 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.12.1 shows the block diagram of the DMAC. Table 1.12.1 shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the registers used by the DMAC. AA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA AA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAA AAA A AAA AAA A AA AAA A AA AA AA AA A A AA A AA AA A A AAAA A AA AAAA AA AA AA AA AA A A AA AA A A A AA A A AA AA AA AA Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) (addresses 002916, 002816) DMA0 transfer counter TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20) (addresses 003616 to 003416) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.12.1. Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. 58 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Table 1.12.1. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred Specification 2 (cycle steal method) * From any address in the 1M bytes space to a fixed address * From a fixed address to any address in the 1M bytes space * From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ ________ DMA request factors (Note) Falling edge of INT0 or INT1, or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrpt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode * Single transfer mode After the transfer counter underflows, the DMA enable bit turns to "0", and the DMAC turns inactive * Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a "0" is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to "1", the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive * When the DMA enable bit is set to "0", the DMAC is inactive. * After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, the Reload timing for forward value of one of source pointer and destination pointer - the one specified for the address pointer and forward direction - is reloaded to the forward direction address pointer,and the value transfer counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. 59 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Bit symbol DSEL0 Address 03B816 When reset 0016 Function Bit name DMA request cause select bit DSEL1 DSEL2 DSEL3 b3 b2 b1 b0 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMS DMA request cause expansion select bit 0 : Normal 1 : Expanded cause DSR Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0") Figure 1.12.2. DMAC register (1) 60 AA A A AA AA AA AA R W A A AA Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Address 03BA16 Function Bit name Bit symbol DSEL0 When reset 0016 DMA request cause select bit DSEL1 DSEL2 DSEL3 b3 b2 b1 b0 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMS DMA request cause expansion select bit 0 : Normal 1 : Expanded cause DSR Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0") AA A AA A AA AA AA A A AA R W DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiCON(i=0,1) Bit symbol Address 002C16, 003C16 When reset 00000X002 Bit name Function DMBIT Transfer unit bit select bit 0 : 16 bits 1 : 8 bits DMASL Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMAS DMA request bit (Note 1) 0 : DMA not requested 1 : DMA requested DMAE DMA enable bit 0 : Disabled 1 : Enabled DSD Source address direction select bit (Note 3) 0 : Fixed 1 : Forward DAD Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". AA AA AA AA AA A A AA R W (Note 2) Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously. Figure 1.12.3. DMAC register (2) 61 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 When reset Indeterminate Indeterminate Transfer address specification Function * Source pointer Stores the source address R W AA 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 002416 003616 to 003416 When reset Indeterminate Indeterminate Transfer address specification Function * Destination pointer Stores the destination address AAAA R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 002816 003916, 003816 Function * Transfer counter Set a value one less than the transfer count Figure 1.12.4. DMAC register (3) 62 When reset Indeterminate Indeterminate Transfer count specification 000016 to FFFF16 AA R W Mitsubishi microcomputers M16C / 62N Group (80-pin) DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.12.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 1.12.5, if data is being transferred in 16-bit units and source address is odd, two bus cycles are required for both the source read cycle and the destination write cycle. 63 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (1) 16-bit transfers from even address and the source address is even. BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use (2) 16-bit transfers and the source address is odd BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source + 1 Destination Source Dummy cycle CPU use (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use (4) One wait is inserted into the source read under the conditions in (2) BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.12.5. Example of the transfer cycles for a source read 64 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.12.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.12.2. No. of DMAC transfer cycles Transfer unit 8-bit transfers (DMBIT= "1") 16-bit transfers (DMBIT= "0") Bus width 16-bit (BYTE= "L") 16-bit (BYTE = "L") Access address Even Odd Even Odd Single-chip mode No. of read cycles No. of write cycles 1 1 1 1 1 1 2 2 Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2 65 Mitsubishi microcomputers M16C / 62N Group (80-pin) DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set to "1" or "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors _______ An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). _______ Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchro_______ nizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected. 66 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 1.12.6 shows an example of DMA transfer effected by external factors. An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur. BCLK DMA0 DMA1 CPU INT0 AAAA AAAA AAAA AAA AAAAAA AAAAAA AA AAAAAA AAA AAAAAA AA Obtainm ent of the bus right DMA0 request bit INT1 DMA1 request bit Figure 1.12.6. An example of DMA transfer effected by external factors 67 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Figures 1.13.1 and 1.13.2 show the block diagram of timers. Clock prescaler f1 XIN f8 1/8 1/4 f32 1/32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" fC32 Reset f1 f8 f32 fC32 * Timer mode * One-shot timer mode * PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 * Event counter mode * Timer mode * One-shot timer mode Timer A1 interrupt Timer A1 * Event counter mode * Timer mode * One-shot timer mode Timer A2 interrupt Timer A2 * Event counter mode * Timer mode * One-shot timer mode * PWM mode Timer A3 interrupt TA3IN Noise filter Timer A3 * Event counter mode * Timer mode * One-shot timer mode * PWM mode Timer A4 interrupt TA4IN Noise filter Timer A4 * Event counter mode Timer B2 overflow Note 1: The TA0IN pin (P71) is shared with RxD2, SCL and the TB5IN pin, so be careful. Note 2: Timer A1 and A2 have no pin to perform input/output. Thus I/O functions like as external event input, PWM output and one-shot output cannot be used. Figure 1.13.1. Timer A block diagram 68 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Clock prescaler f1 XIN f8 1/8 1/4 f32 fC32 1/32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" Reset f1 f8 f32 fC32 Timer A * Timer mode * Pulse width measuring mode TB0IN Noise filter Timer B0 interrupt Timer B0 * Event counter mode * Timer mode Timer B1 interrupt Timer B1 * Event counter mode * Timer mode * Pulse width measuring mode TB2IN Noise filter Timer B2 interrupt Timer B2 * Event counter mode * Timer mode * Pulse width measuring mode TB3IN Noise filter Timer B3 interrupt Timer B3 * Event counter mode * Timer mode * Pulse width measuring mode TB4IN Noise filter Timer B4 interrupt Timer B4 * Event counter mode * Timer mode * Pulse width measuring mode TB5IN Noise filter Timer B5 interrupt Timer B5 * Event counter mode Note 1: The TB5IN pin (P71) is shared with RxD2, SCL and the TA0IN pin, so be careful. Note 2: TB1IN pin is not connect to outside. Thus, timer B1 can use neither in external event count mode or pulse width measurement mode. Figure 1.13.2. Timer B block diagram 69 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer A Figure 1.13.3 shows the block diagram of timer A. Figures 1.13.4 to 1.13.6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. However, in M16C/62N (80-pin version) group, timer A1 and A2 are used for internal timer since timer A1 and A2 have no pin to perform input/output. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. AAA AAA Data bus high-order bits Clock source selection Data bus low-order bits * Timer * One shot * PWM f1 f8 f32 Low-order 8 bits * Timer (gate function) fC32 * Event counter AA AA Reload register (16) Clock selection High-order 8 bits Counter (16) Polarity selection Up count/down count Clock selection TAiIN (i = 0 to 4) Always down count except in event counter mode Count start flag (Address 038016) TB2 overflow To external trigger circuit TAj overflow (j = i - 1. Note, however, that j = 4 when i = 0) Down count TAk overflow Up/down flag (k = i + 1. Note, however, that k = 0 when i = 4) TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 (Address 038416) Pulse output TAiOUT (i = 0 to 4) Toggle flip-flop Note 1: The TA0IN pin (P71) is shared with RxD2, SCL and the TB5IN pin, so be careful. Note 2: TA1IN, TA1OUT, TA2IN and TA2OUT do not connect to outside. Do not set functions using these pins. Figure 1.13.3. Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 Bit name Operation mode select bit TMOD1 MR0 MR1 Address When reset 039616 to 039A16 0016 Function b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode Function varies with each operation mode MR2 MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Figure 1.13.4. Timer A-related registers (1) 70 A A A A AA A AA A A AA A AA AA RW Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 Symbol TA0 TA1 TA2 TA3 TA4 b0 Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate AA AAAA AA AA AA Function Values that can be set * Timer mode Counts an internal count source 000016 to FFFF16 RW * Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow * One-shot timer mode Counts a one shot width 000016 to FFFF16 (Note 2,4) * Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator 000016 to FFFE16 (Note 3,4) 0016 to FE16 * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator (High-order address) 0016 to FF16 (Low-order address) (Note 3,4) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016", the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to "000016", the pulse width modulator does not operate and the output level of the TAiOUT pin remains "L" level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to "0016". Note 4: Use MOV instruction to write to this register. Count start flag b7 b6 b5 b4 b3 b2 b1 Symbol TABSR b0 Address 038016 When reset 0016 AAAA AA AA A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA A AA Bit symbol Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag Function R W 0 : Stops counting 1 : Starts counting Up/down flag (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 038416 Bit symbol Bit name TA0UD Timer A0 up/down flag TA1UD Timer A1 up/down flag TA2UD Timer A2 up/down flag TA3UD Timer A3 up/down flag TA4UD TA2P TA3P TA4P When reset 0016 Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause Timer A4 up/down flag Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit (Note 1) 1 : two-phase pulse signal processing enabled (Note 3) Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to "0" AAA A AAA A AA AAAA AA AA AA RW Note 1: Since timer A2 have no pin to perform input/output, must set this bit to "0" . Note 2: Use MOV instruction to write to this register. Note 3: Set the TAiIN and TAiOUT pins correspondent port direction registers to "0". Figure 1.13.5. Timer A-related registers (2) 71 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A One-shot start flag b7 b6 b5 b4 b3 b2 b1 Symbol ONSF b0 Address 038216 When reset 00X000002 Bit symbol Bit name TA0OS Timer A0 one-shot start flag Function TA1OS Timer A1 one-shot start flag TA2OS Timer A2 one-shot start flag TA3OS Timer A3 one-shot start flag TA4OS Timer A4 one-shot start flag 1 : Timer start When read, the value is "0" Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. TA0TGL Timer A0 event/trigger select bit TA0TGH b7 b6 AA AA AA AA AA AA RW 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to "0". Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol TA1TGL Address 038316 Bit name Timer A1 event/trigger select bit TA1TGH TA2TGL Timer A2 event/trigger select bit TA2TGH TA3TGL Timer A3 event/trigger select bit TA3TGH TA4TGL Timer A4 event/trigger select bit TA4TGH When reset 0016 Function b1 b0 AA AA AA AA AA AA AA AA R W 0 0 : Input on TA1IN is selected (Note1,2) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 0 0 : Input on TA2IN is selected (Note1,2) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 0 0 : Input on TA3IN is selected (Note1) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 0 0 : Input on TA4IN is selected (Note1) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note 1: Set the corresponding port direction register to "0". Note 2: Since TA1IN and TA2IN are not connected to external pin, do not select these functions. Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 Bit symbol Bit name When reset 0XXXXXXX2 Function RW AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AA Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag Figure 1.13.6. Timer A-related registers (3) 72 0 : No effect 1 : Prescaler is reset (When read, the value is "0") Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.13.1.) Figure 1.13.7 shows the timer Ai mode register in timer mode. Table 1.13.1. Specifications of timer mode Item Specification Count source f1, f8, f32, fC32 Count operation * Down count * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing When the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Gate function Counting can be started and stopped by the TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed Note: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 0 0 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 Address When reset 039616 to 039A16 0016 Bit name Operation mode select bit Function b1 b0 0 0 : Timer mode AA A AA A AA A AA A AA A AA A AA A AA A RW Pulse output function 0 : Pulse is not output select bit (TAiOUT pin is a normal port pin) (Note 4) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) b4 b3 Gate function select bit 0 X (Note 2): Gate function not available (Note 4) (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3) MR2 MR3 0 (Must always be "0" in timer mode) TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0". Note 4: Set these bits to "0" in timer A1 and A2 mode registers. Figure 1.13.7. Timer Ai mode register in timer mode 73 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.13.2 lists timer specifications when counting a single-phase external signal. Figure 1.13.8 shows the timer Ai mode register in event counter mode. Table 1.13.3 lists timer specifications when counting a two-phase external signal. Figure 1.13.9 shows the timer Ai mode register in event counter mode. Table 1.13.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (effective edge can be selected by software) * TB2 overflow, TAj overflow Count operation * Up count or down count can be selected by external signal or software * When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed Note 1: This does not apply when the free-run function is selected. Note 2: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 0 1 Bit symbol TMOD0 Bit name Function Operation mode select bit b1 b0 MR0 Pulse output function select bit (Note 5) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) MR1 Count polarity select bit (Note 3, 5) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge MR2 Up/down switching cause select bit (Note 5) 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) 0 1 : Event counter mode (Note 1) TMOD1 MR3 0 (Must always be "0" in event counter mode) TCK0 Count operation type select bit TCK1 Invalid when not using two-phase pulse signal processing Can be "0" or "1" 0 : Reload type 1 : Free-run type AA A AA A AA A RW Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0". Note 5: Set these bits "0" in timer A1 and A2 mode registers. Figure 1.13.8. Timer Ai mode register in event counter mode 74 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Table 1.13.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function (Note 3) Specification * Two-phase pulse signals input to TAiIN or TAiOUT pin * Up count or down count can be selected by two-phase pulse signal * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input (Set the TAiIN pin correspondent port direction register to "0") Two-phase pulse input (Set the TAiOUT pin correspondent port direction register to "0") Count value can be read out by reading timer A2, A3, or A4 register * When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter * When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) * Normal processing operation (timer A2 and timer A3) The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H" TAiOUT TAiIN (i=2,3) Up count Up count Up Down count count Down count Down count * Multiply-by-4 processing operation (timer A3 and timer A4) If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges TAiIN (i=3,4) Count up all edges Count down all edges Note 1: This does not apply when the free-run function is selected. Note 2: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Note 3: Timer A3 alone can be selected. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. 75 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer Ai mode register (When using two-phase pulse signal processing) (Note 3) b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 Bit name TMOD0 Operation mode select bit TMOD1 Function b1 b0 0 1 : Event counter mode MR0 0 (Must always be "0" when using two-phase pulse signal processing) MR1 0 (Must always be "0" when using two-phase pulse signal processing) MR2 1 (Must always be "1" when using two-phase pulse signal processing) MR3 0 (Must always be "0" when using two-phase pulse signal processing) TCK0 Count operation type select bit 0 : Reload type 1 : Free-run type TCK1 Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Normal processing operation 1 : Multiply-by-4 processing operation AA AA AA AA A A A A A A AA RW Note 1: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to "1". Also, always be sure to set the event/trigger select bits (addresses 038216 and 038316) to "00". Note 3: Timer A2 cannot be used for two-phase pulse signal processing. Figure 1.13.9. Timer Ai mode register in event counter mode 76 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.13.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.13.10 shows the timer Ai mode register in one-shot timer mode. Table1.13.4. Timer specifications in one-shot timer mode Item Specification Count source f1, f8, f32, fC32 Count operation * The timer counts down * When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition * An external trigger is input * The timer overflows * The one-shot start flag is set (= 1) Count stop condition * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) The count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Note: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Interrupt request generation timing Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 1 0 Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol Bit name TMOD0 Operation mode select bit TMOD1 Function b1 b0 1 0 : One-shot timer mode MR0 Pulse output function 0 : Pulse is not output select bit (TAiOUT pin is a normal port pin) (Note 4) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) MR1 External trigger select bit (Note 2,4) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) MR2 Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select bits MR3 0 (Must always be "0" in one-shot timer mode) TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 AAA AAA A A AA AAA AA A AA AAA AA AAA AA RW Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 3: Set the corresponding port direction register to "0". Note 4: Set these bits to "0" in timer A1 and A2 mode registers. Figure 1.13.10. Timer Ai mode register in one-shot timer mode 77 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.13.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Timer A1 and A2 have no output pin, so it doesn't work in this mode. Figure 1.13.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.13.12 shows the example of how a 16-bit pulse width modulator operates. Figure 1.13.13 shows the example of how an 8-bit pulse width modulator operates. Table 1.13.5. Timer specifications in pulse width modulation mode Item Count source Count operation Specification f1, f8, f32, fC32 * The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting * High level width n / fi n : Set value 16 * Cycle time (2 -1) / fi fixed * High level width n (m+1) / fi n : values set to timer Ai register's high-order address * Cycle time (28-1) (m+1) / fi m : values set to timer Ai register's low-order address * External trigger is input * The timer overflows * The count start flag is set (= 1) * The count start flag is reset (= 0) PWM pulse goes "L" Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) 16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Note: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 Address When reset 039616 to 039A16 0016 Bit name Operation mode select bit Function b1 b0 1 1 : PWM mode A AA AAA A AA AA AA AA AA AA AA AA MR0 1 (Must always be "1" in PWM mode) (Note 3) MR1 External trigger select bit (Note 1,3) 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) MR2 Trigger select bit 0: Count start flag is valid 1: Selected by event/trigger select bits MR3 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator TCK0 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 R W Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding port direction register to "0". Note 3: Set these bits "0" in timer A1 and A2 mode registers. Figure 1.13.11. Timer Ai mode register in pulse width modulation mode 78 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 - 1) Count source "H" TAiIN pin input signal "L" Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin "H" Timer Ai interrupt request bit "1" "L" "0" fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleared by software Note 1: n = 000016 to FFFE16. Note 2: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Figure 1.13.12. Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 - 1) Count source (Note1) TAiIN pin input signal "H" "L" AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA 1 / fi X (m + 1) "H" Underflow signal of 8-bit prescaler (Note2) "L" 1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin "H" Timer Ai interrupt request bit "1" "L" "0" fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Note 4: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT). Figure 1.13.13. Example of how an 8-bit pulse width modulator operates 79 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Timer B Figure 1.13.14 shows the block diagram of timer B. Figures 1.13.15 and 1.13.16 show the timer B-related registers. However, timer B1 is used for internal timer since timer B1 does not have input port. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Clock source selection High-order 8 bits Low-order 8 bits f1 * Timer * Pulse period/pulse width measurement f8 f32 fC32 Reload register (16) Clock selection Counter (16) * Event counter Count start flag Polarity switching and edge pulse TBiIN (i = 0 to 5) (address 038016) Counter reset circuit Can be selected in only event counter mode TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 TBj overflow (j = i - 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Note: TB1IN does not connect to outside. Thus, do not select the function using this pin. Figure 1.13.14. Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16 Bit symbol TMOD0 Function Bit name Operation mode select bit TMOD1 MR0 When reset 00XX00002 00XX00002 b1 b0 AA A AAA AAA AAA AAA A AA AAA R W 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode (Note 3) 1 1 : Must not be set Function varies with each operation mode MR1 MR2 (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Note 3: Do not set this mode in timer B1 mode register because timer B1 does not have input port. Figure 1.13.15. Timer B-related registers (1) 80 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Timer Bi register (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 TB3 TB4 TB5 Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416 Function When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate AA A A AA A A A Values that can be set * Timer mode Counts the timer's period RW 000016 to FFFF16 * Event counter mode 000016 to FFFF16 Counts external pulses input or a timer overflow (Note 2) * Pulse period / pulse width measurement mode Measures a pulse period or width (Note 2) Note 1: Read and write data in 16-bit units. Note 2: Timer B1 is provided with no input pin, so it does not work in this mode. The overflow of the timer, however, can be counted in event counter mode. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAA A AA Bit symbol Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag Function RW 0 : Stops counting 1 : Starts counting Timer B3, 4, 5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 034016 When reset 000XXXXX2 AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAA AA A A Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. TB3S Timer B3 count start flag TB4S Timer B4 count start flag TB5S Timer B5 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit symbol Address 038116 Bit name When reset 0XXXXXXX2 Function R W AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAA Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0") Figure 1.13.16. Timer B-related registers (2) 81 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.13.6.) Figure 1.13.17 shows the timer Bi mode register in timer mode. Table 1.13.6. Timer specifications in timer mode Item Count source Count operation Specification Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer f1, f8, f32, fC32 * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Note: Timer B1 works exclusively as an internal timer since timer B1 does not have input port (TB1IN). AA A AA A Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TBiMR(i=0 to 5) Bit symbol TMOD0 Address 039B16 to 039D16 035B16 to 035D16 Bit name Operation mode select bit TMOD1 MR0 MR1 MR2 When reset 00XX00002 00XX00002 Function b1 b0 0 0 : Timer mode Invalid in timer mode Can be "0" or "1" 0 (Must always be "0" in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. MR3 Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read in timer mode, turns out to be indeterminate. TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 1.13.17. Timer Bi mode register in timer mode 82 AAA A AA AAA A AAA AA AAA A A AAA AAA R (Note 1) (Note 2) W Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.13.7.) However, timer B1 works exclusively as an internal timer because timer B1 does not have input port. Figure 1.13.18 shows the timer Bi mode register in event counter mode. Table 1.13.7. Timer specifications in event counter mode Item Specification Count source * External signals input to TBiIN pin * Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Read from timer Write to timer Count source input Count value can be read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Note: Timer B1 works exclusively as an internal timer since timer B1 does not have input port (TB1IN). AA Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 Bit symbol Bit name TMOD0 Operation mode select bit TMOD1 MR0 MR1 MR2 Count polarity select bit (Note 1) When reset 00XX00002 00XX00002 Function b1 b0 0 1 : Event counter mode b3 b2 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set 0 (Must always be "0" in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. MR3 Invalid in event counter mode. In an attempt to write to this bit, write "0". The value, if read in event counter mode, turns out to be indeterminate. TCK0 Invalid in event counter mode. Can be "0" or "1". TCK1 Event clock select (Note 5) 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3) AAAA AA AAAA AA AAA AAAA R W (Note 2) (Note 3) Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If TBj overflow is selected, this bit can be "0" or "1". Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to "0". Note 5: Must always "1" in timer B1 mode register because timer B1 does not have input port. Figure 1.13.18. Timer Bi mode register in event counter mode 83 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.13.8.) However, this function cannot be used since timer B1 does not have input port. Figure 1.13.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.13.20 shows the operation timing when measuring a pulse period. Figure 1.13.21 shows the operation timing when measuring a pulse width. Table 1.13.8. Timer specifications in pulse period/pulse width measurement mode Item Specification Count source f1, f8, f32, fC32 Count operation * Up count * Counter value "000016" is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing * When measurement pulse's effective edge is input (Note 1) * When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to "1". Assume that the count start flag condition is "1" and then the timer Bi overflow flag becomes "1". If the timer Bi mode register has a writeaccess after next count cycle of the timer from the above condition, the timer Bi overflow flag becomes "0".) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register's content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer has started counting. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol TBiMR(i=0 to 5) Bit symbol TMOD0 TMOD1 MR0 Address 039B16 to 039D16 035B16 to 035D16 Bit name Operation mode select bit Measurement mode select bit MR1 MR2 When reset 00XX00002 00XX00002 Function b1 b0 1 0 : Pulse period / pulse width measurement mode (Note 4) b3 b2 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Must not be set 0 (Must always be "0" in pulse period/pulse width measurement mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. MR3 Timer Bi overflow flag ( Note 1) 0 : Timer did not overflow 1 : Timer has overflowed TCK0 Count source select bit b7 b6 TCK1 AA AA AA AA AA A AA AAAA 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 R W (Note 2) (Note 3) Note 1: It is indeterminate when reset. Assume that the count start flag condition is "1" and then the timer Bi overflow flag becomes "1". If the timer Bi mode register has a write access after next count cycle of the timer from the above condition, the timer Bi overflow flag becomes "0". This flag cannot be set to "1" by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Do not set this mode in timer B1 mode register because timer B1 dose not have input port. Figure 1.13.19. Timer Bi mode register in pulse period/pulse width measurement mode 84 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source "H" Measurement pulse Reload register transfer timing "L" Transfer (indeterminate value) Transfer (measured value) counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches "000016" "1" Count start flag "0" Timer Bi interrupt request bit "1" Timer Bi overflow flag "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software. "0" Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.13.20. Operation timing when measuring a pulse period Count source Measurement pulse Reload register transfer timing "H" "L" counter Transfer (indeterminate value) (Note 1) Transfer (measured value) (Note 1) Transfer (measured value) (Note 1) Transfer (measured value) (Note 1) (Note 2) Timing at which counter reaches "000016" Count start flag "1" "0" Timer Bi interrupt request bit "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag "1" "0" Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.13.21. Operation timing when measuring a pulse width 85 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Serial I/O Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.14.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.14.2 and 1.14.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. UART and IIC mode can be used in UART2. Table 1.14.1 shows the comparison of functions of UART0 through UART2, and Figures 1.14.4 to 1.14.9 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 1.14.1. Comparison of functions of UART0 through UART2 Function UART0 UART1 UART2 CLK polarity selection Possible (Note 1) Possible (Note 1) Possible (Note 5) LSB first / MSB first selection Possible (Note 1) Possible (Note 1) Possible (Note 2) Continuous receive mode selection Possible (Note 1) Possible (Note 1) Possible (Note 5) Transfer clock output from multiple pins selection Impossible Possible (Note 1) Impossible Serial data logic switch Impossible Impossible Sleep mode selection Possible TxD, RxD I/O polarity switch Impossible Impossible Possible TxD, RxD port output format CMOS output CMOS output N-channel open-drain output (Note 6) Parity error signal output Impossible Impossible Possible Bus collision detection Impossible Impossible Possible (Note 3) Possible Possible (Note 3) Impossible Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. Note 5: Since CLK2 and CTS2/RTS2 do not connect to outside, this function cannot be used. Note 6: Connect this pin to Vcc via a pull-up resistor on the outside. 86 (Note 4) (Note 4) Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O (UART0) RxD0 TxD0 UART reception 1/16 Clock source selection f1 f8 f32 Reception control circuit Clock synchronous type Bit rate generator Internal (address 03A116) UART transmission 1 / (n0+1) 1/16 Transmission control circuit Clock synchronous type External Receive clock Transmit/ receive unit Transmit clock Clock synchronous type (when internal clock is selected) 1/2 Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK polarity reversing circuit CLK0 CTS/RTS disabled CTS/RTS selected RTS0 CTS0 / RTS0 Vcc CTS/RTS disabled CTS0 (UART1) RxD1 TxD1 1/16 Clock source selection Bit rate generator Internal (address 03A916) f1 f8 f32 UART reception 1 / (n1+1) UART transmission 1/16 CTS1 / RTS1 / CLKS1 Clock synchronous type (when internal clock is selected) Transmit clock Clock synchronous type (when external clock is selected) CTS/RTS disabled CTS/RTS selected Clock output pin select switch Transmit/ receive unit (when internal clock is selected) 1/2 CLK1 Transmission control circuit Clock synchronous type Clock synchronous type External CLK polarity reversing circuit Reception control circuit Clock synchronous type Receive clock RTS1 VCC CTS/RTS disabled CTS1 (UART2) RxD2 TxD polarity reversing circuit RxD polarity reversing circuit UART reception Clock source selection Bit rate generator f1 Internal (address 037916) f8 f32 1 / (n2+1) 1/16 Clock synchronous type Reception control circuit UART transmission 1/16 Clock synchronous type Transmission control circuit Receive clock TxD2 Transmit/ receive unit Transmit clock Clock synchronous type 1/2 (when internal clock is selected) Note: CLK and CTS/RTS of UART2 do not connect to outside. Clock synchronous serial I/O mode cannot be used in UART2. n0 : Values set to UART0 bit rate generator (U0BRG) n1 : Values set to UART1 bit rate generator (U1BRG) n2 : Values set to UART2 bit rate generator (U2BRG) Figure 1.14.1. Block diagram of UARTi (i = 0 to 2) 87 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Clock synchronous type PAR disabled 1SP RxDi SP SP UART (7 bits) UART (8 bits) Clock synchronous type UARTi receive register UART (7 bits) PAR 2SP PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 UART (9 bits) 2SP SP SP Clock synchronous type UART TxDi PAR 1SP PAR disabled "0" Clock synchronous type UART (7 bits) UARTi transmit register UART (7 bits) UART (8 bits) Clock synchronous type Figure 1.14.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit 88 UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) PAR enabled D0 SP: Stop bit PAR: Parity bit Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O No reverse RxD data reverse circuit RxD2 Reverse Clock synchronous type PAR disabled 1SP SP SP UART2 receive register UART(7 bits) PAR 2SP PAR enabled 0 UART (7 bits) UART (8 bits) Clock synchronous type 0 0 0 UART 0 Clock synchronous type UART (9 bits) 0 0 UART (8 bits) UART (9 bits) D8 D0 UART2 receive buffer register Logic reverse circuit + MSB/LSB conversion circuit Address 037E16 Address 037F16 D7 D6 D5 D4 D3 D2 D1 Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled 2SP SP SP UART (9 bits) Clock synchronous type UART PAR 1SP PAR disabled "0" Clock synchronous type UART (7 bits) UART (8 bits) UART2 transmit register UART(7 bits) Clock synchronous type Error signal output disable No reverse TxD data reverse circuit Error signal output circuit Error signal output enable Note: Clock synchronous serial I/O mode cannot be used in UART2. TxD2 Reverse SP: Stop bit PAR: Parity bit Figure 1.14.3. Block diagram of UART2 transmit/receive unit 89 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function A R W Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Bit symbol Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During clock synchronous serial I/O mode) Bit name Receive data Function (During UART mode) Receive data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". ABT Arbitration lost detecting flag (Note 2) OER Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found FER Framing error flag (Note 1) Invalid 0 : No framing error 1 : Framing error found PER Parity error flag (Note 1) Invalid 0 : No parity error 1 : Parity error found SUM Error sum flag (Note 1) Invalid 0 : No error 1 : Error found 0 : Not detected 1 : Detected Invalid A A A A A A A A R W Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set "0". The value, if read, turns out to be "0". UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 When reset Indeterminate Indeterminate Indeterminate Function Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Figure 1.14.4. Serial I/O-related registers (1) 90 Values that can be set 0016 to FF16 A RW Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 Symbol UiMR(i=0,1) b0 Bit symbol SMD0 Address 03A016, 03A816 When reset 0016 Function (During clock synchronous serial I/O mode) Bit name Must always be 001 Serial I/O mode select bit b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set SMD1 SMD2 Function (During UART mode) b2 b1 b0 AA AA A AA A AA A AA A A A A A A AA R W 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock (Note) 0 : Internal clock 1 : External clock (Note) STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit Must always be "0" 0 : Sleep mode deselected 1 : Sleep mode selected Note : Set the corresponding port direction register to "0". UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 Symbol U2MR b0 Bit symbol SMD0 Address 037816 Bit name Serial I/O mode select bit SMD1 When reset 0016 Function (During clock synchronous serial I/O mode) Clock synchronous serial I/O mode can not be used in UART2 (Note). SMD2 Function (During UART mode) b2 b1 b0 R W AA A A A A A AA A AA A AA AA A A AA 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set CKDIR Internal/external clock select bit Must always be "0" STPS Stop bit length select bit 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit 0 : No reverse 1 : Reverse Usually set to "0" Note : Bit 2 to bit 0 are set to "0102" when I2C mode is used. Figure 1.14.5. Serial I/O-related registers (2) 91 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 Address When reset 0816 03A416, 03AC16 Function (During clock synchronous serial I/O mode) Bit name BRG count source select bit CLK1 Function (During UART mode) b1 b0 b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CRS CTS/RTS function select bit TXEPT Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) NCH Data output select bit 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CKPOL CLK polarity select bit UFORM Transfer format select bit 0 : Transmit data is output at falling Must always be "0" edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : LSB first 1 : MSB first Must always be "0" AAAA AAA AA AA R W AA AA AA AA Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Address 037C16 Bit symbol Bit name CLK0 BRG count source select bit CLK1 When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode) b1 b0 b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CRS CTS/RTS function select bit TXEPT Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CRD CTS/RTS disable bit (Note 4) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0". Must always be "0" 0 : Transmit data is output at falling CKPOL CLK polarity select bit UFORM Transfer format select bit (Note 3) edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : LSB first 1 : MSB first 0 : LSB first 1 : MSB first AAA AAA AA A AAA AAA A A AA AA AA R W Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Note 4: This bit must be set to "1" in M16C/62N (80-pin version) group. Note 5: UART2 clock synchronous serial I/O mode cannot be used in M16C/62N (80-pin version) group. Figure 1.14.6. Serial I/O-related registers (3) 92 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 Symbol UiC1(i=0,1) b0 Bit symbol Address 03A516,03AD16 When reset 0216 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". AA A AA A A R W UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 Symbol U2C1 b0 Bit symbol Address 037D16 Bit name When reset 0216 Function (During clock synchronous serial I/O mode) Function (During UART mode) TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) U2RRM UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Must always be "0" U2LCH Data logic select bit 0 : No reverse 1 : Reverse 0 : No reverse 1 : Reverse U2ERE Error signal output enable bit Must always be "0" 0 : Output disabled 1 : Output enabled U2IRS UART2 transmit interrupt cause select bit R W AA A A AA A AA AA A A A A AA Note: UART2 clock synchronous serial I/O mode cannot be used in M16C/62N (80-pin version) group. Figure 1.14.7. Serial I/O-related registers (4) 93 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol UCON When reset X00000002 Bit name Function (During clock synchronous serial I/O mode) UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed Bit symbol U0IRS Address 03B016 (TXEPT = 1) U1IRS 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed UART1 transmit interrupt cause select bit (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Must always be "0" U1RRM UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Must always be "0" CLKMD0 CLK/CLKS select bit 0 Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) 0 : Normal mode Must always be "0" (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected Must always be set to "0" Reserved bit AA AA A A AA AA AA AA AA RW Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A816) = "0". UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Bit symbol Address 037716 Bit name When reset 8016 Function (During clock synchronous serial I/O mode) Function (During UART mode) R W AA A AA A AA A AA A AA A AA A AA A AA A AAA IICM IIC mode select bit 0 : Normal mode 1 : I2C mode Must always be "0" ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte Must always be "0" BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected Must always be "0" SCLL sync output enable bit 0 : Disabled 1 : Enabled Must always be "0" ABSCS Bus collision detect sampling clock select bit Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 ACSE Auto clear function select bit of transmit enable bit Must always be "0" 0 : No auto clear function 1 : Auto clear at occurrence of bus collision SSS Transmit start condition select bit Must always be "0" 0 : Ordinary 1 : Falling edge of RxD2 SDDS SDA digital delay select bit (Note 2) LSYN (Note 1) 0 : Must always be "0" Must always be "0" when not using I2C mode 1 : Digital delay output is selected Note 1: Nothing but "0" may be written. Note 2: When not in I2C mode, do not set this bit by writing a "1". During normal mode, fix it to "0". When this bit = "0", UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to "000". Also, when SDDS = "0", the U2SMR3 register cannot be read or written to. Note 3: UART2 clock synchronous serial I/O mode cannot be used in M16C/62N (80-pin version) group. Figure 1.14.8. Serial I/O-related registers (5) 94 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Bit symbol Address 037616 When reset 0016 Function (I2C bus exclusive use) Bit name IICM2 I 2C mode select bit 2 Refer to Table 1.14.11 CSC Clock-synchronous bit 0 : Disabled 1 : Enabled SWC SCL wait output bit 0 : Disabled 1 : Enabled ALS SDA output stop bit 0 : Disabled 1 : Enabled STAC UART2 initialization bit 0 : Disabled 1 : Enabled SWC2 SCL wait output bit 2 0: UART2 clock 1: 0 output SDHI SDA output disable bit 0: Enabled 1: Disabled (high impedance) SHTC Start/stop condition control bit Set this bit to "1" in I2C mode (refer to Table 1.14.12) AA AA A A AA AA AA AA AA AA R W UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol Address 037516 When reset 0016 Function (I 2 C bus exclusive use register) Bit name Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. However, when SDDS = "1", the value "0" is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3) DL1 DL2 b7 b6 b5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Must not be set when using I2C mode 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) Digital delay 0 : 4 to 5 cycles of 1/f(XIN) is selected 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) R W AA AA A A AA Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = "1", the value is "0016". When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = "1", be sure to write 0's to bits 0-4. When SDDS = "0", this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to "000" when SDDS = "0". After a reset, these bits are set to "000". However, because these bits can be read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate. Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 200 ns, so be sure to take this into account when using the device. Figure 1.14.9. Serial I/O-related registers (6) 95 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.14.2 and 1.14.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.14.10 shows the UARTi transmit/receive mode register. Clock synchronous serial I/O mode cannot be used in UART2. Table 1.14.2. Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format * Transfer data length: 8 bits Transfer clock * When internal clock is selected (bit 3 at addresses 03A016, 03A816 = "0") : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816 = "1") : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control * CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = "0" _______ _______ _ When CTS function selected, CTS input level = "L" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = "0" : CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = "1" : CLKi input level = "L" Reception start condition * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16) = "1" _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = "0" : CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = "1" : CLKi input level = "L" * When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = "0" generation timing : Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = "1" : Interrupts requested when data transmission from UARTi transfer register is completed * When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. 96 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode Table 1.14.3. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification * CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) (Note) UART1 transfer clock can be chosen by software to be output from one of the two pins set Note : Clock synchronous serial I/O mode cannot be used in UART2. 97 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode UARTi transmit/receive mode registers b7 0 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A016, 03A816 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Internal/external clock select bit Function b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note) STPS PRY Invalid in clock synchronous serial I/O mode PRYE SLEP 0 (Must always be "0" in clock synchronous serial I/O mode) Note : Set the corresponding port direction register to "0". AA A AA A A A A AA AA A A A AA A AA A A RW Figure 1.14.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode 98 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode Table 1.14.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.14.4. Input/output pin functions in clock synchronous serial I/O mode (when transfer clock output from multiple pins is not selected) Pin name Function Method of selection TxDi (P63, P67) Serial data output (Outputs dummy data when performing reception only) RxDi (P62, P66) Serial data input Port P62 and P66 direction register (bits 2 and 6 at address 03EE16)= "0" (Can be used as an input port when performing transmission only) CLKi (P61, P65) Transfer clock output Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "0" Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "1" Port P61 and P65 direction register (bits 1 and 5 at address 03EE16) = "0" CTS input CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = "0" Port P60 and P64 direction register (bits 0 and 4 at address 03EE16) = "0" RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = "1" Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = "1" CTSi/RTSi (P60, P64) Note: Clock synchronous serial I/O mode cannot be used in UART2. 99 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode * Example of transmit timing (when internal clock is selected) Tc Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) "1" "0" Data is set in UARTi transmit buffer register "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi TCLK "L" Stopped pulsing because CTS = "H" Stopped pulsing because transfer enable bit = "0" CLKi TxDi D0 D 1 D2 D3 D4 D5 D6 D7 Transmit register empty flag (TXEPT) D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 "1" "0" Transmit interrupt "1" request bit (IR) "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi * Example of receive timing (when external clock is selected) "1" Receive enable bit (RE) "0" Transmit enable bit (TE) "0" Transmit buffer empty flag (Tl) "1" "0" "H" RTSi Dummy data is set in UARTi transmit buffer register "1" Transferred from UARTi transmit buffer register to UARTi transmit register "L" 1 / fEXT CLKi Receive data is taken in D 0 D1 D 2 D3 D 4 D5 D6 D 7 RxDi Receive complete "1" flag (Rl) "0" Receive interrupt request bit (IR) Transferred from UARTi receive register to UARTi receive buffer register D0 D 1 D 2 D3 D4 D5 Read out from UARTi receive buffer register "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". Meet the following conditions are met when the CLK input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register fEXT: frequency of external clock Figure 1.14.11. Typical transmit/receive timings in clock synchronous serial I/O mode 100 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure 1.14.12, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16) allows selection of the polarity of the transfer clock. * When CLK polarity select bit = "0" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 1: The CLK pin level when not transferring data is "H". * When CLK polarity select bit = "1" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 2: The CLK pin level when not transferring data is "L". Figure 1.14.12. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.14.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first". * When transfer format select bit = "0" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D2 D1 D0 LSB first RXDi * When transfer format select bit = "1" CLKi TXDi D7 D6 D5 D4 D3 MSB first RXDi D7 D6 D5 D4 D3 D2 D1 D0 Note: This applies when the CLK polarity select bit = "0". Figure 1.14.13. Transfer format 101 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.14.3.) The multiple pins function is valid only when the internal clock is selected for UART1. Note that when _______ _______ this function is selected, UART1 CTS/RTS function cannot be used. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN IN CLK CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.14.14. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. 102 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.14.5 and 1.14.6 list the specifications of the UART mode. Figure 1.14.15 shows the UARTi transmit/receive mode register. Table 1.14.5. Specifications of UART Mode (1) Item Specification Transfer data format * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected Transfer clock * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816 ="1") : fEXT/16(n+1)(Note 1,2,4) _______ _______ _______ _______ Transmission/reception control * CTS function, RTS function, CTS and RTS function invalid: selectable (Note 5) Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" buffer empty flag (bit 1_______ at addresses 03A516, 03AD16, 037D16) = "0" - Transmit _______ - When CTS function selected, CTS input level = "L" Reception start condition * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" - Start bit detection Interrupt request * When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. Note 4: Since CLK 2 does not have external port, external clock cannot be selected as UART2 transfer clock. _______ _______ _________ ________ Note 5: Set the CTS/RTS disable bit (bit 4 at address 037C16) to "1" because CTS2/RTS2 does not have external port. 103 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.14.6. Specifications of UART Mode (2) Item Select function 104 Specification * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. * TxD, RxD I/O polarity switch (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A016, 03A816 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Internal / external clock select bit Stop bit length select bit 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit 0 : Sleep mode deselected 1 : Sleep mode selected STPS AA AA A A AA A A A A A A AA AA RW Note : Set the corresponding port direction register to "0". UART2 transmit / receive mode register b7 b6 b5 b4 b3 0 b2 b1 b0 Symbol U2MR Address 037816 Bit symbol SMD0 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Internal / external clock select bit Stop bit length select bit Must always be "0". PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse 1 : Reverse STPS A AA A AA AA AA AA AA AA AA RW 0 : One stop bit 1 : Two stop bits Note: Usually set to "0". Figure 1.14.15. UARTi transmit/receive mode register in UART mode 105 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.14.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the Nchannel open-drain is selected, this pin is in floating state.) Table 1.14.7. Input/output pin functions in UART mode Pin name Function Method of selection TxDi Serial data (P63, P67, P70) output RxDi (P62, P66, P71) Serial data input Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) CLKi (P61, P65) Programmable I/O port Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "0" Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "1" Port P61 and P65 direction register (bits 1 and 5 at address 03EE16) = "0" CTS input CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = "0" Port P60 and P64 direction register (bits 0 and 4 at address 03EE16) = "0" RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = "1" Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = "1" CTSi/RTSi (P60, P64) Note 1: Since CLK2(P72) does not have external port, use internal as UART2 transfer clock. _______ _______ _______ _______ Note 2: Set the CTS/RTS disable bit (bit 4 at address 037C16) to "1" because CTS2/RTS2(P73) does not have external port. 106 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode * Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L". Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register. "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi "L" Start bit TxDi Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stopped pulsing because transmit enable bit = "0" Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 SP "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Note: CTS2 does not have external port so that this porrt function cannot be used. * Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register "0" Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.14.16. Typical transmit timings in UART mode(UART0, UART1) 107 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode * Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" Data is set in UART2 transmit buffer register "0" Note "0" Transferred from UART2 transmit buffer register to UARTi transmit register Start bit TxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Figure 1.14.17. Typical transmit timings in UART mode(UART2) 108 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode * Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit "1" "0" Stop bit Start bit RxDi D1 D0 D7 Sampled "L" Receive data taken in Transfer clock Reception triggered when transfer clock "1" is generated by falling edge of start bit Receive complete flag Transferred from UARTi receive register to UARTi receive buffer register "0" "H" "L" RTSi Receive interrupt request bit "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected. Note: RTS in UART2 is not connected to the outside. Figure 1.14.18. Typical receive timing in UART mode (a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0". (b) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned "1", data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.14.19 shows the example of timing for switching serial data logic. * When LSB first, parity enabled, one stop bit Transfer clock "H" "L" TxD2 "H" (no reverse) "L" TxD2 "H" (reverse) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 1.14.19. Timing for switching serial data logic 109 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use. (d) Bus collision detection function (UART2) This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.14.20 shows the example of detection timing of a bus collision (in UART mode). Transfer clock "H" "L" TxD2 "H" ST SP ST SP "L" RxD2 "H" "L" Bus collision detection interrupt request signal "1" Bus collision detection interrupt request bit "1" "0" "0" ST : Start bit SP : Stop bit Figure 1.14.20. Detection timing of a bus collision (in UART mode) 110 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (3) Clock-asynchronous serial I/O mode (used for the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.14.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface). Table 1.14.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface) Item Transfer data format Transfer clock Specification * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 037816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") * With the internal clock chosen (bit 3 of address 037816 = "0") : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 _______ _______ Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") Other settings * The sleep mode select function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" Reception start condition * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit Interrupt request * When transmitting generation timing When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TxD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UART2 bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UART2 receive interrupt request bit does not change. 111 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UART2 transmit buffer register Note 1 "0" Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2 ST D0 Parity bit D 1 D2 D3 D4 D5 D 6 D 7 P Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP P SP RxD2 An "L" level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. The level is detected by the interrupt routine. "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Tc Transfer clock Receive enable bit (RE) "1" "0" Start bit RxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 An "L" level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) Receive complete flag (RI) "1" Receive interrupt request bit (IR) "1" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "0" Read to receive buffer Read to receive buffer "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Note 2: Equal in waveform because TxD2 and RxD2 are connected. Figure 1.14.21. Typical transmit/receive timing in UART mode (used for the SIM interface) 112 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (a) Function for outputting a parity error signal During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned "1", you can output an "L" level from the TXD2 pin when a parity error is detected. And during transmission, comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is assigned "0", the transmission completion interrupt occurs in the half cycle later of the transfer clock. Therefore parity error signals can be detected by a transmission completion interrupt program. Figure 1.14.22 shows the output timing of the parity error signal. * LSB first Transfer clock "H" "L" RxD2 "H" "L" TxD2 "H" "L" Receive complete flag "1" "0" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Hi-Z ST : Start bit P : Even Parity SP : Stop bit Figure 1.14.22. Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.14.23 shows the SIM interface format. Transfer clcck TxD2 (direct) D0 D1 D2 D3 D4 D5 D6 D7 P TxD2 (inverse) D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.14.23. SIM interface format 113 Mitsubishi microcomputers M16C / 62N Group (80-pin) Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.14.24 shows the example of connecting the SIM interface. Connect TxD2 and RxD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 1.14.24. Connecting the SIM interface 114 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register UART2 Special Mode Register The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.14.25 shows the UART2 special mode register. Bit 0 of the UART2 special mode register (037716) is used as the I2C mode select bit. Setting "1" in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus) interface effective. Table 1.14.9 shows the relation between the I2C mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Bit symbol Address 037716 When reset 8016 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) A AA AA AA AA A AA AAA AA AA AA A AA AAA AA A R W IICM IIC mode select bit 0 : Normal mode 1 : I2C mode Must always be "0" ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte Must always be "0" BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected Must always be "0" SCLL sync output enable bit 0 : Disabled 1 : Enabled Must always be "0" ABSCS Bus collision detect sampling clock select bit Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 ACSE Auto clear function select bit of transmit enable bit Must always be "0" 0 : No auto clear function 1 : Auto clear at occurrence of bus collision SSS Transmit start condition select bit Must always be "0" 0 : Ordinary 1 : Falling edge of RxD2 SDDS SDA digital delay select bit (Note 2) LSYN (Note 1) 0 : Must always be "0" Must always be "0" when not using I2C mode 1 : Digital delay output is selected Note 1: Nothing but "0" may be written. Note 2: When not in I2C mode, do not set this bit by writing a "1". During normal mode, fix it to "0". When this bit = "0", UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to "000". Also, when SDDS = "0", the U2SMR3 register cannot be read or written to. Note 3: UART2 clock synchronous serial I/O mode cannot be used in M16C/62N (80-pin version) group. 2 UART2 special mode register 3 (I C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol Address 037516 When reset 0016 Function (I 2C bus exclusive use register) Bit name Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. However, when SDDS = "1", the value "0" is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3) DL1 DL2 b7 b6 b5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 R W AAAA AAAA 0 : Must not be set when using I2C mode 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) Digital delay 0 : 4 to 5 cycles of 1/f(XIN) is selected 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = "1", the value is "0016". When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = "1", be sure to write 0's to bits 0-4. When SDDS = "0", this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to "000" when SDDS = "0". After a reset, these bits are set to "000". However, because these bits can be read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate. Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 200 ns, so be sure to take this into account when using the device. Figure 1.14.25. UART2 special mode register 115 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register P70 through P72 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 Digital delay (Divider) To DMA0, DMA1 UART2 SDDS=0 or DL=000 Transmission register SDDS=1 and DL 000 D IICM=0 or IICM2=1 UART2 transmission/ NACK interrupt request IICM=1 and IICM2=0 SDHI ALS Q Arbitration T Noize Filter Timer To DMA0 IICM=1 IICM=0 or IICM2=1 Reception register IICM=0 UART2 reception/ACK interrupt request, DMA1 request UART2 IICM=1 and IICM2=0 Start condition detection S Q R Stop condition detection Bus busy NACK D L-synchronous output enabling bit Falling edge detection Q T D P71/RxD2/SCL I/O R Q IICM=1 SWC2 IICM=1 Noize Filter External clock Noize Filter ACK 9th pulse (Port P71 output data latch) Internal clock UART2 Selector Q T Data bus IICM=1 Bus collision CLK control detection Bus collision/start, stop condition detection interrupt request IICM=0 UART2 Falling edge of 9 bit IICM=0 SWC Port reading UART2 * With IICM set to 1, the port terminal is to be readable IICM=0 P72/CLK2 Selector even if 1 is assigned to P71 of the direction register. I/O Timer Note: P72/CLK2 is not connected to the outside. Figure 1.14.26. Functional block diagram for I2C mode Table 1.14.9. Features in I2C mode Function Normal mode I2C mode (Note 1) Start condition detection or stop condition detection 1 Factor of interrupt number 10 (Note 2) Bus collision detection 2 Factor of interrupt number 15 (Note 2) UART2 transmission No acknowledgment detection (NACK) 3 Factor of interrupt number 16 (Note 2) UART2 reception Acknowledgment detection (ACK) 4 UART2 transmission output delay Not delayed Delayed (digital delay) 5 P70 at the time when UART2 is in use TxD2 (output) SDA (input/output) (Note 3) 6 P71 at the time when UART2 is in use RxD2 (input) SCL (input/output) 7 DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits UART2 reception Acknowledgment detection (ACK) 8 Noise filter width 15ns 200ns Reading P71 Reading the terminal when 0 is assigned to the direction register Reading the terminal regardless of the value of the direction register H level (when 0 is assigned to the CLK polarity select bit) The value set in latch P70 when the port is selected 9 10 Initial value of UART2 output Note 1: Make the settings given below when I2C mode is in use. Set "0 1 0 2" in bits 2, 1, and 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid. 116 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register Figure 1.14.26 shows the functional block diagram for I2C mode. Setting "1" in the I2C mode select bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to "L". The amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.14.10. Table 1.14.10. Delay circuit select conditions Register value Contents Digital delay is selected No delay IICM SDDS 1 1 0 0 DL 001 to 111 (000) Digital delay is added When IICM = "0", no delay circuit is selected. When IICM = "0", however, always make sure SDDS = "0". An attempt to read Port P71 (SCL) results in getting the terminal's level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment nondetection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the start condition detection, and set to "0" by the stop condition detection. The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer register, and "1" is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to "1" goes the P71 data register to "0" in synchronization with the SCL terminal level going to "L". 117 Mitsubishi microcomputers M16C / 62N Group (80-pin) UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Some other functions added are explained here. Figure 1.14.27 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal. 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK TxD/RxD 1: Timer A0 overflow Timer A0 2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UART2 special mode register) 0: In normal state CLK TxD Enabling transmission With "1: falling edge of RxD2" selected CLK TxD RxD Figure 1.14.27. Some other functions added 118 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 UART2 Special Mode Register 2 UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.14.28 shows the UART2 special mode register 2. UART2 special mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Bit symbol Address 037616 When reset 0016 Bit name Function IICM2 I 2C mode select bit 2 Refer to Table 1.14.11 CSC Clock-synchronous bit 0 : Disabled 1 : Enabled SWC SCL wait output bit 0 : Disabled 1 : Enabled ALS SDA output stop bit 0 : Disabled 1 : Enabled STAC UART2 initialization bit 0 : Disabled 1 : Enabled SWC2 SCL wait output bit 2 SDHI SDA output disable bit 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) SHTC Start/stop condition control bit 1: Set this bit to "1" in I2C mode (refer to Table 1.14.12) R W AA A AA A AA A AA A AA A AA A AA A AA A Figure 1.14.28. UART2 special mode register 2 119 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode select bit 2. Table 1.14.11 shows the types of control to be changed by I2C mode select bit 2 when the I2C mode select bit is set to "1". Table 1.14.12 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I2C mode. Table 1.14.11. Functions changed by I2C mode select bit 2 IICM2 = 0 IICM2 = 1 1 Factor of interrupt number 15 No acknowledgment detection (NACK) UART2 transmission (the rising edge of the final bit of the clock) 2 Factor of interrupt number 16 Acknowledgment detection (ACK) UART2 reception (the falling edge of the final bit of the clock) Function 3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK) is assigned to the DMA request factor selection bits UART2 reception (the falling edge of the final bit of the clock) 4 Timing for transferring data from the UART2 reception shift register to the reception buffer. The rising edge of the final bit of the reception clock The falling edge of the final bit of the reception clock 5 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The falling edge of the final bit of the reception clock Table 1.14.12. Timing characteristics of detecting the start condition and the stop condition (Note 1) 3 to 6 cycles < duration for setting-up (Note2) 3 to 6 cycles < duration for holding (Note2) Note 1 : When the start/stop condition control bit SHTC is "1" . Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up SCL SDA (Start condition) SDA (Stop condition) 120 Duration for holding Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 P70 through P72 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 Digital delay (Divider) To DMA0, DMA1 UART2 SDDS=0 or DL=000 Transmission register SDDS=1 and DL 000 IICM=0 or IICM2=1 UART2 transmission/ NACK interrupt request IICM=1 and IICM2=0 SDHI ALS D Q Arbitration T Noize Filter Timer To DMA0 IICM=1 IICM=0 or IICM2=1 Reception register IICM=0 UART2 reception/ACK interrupt request, DMA1 request UART2 IICM=1 and IICM2=0 Start condition detection S Q R Stop condition detection Bus busy NACK D L-synchronous output enabling bit Falling edge detection Q T D P71/RxD2/SCL I/O R Q Selector (Port P71 output data latch) Internal clock UART2 IICM=1 SWC2 IICM=1 Noize Filter External clock Noize Filter Q T ACK Data bus 9th pulse IICM=1 Bus collision CLK control detection Bus collision/start, stop condition detection interrupt request IICM=0 UART2 Falling edge of 9 bit IICM=0 SWC Port reading UART2 * With IICM set to 1, the port terminal is to be readable IICM=0 P72/CLK2 Selector even if 1 is assigned to P71 of the direction register. I/O Timer Note: P72/CLK2 is not connected to the outside. Figure 1.14.29. Functional block diagram for I2C mode Functions available in I2C mode are shown in Figure 1.14.29 -- a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the instant when the arbitration lost detecting flag is set to "1". Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to "0" frees the output fixed to "L". 121 Mitsubishi microcomputers M16C / 62N Group (80-pin) UART2 Special Mode Register 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn't change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn't change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting flag is turned on. 122 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/O3, 4 S I/O3, 4 S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. Figure 1.14.30 shows the S I/O3, 4 block diagram, and Figure 1.14.31 shows the S I/O3, 4 related register. Table 1.14.13 shows the specifications of S I/O3, 4. f1 Data bus SMi1 SMi0 f8 f32 Synchronous circuit SMi3 SMi6 1/2 1/(ni+1) Bit rate generator (8) SMi6 P90/CLK3 (P95/CLK4) S I/O counter i (3) S I/Oi interrupt request SMi2 SMi3 P92/SOUT3 (P96/SOUT4) SMi5 LSB P91/SIN3 (P97/SIN4) MSB S I/Oi transmission/reception register (8) 8 Note 1: i = 3, 4. ni = A value set in the S I/Oi bit rate generator (036316, 036716). Note 2: P91/SIN3 is not connected to outside. Figure 1.14.30. S I/O3, 4 block diagram 123 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/O3, 4 S I/Oi control register (i = 3, 4) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SiC Bit symbol Address 036216, 036616 When reset 4016 Description Bit name R W Internal synchronous clock select bit b1 b0 SMi2 SOUTi output disable bit 0 : SOUTi output 1 : SOUTi output disable(high impedance) SMi3 S I/Oi port select bit (Note 2) 0 : Input-output port 1 : SOUTi output, CLK function SMi0 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Must not be set. SMi1 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0". SMi5 Transfer direction select bit 0 : LSB first 1 : MSB first SMi6 Synchronous clock select bit (Note 2) 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to "0", be sure to set the sync clock select bit to "1". SMi7 SOUTi initial value set bit SI/Oi bit rate generator (Note 1, 2) b7 b0 Symbol S3BRG S4BRG Address 036316 036716 When reset Indeterminate Indeterminate Indeterminate Values that can be set Assuming that set value = n, BRGi divides the count source by n + 1 R W 0016 to FF16 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. SI/Oi transmit/receive register (Note 1, 2) b7 b0 Symbol S3TRR S4TRR Address 036016 036416 When reset Indeterminate Indeterminate Indeterminate Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. Note 1: SI/O3 is exclusive to transmission. Note 2: Write a value to this register while transmit/receive halts. Figure 1.14.31. S I/O3, 4 related register 124 R W Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/O3, 4 Table 1.14.13. Specifications of S I/O3, 4 Item Transfer data format Transfer clock Conditions for transmission/ reception start Interrupt request generation timing Select function Precaution Specifications * Transfer data length: 8 bits * With the internal clock selected (bit 6 of 036216, 036616 = "1"): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) * With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2) * To start transmit/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616) -Write transfer data to SI/Oi transmit/receive register (036016, 036416) * To use S I/Oi interrupts, the following requirements must be met: - Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi transmit/receive register (bit 3 of 004916, 004816) = 0. * Rising edge of the last transfer clock. (Note 3) * LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. * Function for setting an SOUTi initial value selection When using an external clock for the transfer clock, the user can choose the SOUTi pin output level during a non-transfer time. For details on how to set, see Figure 1.14.33. * Unlike UART0-2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer. Therefore, do not write the next transfer data to the SI/Oi transmit/receive register (addresses 036016, 036416) during a transfer. * When the internal clock is selected for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a highimpedance state. However, if the transfer data is written to the SI/Oi transmit/ receive register (addresses 036016, 036416) during this time, SOUTi is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced. Note 1: n is a value from 0016 through FF16 set in the S I/Oi bit rate generator (i = 3, 4). Note 2: With the external clock selected: * Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the CLKi pin input must be in the high state. Also, before rewriting the SI/Oi control register (addresses 036216, 036616)'s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held high. * The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the "H" state. Note 4: SI/O3 is provided with no connection to the external pin, so is used exclusively for transmission. 125 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/O3, 4 Functions for setting an SOUTi initial value When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer time can be set to the high or the low state. Figure 1.14.32 shows the timing chart for setting an SOUTi initial value and how to set it. (Example) With "H" selected for SOUTi: S I/Oi port select bit SMi3 = 0 Signal written to the S I/Oi transmit/receive register SOUTi initial value select bit SMi7 = 1 (SOUTi: Internal "H" level) SOUTi's initial value set bit (SMi7) S I/Oi port select bit SMi3 = 0 1 (Port select: Normal port SOUTi) S I/Oi port select bit (SMi3) D0 SOUTi terminal = "H" output D0 Signal written to the S I/Oi register ="L" "H" "L" (Falling edge) SOUTi (internal) Port output SOUTi terminal output Initial value = "H" (Note) (i = 3, 4) Setting the SOUTi initial value to H Port selection (normal port SOUTi terminal = Outputting stored data in the S I/Oi transmission/ reception register SOUTi) Note: The set value is output only when the external clock has been selected. When initializing SOUTi, make sure the CLKi pin input is held "H" level. If the internal clock has been selected or if SOUT output disable has been set, this output goes to the high-impedance state. Figure 1.14.32. Timing chart for setting SOUTi's initial value and how to set it S I/Oi operation timing Figure 1.14.33 shows the S I/Oi operation timing 1.5 cycle (max) SI/Oi internal clock "H" "L" Transfer clock (Note 1) "H" "L" Signal written to the S I/Oi transmit/receive register "H" "L" S I/Oi output SOUTi "H" "L" (i= 3, 4) S I/Oi input SINi (i= 3, 4) SI/Oi interrupt request (i= 3, 4) bit Note2 Hiz D0 D1 D2 D3 D4 D5 D6 D7 Hiz "H" "L" "1" "0" Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register. (i=3,4) (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi pin becomes to the high-impedance state after the transfer finishes. Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit ="1". Figure 1.14.33. S I/Oi operation timing chart 126 Mitsubishi microcomputers M16C / 62N Group (80-pin) A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, P96 and P00 to P07 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.15.1 shows the performance of the A-D converter. Figure 1.15.1 shows the block diagram of the A-D converter, and Figures 1.15.2 and 1.15.3 show the A-D converter-related registers. Table 1.15.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock AD (Note 2) VCC =3.3V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 3.3V * Without sample and hold function 5LSB * With sample and hold function (8-bit resolution) 2LSB * With sample and hold function (10-bit resolution) AN0 to AN7 input : 5LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected) : 7LSB AN00 to AN07 input : 7LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) + 8pins (AN00 to AN07) A-D conversion start condition * Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" * External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the ___________ ADTRG/P97 input changes from "H" to "L" Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide the fAD if f(XIN) exceeds 10MHZ, and make AD frequency equal to or less than 10MHz. And divide the fAD if VCC is less than 3.0V, and make AD frequency equal to or lower than fAD/2. Without sample and hold function, set the AD frequency to 250kHZ min. With the sample and hold function, set the AD frequency to 1MHZ min. 127 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter A-D conversion rate selection AD CKS1 = 1 fAD 1/2 VREF CKS1 = 0 Resistor ladder VCUT = 0 AVSS CKS0 = 1 CKS0 = 0 1/2 VCUT = 1 Successive conversion register A-D control register 1 (address 03D716) A-D control register 0 (address 03D616) Addresses (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) A-D register 0 (16) A-D register 1 (16) A-D register 2 (16) A-D register 3 (16) A-D register 4 (16) A-D register 5 (16) A-D register 6 (16) A-D register 7 (16) Decoder for A-D register Data bus high-order Data bus low-order A-D control register 2 (address 03D416) PM00 PM01 Vref Decoder for channel selection Comparator VIN CH2,CH1,CH0 = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 Port P10 group Port P0 group P00/AN00 P01/AN01 P02/AN02 P03/AN03 P04/AN04 P05/AN05 P06/AN06 P07/AN07 PM01,PM00,CH2,CH1,CH0 = 00000 = 00001 = 00010 = 00011 = 00100 = 00101 = 00110 = 00111 P100/AN0 P101/AN1 P102/AN2 P103/AN3 P104/AN4 P105/AN5 P106/AN6 P107/AN7 ADGSEL1,ADGSEL0 = 00 OPA1,OPA0 = 00 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 10 OPA1,OPA0 = 00 ADGSEL1,ADGSEL0 = 00 OPA1,OPA0 = 11 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 10 OPA1,OPA0 = 11 ANEX0 ANEX1 OPA0 = 1 OPA1,OPA0 = 01 OPA1 = 1 OPA1 = 1 Figure 1.15.1. Block diagram of A-D converter 128 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol Address 03D616 When reset 00000XXX2 Bit name AAA AA A AA A AA A AA A AA A AA A AA A AAA Function RW b2 b1 b0 CH0 Analog input pin select bit CH1 CH2 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected MD0 MD1 TRG (Note 2) (Note 3) (Note 3) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol Address 03D716 When reset 0016 Bit name A-D sweep pin select bit SCAN0 RW Function When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) When repeat sweep mode 1 is selected SCAN1 b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) (Note 2) MD2 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 0 : Vref not connected 1 : Vref connected External op-amp connection mode bit b7 b6 VCUT OPA0 AAA AAA AA A AA A AA A AA A AA A AAAA AA OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Figure 1.15.2. A-D converter-related registers (1) 129 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter A-D control register 2 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address When reset ADCON2 03D416 0000XXX02 Bit symbol SMP Bit name A-D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold b2 b1 ADGSEL0 Analog input group select bit ADGSEL1 0 0 1 1 0 1 0 1 : : : : Port10 group is selected Must not be set. Port0 group is selected (Note 2) Must not be set. Must always be set to "0" Reserved bit A A A A A A AA AA RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: In selecting port P0 group, P104 to P107 can not be used as a key-input interrupt function input pin. Symbol A-D register i (b15) b7 ADi(i=0 to 7) (b8) b0 b7 Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Figure 1.15.3. A-D converter-related registers (2) 130 A A R W Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.15.2 shows the specifications of one-shot mode. Figure 1.15.4 shows the A-D control register in one-shot mode. Table 1.15.2. One-shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing "1" to A-D conversion start flag Stop condition * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin One of AN0 to AN7, as selected (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name Analog input pin select bit CH1 CH2 MD0 MD1 TRG When reset 00000XXX2 A-D operation mode select bit 0 Trigger select bit Function 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) (Note 3) b4 b3 0 0 : One-shot mode (Note 3) 0 : Software trigger 1 : ADTRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 AAA AAA AA A AA A AAA AA A AAA RW b2 b1 b0 0: fAD/4 is selected 1: fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Bit symbol Address 03D716 When reset 0016 Bit name Function A-D sweep pin select bit Invalid in one-shot mode MD2 A-D operation mode select bit 1 Set to "0" when this mode is selected BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit SCAN0 SCAN1 OPA0 OPA1 External op-amp connection mode bit 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode AA A AA A AAA AA A AA A AA A AA A AAA RW Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.15.4. A-D conversion register in one-shot mode 131 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.15.3 shows the specifications of repeat mode. Figure 1.15.5 shows the A-D control register in repeat mode. Table 1.15.3. Repeat mode specifications Item Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated One of AN0 to AN7, as selected (Note) Read A-D register corresponding to selected pin (at any time) Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Analog input pin select bit CH1 CH2 Function 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 MD1 A-D operation mode select bit 0 TRG Trigger select bit ADST A-D conversion start flag 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 MD0 0 1 : Repeat mode AA A AAA AA A AAA AA A AAA AAA RW b2 b1 b0 (Note 2) (Note 3) (Note 3) 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Bit symbol Address 03D716 When reset 0016 Bit name Function A-D sweep pin select bit Invalid in repeat mode A-D operation mode select bit 1 Set to "0" when this mode is selected 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit 1 : Vref connected OPA0 External op-amp connection mode bit SCAN0 SCAN1 MD2 BITS OPA1 b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode AAA AA A AA A AA A AA A AAA AA A AA A AAA Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.15.5. A-D conversion register in repeat mode 132 RW Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.15.4 shows the specifications of single sweep mode. Figure 1.15.6 shows the A-D control register in single sweep mode. Table 1.15.4. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing "1" to A-D converter start flag Stop condition * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Analog input pin select bit AAA AAA AAA AAA AAA AAA AAA Function RW Invalid in single sweep mode CH1 CH2 MD0 A-D operation mode select bit 0 b4 b3 1 0 : Single sweep mode MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 When reset 0016 Bit name A-D sweep pin select bit Function b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 (Note 2) MD2 A-D operation mode select bit 1 Set to "0" when this mode is selected BITS 8/10-bit mode select bit CKS1 Frequency select bit 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit OPA0 External op-amp connection mode bit (Note 3) OPA1 AAA AA AA AA AAA AAA AAA AAA AA AA AA R W When single sweep and repeat sweep mode 0 are selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: Neither `01' nor `10' can be selected with the external op-amp connection mode bit. Figure 1.15.6. A-D conversion register in single sweep mode 133 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.15.5 shows the specifications of repeat sweep mode 0. Figure 1.15.7 shows the A-D control register in repeat sweep mode 0. Table 1.15.5. Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin select bit are used for repeat A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (Note) Read A-D register corresponding to selected pin (at any time) Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Analog input pin select bit AA A AAA AAA AAA AA A AAA AA A AAA Function RW Invalid in repeat sweep mode 0 CH1 CH2 MD0 A-D operation mode select bit 0 b4 b3 1 1 : Repeat sweep mode 0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 When reset 0016 Bit name A-D sweep pin select bit Function b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 (Note 2) A-D operation mode select bit 1 Set to "0" when this mode is selected 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit 1 : Vref connected OPA0 External op-amp connection mode bit (Note 3) b7 b6 MD2 BITS CKS1 OPA1 AA A AAA AA A AA A AA A AA A AAA AAA RW When single sweep and repeat sweep mode 0 are selected 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: Neither "01" nor "10" can be selected with the external op-amp connection mode bit. Figure 1.15.7. A-D conversion register in repeat sweep mode 0 134 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.15.6 shows the specifications of repeat sweep mode 1. Figure 1.15.8 shows the A-D control register in repeat sweep mode 1. Table 1.15.6. Repeat sweep mode 1 specifications Item Specification All pins perform repeat A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated With emphasis on these pins ; AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note) Read A-D register corresponding to selected pin (at any time) Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Analog input pin select bit AA AA AA AAA AA AAAA AA AAAA AA A AAA Function RW Invalid in repeat sweep mode 1 CH1 CH2 MD0 A-D operation mode select bit 0 b4 b3 1 1 : Repeat sweep mode 1 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 1 b1 b0 Symbol ADCON1 Address 03D716 Bit symbol Bit name SCAN0 A-D sweep pin select bit When reset 0016 Function b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) SCAN1 MD2 A-D operation mode select bit 1 Set to "1" when this mode is selected BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit 1 : Vref connected OPA0 External op-amp connection mode bit (Note 3) b7 b6 OPA1 AAA AAA AA A AAA AA A AA AA AA AA A AAA R W When repeat sweep mode 1 is selected (Note 2) 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: Neither `01' nor `10' can be selected with the external op-amp connection mode bit. Figure 1.15.8. A-D conversion register in repeat sweep mode 1 135 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "0", input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is "0" and bit 7 is "1", input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. Furthermore, the input via 8 pins of the extended analog input pins AN00 to AN07 can be converted from analog to digital. These pins can be used the same as AN0 to AN7. Use the A-D control register 2 (address 03D416) bit 1 and bit 2 to select the pin group AN0 to AN7, AN00 to AN07. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "1", input via AN0 to AN7 (Note) is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.15.9 is an example of how to connect the pins in external operation amp mode. Note : AN00 to AN07 can be used the same as AN0 to AN7. ADGSEL1,ADGSEL0 = 0,0 Port P10 group Analog input pins AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Resistor ladder Successive conversion register ADGSEL1,ADGSEL0 = 1,0 Port P0 group Analog input pins AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 ANEX0 ANEX1 External op-amp Figure 1.15.9. Example of external op-amp connection mode 136 Comparator Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A Converter D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. When the D-A output is enabled, the pullup function of the corresponding port is automatically disabled. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 1.16.1 lists the performance of the D-A converter. Figure 1.16.1 shows the block diagram of the D-A converter. Figure 1.16.2 shows the D-A control register. Figure J1.16.3 shows the D-A converter equivalent circuit. Table 1.16.1. Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 2 channels Data bus low-order bits D-A register0 (8) (Address 03D816) D-A0 output enable bit R-2R resistor ladder D-A register1 (8) AAA P93/DA0 (Address 03DA16) D-A1 output enable bit R-2R resistor ladder AAA P94/DA1 Figure 1.16.1. Block diagram of D-A converter 137 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A Converter D-A control register b7 b6 b5 b4 b3 b2 b1 Symbol DACON b0 Address 03DC16 Bit symbol When reset 0016 Bit name AA A AA A Function DA0E D-A0 output enable bit 0 : Output disabled 1 : Output enabled DA1E D-A1 output enable bit 0 : Output disabled 1 : Output enabled RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". D-A register b7 Symbol DAi (i = 0,1) b0 Address 03D816, 03DA16 When reset Indeterminate AA A AA A Function RW R W Output value of D-A conversion Figure 1.16.2. D-A control register D-A0 output enable bit "0" R R R R 2R 2R 2R 2R R R R 2R DA0 "1" 2R MSB D-A register 0 "0" 2R 2R 2R LSB "1" AVSS VREF Note 1: The above diagram shows an instance in which the D-A register is assigned "2A16". Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to "0016" so that no current flows in the resistors Rs and 2Rs. Figure 1.16.3. D-A converter equivalent circuit 138 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.17.1 shows the block diagram of the CRC circuit. Figure 1.17.2 shows the CRC-related registers. Figure 1.17.3 shows the calculation example using the CRC calculation circuit Data bus high-order bits Data bus low-order bits AAAAAA AAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAA AAAAAA Eight low-order bits Eight high-order bits CRC data register (16) (Addresses 03BD16, 03BC16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) (Address 03BE16) Figure 1.17.1. Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16, 03BC16 When reset Indeterminate Values that can be set Function CRC calculation result output register 000016 to FFFF16 A RW CRC input register b7 Symbo CRCIN b0 Function Data input register Address 03BE16 When reset Indeterminate Values that can be set 0016 to FF16 A RW Figure 1.17.2. CRC-related registers 139 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC b15 b0 CRC data register CRCD [03BD16, 03BC16] (1) Setting 000016 b7 b0 CRC input register (2) Setting 0116 CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 CRC data register 118916 CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB MSB Modulo-2 operation is operation that complies with the law given below. 1000 1000 1 0001 0000 0010 0001 9 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 0000 1 1000 0000 1000 0000 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 0 1 1000 MSB 1 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 CRC input register (3) Setting 2316 CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [03BD16, 03BC16] Stores CRC code Figure 1.17.3. Calculation example using the CRC calculation circuit 140 Mitsubishi microcomputers M16C / 62N Group (80-pin) Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports The M16C/62N (80-pin version) group has 70 programmable input/output ports given below (except P85). * P00-P07 * P20-P27 * P30-P37 * P40-P43 * P50-P57 * P60-P67 * P70, P71, P76, P77 * P80-P84, P86, P87 (P85 is input port) * P90, P92-P97 * P100-P107 Note: P1, P44 to P47, P72 to P75, P91 are not connected to external pins. Figures 1.18.1 to 1.18.4 show the programmable I/O ports. Figure 1.18.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure 1.18.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P85. (2) Port registers Figure 1.18.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. (3) Pull-up control registers Figure 1.18.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. 141 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Pull-up selection Direction register P00 to P07 Inside dotted-line included P20 to P27, P30 to P37, P40 to P47, P50 to P54, P56 Inside dotted-line not included Data bus Port latch (Note 1) Analog input Pull-up selection Direction register P10 to P14 Port P1 control register Data bus Port latch (Note 1) Pull-up selection Direction register P15 to P17 Port P1 control register Data bus Port latch (Note 1) Input to respective peripheral functions Pull-up selection Direction register P57, P60, P61, P64, P65, P72 to P76, P80, P81, P90, P92 "1" Output Data bus Port latch (Note 1) Input to respective peripheral functions Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: P1, P44 to P47, P72 to P75, P91 are not connected to external pins, but are present within the microcomputer. Figure 1.18.1. Programmable I/O ports (1) 142 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Pull-up selection P82 to P84 Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Pull-up selection Direction register P55, P62, P66, P77, P91, P97 Data bus Port latch (Note 1) Input to respective peripheral functions Pull-up selection Direction register P63, P67 "1" Data bus Port latch Output (Note 1) P85 Data bus NMI interrupt input (Note 1) Direction register P70, P71 "1" Data bus Port latch Output (Note 2) Input to respective peripheral functions Note 1: Note 2: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. symbolizes a parasitic diode. Note 3: P1, P44 to P47, P72 to P75, P91 are not connected to external pins, but are present within the microcomputer. Figure 1.18.2. Programmable I/O ports (2) 143 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Pull-up selection P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included) Direction register Data bus Port latch (Note 1) Analog input Input to respective peripheral functions Pull-up selection D-A output enabled Direction register P93, P94 Data bus Port latch (Note 1) Input to respective peripheral functions Analog output D-A output enabled Pull-up selection Direction register P96 "1" Data bus Port latch Output (Note 1) Analog input Pull-up selection Direction register P95 "1" Data bus Port latch Output (Note 1) Input to respective peripheral functions Analog input Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: P1, P44 to P47, P72 to P75, P91 are not connected to external pins, but are present within the microcomputer. Figure 1.18.3. Programmable I/O ports (3) 144 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Pull-up selection Direction register P87 Data bus Port latch (Note 1) fc Input to respective peripheral functions Rf Pull-up selection Rd Direction register P86 "1" Data bus Port latch Output (Note 1) Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: P1, P44 to P47, P72 to P75, P91 are not connected to external pins, but are present within the microcomputer. Figure 1.18.4. Programmable I/O ports (4) (Note2) BYTE BYTE signal input (Note1) (Note2) CNVSS CNVSS signal input (Note1) RESET RESET signal input (Note1) Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. Note 2: A parasitic diode on the VCC side is added to the mask ROM version. Do not apply a voltage higher than Vcc to each pin. Note 3: The BYTE and CNVss pins are connected on the inside. Figure 1.18.5. I/O pins 145 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Port Pi direction register (Note 1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Bit symbol Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 Bit name PDi_0 Port Pi0 direction register PDi_1 Port Pi1 direction register PDi_2 Port Pi2 direction register PDi_3 PDi_4 Port Pi3 direction register Port Pi4 direction register PDi_5 Port Pi5 direction register PDi_6 Port Pi6 direction register PDi_7 Port Pi7 direction register Function When reset 0016 0016 AA A AA A AA A AA A AA A RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to the port P9 direction register. Note 2: P1, P44 to P47, P72 to P75, P91 are not connected to the outside, but are present within the microcomputer, so set the direction registers to output so that these pin are reserved for future use. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Bit symbol PD8_0 Address 03F216 Bit name Port P80 direction register PD8_1 Port P81 direction register PD8_2 Port P82 direction register PD8_3 Port P83 direction register When reset 00X000002 Function AA A AA A AA A AA A AA A AA A 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. PD8_6 Port P86 direction register PD8_7 Port P87 direction register Figure 1.18.6. Direction register 146 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) RW Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Port Pi register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Bit symbol Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 Bit name Pi_0 Port Pi0 register Pi_1 Pi_2 Port Pi1 register Port Pi2 register Pi_3 Port Pi3 register Pi_4 Port Pi4 register Pi_5 Port Pi5 register Pi_6 Port Pi6 register Pi_7 Port Pi7 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (Note1) (i = 0 to 10 except 8) When reset Indeterminate Indeterminate AA AA A AA A A AA A AA A A RW Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: P1, P44 to P47, P72 to P75, P91 are not connected to external pins, but are present within the microcomputer, so set the unused pin processing. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol Address 03F016 Bit name P8_0 Port P80 register P8_1 Port P81 register P8_2 Port P82 register P8_3 Port P83 register P8_4 Port P84 register P8_5 Port P85 register P8_6 Port P86 register P8_7 Port P87 register When reset Indeterminate Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : "L" level data 1 : "H" level data AA A A A AA A AA A A A A AA R W Figure 1.18.7. Port register 147 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Pull-up control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Address 03FC16 Bit symbol Bit name PU00 P00 to P03 pull-up PU01 P04 to P07 pull-up PU02 P10 to P13 pull-up PU03 P14 to P17 pull-up PU04 P20 to P23 pull-up PU05 P24 to P27 pull-up PU06 P30 to P33 pull-up PU07 P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high A A A A A A RW Note: P1 is not connected to external pins, but are present within the microcomputer, so set the unused pin processing. Pull-up control register 1 (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Address 03FD16 Bit symbol Bit name PU10 P40 to P43 pull-up PU11 P44 to P47 pull-up PU12 PU13 P50 to P53 pull-up P54 to P57 pull-up PU14 P60 to P63 pull-up PU15 P64 to P67 pull-up PU16 P72 to P73 pull-up (Note 1) PU17 P74 to P77 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high A A A A A R W Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: P44 to P47, P72 to P75 are not connected to external pins, but are present within the microcomputer, so set the unused pin processing. Pull-up control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Address 03FE16 Bit symbol Bit name PU20 P80 to P83 pull-up PU21 P84 to P87 pull-up (Except P85) PU22 P90 to P93 pull-up PU23 PU24 P94 to P97 pull-up P100 to P103 pull-up PU25 P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". A A A A A RW Note: P91 is not connected to external pins, but are present within the microcomputer, so set the unused pin processing. Figure 1.18.8. Pull-up control register 148 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port Table 1.18.1. Example connection of unused pins in single-chip mode Pin name Connection Ports P0 to P10 (excluding P85) (Note 1) After setting for input mode, connect every pin to VSS via a resistor; or after setting for output mode, leave these pins open. XOUT (Note 2) Open NMI Connect via resistor to VCC (pull-up) AVCC Connect to VCC AVSS, VREF, BYTE Connect to VSS Note 1: P1, P44 to P47, P72 to P75, P91 are not connected to external pins, but are present within the microcomputer, so set the unused pin processing. Note 2: With external clock input to XIN pin. Microcomputer Port P0 to P10 (except for P85) (Input mode) * * * (Input mode) (Output mode) ** * Open NMI XOUT Open VCC AVCC CNVSS (BYTE) AVSS VREF VSS Note: P1, P44 to P47, P72 to P75, P91 are not connected to external pins. Figure 1.18.9. Example connection of unused pins 149 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Electrical characteristics Table 1.20.1. Absolute maximum ratings Parameter Symbol Vcc AVcc VI VO Pd Topr Tstg Supply voltage Analog supply voltage RESET, CNVSS (BYTE) Input P00 to P07, P20 to P27, voltage P30 to P37, P40 to P43, P50 to P57, P60 to P67, P76 to P77, P80 to P87, P90, P92 to P97, P100 to P107, VREF, XIN P70, P71 Output P00 to P07, P20 to P27, voltage P30 to P37,P40 to P43, P50 to P57, P60 to P67,P76 to P77, P80 to P84, P86, P87, P90, P92 to P97, P100 to P107, XOUT P70, P71 Power dissipation Operating ambient temperature Storage temperature Note: Specify a product of -40 to 85C to use it. 150 Condition Rated value VCC=AVCC VCC=AVCC -0.3 to 4.2 Unit V -0.3 to 4.2 V -0.3 to Vcc+0.3 V -0.3 to 4.2 V -0.3 to Vcc+0.3 V Topr=25 C -0.3 to 4.2 V 300 -20 to 85 / -40 to 85 (Note) -65 to 150 mW C C Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Table 1.20.2. Recommended operating conditions (referenced to VCC = 2.4V (Mask ROM version is 2.2V) to 3.6V at Topr = -20C to 85oC / - 40C to 85oC(Note 3) unless otherwise specified) Symbol Standard Typ. 2.4(Note 4) 3.3 Vcc 0 Parameter Min. Vcc AVcc Vss Supply voltage Analog supply voltage Supply voltage AVss Analog supply voltage P00 to P07, P20 to P27, HIGH input P30 to P37, P40 to P43, P50 to P57, P60 to P67, voltage P76, P77, P80 to P87,P90, P92 to P97, P100 to P107, XIN, RESET, CNVSS (BYTE) VIH P70 , P71 LOW input voltage P00 to P07, P20 to P27, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70, P71,P76, P77, P80 to P87, P90, P92 to P97, P100 to P107, XIN, RESET, CNVSS (BYTE) P00 to P07, P20 to P27,P30 to P37, HIGH peak output current P40 to P43, P50 to P57, P60 to P67, P76, P77, P80 to P84, P86, P87, P90, P92 to P97, P100 to P107 HIGH average output P00 to P07, P20 to P27, P30 to P37, current P40 to P43, P50 to P57, P60 to P67, P76, P77, P80 to P84, P86, P87, P90, P92 to P97, P100 to P107 P00 to P07, P20 to P27,P30 to P37, LOW peak output current P40 to P43, P50 to P57, P60 to P67, P70, P71, P76, P77 P80 to P84, P86, P87, P90, P92 to P97, P100 to P107 P00 to P07, P20 to P27,P30 to P37, LOW average output current P40 to P43, P50 to P57, P60 to P67, P70, P71, P76, P77 P80 to P84, P86, P87, P90, P92 to P97, P100 to P107 VIL I OH (peak) I OH (avg) I OL (peak) I OL (avg) No wait Main clock input oscillation frequency (Note 5, Note 6) f (XIN) V 0.8Vcc Vcc V 0.8Vcc 4.2 V 0 0.2Vcc V -10.0 mA -5.0 mA 10.0 mA 5.0 mA 0 Vcc=2.4V to 3.0V 0 Mask ROM version Vcc=2.2V to 2.4V 0 Mask ROM version with wait Flash memory version V V V 0 Mask ROM version Flash memory version Mask ROM version f (XCIN) Vcc=3.0V to 3.6V Unit Max. 3.6 Vcc=3.0V to 3.6V 0 Vcc=2.4V to 3.0V 0 Vcc=2.2V to 2.4V 0 16 15 X Vcc - 29 17.5 X Vcc - 35 16 11.25 X Vcc - 17.75 11.25 X Vcc - 17.75 Subclock oscillation frequency 32.768 50 MHz MHz MHz MHz MHz MHz kHz Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for all ports must be 80mA max. The total IOH (peak) for all ports must be 80mA max. Note 3: Specify a product of -40C to 85C to use it. Note 4: 2.2V is minimum supply voltage of mask ROM version. Note 5: Relationship between main clock oscillation frequency and supply voltage. Main clock input oscillation frequency (No wait) AA Main clock input oscillation frequency (With wait) A Mask ROM and flash memory versions 16.0 AAAAA AAAAAAAA AAAAA AAA AAAAA AAA AAAAA AAA AAAAA AAA AAAAAAAA AAAAA 15 X VCC -29MHZ 17.5 X VCC-35MHZ 7.0 3.5 0.0 2.2 2.4 3.0 Supply voltage[V] (BCLK: no division) 3.6 Operating maximum frequency [MHZ] Operating maximum frequency [MHZ] Mask ROM version Mask ROM version Mask ROM and flash memory versions AAAAA AAA AAAAAAAA AAAAA AAA AAAAA AAA AAAAA AAA AAAAA AAA AAAAAAAA AAAAA 11.25 X VCC -17.75MHZ 16.0 9.25 7.0 0.0 2.2 2.4 3.0 Flash memory version program/erase voltage and read operation voltage characteristics Flash program/erase voltage Flash read operation voltage VCC=3.0V to 3.6V VCC=2.4V to 3.6V 3.6 Supply voltage[V] (BCLK: no division) Note 5: Execute case without wait, program / erase of flash memory by VCC=3.0V to 3.6V and f(BCLK) 6.25 MHz. Execute case with wait, program / erase of flash memory by VCC=3.0V to 3.6V and f(BCLK) 10.0 MHz. 151 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Table 1.20.3. Electrical characteristics (referenced to VCC = 3.0V to 3.6V, VSS = 0V at Topr = - 20oC to 85oC / - 40oC to 85oC (Note 1), f(XIN) = 16MHZ unless otherwise specified) Standard Symbol VOH VOH Parameter HIGH output XOUT voltage HIGH output XCOUT voltage VOL Measuring condition P00 to P07, P20 to P27, P30 to P37, HIGH output P40 to P43, P50 to P57, P60 to P67, voltage P76, P77, P80 to P84, P86, P87, P90, P92 to P97, P100 to P107 Min. IOH=-1mA, VCC=3.3V 2 .8 HIGHPOWER IOH=-0.1mA, VCC=3.3V 2 .8 LOWPOWER IOH=-50A, VCC=3.3V 2 .8 HIGHPOWER LOWPOWER P00 to P07, P20 to P27, P30 to P37, LOW output P40 to P43, P50 to P57, P60 to P67, P70, P71, P76, P77, P80 to P84, P86, voltage P87, P90, P92 to P97, P100 to P107 Typ. V 2.8 1.6 With no load applied, VCC=3.3V With no load applied, VCC=3.3V 0 .5 0 .5 HIGHPOWER IOL=0.1mA, VCC=3.3V LOWPOWER IOL=50A, VCC=3.3V LOW output XCOUT voltage HIGHPOWER With no load applied, VCC=3.3V 0 LOWPOWER With no load applied, VCC=3.3V 0 TA0IN, TA3IN, TA4IN, TB0IN, TB2IN to TB5IN, INT0 to INT2, ADTRG,CTS0,CTS1 CLK0,CLK1,CLK3, VCC=3.3V CLK4, TA3OUT, TA4OUT, NMI, KI0 to KI3, SIN4, RXD0 to RXD2 Hysteresis VT+-VT- Hysteresis RESET VCC=3.3V HIGH input current P00 to P07, P20 to P27, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70, P71, P76, P77, P80 to P87, P90, P92 to P97, P100 to P107, XIN, RESET, CNVss (BYTE) I IL Pull-up RPULLUP resistance IIH LOW input current V IOL=1mA, VCC=3.3V VT+-VT- Unit V LOW output XOUT voltage VOL Max. 0 .5 V V V 0 .2 0 .8 V 0 .2 1 .8 V VI=3V, VCC=3.3V 4.0 A P00 to P07, P20 to P27, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70, P71, P76, P77, P80 to P87, P90, P92 to P97, P100 to P107, XIN, RESET, CNVss (BYTE) VI=0V, VCC=3.3V -4.0 A P00 to P07, P20 to P27, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P76, P77, P80 to P84, P86,P87, P90, P92 to P97, P100 to P107 VI=0V, VCC=3.3V 20.0 100.0 500.0 k RfXIN Feedback resistance XIN 3 .0 M RfCXIN Feedback resistance XCIN 10.0 M VRAM RAM retention voltage When clock is stopped The output pins Mask ROM are open and version other pins are Flash memory VSS version Icc f(XIN)=16MHz Square wave, no division f(XIN)=16MHz Square wave, no division Mask ROM version f(XCIN)=32kHz, VCC=3.3V Flash memory version f(XCIN)=32kHz, VCC=3.3V Flash memory version f(XCIN)=32kHz, VCC=3.3V Flash memory version, program f(XIN)=16MHz , VCC=3.3V Flash memory version, erase f(XIN)=16MHz , VCC=3.3V V 2.0 12.5 20.0 25.0 mA 32.0 mA 40.0 A 45 A 225 A 19.0 mA 21.0 mA 5.8 A 2 .7 A 7 .0 A 3 .0 A Square wave Square wave, in RAM (Note 3) Square wave, in flash memory Division by 2 Division by 2 f(XCIN)=32kHz, VCC=3.3V Power supply current Mask ROM version When a WAITinstruction is executed. Oscillation capacity High (Note2) f(XCIN)=32kHz, VCC=3.3V When a WAIT instruction is executed. Oscillation capacity Low (Note2) f(XCIN)=32kHz, VCC=3.3V Flash memory version When a WAITinstruction is executed. Oscillation capacity High (Note2) f(XCIN)=32kHz, VCC=3.3V When a WAIT instruction is executed. Oscillation capacity Low (Note2) Mask ROM version Topr=25C, VCC=3.3V when clock is stopped 0 .1 2.0 Flash memory version Topr=85C, VCC=3.3V when clock is stopped 0 .4 100 Note 1: Specify a product of -40C to 85C to use it. Note 2: With one timer operated using fC32. Note 3: Refer to the shifting to the low power dissipation mode flowchart (Figure 1.29.2b). 152 A Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Table 1.20.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V, at Topr = - 20oC to 85oC / - 40oC to 85oC (Note 4), f(XIN) =16MHZ unless otherwise specified) Symbol RLADDER tCONV tCONV tSAMP VREF VIA Paramete Standard Min. Typ. Max. Measuring condition 10 Resolution VREF = VCC Absolute accuracy Sample & hold function not available VREF = VCC = 3.3V Sample & hold function available(10bit) AN0 to AN7 input VREF=VCC ANEX0, ANEX1 input, = 3.3V AN00 to AN07 input Sample & hold function available(8bit) VREF = VCC = 3.3V Ladder resistance Conversion time(10bit) Conversion time(8bit) Sampling time Reference voltage Analog input voltage 2 2 VREF = VCC Unit 5 5 Bits LSB LSB 7 LSB 2 40 LSB k s 10 3.3 2.8 0.3 2.4 VCC s s V 0 VREF V Note 1: Do f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating conditions of table 1.20.2. Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (OAD) equal to or lower than 10MHz. And divide the fAD if VCC is less than 3.0V, and make AD operation clock frequency (OAD) equal to or lower than fAD/2. Note 2: A case without sample & hold function turn AD operation clock frequency (OAD) into 250 kHz or more in addition to a limit of Note 1. A case with sample & hold function turn AD operation clock frequency (OAD) into 1MHz or more in addition to a limit of Note 1. Note 3: Connect AVCC pin to VCC pin and apply the same electric potential. Note 4: Specify a product of -40C to 85C to use it. Table 1.20.5. D-A conversion characteristics (referenced to VCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V, at Topr = - 20oC to 85oC / - 40oC to 85oC (Note 2), f(XIN) =16MHZ unless otherwise specified) Symbol - - Parameter Standard Min. Typ. Max Measuring condition tsu Resolution Absolute accuracy, VREF = VCC = 3.3V Setup time RO IVREF Output resistance Reference power supply input current 4 15 (Note1) Unit 8 1.0 Bits % 3 25 s k 1.0 mA Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. Also, when D-A register contents are not "0016", the current IVREF always flows even though Vref may have been set to be unconnected by the A-D control register. Note 2: Specify a product of -40C to 85C to use it. Table 1.20.6. Flash memory version electrical characteristics (referenced to VCC = 3.0V to 3.6V, at Topr = 0oC to 60oC unless otherwise specified) Parameter Min. Word program time Standard Typ. Max Unit s 15 150 4K block erase time 0.3 8 s 64K block erase time 0.5 8 s 0.5 X n 8Xn Erase all unlocked blocks time Lock bit program time 0.02 0.4 s ms Note : n denotes the number of block erases. Table 1.20.7. Flash memory version program/erase voltage and read operation voltage characteristics (at Topr = 0oC to 60oC) Flash program/erase voltage Flash read operation voltage VCC=3.0V to 3.6V VCC=2.4V to 3.6V 153 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = - 20oC to 85oC / - 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40C to 85C to use it. Table 1.20.8. External clock input Symbol tc tw(H) tw(L) tr tf 154 Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. Unit 62.5 ns 25 25 ns ns ns ns 15 15 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = - 20oC to 85oC / - 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40C to 85C to use it. Table 1.20.9. Timer A input (counter input in event counter mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.20.10. Timer A input (gating input in timer mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Max. Min. 400 200 200 Unit ns ns ns Table 1.20.11. Timer A input (external trigger input in one-shot timer mode) Symbol Parameter Standard Max. Min. Unit tc(TA) TAiIN input cycle time 200 ns tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 ns ns Table 1.20.12. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Max. Min. 100 100 Unit ns ns Table 1.20.13. Timer A input (up/down input in event counter mode) tc(UP) TAiOUT input cycle time tw(UPH) tw(UPL) tsu(UP-TIN) TAiOUT input HIGH pulse width Standard Max. Min. 2000 1000 TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time 1000 400 400 Symbol th(TIN-UP) Parameter Unit ns ns ns ns ns 155 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = - 20oC to 85oC / - 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40C to 85C to use it. Table 1.20.14. Timer B input (counter input in event counter mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 100 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) ns tc(TB) TBiIN input cycle time (counted on both edges) 40 200 tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns ns Table 1.20.15. Timer B input (pulse period measurement mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) tw(TBL) TBiIN input HIGH pulse width TBiIN input LOW pulse width 200 200 ns ns Table 1.20.16. Timer B input (pulse width measurement mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 tw(TBH) TBiIN input HIGH pulse width 200 ns ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 1.20.17. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 1.20.18. Serial I/O Symbol Parameter Standard Min. Max. Unit tc(CK) CLKi input cycle time 300 ns tw(CKH) CLKi input HIGH pulse width 150 ns tw(CKL) CLKi input LOW pulse width 150 ns td(C-Q) TxDi output delay time th(C-Q) TxDi hold time tsu(D-C) RxDi input setup time RxDi input hold time th(C-D) 100 ns 0 50 ns 90 ns ns _______ Table 1.20.19. External interrupt INTi inputs Symbol Parameter tw(INH) INTi input HIGH pulse width tw(INL) INTi input LOW pulse width 156 Standard Min. 250 250 Max. Unit ns ns Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) tsu(UP-TIN) th(TIN-UP) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) th(C-D) RxDi tw(INL) INTi input tw(INH) Figure 1.20.1. Timing diagram 157 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description (Flash Memory Version) Outline Performance (Flash Memory Version) Table 1.28.1 shows the outline performance of the M16C/62N (flash memory version). Table 1.28.1. Outline performance of the M16C/62N (flash memory version) Item Performance Flash memory operation mode Three modes (parallel I/O, standard serial I/O, CPU rewrite) Erase block division User ROM area See Figure 1.28.1 Boot ROM area One division (4 Kbytes) (Note 1) Program method In units of word/byte (Note 2) Erase method Collective erase/block erase Program/erase control method Program/erase control by software command Protect method Protected for each block by lock bit Number of commands 8 commands Program/erase count 100 times Data Retention 10 years ROM code protect Parallel I/O and standard serial I/O modes are supported. Note 1: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. Note 2: Can be programmed in byte unit only when using parallel I/O mode. 158 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description (Flash Memory Version) Flash Memory The M16C/62N (flash memory version) contains the flash memory that can be rewritten with a single voltage. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 1.28.1, so that memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user's application system. This boot ROM area can be rewritten in only parallel I/O mode. 0C000016 Block 6 : 64K byte 0D000016 Block 5 : 64K byte 0E000016 Block 4 : 64K byte 0F000016 Flash memory size 256Kbytes 128Kbytes Flash memory start address 0F800016 Note 1: The boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use an even address in the block. Block 3 : 32K byte Block 2 :24K byte 0C000016 0E000016 0FE00016 Block 1 : 4K byte 0FF00016 0FFFFF16 Block 0 : 4K byte User ROM area 0FF00016 0FFFFF16 4K byte Boot ROM area Figure 1.28.1. Block diagram of flash memory version 159 Mitsubishi microcomputers M16C / 62N Group (80-pin) CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 1.28.1 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.28.1 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the CPU starts operating using the control program in the boot ROM area. This mode is called the "boot" mode. The control program in the boot ROM area can also be used to rewrite the user ROM area (When rewriting the user ROM area in boot mode, bit 5 of the flash memory control register 0 must be set to "1". Write to this bit only when executing out of an area other than the internal flash memory). Block Address Block addresses refer to an even address of each block. These addresses are used in the block erase command, lock bit program command, and read lock status command. 160 Mitsubishi microcomputers M16C / 62N Group (80-pin) CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. Operations must be executed from a memory other than the internal flash memory, such as the internal RAM. When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to "1", transition to CPU rewrite mode occurs and software commands can be accepted. In the CPU rewrite mode, write to and read from software commands and data into even-numbered address ("0" for byte address A0) in 16-bit units. Write data into even address in 16-bit units. Do not write 16bit data into odd address or data in 8-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Read data from an even address in the user ROM area when reading the status register. Figure 1.29.1 shows the flash identification register and flash memory control register 0. _____ Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming, erase and lock-bit programming operations, it is "0". Otherwise, it is "1". Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to "1", so that software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, Write to this bit only when _______ executing out of an area other than the internal flash memory. Also only when NMI pin is "H" level. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. To set this bit to "0" by only writing a "0" . Bit 2 of the flash memory control register 0 is a lock bit disable select bit. By setting this bit to "1", it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation is performed when this bit ="1", the lock bit data that is "0" (locked) is set to "1" (unlocked) after erasure. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. This bit can be manipulated only when the CPU rewrite mode select bit = "1". Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1", writing "1" for this bit resets the control circuit. To _____ release the reset, it is necessary to set this bit to "0" when RY/BY status flag is "1". Also when this bit is set to "1", power is not supplied to the internal flash memory, thus power consumption can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to "1", it is necessary to write "0" and then write "1" in succession when the CPU rewrite mode select bit is "1". Use this bit mainly in the low speed mode (when XCIN is the count source of BCLK). When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly necessary to set flash memory control register 0. Figure 1.29.2b shows a flowchart for shifting to the low power dissipation mode. Always perform operation as indicated in these flowcharts. 161 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot mode. If this bit is set to "1" in boot mode, the area to be accessed is switched from the boot ROM area to the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to "1". Note that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Write to this bit only when executing out of an area other than the internal flash memory. Bit 6 of the flash memory control register 0 is the program status flag used exclusively to read the operating status of the auto program operation. If a program error occurs, it is set to "1". Otherwise, it is "0". Bit 7 of the flash memory control register 0 is the erase status flag used exclusively to read the operating status of the auto erase operation. If an erase error occurs, it is set to "1". Otherwise, it is "0". Flash identification register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset FIDR 03B416 0016 Bit name Bit symbol FIDR0 Function Flash identification value Flash value output HND: 0016 Procedure AA R WW R (1) Write FF16 to the address 03B416 (2) Read address 03B416 Read value = FF16 *** DINOR flash memory Read value = 0016 *** HND flash memory Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address When reset FMR0 03B716 XX0000012 Bit name Bit symbol Function FMR00 RY/BY status flag 0: Busy (being written or erased) 1: Ready FMR01 CPU rewrite mode select bit (Note 1) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) FMR02 Lock bit disable select bit (Note 2) 0: Block lock by lock bit data is enabled 1: Block lock by lock bit data is disabled FMR03 Flash memory reset bit (Note 3) 0: Normal operation 1: Reset Reserved bit Must always be set to "0" FMR05 User ROM area select bit (Note 4) (Effective in only boot mode) 0: Boot ROM area is accessed 1: User ROM area is accessed FMR06 Program status flag 0: Pass 1: Error FMR07 Erase status flag 0: Pass 1: Error AA A A AA AA AA R WW R Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of an area other than the internal flash memory. Also only when NMI pin is "H" level. Clear this bit to "0" after read array command. Note 2: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession when the CPU rewrite mode select bit = "1". When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 3: Effective only when the CPU rewrite mode select bit = 1. After write "1", write "0" when RY/BY status flag is "1". Note 4: Write to this bit only when executing out of an area other than the internal flash memory. Figure 1.29.1. Flash identification register and flash memory control register 0 162 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Program in ROM Program in RAM Start *1 (Boot mode only) Set user ROM area select bit to "1" Single-chip mode, or boot mode Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession)(Note 2) Set processor mode register (Note 1) Transfer CPU rewrite mode control program to internal RAM Using software command execute erase, program, or other operation (Set lock bit disable bit as required) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 3) *1 Write "0" to CPU rewrite mode select bit (Boot mode only) Write "0" to user ROM area select bit (Note 4) End Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.25 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state) Note 2: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of an area other than the internal flash memory. Also only when NMI pin is "H" level. Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Note 4: "1" can be set. However, when this bit is "1", user ROM area is accessed. Figure 1.29.2. CPU rewrite mode set/reset flowchart Program in ROM Program in RAM Start Transfer the program to be executed in the low power dissipation mode, to the internal RAM. Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) *1 *1 Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession) Set flash memory reset bit to "1" (by writing "0" and then "1" in succession)(Note 1) Switch the count source of BCLK. XIN stop. (Note 2) Process of low power dissipation mode XIN oscillating Wait until the XIN has stabilized Switch the count source of BCLK (Note 2) Set flash memory reset bit to "0" Set CPU rewrite mode select bit to "0" Wait time until the internal circuit stabilizes (10 s) (Note 3) End Note 1: For flash memory reset bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Note 3: Make a waiting time for 10 s by software. In this waiting time, do not access flash memory. Figure 1.29.2b. Shifting to the low power dissipation mode flowchart 163 Mitsubishi microcomputers M16C / 62N Group (80-pin) CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The address match interrupt cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be _______ used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be used to automatically initialize the flash identification register and flash memory control register 0 to "0", then return to normal operation. However, these two interrupts' jump addresses are located in the fixed vector table and there must exsist a routine to be executed. Since the rewrite operation is halted _______ when an NMI or watchdog timer interrupts occurs, you must reset the CPU rewite mode select bit to "1" and the perform the erase/program operation again. (4) Access disable Write to CPU rewrite mode select bit and user ROM area select bit only when executing out of an area other than the internal flash memory. (5) How to access For CPU rewrite mode select bit and lock bit disable select bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to CPU rewrite mode select bit and user ROM area select bit only when executing out of an area other _______ than the internal flash memory.Also only when NMI pin is "H" level. (6)Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks. (7)Using the lock bit To use the CPU rewrite mode, use a boot program that can set and cancel the lock command. (8) Internal reserved area expansion bit (Bit 3 at address 000516) To use the products which RAM size is over 15 Kbytes or flash memory size is over 192 Kbytes, change into the CPU rewrite mode after setting the internal reserved area expansion bit (bit 3 at address 000516) to "1". Even if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to "1", the internal reserved area expansion bit (bit 3 at address 000516) is not set to "1" automatically. 164 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Software Commands Table 1.29.1 lists the software commands available with the M16C/62N (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Table 1.29.1. List of software commands (CPU rewrite mode) First bus cycle Command Second bus cycle Mode Address Data (D0 to D7) Read array Write X FF16 Read status register Write X 7016 Clear status register Write X 5016 Write WA 4016 Write Block erase Write X 2016 Write Erase all unlock block Write X A716 Write X D016 Lock bit program Write BA 7716 Write BA D016 Read lock bit status Write X 7116 Read BA D6 Program (Note 3) Mode Address Data (D0 to D7) Read X SRD (Note 2) WA (Note 3) WD BA (Note 4) D016 (Note 3) (Note 5) Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data (Set an address to even address in the user ROM area) Note 3: WA = Write Address (even address), WD = Write Data (16-bit data) Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.) Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0. Note 6: X denotes a given address in the user ROM area (that is an even address). Read Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0-D15), 16 bits at a time. The read array mode is retained intact until another command is written. However, please begin to read data in the following procedures when a user uses read array command after program command. (1) Set FF16, FF16, FF16, FF16 to arbitrary continuing four address beforehand (2) Input the top address which FF16 was set at (in read array mode) (3) Input the top address till FFFF16 agrees with the value that begins to have been read (4) Input top address +2 (5) Input top address +2 till FFFF16 agrees with the value that begins to have been read (6) Input an arbitrary address Read Status Register Command (7016) When the command code "7016" is written in the first bus cycle, the content of the status register is read out at the data bus (D0-D7) by a read in the second bus cycle (Set an address to even address in the user ROM area). The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle. 165 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Program Command (4016) Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Make an address in the first bus cycle same as an address to program by the second bus cycle. Whether the write operation is completed can be confirmed by reading the status register or the RY/ _____ BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written. ____ The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Figure 1.29.3 shows an example of a program flowchart. Each block of the flash memory can be write protected by using a lock bit. For details, refer to the section where the data protect function is detailed. Additional writes to the already programmed pages are prohibited. Do a command to use in right after of program command as follows Make an address in the first bus cycle same as an address to program by the second bus cycle of program command. Start Write 4016 Write Write address Write data (Set an address to even address in the user ROM area when reading the status register) Status register read SR7=1? or RY/BY=1? NO YES NO SR4=0? YES Program completed Figure 1.29.3. Program flowchart 166 Program error Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Block Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. Whether the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the auto erase operation. In this case, the read status register mode remains active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is reset using its reset bit. ____ The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. After the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. For details, refer to the section where the status register is detailed. Figure 1.29.4 shows an example of a block erase flowchart. Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer to the section where the data protect function is detailed. Start Write 2016 Write D016 Block address (Set an address to even address in the user ROM area when reading the status register) Status register read SR7=1? or RY/BY=1? NO YES Check full status check (Note) Error Erase error Block erase completed Note: Refer to Figure 1.29.7 . Figure 1.29.4. Block erase flowchart 167 Mitsubishi microcomputers M16C / 62N Group (80-pin) CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlock Blocks Command (A716/D016) By writing the command code "A716" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows, the system starts erasing blocks successively. Whether the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for block erase. Also, the status register can be read out to know the result of the auto erase operation. When the lock bit disable select bit of the flash memory control register 0 = 1, all blocks are erased no matter how the lock bit is set. On the other hand, when the lock bit disable select bit = 0, the function of the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased. Lock Bit Program Command (7716/D016) By writing the command code "7716" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows to the block address of a flash memory block, the system sets the lock bit for the specified block to 0 (locked). Make an address in the first bus cycle same as an address to block by the second bus cycle. Figure 1.29.5 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit data) can be read out by a read lock bit status command. Whether the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for page program. For details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. Start Write 7716 Write D016 block address (Set an address to even address in the user ROM area when reading the status register) Status register read SR7=1? or RY/BY=1? NO YES SR4 = 0? NO Lock bit program in error YES Lock bit program completed Figure 1.29.5. Lock bit program flowchart 168 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Read Lock Bit Status Command (7116) By writing the command code "7116" in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data bus(D6). Figure 1.29.6 shows an example of a read lock bit program flowchart. Start Write 7116 Enter block address (Note) NO D6 = 0? YES Blocks locked Blocks not locked Note: Data bus bit 6. Figure 1.29.6. Read lock bit status flowchart 169 Mitsubishi microcomputers M16C / 62N Group (80-pin) CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data Protect Function (Block Lock) Each block in Figure 1.28.1 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0's lock bit disable select bit is set. (1) When the lock bit disable select bit = "0", a specified block can be locked or unlocked by the lock bit status (lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/ write. On the other hand, the blocks whose lock bit data = "1" are not locked, so they are enabled for erase/write. (2) When the lock bit disable select bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. In this case, the lock bit data that is "0" (locked) is set to "1" (nonlocked) after erasure, so that the lock bit-actuated lock is removed. Status Register The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary even address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary even address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input Table 1.29.2 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (5016) After a reset, the status register is set to "8016". Each bit in this register is explained below. Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to "0" (busy) during write or erase operation and is set to "1" upon completion of these operations. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to "1". The erase status is reset to "0" when cleared. 170 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to "1". The program status is reset to "0" when cleared. When an erase command is in error (which occurs if the command entered after the block erase command (2016) is not the confirmation command (D016), both the program status and erase status (SR5) are set to "1". When the program status or erase status ="1", only the following flash commands will be accepted: Read Array, Read Status Register, and Clear Status Register. Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error): (1) When the valid command is not entered correctly (2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase (2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. Table 1.29.2. Definition of each bit in status register Definition Each bit of SRD Status name "1" "0" Ready Busy - - SR7 (bit7) Sequencer status SR6 (bit6) Reserved SR5 (bit5) Erase status Terminated in error Terminated normally SR4 (bit4) Program status Terminated in error Terminated normally SR3 (bit3) Reserved - - SR2 (bit2) Reserved - - SR1 (bit1) Reserved - - SR0 (bit0) Reserved - - 171 Mitsubishi microcomputers M16C / 62N Group (80-pin) CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 1.29.7 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4=1 and SR5 =1 ? YES (Set an address to even when reading the status register) Command sequence error NO SR5=0? NO Block erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. YES SR4=0? NO YES End (block erase, program) Program error Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.29.7. Full status check flowchart and remedial procedure for errors 172 Mitsubishi microcomputers M16C / 62N Group (80-pin) Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM code protect function The ROM code protect function is used to prohibit reading out or modifying the contents of the flash memory during parallel I/O mode and is set by using the ROM code protect control address register (0FFFFF16). Figure 1.30.1 shows the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. If both of the two ROM code protect reset bits are set to "00," ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits. ROM code protect control address b7 b6 b5 b4 b3 b2 b1 1 1 1 1 b0 Symbol ROMCP Address 0FFFFF16 When reset FF16 Bit name Bit symbol Reserved bit Function Always set this bit to 1. ROM code protect reset bit (Note 2) b5 b4 ROMCR ROMCP1 ROM code protect level 1 set bit (Note 1) b7 b6 0 0: Protect removed 0 1: Protect set bit effective 1 0: Protect set bit effective 1 1: Protect set bit effective 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: The ROM code protect reset bits can be used to turn off ROM code protect level 1. However, since these bits cannot be changed in parallel input/output mode, they need to be rewritten in serial input/output or some other mode. Figure 1.30.1. ROM code protect control address 173 Mitsubishi microcomputers M16C / 62N Group (80-pin) Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Address 0FFFDC16 to 0FFFDF16 ID1 Undefined instruction vector 0FFFE016 to 0FFFE316 ID2 Overflow vector 0FFFE416 to 0FFFE716 BRK instruction vector 0FFFE816 to 0FFFEB16 ID3 Address match vector 0FFFEC16 to 0FFFEF16 ID4 Single step vector 0FFFF016 to 0FFFF316 ID5 Watchdog timer vector 0FFFF416 to 0FFFF716 ID6 DBC vector 0FFFF816 to 0FFFFB16 ID7 0FFFFC16 to 0FFFFF16 NMI vector Reset vector 4 bytes Figure 1.30.2. ID code store addresses 174 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Parallel I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parallel I/O Mode The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is parallel. Use an exclusive programer supporting M16C/62N (flash memory version). Refer to the instruction manual of each programer maker for the details of use. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.28.1 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 1.28.1. The boot ROM area is 4 Kbytes in size. In parallel I/O mode, it is located at addresses 0FF00016 through 0FFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area. 175 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin functions (Flash memory standard serial I/O mode) Pin Name I/O Description Apply program/erase protection voltage to VCC pin and 0 V to Vss pin. VCC,VSS Power input CNVSS (BYTE) CNVSS I Connect to VCC pin. RESET Reset input I Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Clock input I XOUT Clock output O Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. AVCC, AVSS Analog power supply input VREF Reference voltage input I P00 to P07 Input port P0 I P20 to P27 Input port P2 I P30 to P37 Input port P3 I P40 to P43 Input port P4 I P51 to P54, P56, P57 Input port P5 I P50 CE input I P55 EPM input I P60 to P63 Input port P6 I P64 BUSY output O P65 SCLK input I P66 RxD input I P67 TxD output O P70 to P77 Input port P7 I Input "H" or "L" level signal or open. P80 to P84, P86, P87 Input port P8 I Input "H" or "L" level signal or open. P85 NMI input I Connect this pin to Vcc. P90, P92 to P97 Input port P9 I P100 to P107 Input port P10 I 176 Connect AVSS to VSS and AVCC to VCC, respectively. Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "L" level signal. Input "H" or "L" level signal or open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L". Serial data input pin Serial data output pin Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Mitsubishi microcomputers M16C / 62N Group (80-pin) P41 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P42 P36 P37 P40 P33 P34 P35 P32 P31 P27 P30 P24 P25 P26 P22 P23 P21 P20 P07/AN07 Appendix Standard Serial I/O Mode (Flash Memory Version) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P06/AN06 P05/AN05 P04/AN04 P03/AN03 61 40 P43 62 39 63 38 64 37 P02/AN02 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 65 36 66 35 P50 P51 P52 P53 P54 P55 P56 P57/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 67 34 M16C/62N (80-pin flash memory version) group 68 69 70 71 72 73 74 32 31 30 29 28 27 75 26 76 25 77 24 78 23 79 22 80 21 2 3 4 5 6 7 8 EPM BUSY SCLK RXD TXD P70/TxD2/SDA/TA0OUT P71/RxD2/SCL/TA0IN/TB5IN P76/TA3OUT 9 10 11 12 13 14 15 16 17 18 19 20 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P90/TB0IN/CLK3 CNVss(BYTE) P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN P80/TA4OUT P77/TA3IN 1 VSS VCC RESET Connect oscillator circuit. CNVss Mode setup method Value Signal CNVss Vcc EPM Vss RESET Vss to Vcc CE Vcc 33 CE Package: 80P6S-A Figure 1.32.1. Pin connections for serial I/O mode 177 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re_____ ________ leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 1.32.1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.32.18 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit are not accepted unless the ID code matches. 178 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc. 179 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Commands Table 1.32.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Software commands are explained here below. Table 1.32.1. Software commands (Standard serial I/O mode 1) Control command 1st byte transfer 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 Page read FF16 Address (middle) Address (high) Data output Data output Data output Data output to 259th byte 2 Page program 4116 Address (middle) Address (high) Data input Data input Data input Data input to 259th byte 3 Block erase 2016 Address (high) D016 4 Erase all unlocked blocks A716 Address (middle) D016 5 Read status register 7016 SRD output SRD1 output 6 Clear status register 5016 7 Read lock bit status 7116 Address (middle) Address (high) Lock bit data output 8 Lock bit program 7716 Address (middle) Address (high) D016 9 Lock bit enable 7A16 10 Lock bit disable 7516 Address (high) Checksum F516 Address (low) 12 Download function Address (middle) Size FA16 Size (low) (high) 13 Version data output function FB16 Version data output Version data output Version data output 14 Boot ROM area output function FC16 Address (middle) Address (high) Data output 15 Read check data Check FD16 data (low) 11 ID check function Check data (high) When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable ID size ID1 To Data required input number of times Version Version data data output output Data output Data output To ID7 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Acceptable Not acceptable Not acceptable Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. 180 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock. CLK1 RxD1 (M16C reception data) FF16 A8 to A15 A16 to A23 TxD1 (M16C transmit data) data255 data0 RTS1(BUSY) Figure 1.32.2. Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. CLK1 RxD1 (M16C reception data) 7016 TxD1 (M16C transmit data) SRD output SRD1 output RTS1(BUSY) Figure 1.32.3. Timing for reading the status register 181 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. CLK1 RxD1 (M16C reception data) 5016 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.4. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. CLK1 RxD1 (M16C reception data) 4116 A8 to A15 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.5. Timing for the page program 182 A16 to A23 data0 data255 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A8 to A23. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) 2016 A8 to A15 A16 to A23 D016 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.6. Timing for block erasing 183 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the erase operation can be known by reading the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) A716 D016 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.7. Timing for erasing all unlocked blocks Lock Bit Program Command This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the "7716" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. When writing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.8 Timing for the lock bit program 184 7716 A8 to A15 A16 to A23 D016 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the "7116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to A23. CLK1 RxD1 (M16C reception data) 7116 A8 to A15 A16 to A23 TxD1 (M16C transmit data) D6 RTS1(BUSY) Figure 1.32.9. Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code "7A16" is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. CLK1 RxD1 (M16C reception data) 7A16 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.10. Timing for enabling the lock bit 185 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Lock Bit Disable Command This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. CLK1 RxD1 (M16C reception data) 7516 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.11. Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. CLK1 RxD1 (M16C reception data) FA16 Check sum Data size (low) TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.12. Timing for download 186 Data size (high) Program data Program data Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. CLK1 RxD1 (M16C reception data) FB16 TxD1 (M16C transmit data) 'V' 'E' 'R' 'X' RTS1(BUSY) Figure 1.32.13. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock. CLK1 RxD1 (M16C reception data) FC16 A8 to A15 TxD1 (M16C transmit data) A16 to A23 data0 data255 RTS1(BUSY) Figure 1.32.14. Timing for boot ROM area output 187 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. CLK1 RxD1 (M16C reception data) F516 DF16 FF16 0F16 ID size ID1 ID7 TxD1 (M16C transmit data) RTS1(BUSY) Figure 1.32.15. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFDC16 to 0FFFDF16 ID1 Undefined instruction vector 0FFFE016 to 0FFFE316 ID2 Overflow vector 0FFFE416 to 0FFFE716 BRK instruction vector 0FFFE816 to 0FFFEB16 ID3 Address match vector 0FFFEC16 to 0FFFEF16 ID4 Single step vector 0FFFF016 to 0FFFF316 ID5 Watchdog timer vector 0FFFF416 to 0FFFF716 ID6 DBC vector 0FFFF816 to 0FFFFB16 ID7 0FFFFC16 to 0FFFFF16 NMI vector Reset vector 4 bytes Figure 1.32.16. ID code storage addresses 188 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. CLK1 RxD1 (M16C reception data) FD16 TxD1 (M16C transmit data) Check data (low) Check data (high) RTS1(BUSY) Figure 1.32.17. Timing for the read check data 189 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data Protection (Block Lock) Each of the blocks in Figure 1.32.18 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command. Also, the lock bit of any block can be read with the read lock bit status command. Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) After the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a "0" lock bit data are locked and cannot be erased or written in. On the other hand, blocks with a "1" lock bit data are unlocked and can be erased or written in. (2) After the lock bit disable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. In this case, lock bit data that was "0" before the block was erased is set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. 0C000016 Block 6 : 64K byte 0D000016 Block 5 : 64K byte 0E000016 Block 4 : 64K byte 0F000016 Flash memory size Flash memory start address 256Kbytes 0C000016 128Kbytes 0E000016 0F800016 Block 3 : 32K byte Block 2 :24K byte 0FE00016 Block 1 : 4K byte 0FF00016 0FFFFF16 Block 0 : 4K byte User ROM area Figure 1.32.18. Blocks in the user area 190 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 1.32.2 gives the definition of each status register bit. After clearing the reset, the status register outputs "8016". Table 1.32.2. Status register (SRD) Definition SRD0 bits Status name "1" SR7 (bit7) Sequencer status Ready Busy SR6 (bit6) Reserved - - SR5 (bit5) Erase status Terminated in error Terminated normally SR4 (bit4) Program status Terminated in error Terminated normally SR3 (bit3) Reserved - - SR2 (bit2) Reserved - - SR1 (bit1) Reserved - - SR0 (bit0) Reserved - - "0" Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to "0" (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0". 191 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.32.3 gives the definition of each status register 1 bit. "0016" is output when power is turned ON and the flag status is maintained even after the reset. Table 1.32.3. Status register 1 (SRD1) Definition SRD1 bits Status name "1" "0" SR15 (bit7) Boot update completed bit Update completed Not update SR14 (bit6) Flash identification value HND DINOR SR13 (bit5) Reserved - - SR12 (bit4) Check sum match bit SR11 (bit3) ID check completed bits Match 00 01 10 11 SR10 (bit2) Mismatch Not verified Verification mismatch Reserved Verified SR9 (bit1) Data receive time out Time out Normal operation SR8 (bit0) Reserved - - Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Flash Identification Value (SR14) This flag indicates whether the flash memor type is HND or DINOR. Check Sum Match Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Receive Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. 192 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 1.32.19 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4=1 and SR5 =1 ? YES Command sequence error NO SR5=0? NO Block erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. YES SR4=0? NO YES End (block erase, program) Program error Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.32.19. Full status check flowchart and remedial procedure for errors 193 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. Clock input BUSY output CLK1 RTS1(BUSY) Data input RXD1 Data output TXD1 M16C/62N (80-pin flash memory version) group CNVss NMI P50(CE) P55(EPM) (1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 1.32.20. Example circuit application for the standard serial I/O mode 1 194 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level. The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 1.32.21) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.32.21). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 or 16 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. MCU with internal flash memory Peripheral unit Reset (1) Transfer "B016" "B016" (2) Transfer "0016" 16 times At least 15ms transfer interval "B016" 1st "0016" 2nd "0016" 15 th "0016" 16th "0016" "B016" If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU outputs "B016". If other than 10 or 16 MHz, the MCU does not output anything. (3) Transfer check code "B016" The bit rate generator setting completes (9600bps) Figure 1.32.21. Peripheral unit and initial communication 195 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 16 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.32.4 gives the operation frequency and the baud rate that can be attained for. Table 1.32.4 Operation frequency and the baud rate Baud rate 9,600bps Baud rate 19,200bps Baud rate 38,400bps Baud rate 57,600bps 16MH Z 12MH Z - 11MH Z - 10MH Z - 8MH Z - 7.3728MH Z 6MH Z - 5MH Z - - 4.5MH Z - 4.194304MH Z - 4MH Z - - 3.58MH Z 3MH Z - 2MH Z - - - Operation frequency (MH Z) : Communications possible - : Communications not possible 196 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Commands Table 1.32.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 1.32.5. Software commands (Standard serial I/O mode 2) Control command 1st byte transfer 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 Page read FF16 Address (middle) Address (high) Data output Data output Data output 2 Page program 4116 Address (middle) Address (high) Data input Data input Data input 3 Block erase 2016 Address (high) D016 4 Erase all unlocked blocks A716 Address (middle) D016 5 Read status register 7016 SRD output SRD1 output 6 Clear status register 5016 7 Read lock bit status 7116 Address (middle) Address (high) 8 Lock bit program 7716 Address (middle) Address (high) 9 Lock bit enable 7A16 10 Lock bit disable 7516 Address (high) Checksum Address (low) 12 Download function Address (middle) Size FA16 Size (low) (high) 13 Version data output function FB16 Version data output Version data output Version data output 14 Boot ROM area output function FC16 Address (middle) Address (high) Data output Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Lock bit data output D016 F516 11 ID check function Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable ID size ID1 To Data required input number of times Version Version data data output output Data output Data output To ID7 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Acceptable Not acceptable 15 Read check data Check FD16 data (low) 16 Baud rate 9600 B016 B016 Acceptable 17 Baud rate 19200 B116 B116 Acceptable 18 Baud rate 38400 B216 B216 Acceptable 19 Baud rate 57600 B316 B316 Acceptable Check data (high) Not acceptable Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. 197 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first. RxD1 (M16C reception data) FF16 A8 to A15 A16 to A23 TxD1 (M16C transmit data) data0 data255 Figure 1.32.22. Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. RxD1 (M16C reception data) 7016 TxD1 (M16C transmit data) Figure 1.32.23. Timing for reading the status register 198 SRD output SRD1 output Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. RxD1 (M16C reception data) 5016 TxD1 (M16C transmit data) Figure 1.32.24. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. RxD1 (M16C reception data) 4116 A8 to A15 A16 to A23 data0 data255 TxD1 (M16C transmit data) Figure 1.32.25. Timing for the page program 199 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A8 to A23. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) 2016 TxD1 (M16C transmit data) Figure 1.32.26. Timing for block erasing 200 A8 to A15 A16 to A23 D016 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. The result of the erase operation can be known by reading the status register. Each block can be eraseprotected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) D016 A716 TxD1 (M16C transmit data) Figure 1.32.27. Timing for erasing all unlocked blocks Lock Bit Program Command This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the "7716" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. RxD1 (M16C reception data) 7716 A8 to A15 A16 to A23 D016 TxD1 (M16C transmit data) Figure 1.32.28. Timing for the lock bit program 201 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the "7116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to A23. RxD1 (M16C reception data) 7116 A8 to A15 A16 to A23 TxD1 (M16C transmit data) D6 Figure 1.32.29. Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code "7A16" is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. RxD1 (M16C reception data) TxD1 (M16C transmit data) Figure 1.32.30. Timing for enabling the lock bit 202 7A16 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Lock Bit Disable Command This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. RxD1 (M16C reception data) 7516 TxD1 (M16C transmit data) Figure 1.32.31. Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. RxD1 (M16C reception data) FA16 Check sum Program data Program data Data size (low) TxD1 (M16C transmit data) Data size (high) Figure 1.32.32. Timing for download 203 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. RxD1 (M16C reception data) FB16 TxD1 (M16C transmit data) 'V' 'E' 'R' 'X' Figure 1.32.33. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first. RxD1 (M16C reception data) FC16 A8 to A15 TxD1 (M16C transmit data) Figure 1.32.34. Timing for boot ROM area output 204 A16 to A23 data0 data255 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. RxD1 (M16C reception data) F516 DF16 FF16 0F16 ID size ID1 ID7 TxD1 (M16C transmit data) Figure 1.32.35. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFDC16 to 0FFFDF16 ID1 Undefined instruction vector 0FFFE016 to 0FFFE316 ID2 Overflow vector 0FFFE416 to 0FFFE716 BRK instruction vector 0FFFE816 to 0FFFEB16 ID3 Address match vector 0FFFEC16 to 0FFFEF16 ID4 Single step vector 0FFFF016 to 0FFFF316 ID5 Watchdog timer vector 0FFFF416 to 0FFFF716 ID6 DBC vector 0FFFF816 to 0FFFFB16 ID7 0FFFFC16 to 0FFFFF16 NMI vector Reset vector 4 bytes Figure 1.32.36. ID code storage addresses 205 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. RxD1 (M16C reception data) FD16 TxD1 (M16C transmit data) Check data (low) Check data (high) Figure 1.32.37. Timing for the read check data Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps. RxD1 (M16C reception data) B016 TxD1 (M16C transmit data) Figure 1.32.38. Timing of baud rate 9600 206 B016 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps. RxD1 (M16C reception data) B116 TxD1 (M16C transmit data) B116 Figure 1.32.39. Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps. RxD1 (M16C reception data) B216 TxD1 (M16C transmit data) B216 Figure 1.32.40. Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps. RxD1 (M16C reception data) B316 TxD1 (M16C transmit data) B316 Figure 1.32.41. Timing of baud rate 57600 207 Mitsubishi microcomputers M16C / 62N Group (80-pin) Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2. CLK1 Monitor output BUSY Data input RXD1 Data output TXD1 M16C/62N (80-pin flash memory version) group CNVss NMI P50(CE) P55(EPM) (1) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 1.32.42. Example circuit application for the standard serial I/O mode 2 208 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Package Outline Package Outline 80P6S-A MMP EIAJ Package Code QFP80-P-1414-0.65 Plastic 80pin 1414mm body QFP Weight(g) 1.11 Lead Material Alloy 42 MD e JEDEC Code HD 61 1 b2 80 ME D 60 I2 Symbol HE E Recommended Mount Pad 41 20 21 A 40 c F A2 L1 y x M A1 b e A A1 A2 b c D E e HD HE L L1 x y L Detail F b2 I2 MD ME Dimension in Millimeters Min Nom Max 3.05 - - 0.1 0.2 0 2.8 - - 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 0.65 - - 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 - - - - 0.13 0.1 - - 0 10 - 0.35 - - 1.3 - - 14.6 - - - - 14.6 209 Mitsubishi microcomputers M16C / 62N Group (80-pin) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Differences between M16C/62N and M16C/62M Differences between M16C/62N and M16C/62M Differences between M16C/62N and M16C/62M(Note) Item M16C/62N(80-pin) M16C/62M(80-pin) Shortest instruction execution time 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait) Supply voltage 3.0V to 3.6V (f(XIN)=16MHZ, without 2.7V to 3.6V (f(XIN)=10MHZ, without software wait) software wait) 2.4V to 3.0V (f(XIN)=7MHZ, without 2.4V to 2.7V (f(XIN)=7MHZ, without software wait) software wait) 2.2V to 3.0V (f(XIN)=7MHZ, with software 2.2V to 2.4V (f(XIN)=7MHZ with one-wait) :mask ROM version software one-wait) Low power consumption 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait) 28.5mW (VCC = 3V, f(XIN)=10MHZ, without software wait) Clock Generating Circuit Main clock division rate when main clock is stopped: Division by 8 mode Main clock division rate when main clock is stopped: Does not change Watchdog timer Watchdog timer interrupt or reset is selected Watchdog timer interrupt Serial I/O (IIC bus mode) Only digital delay is selected as SDA delay Analog or digital delay is selected as SDA delay A-D converter 10 bits X 8 channels Expandable up to 18 channels 10 bits X 8 channels Expandable up to 10 channels 100ns (f(XIN)=10MHZ, VCC=2.7V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.2V to 3.6V with software one-wait) Note: About the details and the electric characteristics, refer to data sheet. Differences in SFR between M16C/62N and M16C/62M 210 M16C/62N(80-pin) Address Register name 000516 Processor mode register 1 (PM1) b2 037716 UART2 special mode register (U2SMR) b7 SDA digital delay select bit ("1" when reset) b7 SDA digital delay select bit ("0" when reset) 03D416 A-D control register 2 (ADCON2) b2, b1 Analog input group select bit b0 A-D conversion method select bit b2,b1 Reserved bits b0 Reserved bit Watchdog timer function select bit M16C/62M(80-pin) b2 Nothing is assigned 03B416 Flash identification register (FIDR) Have Reserved register 03B616 Flash memory control register 1 (FMR1) Reserved register Have 03B716 Flash memory control register 0 (FMR0) b7 b6 b7 b6 Erase status flag Program status flag Nothing is assigned Nothing is assigned REVISION HISTORY Rev. M16C/62N(80-PIN) GROUP DATA SHEET Date Description Summary Page 1.0 29/05/02 5 14 54 173 Table 1.1.2 M30625FGNGP Delete "**" Figure 1.5.1 Add "More than...needed" _______ (3) The NMI interrupt Line 12 is partly revised. ROM code protect Line 6 to 9 Delete "ROM code...selected by default." Figure 1.30.1 is partly revised. 1.1 30/08/02 1, 5 34 DMAC trigger:24 sources -->25 sources Figure 1.9.5 is partly revised. (1/1) Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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