Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
1
------Table of Contents------
Description
The M16C/62N (80-pin version) group of single-chip microcomputers are built using the high-performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin plastic molded
QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of
instruction efficiency. With 1M bytes of address space, low voltage (2.4V(mask ROM version is 2.2V) to
3.6V), they are capable of executing instructions at high speed. They also feature a built-in multiplier and
DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-
speed processing applications.
The M16C/62N (80-pin version) group includes a wide range of products with different internal memory
types and sizes and various package types.
Features
• Memory capacity..................................ROM (See Figure 1.1.3. ROM Expansion)
RAM 10K to 20K bytes
• Shortest instruction execution time......62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V)
142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait)
• Supply voltage .....................................3.0V to 3.6V (f(XIN)=16MHZ, without software wait)
2.4V to 3.6V (f(XIN)=7MHZ, without software wait)
2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait) :mask ROM version
• Low power consumption ......................34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait)
66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait)
• Interrupts..............................................25 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer......................5 output timers + 6 input timers (3 for timer function only)
• Serial I/O..............................................
5 channels (2 for UART or clock synchronous, 1 for UART, 2 for clock synchronous)
• DMAC ..................................................2 channels (trigger: 25 sources)
• A-D converter.......................................10 bits X 8 channels (Expandable up to 18 channels)
• D-A converter.......................................8 bits X 2 channels
• CRC calculation circuit.........................1 circuit
• Watchdog timer....................................1 line
• Programmable I/O ...............................70 lines
• Input port.............................................. _______
1 line (P85 shared with NMI pin)
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Note: Memory expansion mode and microprocessor mode are not
supported.
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
Timer.............................................................68
Serial I/O .......................................................86
A-D Converter .............................................127
D-A Converter .............................................137
CRC Calculation Circuit ..............................139
Programmable I/O Ports .............................141
Electric Characteristics ...............................151
Flash memory version.................................158
About the M16C/62N (80-pin version) group ..7
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Processor Mode............................................21
Clock Generating Circuit ...............................26
Protection......................................................35
Interrupts.......................................................36
Watchdog Timer............................................56
DMAC ...........................................................58
Rev.1.1
Description
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
1 2 3 4 5 6 7 8 91011121314151617181920
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41424344454647484950515253545557585960
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
56
P4
2
P43
P56
P55
P54
P53
P52
P57/CLKOUT
P63/TXD0
P65/CLK1
P66/RxD1
P67/TXD1
P61/CLK0
P62/RxD0
P60/CTS0/RTS0
P64/CTS1/RTS1/CLKS1
P71/RxD2/SCL/TA0IN/TB5IN (Note)
P50
P51
P70/TxD2/SDA/TA0OUT (Note)
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
P4
0
P4
1
V
CC
X
IN
X
OUT
V
SS
RESET
CNVss(BYTE)
P8
7
/X
CIN
P8
6
/X
COUT
P76/TA3OUT
P7
7
/TA3
IN
P9
3
/DA
0
/TB3
IN
P9
4
/DA
1
/TB4
IN
P9
5
/ANEX0/CLK4
P9
2
/TB2
IN
/S
OUT
3
P8
2
/INT
0
P8
3
/INT
1
P8
1
/TA4
IN
P8
4
/INT
2
P8
0
/TA4
OUT
P8
5/
NMI
P00/AN00
P01/AN01
P02/AN02
P03/AN03
P04/AN04
P05/AN05
P06/AN06
P0
7
/AN
07
VREF
AVSS
AVcc
P100/AN0
P101/AN1
P102/AN2
P103/AN3
P104/AN4/KI0
P105/AN5/KI1
P106/AN6/KI2
P107/AN7/KI3
P96/ANEX1/SOUT4
P97/ADTRG/SIN4
P9
0
/TB0
IN
/CLK3
Note : P70 and P71 are N channel open-drain output pin.
Pin Configuration
Figures 1.1.1 show the pin configurations (top view).
PIN CONFIGURATION (top view)
Package: 80P6S-A
Figure 1.1.1. Pin configuration (top view)
M16C/62N Group (80-pin version)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
3
Block Diagram
Figure 1.1.2 is a block diagram of the M16C/62N (80-pin version) group.
AAAA
AAAA
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits X 8 channels
Expandable up to 18channels)
UART/clock synchronous SI/O
(8 bits X 3 channels)(Note 3)
System clock generator
XIN-XOUT
XCIN-XCOUT
M16C/60 series16-bit CPU core
I/O ports Port P0
8
Port P2
8
Port P3
8
Port P4
4
Port P5
8
Port P6
8
4
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
Registers
ISP
USP
Stack pointer
Vector table
INTB
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Multiplier
778
Port P10
Port P9
Port P8
Port P7
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
Memory
Port P8
5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Note 3: One of three channels is used for UART and IIC mode.
SB FLG
PC
Program counter
Clock synchronous SI/O
(8 bits X 2 channels)
Flag register
Figure 1.1.2. Block diagram of M16C/62N (80-pin version) group
Description
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V)
142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait)
Memory ROM (See the figure 1.1.3. ROM Expansion)
capacity RAM 10K to 20K bytes
I/O port P0 to P10 (except P85) 8 bits x 6, 7 bits x 2, 4 bits x 2
Input port P851 bit x 1
Multifunction TA0, TA3, TA4 16 bits x 3 (timer mode, internal/external event count,
timer
one-shot timer mode and pulse width measurement mode)
TB0, TB2, TB3, TB4, TB5 16 bits x 5 (timer mode, internal/external event count
and pulse period/pulse width measurement mode)
TA1, TA2 16 bits x 2 (timer mode, internal event count
and
a trigger through one-shot timer mode occurs.
)
TB1 16 bits x 1 (timer mode and internal event count
)
Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 2, UART x 1(UART2)
SI/O3, SI/O4 (Clock synchronous) x 2 (SI/O3 is output only)
A-D converter 10 bits x (8 x 2 + 2) channels
D-A converter 8 bits x 2
DMAC 2 channels (trigger: 25 sources)
CRC calculation circuit CRC-CCITT
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt
25 internal and 5 external sources, 4 software sources, 7 levels
Clock generating circuit 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Supply voltage 3.0V to 3.6V (f(XIN)=16MHZ, without software wait)
2.4V to 3.6V (f(XIN)=7MHZ, without software wait)
2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait)
:mask ROM version
Power consumption
34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait)
66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait)
I/O I/O withstand voltage 3.3V
characteristics Output current 1mA
Device configuration CMOS high performance silicon gate
Package 80-pin plastic mold QFP
Note : M16C/62N (80-pin version) group does not support memory expansion or microprocessor mode.
Table 1.1.1. Performance outline of M16C/62N (80-pin version) group
Performance Outline
Table 1.1.1 is a performance outline of M16C/62N (80-pin version) group.
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
5
Mitsubishi plans to release the following products in the M16C/62N (80-pin version) group:
(1) Support for mask ROM version and flash memory version
(2) ROM capacity
(3) Package
80P6S-A : Plastic molded QFP (mask ROM and flash memory versions)
The M16C/62N (80-pin version) group products currently supported are listed in Table 1.1.2.
ROM Size
(Byte)
External
ROM
128K
96K
64K
32K
Mask ROM version Flash memory version
256K
M30621MCN-XXXGP
M30625MGN-XXXGP M30625FGNGP
M30621FCNGP
80K
RAM capacity
ROM capacity Package type Remarks
Type No As of May 2002
Mask ROM version
Flash memory version
M30625MGN-XXXGP 80P6S-A
256 Kbytes 20 Kbytes
M30621MCN-XXXGP 80P6S-A
128 Kbytes 10 Kbytes
M30621FCNGP 80P6S-A
128 Kbytes 10 Kbytes
M30625FGNGP 80P6S-A
256 Kbytes 20 Kbytes
**: Under develo
p
ment
**
**
**
Table 1.1.2. M16C/62N (80-pin version) group
Figure 1.1.3. ROM expansion
Description
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
6
Package type:
GP : Package 80P6S-A
ROM No.
Omitted for flash memory version
ROM capacity:
C : 128K bytes
G: 256K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Type No. M 3 0 6 2 1 M C N – X X X G P
M16C/62 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Figure 1.1.4. Type No., memory size, and package
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
7
About the M16C/62N (80-pin version) group
The M16C/62N (80-pin version) group is packaged in a 80-pin plastic mold package. The number of pins
in comparison with the 100-pin package products is decreased. So be careful about the following.
(a) The M16C/62N (80-pin version) group supports single chip mode alone. It supports neither
memory expansion mode nor microprocessor mode.
(b) The input/output ports given below are absent from the M16C/62N (80-pin version) group. To
stabilize the internal state, set to output mode the direction register of each input/output port. Fail-
ing in setting to output mode involves an increase in current consumption.
<Pins absent from the 80-pin version>
P10 to P17, P44 to P47, P72 to P75, P91
________ ________ ________
(c) INT3 to INT5 allocated to P15 to P17 cannot be used. Keep the INT3 interrupt control register
________ ________
disabled for interrupts. The INT4 interrupt control register and the INT5 interrupt control register
are shared with SI/O3 and SI/O4. When the user don’t use them as SI/O3 and SI/O4, set them
disabled for interrupts.
(d) The output pins of timers A1 and A2 - TA1IN, TA1OUT, TA2IN and TA2OUT - allocated to P72 to P75
cannot be used. In connection with this, the gate function and pulse outputting function of timers A1
and A2 cannot be used. Use timer mode and internal event count, or use as trigger signal genera-
tion in one-shot timer mode.
_________ ________
(e) The UART2 input/output pins - CLK2 and CTS2/RTS2 - allocated to P72 and P73 cannot be used.
In connection with this, UART2 solely as UART of the internal clock can be used. And UART2 must
________ ________
be used by setting the CTS/ RTS disable bit (bit 4 at address 037C16) to “1”.
(f) The input pin TB1IN of timer B1 allocated to P91 cannot be used. With timer B1 under this state, use
only timer mode or the internal event count.
(g) The input pin SIN3 of serial I/O3 allocated to P91 cannot be used. In connection with this, use serial
I/O3 as a serial I/O exclusive to transmission.
(h) The output pins for three-phase motor control allocated to P72 to P75 cannot be used. So set to 0
(ordinary mode) the mode select bit (bit 2) of three-phase PWM control register 0.
(i) The registers given below are reserved registers. Do not access these registers for read or write.
Address Register
0008
16
Chip select control register (CSR)
Address Register
034B
16
Thrree-phase output buffer register 1(IDB1)
000B
16
Data bank register (DBR) 034C
16
Dead time timer(DTT)
0349
16
Three-phase PWM control register 1(INVC1) 034D
16
Timer B2 interrupt occurrence frequency set
counter(ICTB2)
034A
16
Thrree-phase output buffer register 0(IDB0) 03FF
16
Port control register (PCR)
Pin Description
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
8
V
CC
, V
SS
CNV
SS
AV
CC
AV
SS
V
REF
P0
0
to P0
7
P2
0
to P2
7
P3
0
to P3
7
P4
0
to P4
3
Signal name
Power supply
input
CNV
SS
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P2
I/O port P3
I/O port P4
Supply 2.2V to 3.6 V (mask ROM version), 2.4V to 3.6 V (flash memory
version) to the V
CC
pin. Supply 0 V to the V
SS
pin.
Function
This pin switches between processor modes. Connect it to the
V
SS
pin.
This pin is a power supply input for the A-D converter. Connect this
pin to V
CC
.
This pin is a power supply input for the A-D converter. Connect this
pin to V
SS
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input, the user can specify in units of four
bits via software whether or not they are tied to a pull-up resistor.
P0 also function as A-D converter extended input pins as selected by
software.
This is an 8-bit I/O port equivalent to P0.
This is an 8-bit I/O port equivalent to P0.
This is a 4-bit I/O port equivalent to P0.
Pin name
I
X
IN
X
OUT
Clock input
Clock output
These pins are provided for the main clock generating circuit. Connect
a ceramic resonator or crystal between the X
IN
and the X
OUT
pins. To
use an externally derived clock, input it to the X
IN
pin and leave the
X
OUT
pin open.
I
O
(BYTE) External data
bus width
select input
This pin is connected to CNVss in microcomputer. Connect this pin to
V
SS
.
I
I
I/O
I/O
I/O
Analog power
supply input
I/O
I/O
Reset input An “L” on this input resets the microcomputer.IRESET
I/O port P5 I/O
I/O
I/O
I/O
I/O
I
I/O port P6
I/O port P7
I/O port P8
I/O port P8
5
P5
0
to P5
7
P6
0
to P6
7
P7
0
, P7
1
,
P7
6
, P7
7
P8
0
to P8
4
,
P8
6
,P8
7
,
P8
5
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P5
7
in
this port outputs a divide-by-8 or divide-by-32 clock of X
IN
or a clock of
the same frequency as X
CIN
as selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by software.
This is a 4-bit I/O port equivalent to P0 (P7
0
and P7
1
are N channel
open-drain output). Pins in this port also function as timer A
0
–A
3
,
timer B5 or UART2 I/O pins as selected by software.
P8
0
to P8
4
, P8
6
, and P8
7
are I/O ports with the same functions as P0.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts.
P8
6
and P8
7
can be set using software to function as the I/O pins for a
sub clock generation circuit. In this case, connect a quartz oscillator
between P8
6
(X
COUT
pin) and P8
7
(X
CIN
pin).
P8
5
is an input-only port that also functions for NMI. The NMI interrupt
is generated when the input at this pin changes from “H” to “L”. The
NMI function cannot be cancelled using software. The pull-up cannot be
set for this pin.
Pin Description
Pin Description
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
9
Pin Description
Signal name FunctionPin name I/O
I/O
I/O
I/O port P9
I/O port P10
P90,
P92 to P97
P100 to P107
This is an 7-bit I/O port equivalent to P0. Pins in this port also function
as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output
pins, A-D converter extended input pins, or A-D trigger input pins as
selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins. Furthermore, P104–P107 also function as
input pins for the key input interrupt function.
Note: Memory expansion mode and microprocessor mode are not be supported.
Memory
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
10
Operation of Functional Blocks
The M16C/62N (80-pin version) group accommodates certain units in a single chip. These units include
ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/
logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC
calculation circuit, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M16C/62N (80-pin version) group. The address space extends the 1M
bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30621MCN-
XXXGP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts
_______
such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt
routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using
the internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30621MCN-XXXGP, 10K bytes of internal RAM is mapped
to the space from 0040016 to 02BFF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.7.1 to 1.7.3 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
Figure 1.4.1. Memory map
00000
16
YYYYY
16
FFFFF
16
00400
16
XXXXX
16
Internal ROM area
SFR area
For details, see Figures
1.7.1 to 1.7.3
Internal RAM area
Reserved
area
FFE00
16
FFFDC
16
FFFFF
16
Note : These memory maps show an instance in which PM13 is set to 0; but in the
case of products in which the internal RAM and the internal ROM are expanded
to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which
PM13 is set to 1.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
Special page
vector table
DBC
NMI
Address YYYYY
16
053FF
16
Address XXXXX
16
ROM size
02BFF
16
10K bytes
20K bytes
RAM size
C0000
16
E0000
16
128K bytes
256K bytes
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
11
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
AAAAAAA
AAAAAAA
HL
b15 b8 b7 b0
R0(Note)
AAAAAAA
HL
b15 b8 b7 b0
R1(Note)
R2(Note)
AAAAAAA
AAAAAAA
b15 b0
R3(Note)
AAAAAAA
AAAAAAA
b15 b0
A0(Note)
AAAAAAA
AAAAAAA
b15 b0
A1(Note)
AAAAAAA
AAAAAAA
b15 b0
FB(Note)
AAAAAAA
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0
b19
b0
b19
HL
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These re
g
isters consist of two re
g
ister banks.
A
A
AA
AA
AA
AA
A
A
AAAAAAA
AAAAAAA
A
A
AA
AA
AA
AA
AA
AA
A
A
CDZSBOIU
IPL
Figure 1.5.1. Central processing unit register
CPU
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
12
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
13
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
Figure 1.5.2. Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
AA
AA
AA
AA
A
A
AA
AA
AAAAAAA
AAAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL b0b15
Reset
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
14
Figure 1.6.2. Reset sequence
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
The RAM is undefined at power on. The initial values must therfore be set. When a reset signal is applied
while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the
CPU access.
Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
Figure 1.6.1. Example reset circuit
BCLK
Address
Content of reset vector
Single chip
mode
BCLK 28cycles
FFFFE
16
X
IN
RESET
FFFFC
16
More than 20 cycles are needed
RESET VCC
0.48V
RESET
VCC
0V
0V
3V
3V
2.4V
Example when VCC = 3V
.
More than 20 cycles of XIN are needed.
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
15
____________
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.6.3 and 1.6.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.6.1. Pin status when RESET pin level is “L”
Status
CNV
SS
= V
SS
Pin name
P0, P2, P3, P4
0
to P4
3
, P5, P6,
P7
0
, P7
1
, P7
6
, P7
7
, P8
0
to P8
4
, Input port (floating)
P8
6
, P8
7
, P9
0
, P9
2
to P9
7
, P10
Reset
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
Figure 1.6.3. Device's internal status after a reset is cleared
x : Nothing is mapped to this bit
? : Undefined
The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.
The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM,
the value may be set as unknown due to the termination of the CPU access.
(1) (000416)···Processor mode register 0 0016
(2) (000516)···Processor mode register 1
000
(3) (000616)···System clock control register 0
10000100
(4) (000716)···System clock control register 1
00010000
(5)
(6) (000916)···
Address match interrupt enable
register
00
(7) Protect register (000A16)···
000
(8)
(000F16)···Watchdog timer control register 00?0????
(10)
(001416)···Address match interrupt register 1
(001516)···
(001616)···
0
0016
0016
0 0 0
(11)
(002C16)···DMA0 control register
00000?00
(12)
(003C16)···DMA1 control register
00000?00
(20)
(004B16)···DMA0 interrupt control register
? 0 0 0
(21)
(004C16)···DMA1 interrupt control register
? 0 0 0
(22)
(004D16)···Key input interrupt control register
? 0 0 0
(19)
(004A16)···
Bus collision detection interrupt
control register
0 0 0?
(001016)···Address match interrupt register 0
(001116)···
(001216)···
0
0016
0016
0 0 0
(9)
(13)
(004416)···INT3 interrupt control register
00?000
(14)
(004516)···Timer B5 interrupt control register
?000
(15)
(004616)···Timer B4 interrupt control register
?000
(16)
(004716)···Timer B3 interrupt control register
?000
(17)
(004816)···SI/O4 interrupt control register
00?000
(18)
(004916)···SI/O3 interrupt control register
00?000
(23)
A-D conversion interrupt control
register
(24)
(25)UART2 transmit interrupt control
register
UART2 receive interrupt control
register
(004E16)···
? 0 0 0
(004F16)···
(005016)···
? 0 0 0
? 0 0 0
000
(26)
(27)
(28)
(29)
UART0 transmit interrupt control
register
UART0 receive interrupt control
register
UART1 transmit interrupt control register
UART1 receive interrupt control register
(30)
(31)
(32)
(33)
(34)
(35)
(36)
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
(37)
Timer B2 interrupt control register
(38)
INT0 interrupt control register
(39)
INT1 interrupt control register
(40)
INT2 interrupt control register
(44)
Three-phase output buffer register 0
(45)
Three-phase output buffer register 1
Three-phase PWM control register 0
(42)
Three-phase PWM control register 1
(43)
(41)
Timer B3,4,5 count start flag
(46)
Timer B3 mode register
(47)
Timer B4 mode register
(48)
Timer B5 mode register
(49)
Interrupt cause select register
0016
UART2 transmit/receive control register 1
UART2 transmit/receive control register 0
(037816)···
(037D16)···
(037C16)···
0016
00000001
01000000
(57)
UART2 transmit/receive mode register
(55)
(56)
(51)
SI/O4 control register
(54)
UART2 special mode register
(005116)···
(005216)···
(005316)···
(005416)···
(005516)···
(005616)···
(005716)···
(005816)···
(005916)···
(005A16)···
(005B16)···
(005C16)···
(005D16)···
(005E16)···
(005F16)···
(034A16)···
(034B16)···
(034816)···
(034916)···
(034016)···
(035B16)···
(035C16)···
(035D16)···
(035F16)···
(036616)···
(037716)···
(036216)···SI/O3 control register
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
?00000
?00000
?00000
0016
0016
0016
0016
00? 0000
00? 0000
4016
8016
4016
(50)
000
(53)
UART2 special mode register 2 (037616)···
0016
(52)
UART2 special mode register 3 (037516)···
(000816)···Chip select control register
000 10000
00? 0000?
0
0016
(58)
Data bank register (000B16)···
0016
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
17
(0383
16
)···Trigger select flag
(0384
16
)···Up-down flag
(62)
(61)
(0396
16
)···Timer A0 mode register
(63)
(0397
16
)···Timer A1 mode register
(64)
(0398
16
)···Timer A2 mode register
(67)
(039B
16
)···Timer B0 mode register
(68)
(039C
16
)···Timer B1 mode register
(69)
(039D
16
)···Timer B2 mode register
(70)
(65)
(0399
16
)···Timer A3 mode register
(66)
(039A
16
)···Timer A4 mode register
(0382
16
)···One-shot start flag
(60)
00
16
0
00
16
00
16
00
16
00
16
00
16
0? 0000
00? 0000
00? 0000
(03AC
16
)···UART1 transmit/receive control register 0
(75)
(03AD
16
)···UART1 transmit/receive control register 1
(76)
(03B0
16
)···UART transmit/receive control register 2
(77)
0
(03A0
16
)···UART0 transmit/receive mode register
(71)
(03A4
16
)···UART0 transmit/receive control register 0
(72)
(03A5
16
)···UART0 transmit/receive control register 1
(73)
00
16
000 1000
000 0010
0
0
(03A8
16
)···UART1 transmit/receive mode register
(74)
00
16
000 1000
000 0010
0
0
000000
(03D7
16
)···A-D control register 1 00
16
0000000
Count start flag (0380
16
)··· 00
16
0
(0381
16
)···Clock prescaler reset flag
(59)
x : Nothing is mapped to this bit
? : Undefined
The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.
The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM,
the value may be set as unknown due to the termination of the CPU access.
Note: This register is only exist in flash memory version.
(03E2
16
)···Port P0 direction register
(84)
(03E3
16
)···Port P1 direction register
(85)
(03E6
16
)···Port P2 direction register
(86)
(03E7
16
)···Port P3 direction register
(87)
(03EA
16
)···Port P4 direction register
(88)
(03EB
16
)···Port P5 direction register
(89)
(03EE
16
)···Port P6 direction register
(90)
(03EF
16
)···Port P7 direction register
(91)
(03F2
16
)···Port P8 direction register
(92)
(03F3
16
)···Port P9 direction register
(93)
(03F6
16
)···Port P10 direction register
(94)
(03FC
16
)···Pull-up control register 0
(95)
(03FD
16
)···Pull-up control register 1
(96)
(03FE
16
)···Pull-up control register 2
(97)
Port control register
(98)
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00 00000
(03DC
16
)···
D-A control register
(83)
00
16
Frame base register (FB)
(101)
Address registers (A0/A1)
(100)
Interrupt table register (INTB)
(102)
User stack pointer (USP)
(103)
Interrupt stack pointer (ISP)
(104)
Static base register (SB)
(105)
Flag register (FLG)
(106)
0000
16
0000
16
00000
16
0000
16
0000
16
0000
16
0000
16
Data registers (R0/R1/R2/R3)
(99)
0000
16
(03FF
16
)···
(03B4
16
)···
(107)
(03B7
16
)···
(03BA
16
)···
DMA1 cause select register 00
16
(03D4
16
)···A-D control register 2
(80)
(03D6
16
)···A-D control register 0
(81)
(82)
0
000 0???0
0000
(03B8
16
)···
DMA0 cause select register 00
16
000010
(108)
Flash identification register (Note)
(78)
Flash memory control register 0 (Note)
(79)
?
00
16
(109)
00
16
Figure 1.6.4. Device's internal status after a reset is cleared
SFR
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
18
Figure 1.7.1. Location of peripheral unit control registers (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
032A
16
032B
16
032C
16
032D
16
032E
16
032F
16
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
16
033F
16
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
DMA1 control register (DM1CON)
DMA1 source pointer (SAR1)
DMA1 transfer counter (TCR1)
DMA1 destination pointer (DAR1)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Chip select control register (CSR)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
DMA0 destination pointer (DAR0)
Timer A1 interrupt control register (TA1IC)
UART0 transmit interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
DMA1 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
Bus collision detection interrupt control register (BCNIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A3 interrupt control register (TA3IC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A4 interrupt control register (TA4IC)
INT3 interrupt control register (INT3IC)*
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
SI/O4 interrupt control register (S4IC)
INT5 interrupt control register (INT5IC)*
SI/O3 interrupt control register (S3IC)
INT4 interrupt control register (INT4IC)*
Note 1: M16C/62N (80-pin version) group is not provided with the functions, in whole or in part, of the registers marked with an *. But the relevant
registers need to be dealt with as given on page 7.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Data bank register (DBR)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
19
Figure 1.7.2. Location of peripheral unit control registers (2)
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
Three-phase PWM control register 0(INVC0)*
Three-phase PWM control register 1(INVC1)
Thrree-phase output buffer register 0(IDB0)
Thrree-phase output buffer register 1(IDB1)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer B3, 4, 5 count start flag (TBSR)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
Interrupt cause select register (IFSR)
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
Timer B0 register (TB0)
Timer B1 register (TB1)
Timer B2 register (TB2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Up-down flag (UDF)
Timer A3 register (TA3)
Timer A4 register (TA4)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
DMA1 request cause select register (DM1SL)
DMA0 request cause select register (DM0SL)
CRC data register (CRCD)
CRC input register (CRCIN)
SI/O3
transmit/receive register
(S3TRR)
SI/O4
transmit/receive register
(S4TRR)
SI/O3 control register (S3C)
SI/O3
bit rate generator
(S3BRG)
SI/O4
bit rate generator
(S4BRG)
SI/O4 control register (S4C)
UART2 special mode register (U2SMR)
UART2 receive buffer register (U2RB)
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)*
UART2 transmit/receive mode register (U2MR)
UART2 transmit/receive control register 1 (U2C1)
UART2 bit rate generator (U2BRG)
UART transmit/receive control register 2 (UCON)
Timer A4-1 register (TA41)
UART2 special mode register 2 (U2SMR2)
Note 1 : This register is only exist in flash memory version.
Note 2 : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Note 3 : M16C/62N (80-pin version) group is not provided with the functions, in whole or in part, of the registers marked with an *.
But the relevant registers need to be dealt with as given on page 7.
Flash memory control register 0 (FMR0)
(Note1)
Flash identification register (FIDR)
(Note1)
UART2 special mode register 3 (U2SMR3)
SFR
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
20
Figure 1.7.3. Location of peripheral unit control registers (3)
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
Port P0 register (P0)
Port P0 direction register (PD0)
Port P1 register (P1)
Port P1 direction register (PD1)
Port P2 register (P2)
Port P2 direction register (PD2)
Port P3 register (P3)
Port P3 direction register (PD3)
Port P4 register (P4)
Port P4 direction register (PD4)
Port P5 register (P5)
Port P5 direction register (PD5)
Port P6 register (P6)
Port P6 direction register (PD6)
Port P7 register (P7)
Port P7 direction register (PD7)
Port P8 register (P8)
Port P8 direction register (PD8)
Port P9 register (P9)
Port P9 direction register (PD9)
Port P10 register (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
A-D control register 2 (ADCON2)
Port control register (PCR)
*
*
*
*
*
*
*
*
Note 1: M16C/62N (80-pin version) group is not provided with the functions, in whole or in part, of the registers
marked with an *. But the relevant registers need to be dealt with as given on page 7.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
21
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Processor Mode
Single-chip mode
M16C/62N (80-pin version) group support single-chip mode only.
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be ac-
cessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral
functions.
Figure 1.8.1 shows the processor mode registers 0 and 1.
Figure 1.8.2 shows the memory map.
Processor Mode
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
22
Processor Mode
Processor mode register 0 (Note)
Symbol Address When reset
PM0 0004
16 0016
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0: Single-chip mode
0 1: Must not be set
1 0: Must not be set
1 1: Must not be set
b1 b0
PM03
PM01
PM00 Processor mode bit
Reserved bit
Software reset bit The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note 1)
Symbol Address When reset
PM1 000516 000000X02
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be
indeterminate.
Reserved bit Must always be set to “0”
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
Must always be set to “0”
Reserved bit Must always be set to “0”
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values
to this register.
Note 2: When the reset is revoked, this bit is set to “0”. To expand the internal area,
set this bit to “1” in user program. And the top of user program must be allocated
to D000016 or subsequent address.
Note 3: This bit can only be set to “1”.
PM17 Wait bit 0 : No wait state
1 : Wait state inserted
A
A
A
A
A
Internal reserved area
expansion bit (Note 2)
PM13 0 : The internal RAM area is 15 kbytes
or less and the internal ROM area
is 192 kbytes or less
1 : Expands the internal RAM area
and internal ROM area to over
15 kbytes and to over 192 kbytes
respectively. (Note 2)
A
Reserved bit Must always be set to “0”
00
0000 0
0 : Interrupt
1 : Reset (Note 3)
Watchdog timer function
select bit
PM12
A
A
A
A
(Note 3)
Figure 1.8.1. Processor mode registers 0 and 1
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
23
Single-chip mode
SFR area
Internal
RAM area
Reserved
area
Internal
ROM area
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products
in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes,
respectively, they show an instance in which PM13 is set to 1.
Address YYYYY
16
053FF
16
Address XXXXX
16
ROM size
02BFF
16
10K bytes
20K bytes
RAM size
C0000
16
E0000
16
128K bytes
256K bytes
Figure 1.8.2. Memory map
Internal Reserved Area Expansion Bit (PM13)
This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In
M30625MGN, for example, to set this bit to “1” expands the internal RAM area and the internal ROM area
to 20 Kbytes and 256 Kbytes respectively. When the reset is revoked, this bit is set to “0”. To expand the
internal area, set this bit to “1” in user program. And the top of user program must be allocated to D000016
or subsequent address.
In the case of the product in which the internal ROM is 192 Kbytes or less and the internal RAM is 15
Kbytes or less, set this bit to “0”. The internal area is not expanded and any action is not affected, even if
this bit is set to “1”.
Software Wait
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
24
Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note).
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle
is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. Set this bit
after referring to the recommended operating conditions (main clock input oscillation frequency) of the
electric characteristics.
The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit.
Table 1.8.1 shows the software wait and bus cycles. Figure 1.8.3 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Area Wait bit Bus cycle
1 2 BCLK cycles
SFR
Internal
ROM/RAM 0 1 BCLK cycle
Invalid 2 BCLK cycles
Table 1.8.1. Software waits and bus cycles
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Wait
25
Figure 1.8.3. Typical bus timings using software wait
Output Input
Address Address
< With wait >
BCLK
Read signal
Write signal
Data bus
Address bus (Note2)
Chip select (Note2)
BCLK
Read signal
Write signal
Address bus (Note2) Address Address
Bus cycle (Note1)
< No wait >
Output
Data bus
Chip select (Note2)
Input
Note 1 : These example timing charts indicate bus cycle length.
After this bus cycle sometimes come read and write cycles in succession.
Note 2 : The address bus and chip select may be extended depending on the CPU status
such as that of the instruction queue buffer.
Note 3 : This figure shows microcomputer internal state.
Bus cycle (Note1)
Clock Generating Circuit
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
26
Figure 1.9.2. Examples of sub clock
Table 1.9.1. Main clock and sub clock generating circuits
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Example of oscillator circuit
Figure 1.9.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.9.2 shows some examples of
sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.9.1 and 1.9.2 vary with each oscillator used. Use the
values recommended by the manufacturer of your oscillator.
Figure 1.9.1. Examples of main clock
Main clock generating circuit Sub clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B’s count clock
operating clock source source
Usable oscillator Ceramic or crystal oscillator Crystal oscillator
Pins to connect oscillator XIN, XOUT XCIN, XCOUT
Oscillation stop/restart function Available Available
Oscillator status immediately after reset
Oscillating Stopped
Other Externally derived clock can be input
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
Externally derived clock
Open
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
CIN
and X
COUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
(Note)
C
CIN
C
COUT
R
Cd
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
27
Clock Control
Figure 1.9.3 shows the block diagram of the clock generating circuit.
Sub clock
CM04
f
C32
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
WDCi : Bit i at address 000F
16
X
CIN
CM10 “1”
Write signal
1/32
X
COUT
Q
S
R
WAIT instruction
X
OUT
Main clock
CM05
f
C
CM02
f
1
QS
R
NMI
Interrupt request
level judgment
output
RESET
Software reset f
C
CM07=0
CM07=1
f
AD
AAA
AAA
Divider
ad
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
X
IN
f
8
f
32
c
b
b
1/2
c
f
32SIO2
f
8SIO2
f
1SIO2
BCLK
Figure 1.9.3. Clock generating circuit
Clock Generating Circuit
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
28
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power
dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed
mode, the value before high-speed/medium-speed mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when the port XC select bit (bit 4 at address 000616) is set to “0” , shifting to stop mode and
at a reset.
When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting
from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed
mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
29
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 0006
16 4816
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P5
7
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit 0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
Port X
C
select bit
(Note 10) 0 : I/O port
1 : X
CIN
-X
COUT
generation (Note 9)
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5) 0 : On
1 : Off
Main clock division select
bit 0 (Note 7) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: Changes to “1” when the port X
C
select bit (CM04) is set to “0”, shiffing to stop mode and at a reset.
Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock
oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”. The main clock division select bit 0
(CM06) and the X
IN
-X
OUT
drive capacity select bit (CM15) change to “1” when this bit is set to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X
OUT
turns “H”. The built-in feedback resistor remains being connected, so X
IN
turns pulled up to X
OUT
(“H”) via the feedback resistor.
Note 6: Set port X
C
select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”. Do not write to
both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before
setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation
mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained.
Note 8: f
C32
is not included. Do not set to “1” when using low-speed or low power dissipation mode.
Note 9: When the X
CIN
/X
COUT
is used, set ports P8
6
and P8
7
as the input ports without pull-up.
Note10: The X
CIN
-X
COUT
drive capacity select bit changes to “1” when this bit is set to “0”.
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 000716 2016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note4) 0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation
mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
16
) is “0”. If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, X
OUT
turns “H”, and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-impedance state.
CM15 X
IN
-X
OUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
WR
WR
CM16
CM17
Reserved bit Must always be set to
“0”
Reserved bit Must always be set to
“0”
Main clock division
select bit 1 (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Must always be set to
“0”
Reserved bit Must always be set to
“0”
00
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.9.4 shows the system clock control registers 0 and 1.
Figure 1.9.4. Clock control registers 0 and 1
Clock Generating Circuit
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
30
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4
functions provided an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel
must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a
_______
hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to
0, then shift to stop mode.
The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-speed/
medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from
high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is
retained.
Table 1.9.2. Port status during stop mode
Pin Single-chip mode
Port Retains status before stop mode
CLKOUT When fc selected “H”
When f8, f32 selected Retains status before stop mode
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
31
Table 1.9.3. Port status during wait mode
Pin Single-chip mode
Port Retains status before wait mode
CLKOUT When fC selected Does not stop
When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit
is “0”.
When the WAIT peripheral function clock stop bit is “1”, the sta-
tus immediately prior to entering wait mode is retained.
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32
does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU
running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table
1.9.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that
interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must
have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set
to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware
_______
reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift
to wait mode.
Status Transition of BCLK
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M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
32
01000Invalid Division by 2 mode
10000Invalid Division by 4 mode
Invalid Invalid 0 1 0 Invalid Division by 8 mode
11000Invalid Division by 16 mode
00000Invalid No-division mode
Invalid Invalid 1 Invalid 0 1 Low-speed mode
Invalid Invalid 1 Invalid 1 1 Low power dissipation mode
CM17 CM16 CM07 CM06 CM05 CM04
Operating mode of BCLK
Table 1.9.4. Operating modes dictated by settings of system clock control registers 0 and 1
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.9.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address
000616) and the XIN-XOUT drive capacity select bit (bit 5 at address 000716) change to “1” when shifting
from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset.
When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
CM1i : bit i of the address 000716
CM0i : bit i of the address 000616
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M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
33
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK.
Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its as-
signed clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fC clock is supplied by the
sub-clock. Each peripheral function operates according to its assigned clock.
• Low power dissipation mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fc clock is supplied by the sub-clock. The only peripheral functions that operate are those
with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.9.5 is the state transition diagram of the above modes.
Power control
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34
Figure 1.9.5. State transition diagram of Power control mode
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = “1”
All oscillators stopped CPU operation stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(X
IN
)/8
CM07 = “0” CM06 = “1”
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
Stop mode
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = “1”
Interrupt
Interrupt
CM10 = “1”
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0” BCLK : f(X
IN
)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = “0”
CM06 = “1”
High-speed mode
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(X
CIN
)
CM07 = “1” CM06 = “1”
CM15 = “1”
BCLK : f(X
CIN
)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Note 1, 3)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0” CM05 = “1”
CM04 = “0” CM04 = “1”
CM06 = “0”
(Notes 1,3)
CM06 = “1”
CM04 = “0” CM04 = “1”
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
(Refer to the following for the transition of normal mode.)
CM03 = “1”
Low-speed
mode
Low power
dissipation
mode
Note : To CM0, CM1 registers, do a simultaneous write by word access.
CM07 = “0”
CM06 = “1”
CM05 = “0”
CM10 = “1”
(Note)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
35
Protect register
Symbol Address When reset
PRCR 000A
16
XXXXX000
2
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC0
PRC2
Enables writing to processor mode
registers 0 and 1 (addresses 000416
and 000516)
Function
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716
)
Enables writing to port P9 direction
register (address 03F316) and SI/Oi
control registers (i=3,4) (addresses
036216 and 036616) (Note
)
0 : Write-inhibited
1 : Write-enabled
WR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
A
AA
A
A
AA
AA
A
AA
Figure 1.9.6. Protect register
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.9.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (ad-
dress 03F316), SI/O3 control register (address 036216), and SI/O4 control register (address 036616) can
only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs
can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register and SI/Oi control register
(i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically
reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at
000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return
to “0” after a value has been written to an address. The program must therefore be written to return these
bits to “0”.
Interrupt
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• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 1.10.1. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
_______
NMI
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Overview of Interrupt
Type of Interrupts
Figure 1.10.1 lists the types of interrupts.
Interrupt
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37
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT instruction interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
Interrupt
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Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset ____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______ _______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer
interrupt occurs (initialize watchdog timer).
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt ___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
________ ________
• INT0 interrupt through INT2 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
