89HPES24T3G2ZBAL8 - IDT, Integrated Device Technology Inc

February 2012

6024 Silver Creek Valley Road, San Jose, Californi a 95138

Telephone: (800) 345- 7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

IDT™ 89HPES24T3G2

PCI Express® Switch

User Manual

GENERAL DISCLAIMER

Integrated Device Te chnology, Inc. res erves the right to make changes to i ts products or specificat ions at an y time, wi thout notice, in order to improve design or performance

and to s upply the best possible pr oduct. IDT does not assum e any responsibility for use of any c i rcuitry described other than the circuitry embodied in an IDT product. The

Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No li cense is

grant ed by implication or otherwise under any patent, patent rig h ts or othe r rights, of Inte grated De vice Technology, Inc.

CODE DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely

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Integrated D evice Technology's pro ducts are not authori zed for use as crit ical components in life support devices or systems unless a specific written ag reement pertaining to

such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or syst ems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,

when properly used in accordanc e with ins tructions for us e provided in the labeling, can be reasonabl y expected to result in a significant injury to the user.

2. A cr itic al co mpone nt is an y com pon en ts of a lif e s uppo r t dev ic e or sys te m w ho se f ail ur e to per fo rm c an b e r eas ona bl y ex pec ted to cause the failure of the life support device

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IDT, the IDT logo, and Integrated Devi ce Technology are trademarks or r egistered trademarks of Integr ated Dev i c e Techn ology, Inc.

Notes

PES24T3G2 User Manual 1 February 22, 2012

About This Manual

Introduction

This user manual includes hardware and software information on the 89HPES24T3G2, a member of

IDT’s PRECISE™ family of PCI Express® switchi ng solutions offering the next-generation I/O interconnect

standard.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical character-

istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)

as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES24T3G2 Device Overview,” provides a complete introduction to the performance

capabilities of the 89HPES24T3G2. Included in this chapter is a summary of features for the device as well

as a system block diagram and pin description.

Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-

ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic

and the SerDes.

Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,

link width negotiation, and lane reversal.

Chapter 4, “General Purp ose I/O,” describes how the 8 General Purpose I/O (GPIO) pins may be indi-

vidually configured as general purpose inputs, general purpose outputs, or alternate functions.

Chapter 5, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the

PES24T3G2.

Chapter 6, “Power M anagemen t,” describes the power management capability structure located in the

configuration space of each PCI-PCI bridge in the PES24T3G2.

Chapter 7, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in

the PES24T3G2.

Chapter 8, “Configuration Registers,” discusses the base addresses, PCI configuration space, and

registers associated with the PES24T3G2.

Chapter 9, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic

TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms

assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or

true, independent of wheth er that level is represented by a high or low voltage. The term negate or negation

is used to indicate that a signal is inactive or false.

To define the active polarity of a s ignal, a suffix will be used. Signals ending wi th an ‘N’ s hould be i nter-

preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,

buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on

the right. No leading zeros will be included.

IDT

PES24T3G2 User Manual 2 February 22, 2012

Notes

Throughout this manual, when describing signal transitions, the following terminology is used. Rising

edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These

terms are illustrated in Figure 1.

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats w ill be used. The binary

format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:

0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

Data Units

The following data unit terminology is used in this document.

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-

words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always

the most significant bit and bit 0 is the leas t significant bit. In bytes, bit 7 is always the most significant bit

and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian

systems label byte z ero as the most significant (l eftmost) byte of a word. Little endian systems label byte

zero as the least significant (rightmost) byte of a word. See Figure 2.

Term Words Bytes Bits

Byte 1/2 1 8

Word 1 2 16

Doubleword (Dword) 2 4 32

Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

1 2 3 4

high-to-low

transition low-to-high

transition

single clock cycle

IDT

PES24T3G2 User Manual 3 February 22, 2012

Notes

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Software in the context of this register terminology refers to modifications made by PCIe root configura-

tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-

ization. See Table 2.

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hard-

ware initialization is only allowed for system integrated devices.)

Bits are read-only after initialization and can only be reset (for

write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero.

Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero.

Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On

reads, software must use appropriate masks to extract the defined

bits and not rely on reserved bits being any particular value. On

writes, software must ensure that the values of reserved bit posi-

tions are preserved. That is, the values of reserved bit positions

must first be read, merged with the new values for other bit posi-

tions and then written back.

Read Only RO Software can only read registers/bits with this attribute. Contents

are hardwired to a constant value or are status bits that may be

set and cleared by hardware. Writing to a RO location has no

effect.

Read and Write RW Software can both read and write bits with this attribute.

Table 2 Register Terminology (Sheet 1 of 2)

0123

bit 0bit 31

Address of Bytes within Words: Big Endian

3210

bit 0bit 31

Address of Bytes within Words: Little Endian

IDT

PES24T3G2 User Manual 4 February 22, 2012

Notes

Use of Hypertext

In Chapter 8, Tables 8.2 and 8.3 contain register nam es and page numbers highlighted in blue under the

clicking on the register name in the source table. Each register name in the table is linked directly to the

appropriate register in the register section of the chapter. To return to the source table after having jumped

to the register section, click on the same register name (in blue) in the register section.

Reference Documents

PCI Express Base Specification, Revision 2.0, PCI Special Interest Group.

PCI Power Management Interface Specification, Revision 1.2, PCI Special Interest Group.

PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.

SMBus Specification, Revision 2.0.

Revision History

September 26, 2007: Initial publication of preliminary user manual.

November 28, 2007: Updated Chapter 1 to reflect some pins are not available in the 19x19 pinout

package.

December 4, 2007: Added hardwired address locations for MSMBADD R and SS MBADDR to Chapters

1 and 5.

January 7, 2008: In Chapter 1, Table 1.9, MSMBADDR[4:1] pins changed to pull-down. In Chapter 5, I/

O Expanders section, added text explaining legacy compatibility with Gen1 PCIe switches. In Chapter 8,

modified the following fields: L0SEL in PCIELCAP has default value of 0x6, ARIS in PCIEDCAP2 is RO,

and ARIFEN in PCIEDCTL2 is RO.

July 15, 2008: In Chapter 8. added A utonomous Link Reliability Management section and 4 registers.

Removed General Purpose Register (0x40C).

August 25, 2008: In Chapter 2, deleted reference to FRSTS pins.

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However, writing a value of zero to a bit with this attribute has no

effect. A RW1C bit can only be set to a value of 1 by a hardware

event. To clear a RW1C bit (i.e., change its value to zero) a value

of one must be written to the location. An RW1C bit is never

cleared by hardware.

Read and Write when

Unlocked RWL Software can read the register/bits with this attribute. Writing to

fied if the REGUNLOCK bit in the SWCTL register is set. When

the REGUNLOCK bit is cleared, writes are ignored and the regis-

ter/bits are effectively read-only.

RWL bits are implicitly “Sitcky.”

Write Transient WT The zero is always read from a bit/field of this type. Writing of a

one is used to quality the writing of other bits/fields in the same

Zero Zero A zero register or bit must be written with a value of zero and

returns a value of zero when read.

Type Abbreviation Description

Table 2 Register Terminology (Sheet 2 of 2)

IDT

PES24T3G2 User Manual 5 February 22, 2012

Notes

November 3, 2008: In Chapter 1, updated Table 1.2 with additional silicon revisions. Updated the

description for the following fields in Chapter 8: LDIS and LRET in the PCIELCTL register, ULD in the

ALRSTS register, and TLW in the PHYLCFG0 register, and changed the last Reserved field in the

PCIEDCTL2 register from 31:6 to 15:6.

May 7, 2009: In Chapter 3, revised the Lane Reversal section.

July 21, 2009: In Chapter 3, revised section Dynamic Link Width Reconfiguration Support in the

PES24T3G2. Also, deleted entire section S oftware Management of Link Width Upconfiguration and Down-

configuration.

September 15, 2010: In Table 1.9, changed Buffer type for PCI Express from CML to PCIe differential

and changed reference clocks to HCSL

October 26, 2010: In Chapter 2, revised Clocking section on page 1 to remove reference to REFCLKM.

September 23, 2011: Added DDDNC (Disable Downstream Device Number Checking) bit to Switch

Control register in Chapter 8, Configuration Registers.

February 22, 2012: Added paragraph after Table 5.11 to explain use of DWord addresses.

IDT

PES24T3G2 User Manual 6 February 22, 2012

Notes

PES24T3G2 User Manual i February 22, 2012

Table of Contents

About This Manual

Introduction ....................................................................................................................................1

Content Summary ..........................................................................................................................1

Signal Nomenclature .....................................................................................................................1

Numeric Representations ..............................................................................................................2

Data Units ......................................................................................................................................2

Register Terminology .....................................................................................................................3

Use of Hypertext ............................................................................................................................4

Reference Documents ...................................................................................................................4

Revision History .............................................................................................................................4

PES24T3G2 Device Overview

Introduction.....................................................................................................................................1-1

Features..........................................................................................................................................1-1

Logic Diagram — PES24T3G2.......................................................................................................1-4

Vendor ID........................................................................................................................................1-4

Device ID........................................................................................................................................1-5

Revision ID......................................................................................................................................1-5

JTAG ID..........................................................................................................................................1-5

SSID/SSVID....................................................................................................................................1-5

Pin Description................................................................................................................................1-6

Pin Characteristics........................................................................................................................1-10

Port Configuration.........................................................................................................................1-11

Clocking, Reset and Initialization

Clocking..........................................................................................................................................2-1

Initialization.....................................................................................................................................2-1

Reset...............................................................................................................................................2-2

Fundamental Reset................................................................................................................2-2

Hot Reset................................................................................................................................2-5

Upstream Secondary Bus Reset............................................................................................2-6

Downstream Secondary Bus Reset........................................................................................2-6

Downstream Port Reset Outputs....................................................................................................2-7

Power Enable Controlled Reset Output..................................................................................2-7

Power Good Controlled Reset Output....................................................................................2-8

Link Operation

Introduction.....................................................................................................................................3-1

Polarity Inversion............................................................................................................................3-1

Lane Reversal.................................................................................................................................3-1

Link Width Negotiation....................................................................................................................3-2

Dynamic Link Width Reconfiguration..............................................................................................3-3

Dynamic Link Width Reconfiguration Support in the PES24T3G2.........................................3-3

Link Speed Negotiation...................................................................................................................3-4

Link Speed Negotiation in the PES24T3G2............................................................................3-4

Software Management of Link Speed.....................................................................................3-5

Link Reliability.................................................................................................................................3-5

IDT Table of Contents

PES24T3G2 User Manual ii February 22, 2012

Notes

Autonomous Link Reliability Management .............................................................................3-6

Link Retraining................................................................................................................................3-7

Link Down.......................................................................................................................................3-8

Slot Power Limit Support................................................................................................................3-8

Upstream Port ........................................................................................................................3-8

Downstream Port....................................................................................................................3-8

Link States......................................................................................................................................3-8

Active State Power Management ...................................................................................................3-9

Link Status....................................................................................................................................3-10

De-emphasis Negotiation .............................................................................................................3-10

Low-Swing Transmitter Voltage Mode..........................................................................................3-10

Crosslink.......................................................................................................................................3-10

General Purpose I/O

Introduction.....................................................................................................................................4-1

GPIO Configuration ........................................................................................................................4-1

GPIO Pin Configured as an Input...........................................................................................4-1

GPIO Pin Configured as an Output........................................................................................4-2

GPIO Pin Configured as an Alternate Function......................................................................4-2

SMBus Interfaces

Introduction.....................................................................................................................................5-1

Master SMBus Interface.................................................................................................................5-2

Initialization.............................................................................................................................5-2

Serial EEPROM......................................................................................................................5-2

I/O Expanders.........................................................................................................................5-7

Slave SMBus Interface.................................................................................................................5-12

Initialization...........................................................................................................................5-13

SMBus Transactions ............................................................................................................5-13

Power Management

Introduction.....................................................................................................................................6-1

PME Messages...............................................................................................................................6-2

PCI-Express Power Management Fence Protocol.........................................................................6-2

Power Budgeting Capability............................................................................................................6-3

Hot-Plug and Hot-Swap

Hot-Plug..........................................................................................................................................7-1

Hot-Plug I/O Expander ...........................................................................................................7-4

Hot-Plug Interrupts and Wake-up...........................................................................................7-4

Legacy System Hot-Plug Support ..........................................................................................7-5

Hot-Swap........................................................................................................................................7-6

Configuration Registers

Configuration Space Organization..................................................................................................8-1

Upstream Port (Port 0) ...........................................................................................................8-2

Downstream Ports..................................................................................................................8-6

Register Definitions.......................................................................................................................8-10

Type 1 Configuration Header Registers...............................................................................8-10

PCI Express Capability Structure.........................................................................................8-20

Power Management Capability Structure.............................................................................8-36

Message Signaled Interrupt Capability Structure.................................................................8-37

IDT Table of Contents

PES24T3G2 User Manual iii February 22, 2012

Notes

Subsystem ID and Subsystem Vendor ID............................................................................8-39

Extended Configuration Space Access Registers................................................................8-39

Advanced Error Reporting (AER) Enhanced Capability.......................................................8-40

Device Serial Number Enhanced Capability.........................................................................8-48

PCI Express Virtual Channel Capability...............................................................................8-49

Power Budgeting Enhanced Capability................................................................................8-55

Switch Control and Status Registers....................................................................................8-56

Autonomous Link Reliability Management ...........................................................................8-71

JTAG Boundary Scan

Introduction.....................................................................................................................................9-1

Test Access Point...........................................................................................................................9-1

Signal Definitions............................................................................................................................9-1

Boundary Scan Chain.....................................................................................................................9-3

Test Data Register (DR).................................................................................................................9-4

Boundary Scan Registers.......................................................................................................9-4

Instruction Register (IR)..................................................................................................................9-6

EXTEST..................................................................................................................................9-6

SAMPLE/PRELOAD...............................................................................................................9-7

BYPASS.................................................................................................................................9-7

CLAMP...................................................................................................................................9-7

IDCODE..................................................................................................................................9-7

VALIDATE..............................................................................................................................9-8

RESERVED............................................................................................................................9-8

Usage Considerations............................................................................................................9-8

IDT Table of Contents

PES24T3G2 User Manual iv February 22, 2012

Notes

PES24T3G2 User Manual v February 22, 2012

List of Tables

Table 1.1 PES24T3G2 Device ID........................................................................................................1-5

Table 1.2 PES24T3G2 Revision ID.....................................................................................................1-5

Table 1.3 PCI Express Interface Pins..................................................................................................1-6

Table 1.4 SMBus Interface Pins..........................................................................................................1-6

Table 1.5 General Purpose I/O Pins....................................................................................................1-7

Table 1.6 System Pins.........................................................................................................................1-8

Table 1.7 Test Pins..............................................................................................................................1-8

Table 1.8 Power, Ground, and SerDes Resistor Pins.........................................................................1-9

Table 1.9 Pin Characteristics.............................................................................................................1-10

Table 2.1 Boot Configuration Vector Signals.......................................................................................2-1

Table 4.1 General Purpose I/O Pin Alternate Function.......................................................................4-1

Table 4.2 GPIO Pin Configuration.......................................................................................................4-1

Table 5.1 Serial EEPROM SMBus Address........................................................................................5-2

Table 5.2 PES24T3G2 Compatible Serial EEPROMs.........................................................................5-3

Table 5.3 Serial EEPROM Initialization Errors....................................................................................5-6

Table 5.4 I/O Expander Function Allocation........................................................................................5-7

Table 5.5 I/O Expander Default Output Signal Value..........................................................................5-8

Table 5.6 I/O Expander 0 Signals......................................................................................................5-11

Table 5.7 I/O Expander 2 Signals......................................................................................................5-11

Table 5.8 I/O Expander 4 Signals......................................................................................................5-12

Table 5.9 Slave SMBus Address When a Static Address is Selected...............................................5-13

Table 5.10 Slave SMBus Command Code Fields...............................................................................5-13

Table 5.11 CSR Register Read or Write Operation Byte Sequence...................................................5-14

Table 5.12 CSR Register Read or Write CMD Field Description.........................................................5-15

Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence................................................5-15

Table 5.14 Serial EEPROM Read or Write CMD Field Description.....................................................5-16

Table 6.1 PES24T3G2 Power Management State Transition Diagram...............................................6-2

Table 8.1 Base Addresses for Port Configuration Space Register......................................................8-1

Table 8.2 Upstream Port 0 Configuration Space Registers.................................................................8-2

Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers...........................................8-6

Table 9.1 JTAG Pin Descriptions.........................................................................................................9-2

Table 9.2 Boundary Scan Chain..........................................................................................................9-3

Table 9.3 Instructions Supported by PES24T3G2’s JTAG Boundary Scan........................................9-6

Table 9.4 System Controller Device Identification Register.................................................................9-7

IDT List of Tables

PES24T3G2 User Manual vi February 22, 2012

Notes

PES24T3G2 User Manual vii February 22, 2012

List of Figures

Figure 1.1 PES24T3G2 Architectural Block Diagram ..........................................................................1-3

Figure 1.2 PES24T3G2 Logic Diagram ...............................................................................................1-4

Figure 1.3 PES24T3G2 Port Configuration .......................................................................................1-11

Figure 2.1 Fundamental Reset with Serial EEPROM initialization ......................................................2-4

Figure 2.2 Fundamental Reset using RSTHALT to keep device in Quasi-Reset state .......................2-5

Figure 2.3 Power Enable Controlled Reset Output Mode Operation ..................................................2-7

Figure 2.4 Power Good Controlled Reset Output Mode Operation .....................................................2-8

Figure 3.1 Merged Port Lane Reversal ...............................................................................................3-2

Figure 3.2 PES24T3G2 ASPM Link Sate Transitions .........................................................................3-9

Figure 5.1 SMBus Interface Configuration Examples .........................................................................5-1

Figure 5.2 Single Double Word Initialization Sequence Format ..........................................................5-3

Figure 5.3 Sequential Double Word Initialization Sequence Format ...................................................5-4

Figure 5.4 Configuration Done Sequence Format ..............................................................................5-4

Figure 5.5 Slave SMBus Command Code Format ............................................................................5-13

Figure 5.6 CSR Register Read or Write CMD Field Format ..............................................................5-15

Figure 5.7 Serial EEPROM Read or Write CMD Field Format ..........................................................5-16

Figure 5.8 CSR Register Read Using SMBus Block Write/Read Trans actions with PEC Disabled ..5-17

Figure 5.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC

Disabled ...........................................................................................................................5-17

Figure 5.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........5-18

Figure 5.11 Serial EEPROM Write Using SMBus Block Write Trans actions with PEC Disabled ........5-18

Figure 5.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........5-18

Figure 5.13 CSR Register Read Using SMBus Read and Write Trans actions with PEC Disabled ....5-19

Figure 6.1 PES24T3G2 Power Management State Transition Diagram .............................................6-1

Figure 7.1 Hot-Plug on Switch Downstream Slots Application ............................................................7-1

Figure 7.2 Hot-Plug with Switch on Add-In Card Application ..............................................................7-2

Figure 7.3 Hot-Plug with Carrier Card Application ..............................................................................7-2

Figure 7.4 PES24T3G2 Hot-Plug Event Signalling .............................................................................7-6

Figure 8.1 Port Configuration Space Organization .............................................................................8-2

Figure 9.1 Diagram of the JTAG Logic ................................................................................................9-1

Figure 9.2 State Diagram of PES24T3G2’s TAP Controller ................................................................9-2

Figure 9.3 Diagram of Observe-only Input Cell ...................................................................................9-4

Figure 9.4 Diagram of Output Cell ......................................................................................................9-5

Figure 9.5 Diagram of Bidirectional Cell ..............................................................................................9-5

Figure 9.6 Device ID Register Format .................................................................................................9-7

IDT List of Figures

PES24T3G2 User Manual viii February 22, 2012

Notes

PES24T3G2 User Manual ix February 22, 2012

AERCAP - AER Capabilities (0x100)..................................................................................................... 8-40

AERCEM - AER Correctable Error Mask (0x114).................................................................................. 8-46

AERCES - AER Correctable Error Status (0x110)................................................................................. 8-45

AERCTL - AER Control (0x118)............................................................................................................. 8-47

AERHL1DW - AER Header Log 1st Doubleword (0x11C)..................................................................... 8-47

AERHL2DW - AER Header Log 2nd Doubleword (0x120)..................................................................... 8-47

AERHL3DW - AER Header Log 3rd Doubleword (0x124)...................................................................... 8-48

AERHL4DW - AER Header Log 4th Doubleword (0x128)...................................................................... 8-48

AERUEM - AER Uncorrectable Error Mask (0x108).............................................................................. 8-41

AERUES - AER Uncorrectable Error Status (0x104)............................................................................. 8-40

AERUESV - AER Uncorrectable Error Severity (0x10C)........................................................................ 8-44

ALRCNT - Autonomous Link Reliability Counter (0x56C)...................................................................... 8-73

ALRCTL - Autonomous Link Reliability Control (0x560)......................................................................... 8-71

ALRERT - Autonomous Link Reliability Error Rate Threshold (0x5680)................................................ 8-72

ALRSTS - Autonomous Link Reliability Status (0x564).......................................................................... 8-72

BAR0 - Base Address Register 0 (0x010).............................................................................................. 8-13

BAR1 - Base Address Register 1 (0x014).............................................................................................. 8-14

BCTL - Bridge Control Register (0x03E)................................................................................................ 8-19

BIST - Built-in Self Test Register (0x00F).............................................................................................. 8-13

CAPPTR - Capabilities Pointer Register (0x034)................................................................................... 8-18

CCODE - Class Code Regi ster (0x009)................................................................................................. 8-12

CLS - Cache Line Size Register (0x00C)............................................................................................... 8-13

DID - Device Identification Register (0x002).......................................................................................... 8-10

ECFGADDR - Extended Configuration Space Access Address (0x0F8)............................................... 8-39

ECFGDATA - Extended Configuration Space Access Data (0x0FC)..................................................... 8-40

EEPROMINTF - Serial EEPROM Interface (0x42C).............................................................................. 8-64

EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 8-18

GPECTL - General Purpose Event Control (0x450)............................................................................... 8-66

GPESTS - General Purpose Event Status (0x454)................................................................................ 8-67

GPIOCFG - General Purpose I/O Configuration (0x41C)....................................................................... 8-62

GPIOD - General Purpose I/O Data (0x420).......................................................................................... 8-62

GPIOFUNC - General Purpose I/O Control Function (0x418)................................................................ 8-61

HDR - Header Type Register (0x00E).................................................................................................... 8-13

HPCFGCTL - Hot-Plug Configuration Control (0x408)........................................................................... 8-60

INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 8-18

INTRPIN - Interrupt PIN Register (0x03D)............................................................................................. 8-19

IOBASE - I/O Base Register (0x01C)..................................................................................................... 8-15

IOBASEU - I/O Base Upper Register (0x030)........................................................................................ 8-17

IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434)..................................................................... 8-66

IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438)..................................................................... 8-66

IOEXPINTF - I/O Expander Interface (0x430)........................................................................................ 8-65

IOLIMIT - I/O Limit Register (0x01D)........................................................................................... ........... 8-15

IOLIMITU - I/O Limit Upper Register (0x032)......................................................................................... 8-18

MBASE - Memory Base Register (0x020).............................................................................................. 8-16

MLIMIT - Memory Limit Register (0x022)............................................................................................... 8-16

MSIADDR - Message Signaled Interrupt Address (0x0D4).................................................................... 8-38

MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)................................................ 8-37

MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)....................................................... 8-39

MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8)...................................................... 8-38

IDT Register List

PES24T3G2 User Manual x February 22, 2012

Notes

PBUSN - Primary Bus Number Register (0x018)....................................................................................8-14

PCICMD - PCI Command Register (0x004)............................................................................................8-10

PCIECAP - PCI Express Capability (0x040) ...........................................................................................8-20

PCIEDCAP - PCI Express Device Capabilities (0x044)..........................................................................8-21

PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064).....................................................................8-32

PCIEDCTL - PCI Express Device Control (0x048)..................................................................................8-22

PCIEDCTL2 - PCI Express Device Control 2 (0x068).............................................................................8-33

PCIEDSTS - PCI Express Device Status (0x04A) ..................................................................................8-23

PCIEDSTS2 - PCI Express Device Status 2 (0x06A) .............................................................................8-33

PCIELCAP - PCI Express Link Capabilities (0x04C)..............................................................................8-24

PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C ) .........................................................................8-33

PCIELCTL - PCI Express Link Control (0x050).......................................................................................8-25

PCIELCTL2 - PCI Express Link Control 2 (0x070)..................................................................................8-33

PCIELSTS - PCI Express Link Status (0x052)........................................................................................8-27

PCIELSTS2 - PCI Express Link Status 2 (0x072)...................................................................................8-35

PCIESCAP - PCI Express Slot Capabilities (0x054)...............................................................................8-28

PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074)..........................................................................8-35

PCIESCTL - PCI Express Slot Control (0x058).......................................................................................8-30

PCIESCTL2 - PCI Express Slot Control 2 (0x078)..................................................................................8-35

PCIESSTS - PCI Express Slot Status (0x05A) .......................................................................................8-31

PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ..................................................................................8-36

PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200)................................................8-49

PCISTS - PCI Status Register (0x006) ...................................................................................................8-11

PHYLCFG0 - Phy Link Configuration 0 (0x530)......................................................................................8-68

PHYLSTATE0 - Phy Link State 0 (0x540)...............................................................................................8-70

PHYLSTS0 - Phy Link Status 0 (0x538)..................................................................................................8-69

PHYPRBS - Phy PRBS Seed (0x55C)....................................................................................................8-71

PLTIMER - Primary Latency Timer (0x00D)............................................................................................8-13

PMBASE - Prefetchable Memory Base Register (0x024).......................................................................8-16

PMBASEU - Prefetchable Memory Base Upper Register (0x028)..........................................................8-17

PMCAP - PCI Power Management Capabilities (0x0C0)........................................................................8-36

PMCSR - PCI Power Management Control and Status (0x0C4) ............................................................8-37

PMLIMIT - Prefetchable Memory Limit Register (0x026)........................................................................ 8-17

PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)..........................................................8-17

PVCCAP1- Port VC Capability 1 (0x204)................................................................................................8-49

PVCCAP2- Port VC Capability 2 (0x208)................................................................................................8-50

PVCCTL - Port VC Control (0x20C)........................................................................................................8-50

PVCSTS - Port VC Status (0x20E) .........................................................................................................8-50

PWRBCAP - Power Budgeting Capabilities (0x280)...............................................................................8-55

PWRBD - Power Budgeting Data (0x288)...............................................................................................8-56

PWRBDSEL - Power Budgeting Data Select (0x284).............................................................................8-55

PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) .....................................................8-56

PWRBPBC - Power Budgeting Power Budget Capability (0x28C) .........................................................8-56

RID - Revision Identification Register (0x008) ........................................................................................8-12

SBUSN - Secondary Bus Number Register (0x019)...............................................................................8-14

SECSTS - Secondary Status Register (0x01E) ......................................................................................8-15

SERDESCTL- SerDes Control (0x500)...................................................................................................8-67

SLTIMER - Secondary Latency Timer Register (0x01B).........................................................................8-14

SMBUSCTL - SMBus Control (0x428)....................................................................................................8-63

SMBUSSTS - SMBus Status (0x424) .....................................................................................................8-62

SNUMCAP - Serial Number Capabilities (0x180) ...................................................................................8-48

SNUMLDW - Serial Number Lower Doubleword (0x184) .......................................................................8-48

SNUMUDW - Serial Number Upper Doubleword (0x188).......................................................................8-48

SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4)...........................................................8-39

SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0)...................................8-39

IDT Register List

PES24T3G2 User Manual xi February 22, 2012

Notes

SUBUSN - Subordinate Bus Number Register (0x01A)..........................................................................8-14

SWCTL - Switch Control (0x404)............................................................................................................8-57

SWSTS - Switch Status (0x400) .............................................................................................................8-56

VCR0CAP- VC Resource 0 Capability (0x210).......................................................................................8-51

VCR0CTL- VC Resource 0 Control (0x214)............................................................................................8-51

VCR0STS - VC Resource 0 Status (0x218)............................................................................................8-52

VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............................................................8-53

VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............................................................8-53

VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............................................................8-54

VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C).............................................................8-54

VID - Vendor Identification Register (0x000)...........................................................................................8-10

IDT Register List

PES24T3G2 User Manual xii February 22, 2012

Notes

PES24T3G2 User Manual 1 - 1 February 22, 2012

Chapter 1

PES24T3G2 Device Overview

Introduction

The 89HPES24T3G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The

PES24T3G2 is a 24-lane, 3-port Gen2 peripheral chip that performs PCI Express base switching with a

feature set optimized for high performance applications such as servers, storage, and communications

systems. It provides connectivity and switching functions between a PCI Express upstream port and two

downstream ports and supports switching between downstream ports.

Features

High Performance PCI Express Switch

– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting

5 Gbps and 2.5 Gbps operation

– Up to three switch ports

– Support for Max Payload Size up to 2048 bytes

– Supports one virtual channel and eight traffic classes

– Fully compliant with PCI Express base specification Revision 2.0

Flexible Architecture with Numerous Configuration Opt ions

– Automatic per port link width negotiation to x8, x4, x2, or x1

– Automatic lane reversal on all ports

– Automatic polarity inversion

– Supports in-band hot-plug presence detect capability

– Supports external signal for hot plug event notification allowing SCI/SMI generation for legacy

operating systems

– Dynamic link width reconfiguration for power/performance optimization

– Configurable downstream port PCI-to-PCI bridge device numbering

– Crosslink support

– Supports ARI forwarding defined in the Alternative Routing-ID Interpretation (ARI) ECN for virtu-

alized and non-virtualized environments

– Ability to load device configuration from serial EEPROM

Legacy Support

– PCI compatible INTx emulation

– Supports bus locked transactions, allowing use of PCI Express with legacy software

Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and queueing

– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded S erDes, 8B/10B encoder /decoder (no sepa-

rate transceivers needed)

Reliability, Availability, and Serviceability (RAS) Features

– Ability to disable peer-to-peer communications

– Supports ECRC and Advanced Error Reporting

– All internal data and control RAMs are SECDED ECC protected

– Supports PCI Express hot-plug on all downstream ports

– Supports upstream port hot-plug

– Hot-swap capable I/O

– External Serial EEPROM contents are checksum protected

– Supports PCI Express Device Serial Number Capability

– Capability to monitor link reliability and autonomously change link speed to prevent link instability

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 2 February 22, 2012

Notes

Power Management

– Utilizes advanced low-power design techniques to achieve low typical power consumption

– Support PCI Power Management Interface specification (PCI-PM 1.1)

• Supports device power management states: D0, D3hot and D3cold

– Support for PCI Express Active State Power Management (ASPM) link state

• Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3

– Supports PCI Express Power Budgeting Capability

– Configurable SerDes power consumption

• Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode

• Supports numerous SerDes Transmit Voltage Margin settings

– Unused SerDes are disabled

Testability and Debug Features

– Per port link up and activity status outputs available on I/O expander outputs

– Built in SerDes 8-bit and 10-bit pseudo-random bit stream (PRBS) generators

– Numerous SerDes test modes, including a PRBS Master Loopback mode for in-system link

testing

– Ability to read and write any internal register via SMBus and JTAG interfaces, including SerDes

internal controls

– Per port statistics and performance counters, as well as proprietary link status registers

General Purpose Input/Output Pins

– Each pin may be individually configured as an input or output

– Each pin may be individually configured as an interrupt input

– Some pins have selectable alternate functions

Option A Package: 19mm x 19mm 324-ball Flip Chip BGA with 1mm ball spacing

Option B Package: 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spacing

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 3 February 22, 2012

Figure 1.1 PES24T3G2 Architectural Block Diagram

TDM Demux

D-Bus U-Bus

ESP & Arb

Route Map

Table

Ingress

Processor

TLP

Checker

Egress

Processor

Completion

Processor

Message

Processor

TLP

Generator

Hot-Plug

Controller

Application Layer

Data Link Layer

Physical Layer & SerDes Mux/Demux

SerDes

Port 0

Switch Core

GPIO

Controller

Master

SMBus

Interface

Reset

Controller

Slave

SMBus

Interface

Output &

Replay Buffer

TDM Demux

Route Map

Table

Ingress

Processor

TLP

Checker

Egress

Processor

Completion

Processor

Message

Processor

TLP

Generator

Hot-Plug

Controller

Application Layer

Data Link Layer

Physical Layer & SerDes Mux/Demux

Output &

Replay Buffer

TDM Demux

Route Map

Table

Ingress

Processor

TLP

Checker

Egress

Processor

Completion

Processor

Message

Processor

TLP

Generator

Hot-Plug

Controller

Application Layer

Data Link Layer

Physical Layer & SerDes Mux/Demux

Output &

Replay Buffer

Input

Frame

Buffer

Input

Frame

Buffer

Input

Frame

Buffer

Input

Frame

Buffer

Input

Frame

Buffer

Input

Frame

Buffer

D-Bus

Arbiter U-Bus

Arbiter

Bus Decoup ler

Queue

SerDes

Port 2

SerDes

Port 4

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 4 February 22, 2012

Logic Diagram — PES24T3G2

Figure 1.2 PES24T3G2 Logic Diagram

Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT,

GPIO[6:3].

Vendor ID

All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Technology, Inc.

Reference

Clocks PEREFCLKP

PEREFCLKN

JTAG_TCK

GPIO[10:0]

11 General Purpose

I/O*

VDDCORE

VDDI/O

VDDPEA Power/Ground

MSMBADDR[4:1]

MSMBCLK

MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK

SSMBDAT

Master

SMBus Interface

Slave

SMBus Interface

CCLKUS

RSTHALT

System

Pins

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

JTAG Pins

VSS

SWMODE[2:0] 3

CCLKDS

PERSTN

REFCLKM

MSMBSMODE

PE0RP[0]

PE0RN[0]

PE0RP[7]

PE0RN[7]

PCI Express

Switch

SerDes Input

PE0TP[0]

PE0TN[0]

PE0TP[7]

PE0TN[7]

PCI Expres s

Switch

SerDes Output

...

Port 0 Port 0

...

PE2RP[0]

PE2RN[0]

PE2RP[7]

PE2RN[7]

PCI Express

Switch

SerDes Input

PE2TP[0]

PE2TN[0]

PE2TP[7]

PE2TN[7]

PCI Expres s

Switch

SerDes Output

...

Port 2 Port 2

...

PE4RP[0]

PE4RN[0]

PE4RP[7]

PE4RN[7]

PCI Express

Switch

SerDes Input

PE4TP[0]

PE4TN[0]

PE4TP[7]

PE4TN[7]

PCI Expres s

Switch

SerDes Output

...

Port 4 Port 4

...

PES24T3G2

REFRES0

SerDes

Reference

Resistors

REFRES2

REFRES4

REFRES5

VDDPEHA

Reference Clock

Frequency Selection

REFRES1

REFRES3

VDDPETA

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 5 February 22, 2012

Notes

Device ID

The PES24T3G2 device ID is shown in Table 1.1.

Revision ID

The PES24T3G2 revision ID is shown in Table 1.2.

JTAG ID

The JTAG ID is:

–Version: Same value as Revision ID. See Table 1.2.

–Part number: Same value as base Device ID. See Table 1.1.

–Manufacture ID: 0x33

–LSB: 0x1

SSID/SSVID

The PES24T3G2 contains the mechanisms necessary to implement the P CI-to-PCI bridge Subsystem

ID and Subsystem Vendor ID capability structure. However, in the default configuration the Subsystem ID

and Subsystem Vendor ID capability structure is not enabled. To enable the capability, the SSID and SSVID

fields in the Subsystem ID and Subsystem Vendor ID (SSIDSSVID) register must be initialized with the

appropriate ID values. the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be

initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted

to point to the next capability if necessary.

PCIe Device Device ID

0x2 0x806A

Table 1.1 PES24T3G2 Device ID

Revision ID

Offset Description

0x0 Corresponds to ZA silicon.

0x01 Corresponds to ZB silicon.

0x02 Corresponds to ZC silicon.

Table 1.2 PES24T3G2 Revision ID

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 6 February 22, 2012

Notes

Pin Description

The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions

listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals

ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals

(including clocks, buses, and select lines) w ill be interpreted as being active, or asserted, when at a logic

one (high) level.

Note: In the PES24T3G2, the two downstream ports are labeled port 2 and port 4.

Signal Type Name/Description

PE0RP[7:0]

PE0RN[7:0] IPCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0. Port 0 is the upstream port.

PE0TP[7:0]

PE0TN[7:0] OPCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0. Port 0 is the upstream port.

PE2RP[7:0]

PE2RN[7:0] IPCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

PE2TP[7:0]

PE2TN[7:0] OPCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 2.

PE4RP[7:0]

PE4RN[7:0] IPCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

PE4TP[7:0]

PE4TN[7:0] OPCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 4.

PEREFCLKP

PEREFCLKN IPCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

REFCLKM1

1. REFCLKM is not available in the 19mm package and frequency is set at 100MHz.

IPCI Express Reference Clock Mode Select. This signal selects the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

This pin should be static and not change following the negation of

PERSTN.

Table 1.3 PCI Express Interface Pins

Signal Type Name/Description

MSMBADDR[4:1]1IMaster SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1]2ISlave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

Table 1.4 SMBus Interface Pins (Part 1 of 2)

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 7 February 22, 2012

Notes

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

1. MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50.

2. SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77.

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P2RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 2

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P4RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 4

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 0 input

GPIO[3]1

1. GPIO pins 3, 4, 5, 6 are not available in the 19mm package.

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN1

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 1 input

GPIO[4]1I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN2

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 2 input

GPIO[5]1I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[6]1I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: GPEN

Alternate function pin type: Output

Alternate function: General Purpose Event (GPE) output

GPIO[8] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[9] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[10] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Table 1.5 General Purpose I/O Pins

Signal Type Name/Description

Table 1.4 SMBus Interface Pins (Part 2 of 2)

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 8 February 22, 2012

Notes

Signal Type Name/Description

CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be overridden by modifying the SCLK bit in each down-

stream port’s PCIELSTS register.

CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the P0_PCIELSTS register.

MSMBSMODE1

1. MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.

IMaster SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 KHz. This value

may not be overridden.

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside

PES24T3G2 and initiates a PCI Express fundamental reset.

RSTHALT2

2. RSTHALT is not available in the 19mm package.

IReset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES24T3G2 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the SWCTL register by an SMBus master.

SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T3G2 switch

operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0x7 Reserved

These pins should be static and not change following the negation of

PERSTN.

Table 1.6 System Pins

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Da ta I nput . This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG_TMS I JTAG Mod e. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

Table 1.7 Test Pins (Part 1 of 2)

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 9 February 22, 2012

Notes

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is

recommended to meet the JTAG specification in cases where the tester

can access this signal. However, for systems running in functional mode,

one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Signal Type Name/Description

REFRES0,

REFRES1 I/O Port 0 External Reference Resistors. Provides a reference for the Port 0

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from these pins to ground.

REFRES2,

REFRES3 I/O Port 2 External Reference Resistors. Provides a reference for the Port 2

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from these pins to ground.

REFRES4,

REFRES5 I/O Port 4 External Reference Resistors. Provides a reference for the Port 4

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from these pins to ground.

VDDCORE I Core VDD. Power supply for core logic.

VDDI/O I I/O VDD. LVTTL I/O buffer power supply.

VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V).

VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).

VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

power supply (1.0V).

VSS IGround.

Table 1.8 Power, Ground, and SerDes Resistor Pins

Signal Type Name/Description

Table 1.7 Test Pins (Part 2 of 2)

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 10 February 22, 2012

Notes

Pin Characte r istics

Note: Some input pads of the PES24T3G2 do not contain internal pull-ups or pull-downs.

Unused inputs should be tied off to appropriate levels. This is especially critical for unused control

signal inputs which, if left floating, could adversely affect oper ation. Also, any input pin left floating

can cause a slight increase in power consumption.

Function Pin Name Type Buffer I/O

Type Internal

Resistor1Notes

PCI Express

Interface PE0RN[7:0] I PCIe

differential2Serial Link

PE0RP[7:0] I

PE0TN[7:0] O

PE0TP[7:0] O

PE2RN[7:0] I

PE2RP[7:0] I

PE2TN[7:0] O

PE2TP[7:0] O

PE4RN[7:0] I

PE4RP[7:0] I

PE4TN[7:0] O

PE4TP[7:0] O

PERE F CLK N I HCSL Diff . Clo ck

Input Refer to Table 9

in the

PES24T3G2

Data Sheet

PEREFCLKP I

REFCLKM3I LVTTL Input pull-down

SMBus MSMBADDR[4:1]4I LVTTL Input pull-down

MSMBCLK I/O STI5pull-up on board

MSMBDAT I/O STI pull-up on board

SSMBADDR[5,3:1]

4I Input pull-up

SSMBCLK I/O STI pull-up on board

SSMBDAT I/O STI pull-up on board

General Pur-

pose I/O GPIO[10:0]6I/O LVTTL STI,

High Drive pull-up

System Pins CCLKDS I LVTTL Input pull-up

CCLKUS I Input pull-up

MSMBSMODE7I Input pull-down

PERSTN I STI

RSTHALT7I Input pull-down

SWMODE[2:0] I Input pull-down

Table 1.9 Pin Characteristics (Part 1 of 2)

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 11 February 22, 2012

Notes

Port Configuration

The PES24T3G2 operates as a 3-port switch with all ports having a x8 width, as shown in Figure 1.3.

Figure 1.3 PES24T3G2 Port Configuration

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I STI pull-up

JTAG_TDO O

JTAG_TMS I STI pull-up

JTAG_TRST_N I STI pull-up

SerDes Refer-

ence Resistors REFRES0 I/O Analog

REFRES1 I/O

REFRES2 I/O

REFRES3 I/O

REFRES4 I/O

REFRES5 I/O

1. Int ern al resis tor valu es und er typi cal ope rat ing con diti ons are 92K Ω for pull-up and 90K Ω for pull-down.

2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.

3. REFCLKM pin is not available in the 19mm package.

4. SMBus address pins are not available in the 19mm package.

5. Schmitt Trigger Input (STI).

6. GPIO pins 3, 4, 5, 6 are not available in the 19mm package.

7. MSMBSMODE and RSTHALT are not available in the 19mm package.

Function Pin Name Type Buffer I/O

Type Internal

Resistor1Notes

Table 1.9 Pin Characteristics (Part 2 of 2)

PES24T3G2 PCI to PCI

Bridge

PCI to PCI

Bridge

Dev. 2

PCI to PCI

Bridge

Dev. 4

Dev. 0

Port 0

V irtual PCI Bus

Port 2

x8 Port 4

IDT PES24T3G2 Device Overview

PES24T3G2 User Manual 1 - 12 February 22, 2012

Notes

PES24T3G2 User Manual 2 - 1 February 22, 2012

Chapter 2

Clocking, Reset and

Initialization

Clocking

The PES24T3G2 has a single differential reference clock input (PEREFCLKP/PEREFCLKN) that is

used internally to generate all of the clocks required by the internal switch logic and the SerDes. The

frequency of the reference clock input is set to 100MHz.

Note: There are no skew requirement between the reference clock inputs.

Initialization

A boot configuration vector consisting of the signals listed in Table 2.1 is sampled by the PES24T3G2

during a Fundamental Reset when PERSTN is negated. The boot configuration vector defines essential

parameters for switch operation. Since the boot configuration vector is sampled only during a Fundamental

Reset sequence, the value of signals which make up the boot configuration vector is ignored during other

times and their state outside of a Fundamental Reset has no effect on the operation of the PES24T3G2.

While basic switch operation may be configured using signals in the boot configuration vector , advanced

switch features require configuration via an external serial EEPROM. The external serial EEPROM allows

modification of any bit in any software visible register. See Chapter 5, SMBus Interfaces, for more informa-

tion on the serial EEPROM.

The external serial EEPROM and slave SMBus interface may be used to override the function of some

of the signals in the boot configuration vector during a Fundamental Reset. The signals that may be over-

ridden are noted in Table 2.1. The state of all of the boot configuration signals in Table 2.1 sampled during

the most recent Fundamental Reset may be determined by reading the SWSTS register.

Signal May Be

Overridden Description

CCLKDS I Common Clock Downstream. The assertion of this pin indicates

that all downstream ports are using the same clock source as that

provided to downstream devices.This bit is used as the initial value

of the Slot Clock Configuration bit in all of the Link Status Registers

for downstream ports. The value may be overridden by modifying

the SCLK bit in each downstream port’s PCIELSTS register.

CCLKUS I Common Clock Upstream. The assertion of this pin indicates that

the upstream port is using the same clock source as the upstream

device. This bit is used as the initial value of the Slot Clock Configu-

ration bit in the Link Status Register for the upstream port. The value

may be overridden by modifying the SCLK bit in the P0_PCIELSTS

MSMBSMODE1IMaster SMBus Slow Mode. The assertion of this pin indicates that

the master SMBus should operate at 100 KHz instead of 400 KHz.

This value may not be overridden.

Table 2.1 Boot Configuration Vector Signals

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 2 February 22, 2012

Notes

Reset

The PES24T3G2 defines four Conventional Reset categories: Fundamental reset, Hot Reset, Upstream

Secondary Bus Hot-Reset, and Downstream Secondary Bus Hot-Reset.

–A Fundamental Reset causes all logic in the PES24T3G2 to be returned to an initial state.

–A Hot Reset causes all logic in the PES24T3G2 to be returned to an initial state, but does not

cause the state of register fields denoted as “sticky” to be modified.

–An Upstream Secondary Bus Reset causes all devices on the virtual PCI bus to be hot reset

except the upstream port (i.e., upstream PCI to PCI bridge).

–A Downstream Secondary Bus Reset causes a hot reset to be propagated on the corresponding

external secondary bus link.

There are two sub-categories of Fundamental Reset: Cold reset and Warm reset. A Cold Reset occurs

following the PES24T3G2 being powered on and assertion of PERSTN. A Warm Reset is a Fundamental

Reset that occurs without removal of power.

Fundam en t al Reset

A Fundamental Reset may be initiated by any of the following conditions:

–A cold reset initiated by a power-on and the assertion of the PCI E xpress Reset (PERSTN) input

pin.

–A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power

is on.

–A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch

Control (SWCTL) register.

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside

PES24T3G2 and initiates a PCI Express fundamental reset.

RSTHALT2IReset Halt. When this signal is asserted during a PCI Express fun-

damental reset, PES24T3G2 executes the reset procedure and

remains in a reset state with the Master and Slave SMBuses active.

This allows software to read and write registers internal to the device

before normal device operation begins. The device exits the reset

state when the RSTHALT bit is cleared in the SWCTL register by an

SMBus master.

SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T3G2

switch operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0x7 Reserved

These pins should be static and not change following the negation of

PERSTN.

1. MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.

2. RSTHALT is not available in the 19mm package.

Signal May Be

Overridden Description

Table 2.1 Boot Configuration Vector Signals

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 3 February 22, 2012

Notes

When configured to operate in normal mode, the following reset sequence is executed.

1. Wait for the Fundamental Reset condition to clear (e.g., negati on of PE RSTN). Note that PERSTN

must be asserted for at least 100ms (Tpvperl) after the PES24T3G2 power supplies are stable, and

100µs (Tperst-clk) after the reference clock input is stable.

2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.1. If PERSTN was

not asserted, use the previously sampled boot configuration signal values (e.g., when a Funda-

mental Reset is the result of setting the Fundamental Reset (FRST) bit in the Switch Control

(SWCTL) register).

3. Examine the state of the sampled SWMODE[2:0] signals to determine the switch operating mode.

4. The PLL and SerDes are initialized (i.e., PLL/CDR reset and lock).

5. Link training begins. While link training is in progress, proceed to step 6.

6. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the SWSTS register is set.

7. If the switch operating mode is not a test mode, then the reset signal to the PCI Express stacks and

associated logic is negated but they are held in a quasi-reset state in whi ch the following actions

occur.

•All links enter an active link training state within 20ms of the clearing of the Fundamental Reset

condition.

•Within 100ms of the clearing of the Fundamental Reset condition, all of the stacks are able to

process configuration transactions and respond to these transactions with a configuration

request retry status completion. All other transactions are ignored.

8. The master SMBus operating frequency is determined.

The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is ini-

tialized to operate at 100 KHz rather than 400 KHz.

9. The slave SMBus is taken out of reset and initialized. The s lave SMBus address speci fied by the

SSMBADDR[5,3:1] pins is used.

10. The master SMBus is taken out of reset and initialized.

1 1. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then

the contents of the serial EEPROM are read and the appropriate PES24T3G2 registers are updated.

•If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link

State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using

the current link parameters.

•If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM

is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in

the SMBUSSTS register.

When serial EEPROM initialization completes or when an error is detected, the EEPROM D one

(EEPROMDONE) bit in the SMBUSSTS register is set. If the RSTHALT bit is set in the SWCTL reg-

ister, return to step 11. Otherwise, proceed to step 12.

12. If the Reset Halt (RSTHALT) bit is set in the SWCTL regis ter, all of the logic is held i n a reset state

except the master and slave SMBuses, the control/status registers, and the stacks which continue

to be held in a quasi-res et state and respond to configuration transactions with a retry. The device

remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external

agent may read and write any internal control and status registers and may access the external

serial EEPROM via the EEPROMINTF register.

13. Normal device operation begins.

The PCIe specification indicates that a device must respond to Configuration Request transactions

within 100 ms from the end of Conventional Res et (cold, warm, or hot). Additionall y, the PCIe specification

indicates that a device must respond to Configuration Requests with a Successful Completion within 1.0

second after Conventional Reset of a device. The reset sequence above guarantees that the PES24T3G2

will be ready to respond successful ly to configuration request within the 1.0 second period as long as the

serial EEPROM initialization process completes within 200 ms. During EEPROM initialization, the

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 4 February 22, 2012

Notes

PES24T3G2 responds to a Configuration Request with Configuration-Request-Retry-Status Completion.

Under normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a

Master SMBus operating frequency of 100 KHz.

Serial EEPROM initialization may cause writes to register fields that initiate side effects, such as link

retraining. These side effects are initiated at the point where the write occurs. Therefore, serial EEPROM

initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these

side effects.

A warm reset initiated by a configuration request writing a one to the Fundamental Reset (FRST) bit in

the Switch Control (SWCTL) register always results in the PES24T3G2 returning a Successful Completion

to the requester before the warm reset process begins. The PES24T3G2 provides a reset output signal for

each downstream port implemented as a GPIO alternate function. When a Fundamental Reset occurs, all

of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system

designer should use a pull-down on these signals if they are used as reset outputs.

The operation of a Fundamental Reset with serial EEPROM initialization (i.e., S WMODE[2:0] = 0x1) is

illustrated in Figure 2.1.

Figure 2.1 Fundamental Reset with Serial EEPROM initialization

The operation of a Fundamental Reset using RSTHALT is illustrated in Figure 2.2.

REFCLK*

Vdd

PERSTN

SerDes

Master SMBus

Slave SMBus

Tpvperl (100ms)

CDR Reset & Lock Ready for Normal Operation

Ready for Normal Operation

ReadyIdle Serial EEPROM Initializ ation

~70

20 ms max.

Stacks held in Quasi-Reset Mode

Li nk Training

50 µs max

PLL Lock

Tperst-clk

(100µs)

Notes:

1) Reference Clock (REFC LK) not shown to scale.

2) The PES24T3G2 requires a minimum time for Tperst-clk of 1µs. The PES 24T3G2 requires a minimum time for Tpvperl of 1ms.

3) In a system, the values of Tpvperl and Tperst-clk depend on the mech anical form factor in which the PES24T3G2 is used. For example,

the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms .

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 5 February 22, 2012

Notes

Figure 2.2 Fundamental Reset using RSTHALT to keep device in Quasi-Reset state

Hot Reset

A hot reset may be initiated by any of the following conditions:

–Reception of TS1 ordered-sets on the upstream port indicating a hot reset.

–Data link layer of the upstream port transitions to the DL_Down state.

–Writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register.

The initiation of a hot reset due to the data l ink la yer of the upstream port transitioni ng to the DL_Down

state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control

(SWCTL) register. Other hot reset conditions are unaffected by this bit.

When a hot reset occurs, the following sequence is executed.

1. Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets

with the hot reset bit set.

2. All of the logic associated with the PES24T3G2 except the PLLs, SerDes, master SMBus interface,

and slave SMBus interface is reset.

3. All registers fields in all registers, except those denoted as “sticky” or Read and W rite when Unlocked

(i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is preserved

across a hot reset.

4. Link training begins. While link training is in progress, proceed to step 6.

5. The PCI Express stacks and associated logic are held in a quasi-reset state in which the following

actions occur.

•All links enter an active link training state within 20ms of the clearing of the hot reset condition.

•Within 100ms of the clearing of the Hot Reset condition, all of the stacks are able to process

configuration transactions and respond to these transactions with a configuration request retry

status completion. All other transactions are ignored.

6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and

the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control

(SWCTL) register, the contents of the serial EEPROM are read and the appropriate PES24T3G2

registers are updated.

SerDes

Slave SMBus

CDR Reset & Lock Ready for Normal Operation

Ready for Normal Operation

~70

20 ms max.

Stacks held in Quasi-Reset Mode

Link Training

PLL Lock

RSTHALT RSTHALT bit in SWCTL register is set

RSTHALT bit in SWCTL cleared (i.e., by slave SMBus)

REFCLK*

Vdd

PERSTN

Tpvperl (100ms)

Tperst-clk

(100us)

Notes:

1) Reference Clock (REFCLK ) not shown to scale.

2) The PES24T3G2 requires a minimum time for Tperst-clk of 1µs. The PES24T3G2 requires a minimum time for Tpvperl of 1ms.

3) In a system, the values of Tpvperl and Tperst-clk depend on the mec hanical form factor in which the PES24T3G2 is u sed. For example,

the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 6 February 22, 2012

Notes

•If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link

State 0 (PHYLSTATE 0) register, li nk retraining is initiated on the corresponding port using the

current link parameters.

•If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM

is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in

the SMBUSSTS register.

•When serial EEPROM initialization completes or when an error is detected, the DONE bit in the

SMBUSSTS register is set.

7. If the Reset Halt (RSTHALT) bit is set in the SWCTL regis ter, all of the logic is held i n a reset state

except the master and slave SMBuses. The RSTHALT bit is only set if serial EEPROM initialization

is enabled in step 6.

8. Normal device operation begins.

The operation of the slave SMBus interface is unaffected by a hot reset. Using the slave SMBus to

access a register that is reset by a hot reset causes zero to be returned on a read and written data to be

ignored on writes. A hot reset initiated by the writing of a one to the Hot Reset (HRST) bit in the Switch

Control (SWCTL) register always results in the PES24T3G2 returning a completion to the requester before

the hot reset process begins. Additionally, the upstream link is fully retrained (i.e., the upstream LTSSM

transitions to the Detect state).

Upstream Seco nd ary Bus Res et

An Upstream Secondary Bus Reset may be initiated by the following condition:

–A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (i.e., port 0)

Bridge Control Register (BCTL).

When an Upstream Secondary Bus Reset occurs, the following sequence is executed.

1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with

the hot reset bit set.

2. All registers fields in all registers associated with downstream ports, except those denoted as “sticky”

or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields

denoted as “sticky” or RWL is unaffected by an Upstream Secondary Bus Reset.

3. All TLPs received from downstream ports and queued in the PES24T3G2 are discarded.

4. Logic in the stack, application layer, and switch core associated with the downstream ports are

gracefully reset.

5. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge

Control Register (BCTL).

6. Normal downstream port operation begins.

The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and

Type 0 configuration read and write transactions that target the upstream port complete normally. During an

Upstream Secondary Bus Reset, all TLPs destined to the secondary side of the upstream port’s PCI-to-PCI

bridge are treated in an undefined manner. The user should ensure no TLPs are sent to the secondary side

of the upstream port’s PCI-to-PCI bridge until the SRESET bit in the BCTL register is cleared.

The operation of the slave SMBus interface is unaffected by an Upstream Secondary Bus Reset. Using

the slave SMBus to access a register that is reset by an Upstream Secondary Bus Reset causes the

Down stream Second ary Bus Reset

A Downstream Secondary Bus Reset may be initiated by the following condition:

–A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s (i.e., port 0)

Bridge Control Register (BCTL).

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 7 February 22, 2012

Notes

When a Downstream Secondary Bus Reset occurs, the following sequence is executed.

1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are

transmitted.

2. All TLPs received from corresponding downstream port and queued in the PES24T3G2 are

discarded.

3. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge

Control Register (BCTL).

4. Normal downstream port operation begins.

The operation of the upstr eam port is unaf fected by a Downstream Secondary Bus Reset. The operation

of other downstream ports is unaffected by a Downstream Secondary Bus Reset. During a Downstream

Secondary Bus Reset, Type 0 configuration read and write transactions that target the downstream port

complete normally. During a Downstream Secondary Bus Reset, all TLPs destined to the secondary side of

the downstream port’s PCI-to-PCI bridge are treated as unsupported requests. The operation of the slave

SMBus interface is unaffected by a Downstream Secondary Bus Reset.

Downstream Port Reset Outputs

Individual downstream port reset outputs (P1RSTN , P2RSTN, P3RS TN, P4RSTN, P 5RSTN, P6RSTN,

and P7RSTN) are provided as GPIO pin alternate functions. Following a Fundamental Reset, all of the

GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system designer

should use a pull-down on these signals if they are used as reset outputs.

The PES24T3G2 ensures through hardware that the minimum PxRSTN assertion pulse width is no less

than 200 µs.

Downstream port reset outputs can be configured to operate in one of two modes. These modes are

power enable controlled reset output and power good controlled reset output. The downstream port reset

output mode is determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration Control

(HPCFGCTL) register.

Power Enable Controlled Reset Output

In this mode, a downstream port reset output state is controlled as a side effect of slot power being

turned on or off. The operation of this mode is illustrated in Figure 2.3. A downstream port’s slot power is

controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register

Figure 2.3 Power Enable Controlled Reset Output Mode Operation

While slot power is disabled, the corresponding downstream port reset output is asserted. When slot

power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and

then power to the slot is enabled and the corresponding downstream port reset output is negated. The time

between the assertion of the PxPEP signal and the negation of the PxRSTN signal is controlled by the

value in the Slot Power to Reset Negation (PWR2RST) field in the HP CFGCTL register.

While slot power is enabled, the corresponding downstream port reset output is negated. When slot

power is disabled by writing a one to the PCC bit, the corresponding downstream port reset output is

asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal and the

negation of the PxPEP signal is controlled by the value in the R eset Negation to Slot Power (RST2PWR)

field in the HPCFGCTL register.

PxPEP

PxRSTN

PWR2RST

RST2PWR

IDT Clocking, Reset and Initialization

PES24T3G2 User Manual 2 - 8 February 22, 2012

Notes

Power Good Controlled Reset Output

As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is

controlled as a side effect of slot power being turned on or of f. However, the timing in this mode depends on

the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 2.4.

Figure 2.4 Power Good Controlled Reset Output Mode Operation

The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that

when power is enabled, the negation of the corresponding port reset output occurs as a result of and after

assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the

PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to

Reset Negation (PWR2RST) field in the HPCFGCTL register.

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset

output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal

and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power

(RST2PWR) field in the HPCFGCTL register.

If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is

detected (i.e., PxPWRGDN is negated), then the corresponding port reset output is immediately asserted.

Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profile’s power level

invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter

time interval may implement this functionality external to the PES24T3G2.

PxPEP

PxPWRGDN

TPWR2RST

PxRSTN

TRST2PWR

Notes

PES24T3G2 User Manual 3 - 1 February 22, 2012

Chapter 3

Link Operation

Introduction

Link operation in the PES24T3G2 adheres to the PCI Express 2.0 Base Specification, supporting

speeds of 2.5 Gbps and 5.0 Gbps. The PES24T3G2 contains three x8 ports. The default link width of each

port is x8 and the SerDes lanes are statically assigned to a port. A full link retrain is defined as retraining of

a link that transitions through the Detect LTSSM state.

Polarity Inv ersion

Each port of the PES24T3G2 supports automatic polarity inversion as required by the PCIe specifica-

tion. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its

data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for

inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane

automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is

possible for some lanes of link to be inverted and for others to not be inverted.

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES24T3G2 offers limited

support for the automatic lane reversal feature outlined in the PCIe specification. Lane reversal mapping for

the configuration supported by the PES24T3G2 is illustrated in Figure 3.1.

IDT Link Operation

PES24T3G2 User Manual 3 - 2 February 22, 2012

Notes

Figure 3.1 Merged Port Lane Reversal

Link Width Negotiation

The PES24T3G2 supports the optional link variable width negotiation feature outlined in the PCIe 2.0

specification. The actual link width is determined dynamically during link training. Ports limited to a

maximum link width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width.

The current negotiated width of a link may be determined from the Negotiated Link Width (NLW) field in

the corresponding port’s PCIe Link Status (PCIELSTS) register.

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 0

lane 1

lane 2

lane 3

lane 4

lane 5

lane 6

lane 7

(a) x8 Port without lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 7

lane 6

lane 5

lane 4

lane 3

lane 2

lane 1

lane 0

(b) x8 Port with lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 0

lane 1

lane 2

lane 3

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2 lane 3

lane 2

lane 1

lane 0

(d) x4 Port with lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 0

lane 1

(e) x2 Port without lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 1

lane 0

(f) x2 Port with lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 0

(g) x1 Port without lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24T3G2

lane 0

(h) x1 Port with lane reversal

IDT Link Operation

PES24T3G2 User Manual 3 - 3 February 22, 2012

Notes

The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCA P)

the REGUNLOCK bit is s et in the SWCTL register. Modification of this field allows the maximum link width

of the port to be configured. The new link width takes effect the next time full link training occurs.

To force a li nk width to a smaller w idth than the default value, the MAXLNKWDTH field could be config-

ured through Serial EEPROM initialization and full link retraining forced by setting the Full Link Retrain

(FLRET) bit in the PHYLSTATE0 register. The value programmed into the MAXLNKWDTH field should not

exceed the port’s width (x4 for the PES24T3G2). When the MAXLNKWDTH field of a port’s PCIELCAP

link width (i.e., default value of MAXLNKWDTH ). For example, a port which is initially set to x4 Gen2 must

not have the value of the MAXLNKWDTH programmed to x8. If the MAXLNKWDTH field were to be incor-

rectly programmed to x8, the port would operate at x4.

When a port is disabled, all SerDes lanes associated with that port are turned off. Unused lanes associ-

ated with a x4 port are put into a low power state. When only four lanes associated with a x8 port are used,

the upper four lanes are turned off. When fewer than four lanes associated with a x8 port are used, the

upper four lanes are turned off and the unused lower lanes are put into a low power state.

Dynamic Link Width Reconfiguration

The PCI Express 2.0 specification includes support for dynamic upconfiguration of link widths. This

optional capability allows both components of a link to dynamically downconfigure and upconfigure links

based on implementation specific criteria such as power savings, link bandwidth requirements, or link reli-

ability problems. As an example, a link that initial ly does a full link train to x4 may be dynamically downcon-

figured to x1 in order to save power when there is little traffic on the link. As traffic increases, the link may be

dynamically upconfigured to its initial link width of x4. Also, the link width may be downconfigured if a partic-

ular lane is determined to be unreliable.

With dynamic link width upconfiguration, the system designer can choos e to connect components with

enough lanes to handle worst case bandwidth requirements, yet not waste power when the link is not fully

utilized. This capability offers an additional mechanism for link power reduction on top of the traditional

ASPM link states (L0s, L1, etc.).

Dynamic upconfiguration and downconfiguration is done on a per-link basis, and does not result in the

link going into a D L_Down state. A link can be upconfigured up to the negotiated link width set after a full

link train. For example, a link that trained to a width of x2 after a full link train cannot be upconfigured to a

width above x2. A link can be downconfigured down to x1. When a link is downconfigured to a smaller

width, inactive lanes are kept in Electrical Idle with their receiver terminations enabled. These lanes

continue to be associated with the downconfigured port’s LT SSM.

In order for upconfiguration to occur successfully, both of the link components must support it. Further-

more, the PCIe specification recommends that a link c omponent not initiate downconfi guration unless the

link partner supports link upconfiguration, except for link reliability reasons. The capability to upconfigure a

link is transmitted among components using the in-band TS2 ordered set.

When downconfiguration or upconfiguration of a link oc curs, one of the components on the link i nitiates

the process, while the other component responds to the process. The PCIe specification indicates that both

of these capabilities are optional. Software may be notified of link width re-configuration via the link band-

width notification mechanism described in the PCIe 2.0 specification. This mechanism is enabled by setting

the Link Bandwidth Management Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch

downstream ports.

Dynamic Lin k Width R e configurat ion Support in the PES2 4T 3G 2

The PES24T3G2 supports dynamic link width upconfiguration and downconfiguration in response to link

partner requests.

IDT Link Operation

PES24T3G2 User Manual 3 - 4 February 22, 2012

Notes

The PES24T3G2 does not initiate autonomous link width upconfiguration and downconfiguration of

links, except for downconfiguration due to link reliability reasons. Therefore, the Hardware Autonomous

Width Disable (HAWD) bit in the port’s PCIELCTL register has no effect and is hardwired to 0x0. Addition-

ally, the PES24T3G2 port’s never set the ‘Autonomous Change’ bit in the training sets exchanged with the

link partner during link training. A Downstream port link partner may autonomously change link width. When

this occurs, the PES24T3G2 downstream port sets the Link Autonomous Bandwidth Status (LABWSTS) bit

in the PCIELSTS register.

Link Speed Negotiation

The PCIe 2.0 specification introduces support for 5.0 Gbps data rates per lane (Gen2), in addition to the

2.5 Gbps data rates (Gen1) mandated in previous versions of the specification. Per the PCIe 2.0 specifica-

tion, all lanes of a link must operate at the same data rate. During full link training, links initially operate at

2.5 Gbps. Once the LTSSM on both components of the link reaches the L0 state, the link speed may be

upgraded to 5.0 Gbps if this capability is advertised and desired by both components. The process of

upgrading the link speed does not result in a DL_Down state.

It is the responsibility of the upstream component of the link (i.e., switch downstream ports) to keep the

link at the target link speed or at the highest common speed supported by both components of the link. In

addition, either link component may request a link s peed change due to software requests or l ink reliabil ity

reasons (i.e., speed downgrade). Downstream components are further permitted to request link speed

changes due to autonomous hardware initiated mechanisms.

A component must only initiate a link speed change when it knows that its link partner supports the

target speed via prior exchange of Training Sets. As stated before, Gen2 support is optional while Gen1

support is mandatory. Also, a component may advertise supported link speeds via the Recovery state,

without necessarily changing the link speed.

If neither component in the link advertises support for Gen2, then the link remains operating in Gen1

speed. If one of the components decides to adv ertise support for Gen2 (i.e., software sets the Target link

Speed = Gen2), then this component wil l advertise its support for Gen2 speed via the R ecovery state. The

link will continue to operate in Gen1 speed since only one of the components has advertised support for the

higher speed. If one component has advertised support for Gen1 and Gen2, and the other has advertised

support for Gen1 only, then the link w ill remain operating in Gen1 speed until the lesser-speed component

decides to:

–Advertise support for Gen2 via the Recovery state without modifying the link speed. The link

remains operating at Gen1 speed.

–Transition the link speed to Gen2 via the Recovery.Speed state. The link will operate at Gen2

speed. In this case, the advertisement of Gen2 speed by both components is done implicitly in the

Recovery substates entered while modifying the link speed.

Link Speed Ne gotiation in the PES24T3G2

The PES24T3G2 ports support per lane data rates of 5.0 Gbps and 2.5 Gbps. The highest data rate of

each link is determined dynamically, and depends on the following factors:

–Maximum link data rate supported by both components of the link

–The Target Link Speed s et via the Link Control 2 Register (PCIELCTL2)

–The Hardware Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register

–The reliability of the link at 5.0 Gbps

By default, the Target Link Speed (TLS) of each port is set to 5.0 Gbps. Therefore, the PES24T3G2

ports advertise support for 5.0 Gbps during the link training process via training-sets. After a fundamental

reset, each port link trains to the L0 state at 2.5 Gbps. If the Target Link Speed indicates 5.0 Gbps (default

value), the PHY LTSSM automatically initiates link speed upgrade to 5.0 Gbps using the link speed change

mechanism described in the PCIe 2.0 specification. This occurs regardless of the setting of the Hardware

Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register.1

IDT Link Operation

PES24T3G2 User Manual 3 - 5 February 22, 2012

Notes

Note that in this case the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register

of the downstream port is not set, since the initial link speed upgrade was not caused by a software directed

link retrain or by link reliability issues. The same behavior applies after full link retr ain (i.e., when the LTSSM

transitions through the ‘Detect’ state). The current link speed of each port is reported via the Current Link

Speed (CLS) field of the port’s Link Status Register (PCIELSTS).

When a link speed upgrade operation fails, the PHY LTSSM reverts back to the speed before the

upgrade (i.e., 2.5 Gbps) and does not autonomously initiate a subsequent link speed upgrade. The PHY

continues to respond to link partner requests for link speed upgrade or to link speed upgrades triggered by

the software setting the Link Retrain (LRET) bit in the PCIELCTL register.

The PES24T3G2 ports do not autonomously change speed. As a result, the PES24T3G2 ports never

set the ‘Autonomous Change’ bit in the training sets exchanged with the link partner during link training.

Still, a link partner connected to a PES24T3G2 downstream port may autonomously change link speed.

When this occurs, the PES24T3G2 downstream port sets the Link Autonomous Bandwidth Status

(LABWSTS) bit in the P CIELSTS register. A s ystem designer may limit the maxi mum speed at which each

port operates by changing the target link speed v ia software or EEPROM and forcing link retraining. Refer

to section Software Management of Link Speed below for further details.

Software M ana gement of Link Speed

Software can interact with the link control and status registers of each port to set the link speed and

receive notification of link speed changes. This gives software the capability to choose the desired link

speed based on system specific criteria. For example, depending on the traffic load expected on a link, soft-

ware can choose to downgrade link speed to 2.5 Gbps in order to reduce power on a low-traffic link and

later upgrade the link to 5.0 Gbps when the bandwidth is required. Software may also choose to change the

link speed due to link reliabili ty reasons (i.e., a link that has reliability problems at 5.0 Gbps may be down-

graded to 2.5 Gbps).

As mentioned above, the Target Link Speed (TLS) field of the Link Control 2 Register (PCIELCTL2) sets

the preferred link speed. By default, the Target Link Speed of each port is set to 5.0 Gbps.

In order to change link speed, software must write to the TLS field of the port’s PCIELCTL2 register and

subsequently force a link retrain by writing to the Link Retrain (LRET) bit of the Link Control (PCIELCTL)

in the PCIe specification. This mechanism is enabled by setting the Link Bandwidth Management Interrupt

Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream ports.

When the link speed i s changed (i.e., due to reliability reasons or by virtue of s oftware setting the TLS

field and retraining the link), the downstream port’s LTSSM sets the Link Bandwidth Management Status

(LBWSTS) bit in the PCIELSTS register. Software can verify the link speed by reading the Current Link

Speed (CLS) field of the port’s Link Status Register (PCIELSTS). Note that to force link speed to a value

other than the default value, the TLS field could be configured through Serial EEPROM initialization and full

link retraining forced. Finally, note that the Hardware Autonomous Speed Disable (HASD) bit has no effect

on link speed changes triggered by modifications of the TLS field followed by setting the LRET bit.

Link Reliability

An unreliable link is a link that exhibits recurrent errors detected in the physical layer. These errors

include bit-flipping due to electrical problems, SerDes transmitter and receiver problems, lack of synchroni-

zation between transmitter and receiver, etc. All of these usually result in LCRC failures at the data-link

layer. In severe cases, link reliability problems cause the link to be automatically retrained (refer to section

Link Retraining on page 3-7). As the link speed increases (i.e., Gen2 in PCI Express 2.0), the link is more

susceptible to link errors due to tighter margins in the data window.

1. Initial link speed upgrade is not considered an autonomous link speed upgrade, since it is caused by the default

setting of the Target Link Speed field in the PCIELCTL2 register.

IDT Link Operation

PES24T3G2 User Manual 3 - 6 February 22, 2012

Notes

Software may assess the reliability of the link using the PCIe Advanced Error Reporting (AER) structure

or other means offered by the switch or its link partners. In response to an unreliable link, software can

manage the link speed and link width in order to improve the r eliability of the link. For additional information,

refer to section Software Management of Link Speed on page 3-5.

Auto no mous Link Reliabili ty Management

As mentioned above, an unr eliable link exhibits recur rent errors. When the rate of errors is very high, the

LTSSM will likely be unable to communicate with the link partner and automatically revert to the lowest

possible link speed (i.e., 2.5 Gbps). The mechanism to detect severe link errors and downgrade speed is

part of the PCIe 2.0 specification.

However, if the rate of link errors is low enough to keep the LTSSM operating in Gen2 mode, but high

enough that it adversely affects link bandwidth or compromises link stability (i.e., by constantly retraining

the link through the Recovery state), none of the mechanisms in the PCIe 2.0 specification can detect and

react appropriately.

As an example, a bit error rate of 1.0E-6 in Gen2 mode (i.e., 1 error every 200 usec) may result in a

large number of TLP replays on the link, which impact link bandwidth and potentially result in link retrain

events that move the link repeatedly through the Recovery state. A large number of link retrains not only

make the link bandwidth unpredictable, but can potentially bring the link down, resulting in system insta-

bility.

In order to address this, a mechanism is desired that monitors link errors such that when they reach a

programmable rate (i.e., 1.0E-6 as the example above), the mechanism is capable of autonomously down-

grading link speed, potentially enhancing link and bandwidth stability. The Autonomous Link Reliability

Management logic in the PES24T3G2 i s such a mechanism. E ach PES24T3G2 port has the capability to

autonomously detect link unreliability and react by downgrading the link speed to 2.5 Gbps.

This capability is enabled by setting the Enable (EN) bit of the Autonomous Link Reliability Control

mechanism is disabled. When enabled, the Autonomous Link Reliability logic monitors the rate of errors in

the link. When the rate of errors crosses an specified threshold, the Phy’s LTSSM downgrades the link

speed to 2.5 Gbps, removes support for 5.0 Gbps from its advertised data rate in training sets, and remains

in this downgraded data rate until the link fully retrains or the Link R etrain (LRET) field of the PCI Express

Link Control (PCIELCTL) register is set, when the target link speed is 5.0 Gbps.

The Autonomous Link Reliability Management logic is capable of monitoring two types of link error

conditions: individual bit errors (i.e., LCRC errors) or link state errors (i.e., Phy LTSSM transitions through

the Recovery state). Only one of these type of errors may be monitored at a time. The type of error moni-

tored is selected by programming the Link Error T ype (LET) field in the ALRCTL register. A user who wishes

to count all LCRC errors (which don’t neces sarily resu lt in link retraining) can program the LET field appro-

priately. A user who wishes to count link retraining events caused by link errors can program the LET field to

LTSSM Recovery transitions.1

As mentioned above, when the rate of errors crosses an specified threshold, the Phy’s LTSSM down-

grades the link speed. The threshold is programmed via the Autonomous Link Reliability Error Rate

Threshold (ALRERT) register. This register contains two fields: Error Threshold (ERRT) and Monitoring

Period (PERIOD). The PERIOD field is programmed in units of micro-seconds. The Autonomous Link Reli-

ability logic determines that a link is unreliable when it detects ERRT errors in PERIOD time. When this

occurs, the LTSSM downgrades the link speed to 2.5 Gbps2 and sets the Unreliable Link Detected (ULD)

bit in the ALRSTS register3. Additionally, the LTSSM sets the Link Bandwidth Management Status

(LBWSTS) bit in the PCI Express Link Status (PCIELSTS) register.4

1. Note that it is only possible to count link errors that cause the PES24T3G2 port to initiate a link transition to

Recovery. Link errors which cause the link partner to initiate entry into the Recovery state are not counted.

2. This requires that the PHY LTSSM change its advertisement of supported link speeds to 2.5 Gbps only.

3. The ULD bit is a status bit set by hardware. Once set, it will remain set until cleared by software. Hardware

never clears the ULD bit.

IDT Link Operation

PES24T3G2 User Manual 3 - 7 February 22, 2012

Notes

Once the link speed is downgraded, the link speed will remain at 2.5 Gbps until the link fully retrains (i.e.,

the PHY LTSSM transitions through the Detect state) or the LRET bit is set in the PCIELCTL register, with a

target link speed of 5.0 Gbps. If the link partner requests to upgrade the link speed (i.e., via the Recovery

state), the PHY LT SSM enters the Recovery state but the link speed remains at 2.5 Gbps.

The user may determine the current error number and monitoring period counts by reading the Error

Number Count (ENCNT) and Monitoring Period Count (MPCNT) fields in the Autonomous Link Reliability

Count (ALRCNT) register1. The MPCNT value is in units of micro-seconds. When the monitoring period

count (MPCNT) reaches the monitoring period (PERIOD field in the ALRERT register), hardware resets the

ENCNT and MPCNT fields to their initial value and re-starts both counts. These counts are also reset when

a full-link retrain occurs or when the LRET bit in the PCIELCTL register is set.

When a link is determined to be unreliable (i.e., ULD bit set in the ALRSTS register), the error number

count and monitor period counts stop (ENCNT and MPCNT fields are not reset and keep their value

unchanged). The user may read these fields to determine the error count and the monitoring period count at

which the link was determined to be unreliable.2 To re-enable the mechanism, the user must clear the

enable bit (EN) in the ALRCTL register, then clear the ULD bit in the ALRSTS register, and then set the EN

bit again.

The Autonomous Link Reliability mechanis m is not affected by the state of the Hardware Autonomous

Speed Disable (HAS D) bit in the PC I Express Link Control 2 (PCIELCTL2) register, since this bit does not

apply to speed changes caused by link reliability issues. Additionally , note that when the link speed is down-

graded by the ALR mechanism, the Link Bandwidth Management Status (LBWSTS) bit is set in the PCI

Express Link Status (PCIELSTS) register of downstream ports. This may in turn cause an interrupt to be

sent upstream when the Link Bandwidth Management Interrupt Enable (LBWINTEN) bit is set in the PCI

Express Link Control (PCIELCTL) register.

Link Retraining

Per the PCIe 2.0 specification, link retraining can be done autonomously in response to link problems

(i.e., repeated TLP replay attempts) or as a result of software setting the li nk retrain (LRET) bit in the P CI

Express Link Control (PCIELCTL) register. Writing a one to the Link Retrain (LRET) bit in the upstream

port’s PCI Express Link Control (PCIELCTL) register when the REGUNLOCK bit is set in the SWCTL

Recovery state.

Writing a one to the Link Retrain (LRET) bit in a downstream port’s PCI Express Link Control

(PCIELCTL) register regardless of the REGUNLOCK bit state in the SWCTL register forces the down-

stream PCIe link to retrain. When this oc curs, the LTSSM transitions directly to the Recovery state. Writing

a one to the Full Link Retrain (FLRET) bit in the Phy Link State 0 (PHYLSTSE 0) register of any port forces

that port’s PCIe link to retrain. When this occurs, the LTSSM transitions directly to the Detect state.

Link retraining does not result in the link going down, unless the LTSSM transitions through the Detect

state in its retraining attempt. The speed of the link is not necessarily changed as a result of link retraining.

A link that operates at 5.0 Gbps will continue to operate at that speed if the link retraining attempt is

successful at that speed. Otherwise, the link speed is changed to 2.5 Gbps.

When link retraining results in the speed of the link being downgraded from 5.0 Gbps to 2.5 Gbps, the

Link Bandwidth Management Status (LBWSTS) bit is set in the PCI Express Link Status (PCIELSTS)

partner requests a link speed upgrade 3, software sets the LRET bit in the PCIELCTL register, or the link is

fully retained via the FLRET bit in the PHYLSTATE0 register . Refer to section Link Speed Negotiation in the

4. Note that per the PCIe 2.0 specification, the LBWSTS bit is not set if the link transitions through the DL_Down

state.

1. Note that these counts are active even when the ALR mechanism is disabled. A user may read these counts to

monitor link reliability, without enabling the ALR mechanism to reduce link speed. Finally, note that the ALR mech-

anism must be enabled in order for the ULD bit to get set.

2. When a link is determined to be unreliable, the error count (ENCNT) field will match the value of the error

threshold (ERRT).

IDT Link Operation

PES24T3G2 User Manual 3 - 8 February 22, 2012

Notes

PES24T3G2 on page 3-4. When the speed of the link is downgraded as a result of link retraining, the PHY

LT SSM remains at the downgraded speed until the link partner requests a link speed upgrade or software

sets the Link Retrain (LRET) bit in the PCIELCTL register.

Link Down

When a link goes down, all TLPs received by that port and queued in the switch are discarded and all

TLPs received by other ports and destined to the port whose link is down are treated as Unsupported

Requests (UR). While a downstream link is down, it is possible to perform configuration read and write

operations to the PCI-P CI bridge associated with that link. When a link comes up, flow control credits for the

configured size of the IFB queues are advertised. A link down condition on a downstream port’s link may

cause the Surprise Down Error Status (SDOENERR) bit to be set in the port’s AER Uncorrectable Error

Status (AERUES) register. The conditions under which surprise down is reported are described in Section

3.2.1 of the PCIe 2.0 Specification.

Slot Power Limit Support

The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream

switch port or root port to the upstream port of a connected device or switch.

Upst ream Port

When a Set_Slot_Power_Limit message is received by the upstream sw itch port, then the fields in the

message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port:

–Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale

(CSPLS) field.

–Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value

(CSPLV) field.

Downstream Port

A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following

events occur:

–A configuration write is performed to the corresponding P CIESCAP register when the link associ-

ated with the downstream port is up.

–A link associ ated with the dow nstream port transitions from a non-operational state to an opera-

tional (i.e., up) state.

Link States

The PES24T3G2 supports the following link states

–L0

•Fully operational link state

–L0s

•Automatically entered low power state with shortest exit latency

–L1

•Lower power state than L0s

•May be automatically entered or directed by software by placing the device in the D3hot state

–L2/L3 Ready

•The L2/L3 state is entered after the acknowledgement of a PM_Turn_Off Message.

•There is no TLP or DLLP communications over a link in this state.

–L3

•Link is completely unpowered and off

–Link Down

3. If enabled, the Autonomous Link Reliability mechanism described in section 8.7.1 may keep the link speed at

2.5 Gbps in spite of link partner requests to upgrade the link speed.

IDT Link Operation

PES24T3G2 User Manual 3 - 9 February 22, 2012

Notes

•A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the

LTSSM Detect, Polling, Configuration, Disabled, Loopback and Hot-Reset states.

Figure 3.2 PES24T3G2 ASPM Link Sate Transitions

Active State Power Management

The operation of Active State P ower Management (ASPM) is orthogonal to power management. Once

enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi-

tions are initiated by hardware without software involvement. The PES24T3G2 ASPM supports the required

L0s state as well as the optional L1 state. The L0s Entry Timer (L0ET) field in the PCI Power Management

Proprietary Control (PMPC) register controls the amount of time L0s entry conditions must be met before

the hardware transitions the link to the L0s state.

The upstream switch port has the following L0s entry conditions.

–The receive lanes of all of the switch dow nstream ports which are not i n a low power state (i.e.,

D3) and whose link is not down are in the L0s state.

–The switch has no TLPs to transmit on the upstream port or there are no available flow control

credits to transmit a TLP.

–There are no DLLPs pending for transmission on the upstream port.

The downstream switch ports have the following L0s entry conditions.

–The receive lanes of the switch upstream port are in the L0s state.

–The switch has no TLPs to transmit on the downstream port or there are no available flow control

credits to transmit a TLP.

–There are no DLLPs pending for transmission on the downstream port.

The L1 Entry Timer (L1ET) field in the PCI Power Management Proprietary Control (PMPC) register

controls the amount of time L1 entry conditions must be met before the hardware transitions the link to the

L1 state. If these conditions are met and the link is in the L0 or L0s state, the hardware will request a transi-

tion to the L1 state from its link partner. Note that L1 entry requests are only made by the PES24T3G2

upstream port. If the link partner acknowledges the transition, the L1 state is entered. O therwise, the L0s

state is entered. Note that the upstream switch port will only request entry into the L1 state when all of the

downstream ports which are not in a low power state (i.e., D3) and whose link is not down are in the L1

state.

L0s L1

L2/L3 Ready

Link Down

Fundamental Reset

Hot Reset

Etc.

IDT Link Operation

PES24T3G2 User Manual 3 - 10 February 22, 2012

Notes

Link Status

Associated with each port is a Port Link Up (PxLINKUPN) status output and a Port Activity (PxAC-

TIVEN) status output. These outputs are provided on I/O expander 4. See section I/O Expanders on page

5-7 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.

The PxLINKUPN and PxACTIVEN status outputs may be used to provide a visual indication of system

state and activity or for debug. The PxLINKUPN output is asserted when the PCIe data link layer is up (i.e.,

when the LTSSM is in the L0, L0s, L1, or recovery states). When the data link layer is dow n, this output is

negated. The PxACTIVEN output is asserted whenever any TLP, other than a vendor defined mess age, is

transmitted or received on the corresponding port’s link. Whenever a PxACTIVEN output is asserted, it

remains asserted for at least 200 ms. Since an I/O expander output may change no more frequently than

once every 40 ms, this translates into five I/O expander update periods.

De-emphasis Negotiation

The PCI Express 2.0 specification requires that components support the following levels of de-

emphasis, depending on the link data rate:

–2.5 Gbps (Gen1): De-emphasis = -3.5dB

–5.0 Gbps (Gen2): De-emphasis = -3.5dB or -6.0dB

When operating at 5.0 Gbps, the de-emphasis is selected by programming the Selectable De-emphasis

(SDE) field in the PCI Link Control 2 Register (PCIELCTL2). The chosen de-emphasis for the link is the

result of a negotiation between the components of the link. Both components must operate with the same

de-emphasis across all lanes of the link. During normal operation (i.e, not polling.compliance), de-emphasis

selection is done during the Recovery state. The downstream component of the link (i.e., switch upstream

port or endpoint) advertises its desired de-emphasis by transmission of training sets. The upstream compo-

nent of the link (i.e., switch downstream port or root-complex port) notes its link partner desired de-

emphasis and makes a decision about the de-emphasis to be used in the link.

The PES24T3G2’s upstream port PHY advertises its des ired de-emphasis based on the setting of the

port’s SDE field in the PCIELCTL2 register. The upstream PHY always accepts the link-partners decision

on the de-emphasis to be used in the link. The PES24T3G2’s downstream ports ignore the link partner’s

desired de-emphasis and always choose the de-emphasis setting in the SDE field of the port’s PCIELCTL2

Low-Swing Transmitter Voltage Mode

The PES24T3G2 ports support the optional low-swing transmit voltage mode defined in the PCIe 2.0

specification. In this mode, the transmitter ’s voltage level is set to approximately half the value of the full-

swing (default) mode. This reduces power consumption in the SerDes. This mode is enabled by setting the

Low-Swing Enable (LSE) bit in the port’s SerDes Control (SERDESCTL) register.

When Low-Swing mode is enabled, the transmitter driv e level is reduced and de-emphasis is automati-

cally turned off. Therefore, the Selectable De-emphasis (SDE) and Compliance De-emphasis (CDE) fields

in the PCIELCTL2 register have no effect. In addition, the Current De-emphasis (CDE) field in the

PCIELSTS2 register becomes invalid.

Crosslink

The PES24T3G2 ports support the optional crosslink capability specified in PCI Express 2.0. Per this

specification, a crosslink is established between two downstream ports or tw o upstream ports. Crosslink is

enabled when the Crosslink Disable (CLINKDIS) bit in the Phy Link Configuration (PHYLCFG) register is

set to 0x0. The initial value of this field is 0x1 in a ll switch modes except SWMODE[2:0]=0x4 “Normal switch

mode with crosslink enabled (factory use only).” The user may also clear this bit with a configuration write.

Notes

PES24T3G2 User Manual 4 - 1 February 22, 2012

Chapter 4

General Purpose I/O

Introduction

The PES24T3G2 has 8 General Purpose I/O (GPIO) pins that may be individually configured as:

general purpose inputs, general purpose outputs, or alternate functions.GPIO pins are controlled by the

General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General

Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space. As shown in Table 4.1,

6 GPIO pins are shared with other on-chip functions. The GPIO Function (GPIOFUNC) register controls

whether a GPIO bit operates as a general purpose I/O or as the specified alternate function.

After reset, all GPIO pins default to the GPIO input function. GPIO pins configured as GPIO inputs are

sampled no more frequently than once every 128 ns and may be treated as asynchronous inputs. When a

GPIO pin is configured to use the GPIO function, the unneeded alternate function associated with the pin is

held in an inactive state by internal logic. Care should be exercised when configuring the GPIO pins as

outputs since an incorrect configuration could cause damage to external components as well as the

PES24T3G2.

GPIO Configuration

Associated with each GPIO pin is a bit in the GPIOFUNC, GPIOCFG and GPIOD registers. Table 4.2

summarizes the configuration of GPIO pins.

GPIO Pin Configured as an Input

When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC

determined at any time by reading the GPIOD register. Note that the value in this register corresponds to

the value of the pin irrespective of whether the pin is configured as a GPIO input, GPIO output, or alternate

function.

GPIO

Alternate

Function

Pin Name

Alternate Function

Description

Alternate

Function

Pin Type

0 PE2RSTN Reset output for downstream port 2 Output

1 PE4RSTN Reset output for downstream port 4 Output

2 IOEXPINTN0 SMBus I/O expander interrupt 0 Input

3 IOEXPINTN1 SMBus I/O expander interrupt 1 Input

4 IOEXPINTN2 SMBus I/O expander interrupt 2 Input

7 GPEN General purpose event output Output

Table 4.1 General Purpose I/O Pin Alternate Function

GPIOFUNC GPIOCFG Pin Function

0 0 GPIO input

0 1 GPIO output

1 don’t care Alternate function

Table 4.2 GPIO Pin Configuration

IDT General Purpose I/O

PES24T3G2 User Manual 4 - 2 February 22, 2012

Notes

GPIO Pi n Configured as an Output

When configured as an output in the GPIOCFG register and as a GPIO function in the GPIOFUNC

designers should treat the GPIO outputs as asynchronous outputs. The actual value of the output pin can

be determined by reading the GPIOD register.

GPIO Pi n Configu red as an Alternate Fu nction

When configured as an alternate function in the GPIOFUNC register, the pin behaves as described by

the section associated with that function. The value of the alternate function pin can be determined at any

time by reading the GPIOD register.

Notes

PES24T3G2 User Manual 5 - 1 February 22, 2012

Chapter 5

SMBus Interfaces

Introduction

The PES24T3G2 contains two S MBus interfaces. The s lave SMBus interface provides full acc ess to all

software visible registers in the PES24T3G2, allowing every register in the device to be read or written by

an external SMBus master. The slave SMBus may also be used to initialize the serial EEPROM used for

initialization. The Master SMBus interface provides connection for an optional external serial EEPROM

used for initialization and optional external I/O expanders.

Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an

SMBus data pin, and 4 SMBus address pins.

Note: MSMBADDR and SSMBADDR address pins are not available in the 19mm package. The

MSMBADDR address is hardwired to 0x50, and the SSMBADDR address is hardwired to 0x77.

As shown in Figure 5.1, the master and slave SMBuses may be used in a unified or split configuration.

Figure 5.1 SMBus Interface Configuration Examples

In the unified configuration, shown in Figure 5.1(a), the master and slave SMBuses are tied together and

the PES24T3G2 acts both as an SMBus master as well as an SMBus slave on this bus. This requires that

the external SMBus master or processor that has access to the PES24T3G2 registers support SMBus arbi-

Processor

PES24T3G2

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

Processor

PES24T3G2

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

...

(a) Unified Configuration

(b) Split Configuration

Hot-Plug

I/O

Expander

Hot-Plug

I/O

Expander

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 2 February 22, 2012

Notes

tration. In some systems, this external SMBus master interface may be implemented using gener al purpose

I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these

systems, the PES24T3G2 may be configured to operate in a split configuration as shown in Figure 5.1(b).

In the split configuration, the master and slave SMBuses operate as two independent buses and thus

multi-master arbitration is not required.

Master SMBus Interface

The master SMBus interface is used during a fundamental reset to load configuration values from an

optional serial EEPROM. It is also used to support optional I/O expanders used for hot-plug and other

status signals.

Initialization

Master SMBus initialization occurs during a fundamental reset (see Fundamental Reset on page 2-2).

During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode (MSMB-

SMODE) signal is examined. If this signal is asserted, then the Master SMBus Clock Prescalar (MSMBCP)

field in the SMBus Control (SMBUSCTL) register is initialized to support 100 KHz SMBus operation. If the

signal is negated, the MSMBCP field is initialized for 400 KHz SMBus operation.

Serial EEPROM

During a fundamental or hot reset, an optional serial EEPROM may be used to initialize any software

visible register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[2:0]) field

selects an operating mode that performs serial EEPROM initialization. The address used by the SMBus

interface to access the serial EEPROM is specifi ed by the MSMBADDR[4:1] signals as shown in Table 5.1.

Note: MSMBADDR address pins are not available in the 19mm package. The MSMBADDR

address is hardwired to 0x50.

Device Initialization from a Serial EEPROM

During initialization from the optional serial EEPROM, the master SMBus interface reads configuration

blocks from the serial EEPROM and updates corresponding registers in the PES24T3G2. Any PES24T3G2

software visible register in any port may be initialized with values stored in the serial EEPROM. Each soft-

ware visible register in the PES24T3G2 has a CSR system address which is formed by adding the PCI

configuration space offset value of the register to the base address of the configuration space in which the

right two bits (i.e., configuration blocks in the serial EEP ROM use doubleword CSR s ystem addresses and

not byte CSR system addresses).

Base addresses for the PCI configuration spaces in the PES24T3G2 are listed in Table 8.1, Base

Addresses for Port Configuration Space Register. Since configuration blocks are used to store only the

value of those registers that are initialized, a serial EEPROM much smaller than the total size of all of the

Address

Bit Address Bit Value

1 MSMBADDR[1]

2 MSMBADDR[2]

3 MSMBADDR[3]

4 MSMBADDR[4]

Table 5.1 Serial EEPROM SMBus Address

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 3 February 22, 2012

Notes

configuration spaces may be used to initialize the device. Any serial EEPROM compatible with those listed

in Table 5.2 may be used to s tore the PES24T3G2 initialization values. Some of these devices are larger

than the total size of all of the PCI configuration spaces in the PES24T3G2 that may be initialized and thus

may not be fully utilized.

During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial

EEPROM address zero. These bytes are interpreted as configuration blocks and sequential reading of the

serial EEPROM continues until the end of a configuration done block is reached or the serial EEPROM

address rolls over from 0xFFFF to 0x0.

A blank serial EEPROM contains 0xFF in all data bytes. Therefore, when the PES24T3G2 is configured

to initialize from serial EEPROM and the second byte read from the EEPROM is0xFF, loading of the serial

EEPROM is aborted, the computed checksum is ignored, and normal device operation beings (i.e., the

device operates in the same manner as though i were not configured to initialize from the serial EEPROM).

–This behavior allows a board manufacturing flow that utilizes uninitialized serial EEPROMs. S ee

section Programming the Serial EEPROM on page 5-6 for information on in-system initialization

of the serial EEPROM.

All register initialization performed by the serial EEPROM is performed in double word quantities.

There are three configuration block types that may be stored in the serial EEPROM. The first type is a

single double word initializati on sequence. A double word initialization sequence oc cupies six bytes in the

serial EEPROM and is used to initialize a single double word quantity in the PES24T3G2. A single double

word initialization sequence consists of three fields and its format is shown in Figure 5.2. The

CSR_SYSADDR fiel d contains the double word CSR system address of the double word to be initialized.

The actual CSR system address, which is a byte address, equals this value with two lower zero bits

appended. The next field is the TYPE field that indicates the type of the configuration block. For single

double word initialization sequence, this value is always 0x0. The final DATA field contains the double word

initialization value.

Figure 5.2 Single Double Word Initialization Sequence Format

Serial EEPROM Size

24C32 4 KB

24C64 8 KB

24C128 16 KB

24C256 32 KB

24C512 64 KB

Table 5.2 PES24T3G2 Compatible Serial EEPROMs

Bit

Byte 0 CSR_SYSADDR[7:0]

CSR_SYSADDR[13:8]

TYPE

0x0

Byte 1

Byte 2 DATA[7:0]

Byte 3 DATA[15:8]

Byte 4 DATA[23:16]

Byte 5 DATA[31:24]

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 4 February 22, 2012

Notes

The second type of configuration block is the sequential double word initialization sequence. It is similar

to a single double word initialization sequence except that it contains a double word count that allows

multiple sequential double words to be initialized in one configuration block.

A sequential double word initialization sequence consists of four required fields and one to 65535

double word initialization data fields. The format of a sequential double word initialization sequence is

shown in Figure 5.3. The CSR_SYSADDR field contains the starting double word CSR system address to

be initialized. The next field is the TYPE field that indicates the type of the configuration block. For sequen-

tial double word initialization sequences, this value is always 0x 1. The NUMDW field specifi es the number

of double words initialized by the configuration block. This is followed by the number of D ATA fields speci-

fied in the NUMDW field.

Figure 5.3 Sequential Double Word Initialization Sequence Format

The final type of configuration block is the configuration done sequence which is used to signify the end

of a serial EEPROM initialization sequence. If during serial EEPROM initialization, an attempt is made to

initialize a register that is not defined in a configuration space (i.e., not defined in chapter 8!!!), then the

Unmapped Register Initialization Attempt (URIA) bit is set in the SMBUSSTS register and the write is

ignored.

The configuration done sequence consists of two fields and its format is shown in Figure 5.4. The

CHECKSUM field contains the checksum of all of the bytes in all of the fields read from the serial EEPROM

from the first configuration block to the end of this done sequence. The second field is the TYPE field which

is always 0x3 for configuration done sequences.

Figure 5.4 Configuration Done Sequence Format

Bit

Byte 0 CSR_SYSADDR[7:0]

CSR_SYSADDR[13:8]

TYPE

0x1

Byte 1

Byte 2 NUMDW[7 :0 ]

Byte 3 NUMDW[15:8]

Byte 4 DATA0[7:0]

Byte 5 DATA0[15:8]

Byte 6 DATA0[23:16]

Byte 7 DATA0[31:24]

Byte 4n+4 DATAn[7:0]

Byte 4n+ 5 DATAn[15:8]

Byte 4n+6 DATAn[23:16]

Byte 4n+7 DATAn[31:24]

...

Bit

Byte 0 CHECKSUM[7:0]

ReservedTYPE

0x3

Byte 1 (mus t be zero )

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 5 February 22, 2012

Notes

The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa-

tion to be verified. Since uninitialized EEPROMs typically have a value of all ones, initialization from an

uninitialized serial EEPROM will result in a checksum mismatch. The checksum is computed in the

following manner. An 8-bit counter is initialized to zero and the 8-bit sum is computed over the configuration

bytes stored in the serial E EPROM, including the entire contents of the c onfiguration done sequence, with

the checksum field initialized to zero.1 The 1’s complement of this sum is placed in the checksum field.

1. This includes the byte containing the TYPE field.

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 6 February 22, 2012

Notes

The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is

computed over the bytes read from the serial E EPROM, including the entire contents of the configuration

done sequence.1 The correct result should always be 0xFF (i.e., all ones). Checksum checking may be

disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the SMBus Control (SMBUSCTL)

If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is

aborted and the RSTHALT bit is set in the SWCTL register. This allows debugging of the error condition via

the slave SMBus interface but prevents normal system operation with a potentially incorrectly initialized

device. Error information is recorded in the SMBUSSTS register.

Once serial EEPROM initialization completes, or when an error is detected, the EEPROM Done

(EEPROMDONE) bit is set in the SMBus Status (SMBUSSTS) register. A summary of possible errors

during serial EEPROM initialization and specific action taken when detected is summarized in Table 5.3.

Programming the Ser ial EEPROM

The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus

interface or a PCIe root. Programming the serial EEPROM via the slave SMBus is described in section

Serial EEPROM Read or Write Operation on page 5-15.

A PCIe root may read and write the serial EEPROM by performing configuration read and write transac-

tions to the Serial EEPROM Interface (EEPROMINTF) register. To read a byte from the serial EEPROM, the

root should configure the Address (ADDR) field in the EEPROMINTF register with the byte address of the

serial EEPROM location to be read and the Operation (OP) field to “read.” The Busy ( BUSY) bit should then

be checked. If the EEPROM is not busy, then the read operation may be initiated by performing a write to

the Data (DATA) field. When the serial EEPROM read operation completes, the Done (DONE) bit in the

EEPROMINTF register is set and the busy bit is cleared. When this occurs, the DA TA field contains the byte

data of the value read from the serial EEPROM.

To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of

the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM i s not busy

(i.e., the BUSY bit is cleared), then the write operation may be initi ated by w riting the value to be w ritten to

the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared. Initi-

ating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.

1. This includes the checksum byte as well as the byte that contains the type and reserved field.

Error Action Taken

Configuration Done Sequence checksum

mismatch with that computed by the

PES24T3G2

- Set RSTHALT bit in SWCTL register

- ICSERR bit is set in the SMBUSSTS register

- Abort initialization, set DONE bit in the SMBUSSTS register

Invalid configuration block type

(only invalid type is 0x2) - Set RSTHALT bit in SWCTL register

- ICSERR bit is set in the SMBUSSTS register

- Abort initialization, set DONE bit in the SMBUSSTS register

An unexpected NACK is observed during a

master SMBus transaction - Set RSTHALT bit in SWCTL register

- NAERR bit is set in the SMBUSSTS register

- Abort initialization, set DONE bit in the SMBUSSTS register

Master SMBus interface loses 16 consecu-

tive arbitration attempts - Set RSTHALT bit in SWCTL register

- LAERR bit is set in the SMBUSSTS register

- Abort initialization, set DONE bit in the SMBUSSTS register

A misplaced START or STOP condition is

detected by the master SMBus interface - Set RSTHALT bit in SWCTL register

- OTHERERR bit is set in the SMBUSSTS register

- Abort initialization, set DONE bit in the SMBUSSTS register

Tab le 5.3 Serial EEPROM Initialization Errors

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 7 February 22, 2012

Notes

SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in

the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial

EEPROM access.

I/O Expanders

The PES24T3G2 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus inter-

face for hot-plug and port status signals. The PES24T3G2 is designed to work with Phillips PCA9555

compatible I/O expanders (i.e., PCA9555, PCA9535, and PCA9539). See the Phillips PCA9555 data sheet

for details on the operation of this device. An external SMBus I/O expander provides 16 bit I/O pins that

may be configured as inputs or outputs.

The PES24T3G2 supports up to three external I/O expanders. Table 5.4 summarizes the allocation of

functions to I/O expanders. I/O expanders zero through three are used to provide hot-plug I/O signals while

I/O expander four is used to provide link status and activity LED control. I/O expander signals associated

with LED control (i.e., link status and activity) are active low (i.e., driven low when an LED should be turned

on). I/O expander signals associated with hot-plug signals are not inverted.

During the PES24T3G2 initialization process, the SMBus/I2C-bus address allocated to each I/O

expander used in that system configuration should be written to the corresponding IO Expander Address

(IOE[0,2,4]ADDR) field.

Hot-plug outputs and I/O expanders may be initialized via serial EEPROM. Since the I/O expanders and

serial EEPROM both utilize the master SMBus, no I/O expander transactions are initiated until serial

EEPROM initialization completes.

–Since no I/O expander transactions are initiated until serial E EPROM initialization completes, it is

not possible to toggle a hot-plug output through serial EEPROM initialization (i.e., it is not possible

to cause a 0 -> 1 -> 0 transition or a 1 -> 0 -> 1 transition).

Whenever the value of an IOEXPADDR field is written, SMBus write transactions are issued to the

corresponding I/O expander by the PES24T3G2 to configure the device. This configuration initializes the

direction of each I/O expander signal and sets outputs to their default value. Outputs for ports that are

disabled are set to their negated value (e.g., the power indicator is turned off, the link is down, there is no

activity, etc.).

The default value of I/O expander outputs is shown in Table 5.5. Note that this default value may be

modified via serial EEPROM or SMBus configuration prior to SMBus initi alization by changing the state of

the PCI Express Slot Control Register (PCIESCTL) or Hot-Plug Configuration Control (HPCFGCTL).

SMBus I/O

Expander Section Function

0 Lower Port 2 hot-plug

Upper Port 4 hot-plug

2 Lower Unused

Upper Power good inputs

4 Lower Link status

Upper Link activity

Table 5.4 I/O Expander Function Allocation

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 8 February 22, 2012

Notes

The following I/O expander c onfiguration sequence is issued by the P ES24T3G2 to I/O expander zero

(which contains the hot-plug signals).

–Write the default value of the outputs bits on the lower eight I/O expander pins (i.e., I/O-0.0 through

I/O-0.7) to I/O expander register 2.

–Write the default value of the outputs bits on the upper eight I/O expander pins (i.e., I/O-1.0

through I/O-1.7) to I/O expander register 3.

–write value 0x0 to I/O expander register 4 (no inversion in IO-0)

–write value 0x0 to I/O expander register 5 (no inversion in IO-1)

–Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-

0.0 through I/O-0.7) to I/O expander register 6.

–Write the configuration value to select inputs/outputs in the upper eight I/O expander bits (i.e., I/

O-1.0 through I/O-1.7) to I/O expander register 7.

–Read value of I/O expander register 0 to obtain the current state of the low er eight I/O expander

bits (i.e., I/O-0.0 through I/O-0.7)

–Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander

bits (i.e., I/O-1.0 through I/O-1.7)

The following I/O expander configuration sequence is issued by the PES24T3G2 to I/O two ( i.e., the one

that contain hot-plug signals and power good inputs).

–Write the default value of the outputs bits on the lower eight I/O expander pins (i.e., I/O-0.0 through

I/O-0.7) to I/O expander register 2.

–write value 0x0 to I/O expander register 4 (no inversion in IO-0)

–write value 0x0 to I/O expander register 5 (no inversion in IO-1)

–Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-

0.0 through I/O-0.7) to I/O expander register 6.

–Write the configuration value to select all input s upper eight I/O expander bits (i.e., I/O-1.0 through

I/O-1.7) to I/O expander register 7.

–Read value of I/O expander register 0 to obtain the current state of the low er eight I/O expander

bits (i.e., I/O-0.0 through I/O-0.7)

–read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander

bits (i.e., I/O-1.0 through I/O-1.7)

SMBus I/O

Expander

Bit Signal Description Default

Value

(I/O-x.4) P2AIN Attention indicator output (off) 1

(I/O-x.5) P2PIN Power indicator output (on) 0

(I/O-x.6) P2PEP Power enable output (on) 1

(I/O-x.7) P2ILOCKP Electromechanical interlock (negated - off) 0

Table 5.5 I/O Expander Default Output Signal Value

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 9 February 22, 2012

Notes

The following I/O expander configuration sequence is issued by the PES24T3G2 to I/O expander four

(i.e., the one that contains link up and link activity status).

–Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7)

to I/O expander register 2.

–Write link activity status for all ports to the upper eight I/O expander pins (i.e., I/O-1.0 through I/O-

1.7) to I/O expander register 3.

–write value 0x0 to I/O expander register 4 (no inversion in IO-0)

–write value 0x0 to I/O expander register 5 (no inversion in IO-1)

–Write the configuration value to select all outputs in the lower eight I/O expander bits (i.e., I/O-0.0

through I/O-0.7) to I/O expander register 6.

–Write the configuration value to select all outputs in the upper eight I/O expander bits (i.e., I/O-1.0

through I/O-1.7) to I/O expander register 7.

While the I/O expander is enabled, the PES24T3G2 maintains the I/O bus expander signals and the

PES24T3G2 internal view of the hot-plug signals in a consistent state. This means that whenever that I/O

bus expander state and the PES24T3G2 internal view of the signal state differs, an SMBus transaction is

initiated by the PES24T3G2 to resolve the state conflict. An example of an event that may lead to a state

conflict is a hot reset. When a hot reset occurs, one or more hot-plug register control fields may be re-initial-

ized to its default value. When this occurs, the internal PES24T3G2 state of the hot-plug signals is in

conflict with the state of I/O expander hot-plug output signals. In such a situation, the PES24T3G2 will

initiate an SMBus transaction to modify the state of the I/O expander hot-plug outputs

The PES24T3G2 has one combined I/O expander interrupt input, labeled IOEXPINTN0, which is an

alternate function of GPIO[2]. Associated with each I/O expander is an open drain interrupt output that is

asserted when an I/O expander input pin changes state. The open drain I/O expander interrupt output of all

I/O expanders should be tied together on the board and connected to GPIO[2]. Whenever IOEXPINTN0 is

asserted, the PES24T3G2 reads the state of all I/O expanders.

For compatibility with legacy Gen. 1 PCIe switches, the PES24T3G2 supports individual I/O expander

interrupt inputs (i.e., IOEXPINTN2,0]) as GPIO alternate functions. New designs should use the combined I/

O expander interrupt input.

In legacy applications, each interrupt output from an I/O expander should be connected to the corre-

sponding PES24T3G2 I/O expander interrupt input. For Legacy Gen 1 switch compatibility, the

PES24T3G2 internally logically “ORs” the legacy I/O expander interrupts on GPIO alternate functions and

presents a single combined interrupt value to internal logic in the same manner as the external combined I/

O expander interrupt input. Therefore, the PES24T3G2 behaves in the same manner in applications that

use a single external combined I/O expander interrupt input as it does in applications that use legacy indi-

vidual I/O expander interrupt inputs. In both cases, the assertion of any I/O expander interrupt results in a

status read of all I/O expanders. Since the PES24T3G2 I/O expander interrupt input(s) are GPIO alternate

functions, the corresponding GPIO(s) should be initialized during configuration to operate in alternate func-

tion mode. See Chapter 4, General Purpose I/O.

Whenever the PES24T3G2 needs to change the state of an I/O expander signal output, a master

SMBus transaction is initiated to update the state of the I/O expander. This write operation causes the

corresponding I/O expander to change the state of its output(s). The PES24T3G2 will not update the state

of an I/O expander output more frequently than once every 40 milliseconds. This 40 millisecond time

interval is referred to as the I/O expander update period.

Whenever an input to the I/O expander changes state from the value previously read, the interrupt

output of the I/O expander is asserted. This causes the PES24T3G2 to issue a master SMBus transaction

to read the updated state of all I/O expander inputs. In legacy Gen1 devices, the PCIe switch would only

read the state of the I/O expander that asserted the interrupt. Whenever any I/O expander interrupt is

asserted, the PES24T3G2 reads and updates the state of all I/O expander inputs.

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 10 February 22, 2012

Notes

Regardless of the state of the interrupt output of the I/O expander, the PES24T3G2 will not issue a

master SMBus transaction to read the updated state of the I/O expander inputs more frequently than once

every 40 milliseconds (i.e., the I/O expander update period). This delay in sampling may be used to elimi-

nate external debounce circuitry. The I/O expander interrupt request output is negated whenever the input

values are read or when the input pin changes state back to the value previously read.

The PES24T3G2 ensures that I/O expander transactions are initiated on the master SMBus in a fair

manner. This guarantees that all I/O expanders have equal service latencies. Any errors detected during I/

O expander SMBus read or write transactions is reflected in the status bits of the SMBus Status

(SMBUSSTS) register.

The I/O Expander Interface (IOEXPINTF) register allows direct testing and debugging of the I/O

expander functionality. The Selec t (SEL) field in the IOEXPINTF register selects the I/O expander number

on which other fields in the register operate. The I/O Expander Data field in the IOEXPINTF register reflect

the current state, as viewed by the PES24T3G2, of the I/O expander inputs and outputs selected by the

SEL field.

Writing a one to the Reload I/O Expander Signals (RELOADIOEX) bit in the IOEXPINTF register causes

the PES24T3G2 to generate SMBus write and read transactions to the I/O expander number selected in the

SEL field. This results in the value of the IOEDATA field being updated to reflect the current state of the

corresponding I/O expander signals. This feature may be used to aid in debugging I/O expander operation.

For example, a user who neglects to configure a GPIO as an alternate function may use this feature to

determine that master SMBus transactions to the I/O expander function properly and that the issue is with

the interrupt logic.

The IO Expander Test Mode (IOEXTM) bit in the IOEXPTINF register allows an I/O expander test mode

to be entered. When this bit is set, the PES24T3G2 core logic outputs are ignored and the values written to

the I/O expander for output bits are the values in the IOEDATA field. In this mode, the PES24T3G2 issues a

transaction to update the state of the I/O expander whenever a bit corresponding to an I/O expander output

changes state due to a write to the IOEDATA field.

Bits in the IOEDATA field that correspond to outputs are dependent on the I/O expander number

selected in the SEL field in the IOEXPINTF register. The outputs for each I/O expander number are shown

in Table 5.6 through 5.8.

IDT suggests the following system design recommendations:

–I/O expander addresses and default output values may be configured during serial EEPROM

initialization. If I/O expander addresses are configured via the serial EEPROM, then the

PES24T3G2 will initialize the I/O expanders when normal device operation begins foll owing the

completion of the fundamental reset sequence.

–If the I/O expanders are initialized via serial EEPROM, the data value for output signals during the

SMBus initialization sequence will correspond to those at the time the SMBus transactions are

initiated. It is not possible to toggle SMBus I/O expander outputs by modifying data values during

serial EEPROM initialization.

–During a fundamental reset and before the I/O expander outputs are initialized, all I/O expander

output signals default to inputs. Therefore, pull-up or pull-down resistors should be placed on

outputs to ensure that they are held in the desired state during this period.

–All hot-plug data value modifications that correspond to hot-plug outputs r esult in SMBus transac-

tions. This includes modifications due to upstream secondary bus resets and hot-resets.

–I/O expander outputs are not modified when the device transitions from normal operation to a

fundamental reset. In systems where I/O expander output values must be reset during a funda-

mental reset, a PCA9539 I/O expander should be used.

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 11 February 22, 2012

Notes

I/O Expander 0

I/O Expander 2

SMBus I/O

Expander

Bit Type Signal Description

0 (I/O-0.0)1

1. I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

I P2APN Port 2 attention push button input

1 (I/O-0.1) I P2PDN Port 2 presence detect input

2 (I/O-0.2) I P2PFN Port 2 power fault input

3 (I/O-0.3) I P2MRLN Port 2 manually-operated retention latch (MRL) input

4 (I/O-0.4) O P2AIN Port 2 attention indicator output

5 (I/O-0.5) O P2PIN Port 2 power indicator output

6 (I/O-0.6) O P2PEP Port 2 power enable output

7 (I/O-0.7) O P2ILOCKP Port 2 electromechanical interlock

8 (I/O-1.0) I P4APN Port 4 attention push button input

9 (I/O-1.1) I P4PDN Port 4 presence detect input

10 (I/O-1.2) I P4PFN Port 4 power fault input

11 (I/O-1.3) I P4MRLN Port 4 manually-operated retention latch (MRL) input

12 (I/O-1.4) O P4AIN Port 4 attention indicator output

13 (I/O-1.5) O P4PIN Port 4 power indicator output

14 (I/O-1.6) O P4PEP Port 4 power enable output

15 (I/O-1.7) O P4ILOCKP Port 4 electromechanical interlock

Table 5.6 I/O Expander 0 Signals

SMBus I/O

Expander

Bit Type Signal Description

0 (I/O-0.0)1I - Unused

1 (I/O-0.1) I - Unused

2 (I/O-0.2) I - Unused

3 (I/O-0.3) I - Unused

4 (I/O-0.4) O - Unused

5 (I/O-0.5) O - Unused

6 (I/O-0.6) O - Unused

7 (I/O-0.7) O - Unused

8 (I/O-1.0) I - Unused

9 (I/O-1.1) I - Unused

10 (I/O-1.2) I P2PWRGDN Port 2 power good input

Table 5.7 I/O Expander 2 Signals

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 12 February 22, 2012

Notes

I/O Expander 4

Slave SMBus Interface

The slave SMBus interface provides the PES24T3G2 with a configuration, management, and debug

interface. Using the slave SMBus interface, an external master can read or write any software visible

11 (I/O-1.3) I - Unused

12 (I/O-1.4) I P4PWRGDN Port 4 power good input

13 (I/O-1.5) I - Unused

14 (I/O-1.6) I - Unused

15 (I/O-1.7) I - Unused

1. I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

SMBus I/O

Expander

Bit Type Signal Description

0 (I/O-0.0)1

1. I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.

O P0LINKUPN Port 0 link up status output

1 (I/O-0.1) - Unused

2 (I/O-0.2) O P2LINKUPN Port 2 link up status output

3 (I/O-0.3) O - Unused

4 (I/O-0.4) O P4LINKUPN Port 4 link up status output

5 (I/O-0.5) O - Unused

6 (I/O-0.6) O - Unused

7 (I/O-0.7) O - Unused

8 (I/O-1.0) O - Unused

9 (I/O-1.1) O - Unused

10 (I/O-1.2) O P2ACTIVEN Port 2 activity output

11 (I/O-1.3) O - Unused

12 (I/O-1.4) O P4ACTIVEN Port 4 activity output

13 (I/O-1.5) O - Unused

14 (I/O-1.6) O - Unused

15 (I/O-1.7) O - Unused

Table 5.8 I/O Expander 4 Signals

SMBus I/O

Expander

Bit Type Signal Description

Table 5.7 I/O Expander 2 Signals

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 13 February 22, 2012

Notes

Initialization

Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page

2-2). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The

address is specified by the SSMBADDR[5,3:1] signals as shown in Table 5.9.

Note: SSMBADDR address pins are not available in the 19mm package. The SSMBADDR

address is hardwired to 0x77.

SMBus Transactions

The slave SMBus interface responds to the following SMBus transactions initiated by an SM Bus master

(see the SMBus 2.0 specification for a detailed description of these transactions):

–Byte and Word Write/Read

–Block Write/Read

Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces

undefined results. Associated with each of the above transactions is a command code. The command code

format for operations supported by the slave SMBus interface is shown in Figure 5.5 and described in Table

5.10.

Figure 5.5 Slave SMBus Command Code Format

Address Bit Address Bit Value

1 SSMBADDR[1]

2 SSMBADDR[2]

3 SSMBADDR[3]

5 SSMBADDR[5]

Table 5.9 Slave SMBus Address When a Static Address is Selected

Bit

Field Name Description

0 END End of transaction indicator. Setting both START and END signifies a

single transaction sequence

0 - Current transaction is not the last read or write sequence.

1 - Current transaction is the last read or write sequence.

1 START Start of transaction indicator. Setting both START and END signifies a

single transaction sequence

0 - Current transaction is not the first of a read or write sequence.

1 - Current transaction is the first of a read or write sequence.

Table 5.10 Slave SMBus Command Code Fields (Part 1 of 2)

Bit

7Bit

Bit

ENDSTARTFUNCTIONSIZEPEC

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 14 February 22, 2012

Notes

The FUNCTION field in the command code indicates if the SMBus operation is a CSR register read/

write or a serial EEPROM read/write operation. Since the format of these transactions is different. They will

be described individually in the following sections. If a command is issued while one is already i n progress

or if the slave is unable to supply data associated with a command, the command is NACKed. This indi-

cates to the master that the transaction should be retried.

CSR Register Read or Write Operation

Table 5.11 indicates the sequence of data as it is presented on the slave SMBus following the byte

address of the Slave SMBus interface.

Table 5.11 indicates the sequence of data as it is presented on the slave SMBus following the byte

address of the Slave SMBus interface. Dword addresses and not byte addresses must be used to access

all visible software registers. ADDRL and ADDUL represent the lower 8-bit of the doubleword system

4:2 FUNC-

TION This field encodes the type of SMBus operation.

0 - CSR register read or write operation

1 - Serial EEPROM read or write operation

2 through 7 - Reserved

6:5 SIZE This field encodes the data size of the SMBus transaction.

0 - Byte

1 - Word

2 - Block

3 - Reserved

7 PEC This bit controls whether packet error checking is enabled for the cur-

rent SMBus transaction.

0 - Packet error checking disabled for the current SMBus transaction.

1 - Packet error checking enabled for the current SMBus transaction.

Byte

Position Field

Name Description

0 CCODE Command Code. Slave Command Code field described in Table 5.10.

1 BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transac-

tions. SMBus word and byte accesses do not contain this field. The byte count field

indicates the number of bytes following the byte count field when performing a write

or setting up for a read. The byte count field is also used when returning data to indi-

cate the number of following bytes (including status). Note that the byte count field

does not include the PEC byte if PEC is enabled.

2CMDCommand. This field encodes fields related to the CSR register read or write opera-

tion.

3 ADDRL Address Low. Lower 8-bits of the doubleword CSR system address of register to

access.

4 ADDRU Address Upper. Upper 6-bits of the doubleword CSR system address of register to

access. Bits 6 and 7 in the byte must be zero and are ignored by the hardware.

5 DATALL Data Lower. Bits [7:0] of data doubleword.

6 DATALM Data Lowe r Middle. Bits [15:8] of data doubleword.

7 DATAUM Data Uppe r Middle . Bits [23:16] of data doubleword.

8 DATAUU Data Upper. Bits [31:24] of data doubleword.

Table 5.11 CSR Register Read or Write Operation Byte Sequence

Bit

Field Name Description

Table 5.10 Slave SMBus Command Code Fields (Part 2 of 2)

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 15 February 22, 2012

Notes

address and upper 6-bit doubleword system address, respectively. For example, use ADDRU = x00 and

ADDRL = 0x00 to access system address 0x00000 (port 0’s Vendor/Device ID register). Use ADDRU = x00

and ADDRL = 0x01 to access system address 0x00004 (port 0’s Command/Status register).

The format of the CMD field is shown in Figure 5.6 and described in Table 5.12.

Figure 5.6 CSR Register Read or Write CMD Field Format

Serial EEPROM Read or Write Operation

Table 5.12 indicates the sequence of data as it is presented on the slave SMBus following the byte

address of the Slave SMBus interface.

Bit

Field Name Type Description

0 BELL Read/Write Byte Enable Lower. When set, the byte enable for bits [7:0] of the data word

is enabled.

1 BELM Read/Write Byte Enable Lower Middle. When set, the byte enable for bits [15:8] of the

data word is enabled.

2 BEUM Read/Write Byte Enable Upper Middle. When set, the byte enable for bits [23:16] of the

data word is enabled.

3 BEUU Read/Write Byte Enable Upper. When set, the byte enable for bits [31:24] of the data

word is enabled.

4 OP Read/Write CSR Operation. This field encodes the CSR operation to be performed.

0 - CSR write

1 - CSR read

5 0 0 Reserved. Must be zero

6 RERR Read-Only

and Clear Read Error. This bit is set if the last CSR read SMBus transaction was not

claimed by a device. Success indicates that the transaction was claimed and

not that the operation completed without error.

7 WERR Read-Only

and Clear Write Error. This bit is set if the last CSR write SMBus transaction was not

claimed by a device. Success indicates that the transaction was claimed and

not that the operation completed without error.

Table 5.12 CSR Register Read or Write CMD Field Description

Byte

Position Field

Name Description

0 CCODE Command Code. Slave Command Code field described in Table 5.10.

1 BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transac-

tions. SMBus word and byte accesses to not contain this field. The byte count field

indicates the number of bytes following the byte count field when performing a write

or setting up for a read. The byte count field is also used when returning data to indi-

cate the number of following bytes (including status).

2CMDCommand. This field contains information related to the serial EEPROM transaction

Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence (Part 1 of 2)

Bit

7Bit

Bit

BELLBELMWERR BEUMBEUUOPRERR 0

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 16 February 22, 2012

Notes

The format of the CMD field is shown in Figure 5.7 and described in Table 5.14.

Figure 5.7 Serial EEPROM Read or Write CMD Field Format

3 EEADDR Serial EEPROM Address. This field specifies the address of the Serial EEPROM

on the Master SMBus when the USA bit is set in the CMD field. Bit zero must be

zero and thus the 7-bit address must be left justified.

4 ADDRL Address Low. Lower 8-bits of the Serial EEPROM byte to access.

5 ADDRU Address Upper. Upper 8-bits of the Serial EEPROM byte to access.

6DATAData. Serial EEPROM value read or to be written.

Bit

Field Name Type1Description

0 OP RW Serial EEPROM Operation. This field encodes the serial EEPROM oper-

ation to be performed.

0 - Serial EEPROM write

1 - Serial EEPROM read

1USARWUse Specified Address. When this bit is set the serial EEPROM SMBus

address specified in the EEADDR is used instead of that specified in the

ADDR field in the EEPROMINTF register.

When this bit is set the serial EEPROM SMBus address specified in the

EEADDR is used instead of that specified in the MSMBADDR field in the

SMBUSSTS register.

2 Reserved Reserved

3 NAERR RC No Acknowledge Error. This bit is set if an unexpected NACK is observed

during a master SMBus transaction when accessing the serial EEPROM.

This bit has the same function as the NAERR bit in the SMBUSSTS reg-

ister.

The setting of this bit may indicate the following: that the addressed

device does not exist on the SMBus (i.e., addressing error), data is

unavailable or the device is busy, an invalid command was detected by

the slave, invalid data was detected by the slave.

4 LAERR RC Lost Arbitration Error. This bit is set if the master SMBus interface loses

16 consecutive arbitration attempts when accessing the serial EEPROM.

This bit has the same function as the LAERR bit in the SMBUSSTS reg-

ister.

Table 5.14 Serial EEPROM Read or Write CMD Field Description

Byte

Position Field

Name Description

Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence (Part 2 of 2)

Bit

7Bit

Bit

OPUSA0NAERRLAERROTHERERR 0

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 17 February 22, 2012

Notes

Sample Slave SMBus Operation

This section illustrates sample Slave SMBus operations. Shaded items are driven by the PES24T3G2’s

slave SMBus interface and non-shaded items are driven by an SMBus host.

Figure 5.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled

Figure 5.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC Disabled

5 OTHERERR RC Other Error. This bit is set if a misplaced START or STOP condition is

detected by the master SMBus interface when accessing the serial

EEPROM. This bit has the same function as the OTHERERR bit in the

SMBUSSTS register.

7:6 Reserved 0 Reserved. Must be zero

1. See Table Table 2 in the About This Manual chapter for a definition of these abbreviations.

Bit

Field Name Type1Description

Table 5.14 Serial EEPROM Read or Write CMD Field Description

DATAUU N

DATAUM A

BYTCNT=7

AADDRLCMD (status)

SPES24T3G2 Slave

SMBus Address Wr AABYTCNT=3 ACMD=read AADDRL AADDRU AP

CCODE

START,END

SPES24T3G2 Slave

SMBus Address Wr AA

CCODE

START,END SPES24T3G2 Slave

SMBus Addr e ss Rd

DATALMDATALL

A A A

A N P

ADDRU A

SPES24T3G2 Slave

SMBus Address Wr A N

CCODE

START,END P(PES24T3G2 not ready with data)

SPES24T3G2 Slave

SMBus Addr e ss Wr A A BYTCNT=4 ACMD=read AEEADDR AADDRL A

CCODE

START,END

SPES24T3G2 Slave

SMBus Addr e ss Wr A A

CCODE

START,END SPES24T3G2 Slave

SMBus Addr e ss Rd

ADDRU A

BYTCNT=5

AEEADDRCMD (status)

A A A

DATAADDRU A P

ADDRL A

SPES24T3G2 Slave

SMBus Addr e ss Wr A N

CCODE

START,END P(PE S24 T3G2 not ready with data)

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 18 February 22, 2012

Notes

Figure 5.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled

Figure 5.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled

Figure 5.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled

SPES24T3G2 Slave

SMBus Address Wr AABYTCNT=7 ACMD=write AADDRL AADDRU A

CCODE

START,END

DATALL ADATALM ADATAUM ADATAUU AP

SPES24T3G2 Slave

SMBus Address Wr ACCODE

START,END NP(PES24T3G2 busy with previous command, n ot ready for a new command)

SPES24T3G2 Slave

SMBus Address Wr ACCODE

START,END NP(PES24T3G2 busy with previous command, n ot ready for a new command)

SPES24T3G2 Slave

SMBu s Addr e ss Wr A A BYTCNT=5 ACMD=write AEEADDR AADDRL A

CCODE

START,END

ADDRU ADATA AP

SPES24T3G2 Slave

SMBus Ad dr e ss Wr AABYTCNT=5 ACMD=write AEEADDR AADDRL A

CCODE

START,END

ADDRU ADATA AP

PEC A

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 19 February 22, 2012

Notes

Figure 5.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled

ADDRU

AADDRLCMD (status)

SPES24T3G2 Slave

SMBus Address Wr AACMD=read AADDRL A

CCODE

START, Word

SPES24T3G2 Slave

SMBus Address Wr ACCODE

START,Word

SPES24T3G2 Slave

SMBus Address Rd

DATALMDATALL

A N

SPES24T3G2 Slave

SMBus Address Wr A A ADDRU A

CCODE

END, Byte P

SPES24T3G2 Slave

SMBus Address Wr ACCODE

Byte A

ASPES24T3G2 Slave

SMBus Address Rd A P

SPES24T3G2 Slave

SMBus Address Wr ACCODE

Word A

SPES24T3G2 Slave

SMBus Address Rd AA

SPES24T3G2 Slave

SMBus Address Wr ACCODE

START,Word NP(PE S24 T3G2 n ot ready with data)

DATAUUDATAUM P

SPES24T3G2 Slave

SMBus Address Wr ACCODE

END, Word A

SPES24T3G2 Slave

SMBus Address Rd AA

IDT SMBus Interfaces

PES24T3G2 User Manual 5 - 20 February 22, 2012

Notes

PES24T3G2 User Manual 6 - 1 February 22, 2012

Chapter 6

Power Management

Introduction

Located in configuration space of each PCI-PCI bridge in the PES24T3G2 is a power management

capability structure. The power management capability structure associated with a PCI-PCI bridge of a

downstream port only affects that port. Entering the D3Hot state allows the link associated with the bridge to

enter the L1 state.

–The link associated with a port in the D3Hot state will attemp t to transition into L1 link state irre-

spective of the link or power management state of any other switch port.

The power management capability structure associated w ith the upstream port (i.e., Port 0) affects the

entire device. When the upstream port enters a low power state and the PME_TO_Ack messages are

received, then the entire device is placed into a low power state. The PES24T3G2 supports the foll owing

device power management states: D0 Uninitialized, D0 Active, D3Hot, and D3Cold. A power management

state transition diagram for the states supported by the PES24T3G2 is provided in Figure 6.1 and described

in Table 6.1.

Transitioning a port’s power management state from D3hot to D0uninitialized does not result in any logic

being reset or re-initialization of register values. Thus, the default value of the No Soft Reset

(NOSOFTRST) bit in the PCI Power Management Control and Status (PMCSR) register corresponds to the

functional context being maintained in the D3hot state.

Figure 6.1 PES24T3G2 Power Management State Transition Diagram

Uninitialized

Active

D3hot

Power-On Reset

D3cold

IDT Power Management

PES24T3G2 User Manual 6 - 2 February 22, 2012

Notes

The PES24T3G2 PCI-to-PCI bridges (i.e., ports) have the following behavior when in the D3hot power

management state.

–A bridge accepts, processes, and completes all type 0 configuration read and write requests.

–A bridge accepts and processes all message requests that target the bridge.

–All requests received by the bridge on the primary interface, except as noted above, are treated

as unsupported requests (UR).

–Any error message resulting from the receipt of a TLP is reported in the s ame manner as when

the bridge is not in D3hot (e.g, generation of an ERR_NON FATAL message to the root).

–Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no

error message is generated).

–All completions that target the bridge are treated as unexpected completions (UC).

–Completions flowing in either direction through the bridge are routed as normal. This behavi o r of

the bridge does not differ from that of the bridge when it is in the D0 power management state.

–All request TLPs received on the secondary interface are treated as unsupported requests (UR).

PME Messages

The PES24T3G2 does not support generation of PME messages from the D3cold state. Downstream

ports (i.e., PCI-PCI bridges associated with downstream ports) support the generation of hot-plug PME

events (i.e., a PM_PME power management message) from the D3hot state. This includes both the case

when the downstream port is in the D3hot state or the entire switch is in the D3hot state.

The generation of a PME message by downstream ports necessitates the implementation of a PME

service time-out mechanism to ensure that PME messages are not lost. If the PME S tatus (PMES) bit in the

a downstream port’s PCI Power Management Control and Status (PMCSR) register is not cleared within the

time-out period specified in the PM_PME Time-Out (PMPMETO) field in the ports PM_PME Timer

(PMPMETIMER) register after a PM_PME message is transmitted, then the PM_PME message is retrans-

mitted and the timer is restarted.

PCI-Express Power Management Fence Protocol

The Root complex takes the following steps to turn off power to a system:

–The root places all devices in the D3 state

–Upon entry to D3, all devices transition their links to the L1 state

–The root broadcasts a PME_Turn_Off message.

–Devices acknowledge the PME_Turn_Off message by returning a PME_TO_ACK message.

From State To State Description

any D0 Uninitialized Power-on Fundamental Reset.

D0 Uninitialized D0 Active PCI-PCI bridge configured by software

D0 Active D3hot The Power Management State (PMSTATE) field in the PCI Power Man-

agement Control and Status (PMCSR) register is written with the value

that corresponds to the D3hot state.

D3hot D0 Uninitialized The Power Management State (PMSTATE) field in the PCI Power Man-

agement Control and Status (PMCSR) register is written with the value

that corresponds to D0 state.

D3hott D3cold Power is removed from the device.

Table 6.1 PES24T3G2 Power Management State Transition Diagram

IDT Power Management

PES24T3G2 User Manual 6 - 3 February 22, 2012

Notes

The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any

power management state. When the PES24T3G2 receives a PME_Turn_Off message, it broadcasts the

PME_Turn_Off message on all active downstream ports. The PES24T3G2 transmits a PME_TO_Ack

message on its upstream port and transitions its link state to L2/L3 Ready after it has received a

PME_TO_Ack message on each of its active downstream ports. This process is called PME_TO_Ack

aggregation.

The aggregation of PME_TO_Ack messages on downstream ports is abandoned by the PES24T3G2

when it receives a TLP on its upstream port after it has received a PME_Turn_Off message on that port but

before it has responded with a PM E_TO_Ack message. Once a PME_TO_Ack message has been sched-

uled for transmission on the upstream port and the PME_TO_Ack aggregation process has completed,

received TLPs at that point may be discarded.

If the TLP that causes PME_TO_Ack aggregation to be abandoned targets the PES24T3G2, the

PES24T3G2 responds to the TLP normally. If the TLP that causes aggregation to be abandoned targets a

downstream port and the port is in L0, the TLP is transmitted on the dow nstream port. If the downstream

port is not in L0 (i.e., it is in L2/L3 Ready), the switch transitions the link to Detect and then to L0. Once the

link is reaches L0, the TLP is transmitted on the downstream port.

When PME_TO_Ack aggregation is abandoned, the PES24T3G2 makes no attempt to abandon the

PME_Turn_Off and PME_TO_Ack protocol on downstream ports. Devices downstream from the

PES24T3G2 are allowed to respond with a PME_TO_Ack and transition to L2/L3 Ready. When a TLP is

received that targets the downstream port, the switch transitions the link to Detect and then to L0. Once the

link reaches L0, the TLP is transmitted on the downstream port.

In order to avoid deadlock, a downstream port that does not receive a PME_TO_Ack message in the

time-out period specified in the PME_TO_Ack Time-Out (PMETOATO) field in its corresponding

PME_TO_Ack Timer (PMETOATIMER) register declares a time-out, transitions its link to L2/L3 Ready, and

signals to the upstream port that a PME_TO_Ack message has been received. If instead of being transi-

tioned to the D3cold state the PES24T3G2 is transitioned to the D0uninitialized state, the PES24T3G2

resumes generation of PM_PME messages.

Power Budgeting Capability

The PES24T3G2 contains the mechanisms necessary to implement the PCI-Express power budgeting

enhanced capability. However, by default, these mechanisms are not enabled. To enable the power

budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in

one of the other enhanced capabilities should be initialized to point to the power budgeting capability. The

Next Pointer (NXTPTR) of the power budgeting capability should be adjusted if necessary.

The power budgeting capability c onsists of the four power budgeting c apability registers defined in the

PCIe 2.0 base specification and eight general purpose read-write registers. See section P ower Budgeting

Enhanced Capability on page 8-55 for a description of these registers.

The Power Budgeting Capabilities (PWRBCAP) register contains the PCI-Express enhanced capability

header for the power budgeting capability. By default, this register has an initial read-only value of zero. To

enable the power budgeting capability, this register should be initialized via the serial EEPROM. The Power

Budgeting Data Val ue [0..7] (PWRBDV[0..7) registers are used to hold the power budgeting information for

that port in a particular operating condition.

The PWRBDV registers may be read and written when the Power Budgeting Data Value Unlock

(PWRBDVUL) bit is set in the Switch Control (SWCTL) register . When the PWRBDVUL bit is cleared, these

registers are read-only and writes to these registers are ignored. To enable the power budgeting capability,

the PWRBDV registers should be initialized with power budgeting information via the serial EEPROM.

IDT Power Management

PES24T3G2 User Manual 6 - 4 February 22, 2012

Notes

PES24T3G2 User Manual 7 - 1 February 22, 2012

Chapter 7

Hot-Plug and Hot-Swap

Hot-Plug

As illustrated in Figures 7.1 through 7.3, a PCIe switch may be used in one of three hot-plug configura-

tions. Figure 7.1 illustrates the use of the P ES24T3G2 in an application in which two downstream ports are

connected to slots into which add-in cards may be hot-plugged. Figure 7.2 illustrates the use of the

PES24T3G2 in an add-in card application. Here the downstream por ts are har dwired to devices on the add-

in card and the upstream port serves as the add-in card’s PCIe interface. In this application the upstream

port may be hot-plugged into a slot on the main system. Finally, Figure 7.3 illustrates the use of the

PES24T3G2 in a carrier card application. In this application, the downstream ports are connected to slots

which may be hot-plugged and the entire assembly may be hot-plugged into a slot on the main system.

Since this application requires nothing more than the functionality illustrated in both Figures 7.1 through 7.2,

it will not be discussed further.

Figure 7.1 Hot-Plug on Switch Downstream Slots Application

PES24T3G2

Port 0

Port x

Slot

Port x Port y

Master

SMBus

SMBus I/O

Expander

Port y

Slot

Upstream

Link

Hot-Plug Signals

... ... ...

IDT Hot-Plug and Hot-Swap

PES24T3G2 User Manual 7 - 2 February 22, 2012

Notes

Figure 7.2 Hot-Plug with Switch on Add-In Card Application

Figure 7.3 Hot-Plug with Carrier Card Application

The PCI Express Base Specification revision 1.0a allowed a hot-plug attention indicator , power indicator

and attention button to be located on the board on which the slot is implemented or on the add-in board.

When located on the add-in board, state changes are communicated between the hot-plug controller asso-

ciated with the slot and the add-in card via hot-plug messages. This capability was removed in revision 1.1

of the PCI Express Base Specification and is not supported in the PES24T3G2.

PES24T3G2

Port 0

Port x Port y

Upstream

Link

PCI Express

Device

PCI Express

Device

Add-In Card

... ... ...

PES24T3G2

Port 0

Port x

Slot

Port x Port y

Master

SMBus

SMBus I/O

Expander

Port y

Slot

Upstream

Link

Hot-Plug Signals

Carrier

Card

... ... ...

IDT Hot-Plug and Hot-Swap

PES24T3G2 User Manual 7 - 3 February 22, 2012

Notes

The remainder of this section discusses the use of the PES24T3G2 in an application in which one or

more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a

downstream slot. Associated with each downstream port in the PES24T3G2 is a hot-plug controller. The

hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capabilities (PCIESCAP)

sensor inputs and indicator outputs to be located next to the slot or on the plug in module. Regardless of the

physical location, the indicators are controlled by the PES24T3G2’s downstream port.

Tabl e 7.1 lis ts the hot-plug inputs and outputs that may be associated with a slot. W hen enabled during

configuration in the PCIESCAP register, these inputs and outputs ar e made available to external logic using

an external I/O expander located on the master SMBus interface. When the IO E xpander is initiali zed (i.e.,

the HPC bit in the port’s PCIESCAP register transitions from 0 to 1, or the IOEXPADDR field in the

IOEXPADDR0 register is written to), the hot-plug controller for the corresponding port initiates an SMBus

access to configure the IO Expander and updates the status bits in the PCI Express Slot Status

(PCIESSTS) register. During this initial access, the Presence Detect Changed (PDC) and MRL Sensor

Changed (MRLSC) bits in the PCIESSTS register are not set, since this access is used to determine the

initial state of the IO Expander signals.

The PES24T3G2 supports presence detect signalling via assertion of the Presence Detect Input signal

in the external I/O Expander module and through “in-band” presence detect. The Presence D etect Control

(PDETECT) field in the Hot-Plug Configuration Control (HPCFGCTL) register may be used to control the

mechanism used for presence detect.

Since the polarity of hot-plug signals has been defined dif ferently in various specifications, each hot plug

signal has a corresponding control bit in the Hot-Plug Configuration Control (HPCFGCTL) that allows the

polarity of that signal to be inverted. Inversion affects the corresponding signal in all ports. When a one is

written to the EIC bit in the PCIESCTL register, then the PxILOCKP signal is pulsed for a length greater

than 100 ms and less than 150 ms (i.e., it transactions from negated to asserted, maintains an asserted

state for 100 to 150 ms, and then transitions back to negated). When the Toggle Electromechanical Inter-

lock Control. (TEMICTL) bit in the HPCFGCTL register is set, writing a one to the EIC bit inverts the state of

the PxILOCKP signal.

When the Replace MRL Status with EMIL Status (RMRLWEMIL) bit is set in the HPCFGCTL register,

the port’s PxMRLN input is used as the electromechanical state input. The state of this input is used as the

state of the electromechanical interlock state obtained by reading the Electromechanical Interlock Status

(EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode, the state of the Manually-oper-

Signal Type Name/Description

PxAPN I Port x1 Attention Push button Input.

1. x corresponds to downstream port number (i.e., 1 through 7).

PxPDN I Port x Presence Detect Input.

PxPFN I Port x Power Fault Input.

PxMRLN I Port x Manually-o perated Retention Latch (MRL) Input.

PxAIN O Port x Attenti on Indicator Output.

PxPIN O Port x Power Indicator Output.

PxPEP O Port x Power Enable Output.

PxILOCKP O Port x Electromechanical Interlock.

PxPWRGDN I Port x Power Good Input (asserted when slot power is good).

PxRSTN2

2. This signal is a GPIO pin alternate function and is not available as an I/O expander output.

OPort x Reset Output.

Table 7.1 Downstream Port Hot Plug Signals

IDT Hot-Plug and Hot-Swap

PES24T3G2 User Manual 7 - 4 February 22, 2012

Notes

ated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the

RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of the

corresponding PxILOCKP I/O expander signal output.

When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the

Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register,

power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This

occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control

(PCIESCTL) register.

The state of a port’s Power Fault (PxPFN) input is not latched by the PES24T3G2. For proper operation

the system designer should ensure that once the PxPFN signal is asserted, it remains asserted until the

power enable (PxPEP) signal is toggled. This is required adapter behavior for the PCI Express Express-

Module form factor.

Downstream port reset outputs are described in section Downstream Port Reset Outputs on page 2-7.

The default value of hot-plug registers following a hot or fundamental reset may be configured via serial

EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization,

the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result

of serial EEPROM initialization. Following a Hot-Reset to the Entire Device (see section Hot Reset on page

2-5) or an Upstream Secondary Bus Hot-Reset (see section Upstream Secondary Bus Reset on page 2-6),

each downstream port’s PHY will transition the links to the Hot-Reset state and subsequently re-train the

link starting from the Detect state. When this occurs, the Hot-Plug controller for the port does not set the

Presence Detect Changed (PDC) bit in the PCIESSTS register.

Hot-Plug I/O Expander

The PES24T3G2 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus inter-

face for hot-plug related signals associated with downstream ports. See section I/O Expanders on page 5-7

for details on the operation of the I/O expanders and for the mapping of downstream hot-plug signals to I/O

expander inputs and outputs.

Hot-Plug Interrupts and Wake- up

The hot-plug controller associated with a downstream slot may generate an interrupt or wakeup event.

Hot-plug interrupts are only generated when the Hot Plug Interrupt Enable (HPIE) bit is set in the corre-

sponding port’s PCI Express Slot Control (PCIESCTL) register. The following bits, when set in the PCI

Express Slot Status (PCIESSTS) register, generate an interrupt if not masked by the corresponding bit in

the PCI Express Slot Control (PCIESCTL) register or by the HPIE bit:

–Attention Button Pressed (ABP)

–Power Fault Detected (PFD)

–MRL Sensor Changed (MRLSC)

–Presence Detected Changed (PDC)

–Command Completed (CC).

When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable

(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command

(PCICMD) register . When the downstream port or the entire switch is in a D3hot state, the hot-plug controller

generates a wakeup event using a PM_PME message instead of an interrupt if the event interrupt is not

masked in the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE bit. If the

event interrupt is not masked and hot-plug interrupts are enabled, both a PM_PME and an interrupt are

generated. If the event interrupt is masked, then neither a PM_PME nor an interrupt is generated. Note that

a command completed (CC bit) interrupt will not generate a wakeup event.

IDT Hot-Plug and Hot-Swap

PES24T3G2 User Manual 7 - 5 February 22, 2012

Notes

Legacy System Hot-Plug Support

Some systems require support for operating systems that lack PCIe hot-plug support. The PES24T3G2

supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of

GPIO[7] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hot-

plug. Associated with each downstream port’s hot-plug controller is a bit in the General Purpose Event

Control (P0_GPECTL) register. When this bit i s set, then the corresponding PCIe base 1.1 hot plug event

notification mechanisms are disabled for that port and INTx, MSI and PME events wil l not be generated by

that port due to hot-plug events. Instead, hot-plug events are signaled through assertion of the GPEN

signal. GPEN is an alternate function of GPIO[7] and GP IO[7] will not be ass erted when GP EN is asserted

unless it is configured to operate as an alternate function.

Whenever a port signals a hot-plug event through assertion of the GPEN signal, the corresponding

port’s status bit in the General Purpose Event Status (P0_GPESTS) register is set. A bit in the P0_GPESTS

using the general purpose event (GPEN) signal assertion mechanism. The hot-plug event signalling mech-

anism is the only thing that is affected when a port is configured to use general purpose events instead of

the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MS I and PME). Thus, the PCIe defined capa-

bility, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as

normal and all other hot-plug functionality associated with the port remains unchanged. INTx, M SI and PME

events from other sources are also unaffected.

The enhanced hot-plug signalling mechanism supported by the PES24T3G2 is graphically illustrated in

Figure 7.4. This figure provides a conceptual summary of the enhanced hot-plug signalling mechanism in

the form of a pseudo logic diagram. Logic gates in this diagram are intended for conveying general

concepts, and not for direct implementation.

IDT Hot-Plug and Hot-Swap

PES24T3G2 User Manual 7 - 6 February 22, 2012

Notes

Figure 7.4 PES24T3G2 Hot-Plug Event Signalling

Hot-Swap

The PES24T3G2 is hot-swap capable and meets the following requirements:

–All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.)

–All I/O cells function predictably from early power . Th is means that the device is able to tolerate a

non-monotonic ramp-up as well as a rapid ramp-up of the DC power.

–All I/O cells are able to tolerate a precharge voltage

–Since no clock is present during physical connection, the device will maintain all outputs in a high-

impedance state even when no clock is present.

–The I/O cells meet VI requirements for hot-swap.

–The I/O cells respect the required leakage current limits over the entire input voltage range.

In summary, the PES24T3G2 meets all of the I/O requirements necessary to build a PICMG compliant

hot-swap board or system. The hot-swap I/O buffers of the PES24T3G2 may also be used to construct

proprietary hot-swap systems. See the PES24T3G2 Data Sheet for a detailed specification of I/O buffer

characteristics.

Command

Completed

RW1C

Attention Button

Pressed

Power Fault

Detected

MRL Sensor State

Changed

Presence Detected

Changed

Data Link Layer

State Changed

Command

Complete d Enable

Attention Button

Pressed Enable

Power Fault

Detected Enable

MRL Sensor State

Changed Enable

Presence Detected

Changed Enable

Data Link Layer

State Changed Enable

RW1C

PME E nab le

Bit

RW Activate Wak eup

Mechanism

Hot-Plug Interrupt

Enable

MSI Enable

Activate MSI

Mechanism

Acti va te IN Tx

Mechanism

Interrupt

Disable

General Purpose Event

Enable

Gene ral Purpose

Event Mechanism

Slot Control

Slot Status

Bit

Notes

PES24T3G2 User Manual 8 - 1 February 22, 2012

Chapter 8

Configuration Registers

Configuration Space Organization

Each software visible register in the PES24T3G2 is contained in the P CI configuration space of one of

the ports. Thus, there are no registers in the PES24T3G2 that cannot be accessed by the root. Each soft-

ware visible register in the PES24T3G2 has a system address. The system address is formed by adding the

PCI configuration space offset value of the register to the base address of the port in which it is located. The

system address is used for serial EEPROM register initialization and slave SMBus register accesses.

The base address for each PES24T3G2 port is listed in Table 8.1. The PCI configuration space offset

addresses for registers in the upstream port are listed in Table 8.2 while the PCI configuration s pace offset

addresses for registers in downstream ports are listed Table 8.3.

As shown in Figure 8.1, upstream and downstream ports share a similar PCI configuration space

registers which are not present in the configuration space of dow nstream ports. Because of their ability to

generate MSIs as a result of hot-plug events, the downstream ports contain an MSI capability structure. The

upstream port also supports MSI Capability structure to report internal memory errors. Since memory error

reporting via interrupts is an optional capability, the MSI capability s tructure associated w ith the upstream

port is not by default part of the PCI capability structure linked list.

Reading from an upstream port offset not defined in Table 8.2 or a downstream offset not defined in

Table 8.3 returns a value of zero. Writes to such an offset complete successfully but modify no data and

have no other effect.

Software visible configuration registers exist with one or more fields that perform a side-effect action

when written. These side-effect actions may af fect the ability of the switch to respond with a completion. For

example, writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register initiates a hot

reset of the entire switch. Other examples are the FRST bit in SWC TL, the Link-Disable (LDIS) and Link-

Retrain (LRET) bits in the PCI Express Link Control register, as well as the Full Link R etrain (FLRET) field

that in the PHY Link State 0 (PHYLSTATE0) register. A configuration write to such a register returns a

completion to the Root before the side-effect action is performed. This is implemented by delaying the side-

effect action by 1 ms following generation of the completi on. Thus, if the completion is not accepted by the

upstream port link partner in this time interval, then the completion will be l ost.

Base

Address PCI Configuration Space

0x0000 Port 0 configuration space (upstream port)

0x2000 Port 2 configuration space (downstream port)

0x4000 Port 4 configuration space (downstream port)

Table 8.1 Base Addresses for Port Configuration Space Register

IDT Configuration Registers

PES24T3G2 User Manual 8 - 2 February 22, 2012

Notes

Figure 8.1 Port Configuration Space Organization

Upstream Port (Port 0)

Cfg.

Offset Size Register

Mnemonic Register Definition

0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 8-10

0x002 Word P0_DID DID - Device Identification Register (0x002) on page 8-10

0x004 Word P0_PCICMD PCICMD - PCI Command Register (0x004) on page 8-10

0x006 Word P0_PCISTS PCISTS - PCI Status Register (0x006) on page 8-11

0x008 Byte P0_RID RID - Revision Identification Register (0x008) on page 8-12

0x009 3 Bytes P0_CCODE CCODE - Class Code Register (0x009) on page 8-12

0x00C Byte P0_CLS CLS - Cache Line Size Register (0x00C) on page 8-13

0x00D Byte P0_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-13

Table 8.2 Upstream Port 0 Configuration Space Registers (Part 1 of 5)

PCI

Configuration Space

(64 DWords)

Phy Layer Control

& Status Registers

Switch Control

& Status Registers

Power Budgeting

Enhanced Capability

PCIe Virtual Channel

Enhanced Capability

Device Serial Number

Enhanced Capability

Advanced Error Reporting

Enhanced Capability

0x000

0x040

0x0D0

0x0F0

T ype 1

Configuration Header

PCI Express

Capability Structure

Extended Config Access

MSI

Capability Structure

0x0FF

0x100

0x000

0x180

0x200

0x280

0x400

0x4E0

0x500

0xFFF

0x0C0 PCI Power Manageme nt

Capability Structure

Reserved

0x560

SSID/SSVID

Reserved

IDT Configuration Registers

PES24T3G2 User Manual 8 - 3 February 22, 2012

Notes

0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 8-13

0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13

0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13

0x014 DWord P0_BAR1 BAR1 - Base Address Register 1 (0x014) on page 8-14

0x018 Byte P0_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 8-14

0x019 Byte P0_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 8-14

0x01A Byte P0_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 8-14

0x01B Byte P0_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 8-14

0x01C Byte P0_IOBASE IOBASE - I/O Base Register (0x01C) on page 8-15

0x01D Byte P0_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 8-15

0x01E Word P0_SECSTS SECSTS - Secondary Status Register (0x01E) on page 8-15

0x020 Word P0_MBASE MBASE - Memory Base Register (0x020) on page 8-16

0x022 Word P0_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 8-16

0x024 Word P0_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 8-

0x026 Word P0_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 8-17

0x028 DWord P0_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on

page 8-17

0x02C DWord P0_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on

page 8-17

0x030 Word P0_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 8-17

0x032 Word P0_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 8-18

0x034 Byte P0_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 8-18

0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on

page 8-18

0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 8-18

0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 8-19

0x03E Word P0_BCTL BCTL - Bridge Control Register (0x03E) on page 8-19

0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 8-20

0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 8-21

0x048 Word P0_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 8-22

0x04A Word P0_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 8-23

0x04C DWord P0_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 8-24

0x050 Word P0_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 8-25

0x052 Word P0_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 8-27

0x064 DWord P0_PCIEDCAP2 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) on page 8-

0x068 Word P0_PCIEDCTL2 PCIEDCTL2 - PCI Express Device Control 2 (0x068) on page 8-33

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.2 Upstream Port 0 Configuration Space Registers (Part 2 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 4 February 22, 2012

Notes

0x06A Word P0_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 8-33

0x06C DWord P0_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page 8-33

0x070 Word P0_PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 8-33

0x072 Word P0_PCIELSTS2 PCIELSTS2 - PCI Express Link Status 2 (0x072) on page 8-35

0x0C0 DWord P0_PMCAP PMCAP - PCI Power Management Capabilities (0x0C0) on page 8-36

0x0C4 DWord P0_PMCSR PMCSR - PCI Power Management Control and Status (0x0C4) on

page 8-37

0x0D0 DWord P0_MSICAP MSICAP - Message Signaled Interrupt Capability and Control

(0x0D0) on page 8-37

0x0D4 DWord P0_MSIADDR MSIADDR - Message Signaled Interrupt Address (0x0D4) on page 8-

0x0D8 DWord P0_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) on

page 8-38

0x0DC DWord P0_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) on

page 8-39

0x0F0 Dword P0_SSIDSSVIDCA

PSSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capabil-

ity (0x0F0) on page 8-39

0x0F4 Dword P0_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on

page 8-39

0x0F8 Dword P0_ECFGADDR ECFGADDR - Extended Configuration Space Access Address

(0x0F8) on page 8-39

0x0FC Dword P0_ECFGDATA ECFGDATA - Extended Configuration Space Access Data (0x0FC)

on page 8-40

0x100 Dword P0_AERCAP AERCAP - AER Capabilities (0x100) on page 8-40

0x104 Dword P0_AERUES AERUES - AER Uncorrectable Error Status (0x104) on page 8-40

0x108 Dword P0_AERUEM AERUEM - AER Uncorrectable Error Mask (0x108) on page 8-41

0x10C Dword P0_AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 8-44

0x110 Dword P0_AERCES AERCES - AER Correctable Error Status (0x110) on page 8-45

0x114 Dword P0_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 8-46

0x118 Dword P0_AERCTL AERCTL - AER Control (0x118) on page 8-47

0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 8-

0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 8-

0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page 8-

0x128 Dword P0_AERHL4DW AERHL4DW - AER Header Log 4th Doubleword (0x128) on page 8-

0x180 Dword P0_SNUMCAP SNUMCAP - Serial Number Capabilities (0x180) on page 8-48

0x184 Dword P0_SNUMLDW SNUMLDW - Serial Number Lower Doubleword (0x184) on page 8-48

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.2 Upstream Port 0 Configuration Space Registers (Part 3 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 5 February 22, 2012

Notes

0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 8-

0x200 DWord P0_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header

(0x200) on page 8-49

0x204 DWord P0_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 8-49

0x208 DWord P0_PVCCAP2 PVCCAP2- Port VC Capability 2 (0x208) on page 8-50

0x20C Word P0_PVCCTL PVCCTL - Port VC Control (0x20C) on page 8-50

0x20E Word P0_PVCSTS PVCSTS - Port VC Status (0x20E) on page 8-50

0x210 DWord P0_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 8-51

0x214 DWord P0_VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 8-51

0x218 DWord P0_VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 8-52

0x220 DWord P0_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220) on

page 8-53

0x224 DWord P0_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224) on

page 8-53

0x228 DWord P0_VCR0TBL2 VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228) on

page 8-54

0x22C DWord P0_VCR0TBL3 VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C) on

page 8-54

0x280 Dword P0_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 8-55

0x284 Dword P0_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 8-55

0x288 Dword P0_PWRBD PWRBD - Power Budgeting Data (0x288) on page 8-56

0x28C Dword P0_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on

page 8-56

0x300 Dword P0_PWRBDV0 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x304 Dword P0_PWRBDV1 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x308 Dword P0_PWRBDV2 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x30C Dword P0_PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x310 Dword P0_PWRBDV4 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x314 Dword P0_PWRBDV5 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x318 Dword P0_PWRBDV6 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x31C Dword P0_PWRBDV7 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x400 DWord SWSTS SWSTS - Switch Status (0x400) on page 8-56

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.2 Upstream Port 0 Configuration Space Registers (Part 4 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 6 February 22, 2012

Notes

Downstream Ports

0x404 DWord SWCTL SWCTL - Switch Control (0x404) on page 8-57

0x408 DWord HPCFGCTL HPCFGCTL - Hot-Plug Configuration Control (0x408) on page 8-60

0x418 DWord GPIOFUNC GPIOFUNC - General Purpose I/O Control Function (0x418) on page

8-61

0x41C DWord GPIOCFG GPIOCFG - General Purpose I/O Configuration (0x41C) on page 8-62

0x420 DWord GPIOD GPIOD - General Purpose I/O Data (0x420) on page 8-62

0x424 DWord SMBUSSTS SMBUSSTS - SMBus Status (0x424) on page 8-62

0x428 DWord SMBUSCTL SMBUSCTL - SMBus Control (0x428) on page 8-63

0x42C DWord EEPROMINTF EEPROMINTF - Serial EEPROM Interface (0x42C) on page 8-64

0x430 DWord IOEXPINTF IOEXPINTF - I/O Expander Interface (0x430) on page 8-65

0x434 DWord IOEXPADDR0 IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434) on page 8-

0x438 DWord IOEXPADDR1 IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438) on page 8-

0x450 DWord GPECTL GPECTL - General Purpose Event Control (0x450) on page 8-66

0x454 DWord GPESTS GPESTS - General Purpose Event Status (0x454) on page 8-67

0x500 Dword P0_SERDESCTL SERDESCTL- SerDes Control (0x500) on page 8-67

0x530 Dword P0_PHYLCFG0 PHYLCFG0 - Phy Link Configuration 0 (0x530) on page 8-68

0x538 Dword P0_PHYLSTS0 PHYLSTS0 - Phy Link Status 0 (0x538) on page 8-69

0x540 Dword P0_PHYLSTATE0 PHYLSTATE0 - Phy Link State 0 (0x540) on page 8-70

0x55C Dword P0_PHYPRBS PHYPRBS - Phy PRBS Seed (0x55C) on page 8-71

0x560 Dword P0_ALRCTL ALRCTL - Autonomous Link Reliability Control (0x560) on page 8-71

0x564 Dword P0_ALRSTS ALRSTS - Autonomous Link Reliability Status (0x564) on page 8-72

0x568 Dword P0_ALRERT ALRERT - Autonomous Link Reliability Error Rate Threshold

(0x5680) on page 8-72

0x56C Dword P0_ALRCNT ALRCNT - Autonomous Link Reliability Counter (0x56C) on page 8-

Cfg.

Offset Size Register

Mnemonic Register Definition

0x000 Word Px_VID VID - Vendor Identification Register (0x000) on page 8-10

0x002 Word Px_DID DID - Device Identification Register (0x002) on page 8-10

0x004 Word Px_PCICMD PCICMD - PCI Command Register (0x004) on page 8-10

0x006 Word Px_PCISTS PCISTS - PCI Status Register (0x006) on page 8-11

0x008 Byte Px_RID RID - Revision Identification Register (0x008) on page 8-12

0x009 3 Bytes Px_CCODE CCODE - Class Code Register (0x009) on page 8-12

Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers (Part 1 of 5)

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.2 Upstream Port 0 Configuration Space Registers (Part 5 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 7 February 22, 2012

Notes

0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 8-13

0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-13

0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 8-13

0x00F Byte Px_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13

0x010 DWord Px_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13

0x014 DWord Px_BAR1 BAR1 - Base Address Register 1 (0x014) on page 8-14

0x018 Byte Px_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 8-14

0x019 Byte Px_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 8-14

0x01A Byte Px_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 8-14

0x01B Byte Px_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 8-14

0x01C Byte Px_IOBASE IOBASE - I/O Base Register (0x01C) on page 8-15

0x01D Byte Px_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 8-15

0x01E Word Px_SECSTS SECSTS - Secondary Status Register (0x01E) on page 8-15

0x020 Word Px_MBASE MBASE - Memory Base Register (0x020) on page 8-16

0x022 Word Px_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 8-16

0x024 Word Px_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 8-

0x026 Word Px_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 8-17

0x028 DWord Px_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on

page 8-17

0x02C DWord Px_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on

page 8-17

0x030 Word Px_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 8-17

0x032 Word Px_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 8-18

0x034 Byte Px_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 8-18

0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on

page 8-18

0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 8-18

0x03D Byte Px_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 8-19

0x03E Word Px_BCTL BCTL - Bridge Control Register (0x03E) on page 8-19

0x040 DWord Px_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 8-20

0x044 DWord Px_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 8-21

0x048 Word Px_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 8-22

0x04A Word Px_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 8-23

0x04C DWord Px_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 8-24

0x050 Word Px_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 8-25

0x052 Word Px_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 8-27

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers (Part 2 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 8 February 22, 2012

Notes

0x054 DWord Px_PCIESCAP PCIESCAP - PCI Express Slot Capabilities (0x054) on page 8-28

0x058 Word Px_PCIESCTL PCIESCTL - PCI Express Slot Control (0x058) on page 8-30

0x05A Word Px_PCIESSTS PCIESSTS - PCI Express Slot Status (0x05A) on page 8-31

0x064 DWord Px_PCIEDCAP2 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) on page 8-

0x068 Word Px_PCIEDCTL2 PCIEDCTL2 - PCI Express Device Control 2 (0x068) on page 8-33

0x06A Word Px_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 8-33

0x06C DWord Px_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page 8-33

0x070 Word Px_PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 8-33

0x072 Word Px_PCIELSTS2 PCIELSTS2 - PCI Express Link Status 2 (0x072) on page 8-35

0x074 DWord Px_PCIESCAP2 PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) on page 8-35

0x078 Word Px_PCIESCTL2 PCIESCTL2 - PCI Express Slot Control 2 (0x078) on page 8-35

0x07A Word Px_PCIESSTS2 PCIESSTS2 - PCI Express Slot Status 2 (0x07A) on page 8-36

0x0C0 DWord Px_PMCAP PMCAP - PCI Power Management Capabilities (0x0C0) on page 8-36

0x0C4 DWord Px_PMCSR PMCSR - PCI Power Management Control and Status (0x0C4) on

page 8-37

0x0D0 DWord Px_MSICAP MSICAP - Message Signaled Interrupt Capability and Control

(0x0D0) on page 8-37

0x0D4 DWord Px_MSIADDR MSIADDR - Message Signaled Interrupt Address (0x0D4) on page 8-

0x0D8 DWord Px_MSIUADDR MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) on

page 8-38

0x0DC DWord Px_MSIMDATA MSIMDATA - Message Signaled Interrupt Message Data (0x0DC) on

page 8-39

0x0F0 Dword Px_SSIDSSVID

CAP SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capabil-

ity (0x0F0) on page 8-39

0x0F4 Dword Px_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on

page 8-39

0x0F8 Dword Px_ECFGADDR ECFGADDR - Extended Configuration Space Access Address

(0x0F8) on page 8-39

0x0FC Dword Px_ECFGDATA ECFGDATA - Extended Configuration Space Access Data (0x0FC)

on page 8-40

0x100 Dword Px_AERCAP AERCAP - AER Capabilities (0x100) on page 8-40

0x104 Dword Px_AERUES AERUES - AER Uncorrectable Error Status (0x104) on page 8-40

0x108 Dword Px_AERUEM AERUEM - AER Uncorrectable Error Mask (0x108) on page 8-41

0x10C Dword Px_AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 8-44

0x110 Dword Px_AERCES AERCES - AER Correctable Error Status (0x110) on page 8-45

0x114 Dword Px_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 8-46

0x118 Dword Px_AERCTL AERCTL - AER Control (0x118) on page 8-47

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers (Part 3 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 9 February 22, 2012

Notes

0x11C Dword Px_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 8-

0x120 Dword Px_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 8-

0x124 Dword Px_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page 8-

0x128 Dword Px_AERHL4DW AERHL4DW - AER Header Log 4th Doubleword (0x128) on page 8-

0x180 Dword Px_SNUMCAP SNUMCAP - Serial Number Capabilities (0x180) on page 8-48

0x184 Dword Px_SNUMLDW SNUMLDW - Serial Number Lower Doubleword (0x184) on page 8-48

0x188 Dword Px_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 8-

0x200 DWord Px_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header

(0x200) on page 8-49

0x204 DWord Px_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 8-49

0x208 DWord Px_PVCCAP2 PVCCAP2- Port VC Capability 2 (0x208) on page 8-50

0x20C Word Px_PVCCTL PVCCTL - Port VC Control (0x20C) on page 8-50

0x20E Word Px_PVCSTS PVCSTS - Port VC Status (0x20E) on page 8-50

0x210 DWord Px_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 8-51

0x214 DWord Px_VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 8-51

0x218 DWord Px_VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 8-52

0x280 Dword Px_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 8-55

0x284 Dword Px_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 8-55

0x288 Dword Px_PWRBD PWRBD - Power Budgeting Data (0x288) on page 8-56

0x28C Dword Px_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on

page 8-56

0x300 Dword Px_PWRBDV0 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x304 Dword Px_PWRBDV1 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x308 Dword Px_PWRBDV2 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x30C Dword Px_PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x310 Dword Px_PWRBDV4 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x314 Dword Px_PWRBDV5 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x318 Dword Px_PWRBDV6 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers (Part 4 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 10 February 22, 2012

Notes

Type 1 C onfiguration Header Registers

VID - Vendor Identification Register (0x000)

DID - Device Identification Register (0x002)

PCICMD - PCI Command Register (0x004)

0x31C Dword Px_PWRBDV7 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

on page 8-56

0x500 Dword Px_SERDESCTL SERDESCTL- SerDes Control (0x500) on page 8-67

0x530 Dword Px_PHYLCFG0 PHYLCFG0 - Phy Link Configuration 0 (0x530) on page 8-68

0x538 Dword Px_PHYLSTS0 PHYLSTS0 - Phy Link Status 0 (0x538) on page 8-69

0x540 Dword Px_PHYLSTATE0 PHYLSTATE0 - Phy Link State 0 (0x540) on page 8-70

0x55C Dword Px_PHYPRBS PHYPRBS - Phy PRBS Seed (0x55C) on page 8-71

0x560 Dword Px_ALRCTL ALRCTL - Autonomous Link Reliability Control (0x560) on page 8-71

0x564 Dword Px_ALRSTS ALRSTS - Autonomous Link Reliability Status (0x564) on page 8-72

0x568 Dword Px_ALRERT ALRERT - Autonomous Link Reliability Error Rate Threshold

(0x5680) on page 8-72

0x56C Dword Px_ALRCNT ALRCNT - Autonomous Link Reliability Counter (0x56C) on page 8-

Bit

Field Field

Name Type Default

Value Description

15:0 VID RO 0x111D Vendor Identification. This field contains the 16-bit vendor ID

value assigned to IDT.

See section Vendor ID on page 1-4.

Bit

Field Field

Name Type Default

Value Description

15:0 DID RO - Device Identification. This field contains the 16-bit device ID

assigned by IDT to this bridge.

See section Device ID on page 1-5.

Bit

Field Field

Name Type Default

Value Description

0IOAERW0x0I/O Access Enable. When this bit is cleared, the bridge does not

respond to I/O accesses from the primary bus specified by

IOBASE and IOLIMIT.

0x0 - (disable) Disable I/O space.

0x1 - (enable) Enable I/O space.

Cfg.

Offset Size Register

Mnemonic Register Definition

Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers (Part 5 of 5)

IDT Configuration Registers

PES24T3G2 User Manual 8 - 11 February 22, 2012

Notes

PCISTS - PCI Status Register (0x006)

1MAERW0x0Memory Access Enable. When this bit is cleared, the bridge

does not respond to memory and prefetchable memory space

access from the primary bus specified by MBASE, MLIMIT,

PMBASE and PMLIMIT.

0x0 - (disable) Disable memory space.

0x1 - (enable) Enable memory space.

2BMERW0x0Bus Master Enable. When this bit is cleared, the bridge does not

issue requests (e.g., memory, I/O and MSIs since they are in-

band writes) on behalf of subordinate devices and handles these

as Unsupported Requests (UR). Additionally, the bridge handles

non-posted transactions in the upstream direction with a Unsup-

ported Request (UR) completion. This bit does not affect comple-

tions in either direction or the forwarding of non memory or I/O

requests.

0x0 - (disable) Disable request forwarding.

0x1 - (enable) Enable request forwarding.

3 SSE RO 0x0 Special Cycle Enable. Not applicable.

4MWIRO0x0Memory Write Invalidate. Not applicable.

5VGASRO0x0VGA Palette Snoop. Not applicable.

6 PERRE RW 0x0 Parity Error Enable. Not applicable.

7ADSTEPRO 0x0Address Data Stepping. Not applicable.

8 SERRE RW 0x0 SERR Enable. Non-fatal and fatal errors detected by the bridge

are reported to the Root Complex when this bit is set or the bits in

the PCI Express Device Control register are set (see PCIEDCTL

- PCI Express Device Control (0x048)).

In addition, when this bit is set it enables the forwarding of

ERR_NONFATAL and ERR_FATAL error messages from the

secondary to the primary interface. ERR_COR messages are

unaffected by this bit and are always forwarded.

0x0 -(disable) Disable non-fatal and fatal error reporting if also

disabled in Device Control register.

0x1 -(enable) Enable non-fatal and fatal error reporting.

9FB2BRO0x0Fast Back-to-Back Enable. Not applicable.

10 INTXD RW 0x0 INTx Disable. Controls the ability of the PCI-PCI bridge to gener-

ate an INTx interrupt message.

When this bit is set, any interrupts generated by this bridge are

negated. This may result in a change in the resolved interrupt

state of the bridge.

This bit has no effect on interrupts forwarded from the secondary

to the primary interface.

15:11 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

2:0 Reserved RO 0x0 Reserved.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 12 February 22, 2012

Notes

RID - Revision Identification Register (0x008)

CCODE - Class Code Register (0x009)

3INTSRO0x0INTx Status. This bit is set when an INTx interrupt is pending

from the device.

INTx emulation interrupts forwarded by switch ports from devices

downstream of the bridge are not reflected in this bit.

For downstream ports, this bit is set if an interrupt has been

“asserted” by the corresponding port’s hot-plug controller.

For upstream ports, this bit is set if internal memory error is

detected and the memory error reporting is not masked.

4 CAPL RO 0x1 Capabilities List. This bit is hardwired to one to indicate that the

bridge implements an extended capability list item.

5 C66MHZ RO 0x0 66 MHz Capable. Not applicable.

6 Reserved RO 0x0 Reserved.

7FB2BRO0x0Fast Back-to-Back (FB2B). Not applicable.

8 MDPED RO 0x0 Master Data Parity Error Detected. Not applicable.

10:9 DEVT RO 0x0 DEVSEL# TIming. Not applicable.

11 STAS RO 0x0 Signalled Target Abort. Not applicable since a target abort is

never signalled.

12 RTAS RO 0x0 Received Target Abort. Not applicable.

13 RMAS RO 0x0 Received Master Abort. Not applicable.

14 SSE RW1C 0x0 Signalled System Error. This bit is set when the bridge sends a

ERR_FATAL or ERR_NONFATAL message and the SERR

Enable (SERRE) bit is set in the PCICMD register.

0x0 -(noerror) no error.

0x1 - (error) This bit is set when a fatal or non-fatal error is sig-

nalled.

15 DPE RW1C 0x0 Detected Parity Error. This bit is set by the bridge whenever it

receives a poisoned TLP on the primary side regardless of the

state of the PERRE bit in the PCI Command register.

Bit

Field Field

Name Type Default

Value Description

7:0 RID RWL - Revision ID. This field contains the revision identification number

for the device.

See section Revision ID on page 1-5.

Bit

Field Field

Name Type Default

Value Description

7:0 INTF RO 0x00 Interface. This value indicates that the device is a PCI-PCI

bridge that does not support subtractive decode.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 13 February 22, 2012

Notes

CLS - Cache Line Size Register (0x00C)

PLTIMER - Primary Latency Timer (0x00D)

HDR - Header Type Register (0x00E)

BIST - Built-in Self Test Register (0x00F)

BAR0 - Base Address Register 0 (0x010)

15:8 SUB RO 0x04 Sub Class Code. This value indicates that the device is a PCI-

PCI bridge.

23:16 BASE RO 0x06 Base Class Code. This value indicates that the device is a

bridge.

Bit

Field Field

Name Type Default

Value Description

7:0 CLS RW 0x00 Cache Line Size. This field has no effect on the bridge’s func-

tionality but may be read and written by software.

This field is implemented for compatibility with legacy software.

Bit

Field Field

Name Type Default

Value Description

7:0 PLTIMER RO 0x00 Primary Latency Timer. Not applicable.

Bit

Field Field

Name Type Default

Value Description

7:0 HDR RO 0x01 Header Type. This value indicates a type 1 header with a single

function bridge layout.

Bit

Field Field

Name Type Default

Value Description

7:0 BIST RO 0x0 BIST. This value indicates that the bridge does not implement

BIST.

Bit

Field Field

Name Type Default

Value Description

31:0 BAR RO 0x0 Base Address Register. Not applicable.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 14 February 22, 2012

Notes

BAR1 - Base Address Register 1 (0x014)

PBUSN - Primary Bus Number Register (0x018)

SBUSN - Secondary Bus Number Register (0x019)

SUBUSN - Subordinate Bus Number Register (0x01A)

SLTIMER - Secondary Latency Timer Register (0x01B)

Bit

Field Field

Name Type Default

Value Description

31:0 BAR RO 0x0 Base Address Register. Not applicable.

Bit

Field Field

Name Type Default

Value Description

7:0 PBUSN RW 0x0 Primary Bus Number. This field is used to record the bus num-

ber of the PCI bus segment to which the primary interface of the

bridge is connected.

This field has no functional effect within the PES24T3G2 but is

implemented as a read/write register for software compatibility

Bit

Field Field

Name Type Default

Value Description

7:0 SBUSN RW 0x0 Secondary Bus Number. This field is used to record the bus

number of the PCI bus segment to which the secondary interface

of the bridge is connected.

Bit

Field Field

Name Type Default

Value Description

7:0 SUBUSN RW 0x0 Subordinate Bus Number. The Subordinate Bus Number regis-

ter is used to record the bus number of the highest numbered PCI

bus segment which is behind (or subordinate to) the bridge.

Bit

Field Field

Name Type Default

Value Description

7:0 SLTIMER RO 0x0 Secondary Latency Timer. Not applicable.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 15 February 22, 2012

Notes

IOBASE - I/O Base Register (0x01C)

IOLIMIT - I/O Limit Register (0x01D)

SECSTS - Secondary Status Register (0x01E)

Bit

Field Field

Name Type Default

Value Description

0IOCAPRWL0x1I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O

addressing.

0x0 - (io16) 16-bit I/O addressing.

0x1 - (io32) 32-bit I/O addressing.

3:1 Reserved RO 0x0 Reserved field.

7:4 IOBASE RW 0xF I/O Base. The IOBASE and IOLIMIT registers are used to control

the forwarding of I/O transactions between the primary and sec-

ondary interfaces of the bridge. This field contains A[15:12] of the

lowest I/O address aligned on a 4KB boundary that is below the

primary interface of the bridge.

Bit

Field Field

Name Type Default

Value Description

0IOCAPRO0x1I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O

addressing. This bit always reflects the value of the IOCAP field

in the IOBASE register.

3:1 Reserved RO 0x0 Reserved field.

7:4 IOLIMIT RW 0x0 I/O Limit. The IOBASE and IOLIMIT registers are used to control

the forwarding of I/O transactions between the primary and sec-

ondary interfaces of the bridge. This field contains A[15:12] of the

highest I/O address, with A[11:0] assumed to be 0xFFF, that is

below the primary interface of the bridge.

Bit

Field Field

Name Type Default

Value Description

7:0 Reserved RO 0x0 Reserved field.

8 MDPED RO 0x0 Master Data Parity Error. Not applicable.

10:9 DVSEL RO 0x0 Not applicable.

11 STAS RO 0x0 Signalled Target Abort Status. Not applicable.

12 RTAS RO 0x0 Received Target Abort Status. Not applicable.

13 RMAS RO 0x0 Received Master Abort Status. Not applicable.

14 RSE RW1C 0x0 Received System Error. This bit is controlled by the SERR

enable bit in the Bridge Control (BCTL) register. If the SERRE bit

is cleared in BCTL, then this bit is never set. Otherwise, this bit is

set if the secondary side of the bridge receives an ERR_FATAL

or ERR_NONFATAL message.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 16 February 22, 2012

Notes

MBASE - Memory Base Register (0x020)

MLIMIT - Memory Limit Register (0x022)

PMBASE - Prefetchable Memory Base Register (0x024)

15 DPE RW1C 0x0 Detected Parity Error. This bit is set by the bridge whenever it

receives a poisoned TLP on the secondary side regardless of the

state of the PERRE bit in the PCI Command register

Bit

Field Field

Name Type Default

Value Description

3:0 Reserved RO 0x0 Reserved field.

15:4 MBASE RW 0xFFF Memory Address Base. The MBASE and MLIMIT registers are

used to control the forwarding of non-prefetchable transactions

between the primary and secondary interfaces of the bridge. This

field contains A[31:20] of the lowest address aligned on a 1MB

boundary that is below the primary interface of the bridge.

Bit

Field Field

Name Type Default

Value Description

3:0 Reserved RO 0x0 Reserved field.

15:4 MLIMIT RW 0x0 Memory Address Limit. The MBASE and MLIMIT registers are

used to control the forwarding of non-prefetchable transactions

between the primary and secondary interfaces of the bridge. This

field contains A[31:20] of the highest address, with A[19:0]

assumed to be 0xF_FFFF, that is below the primary interface of

the bridge.

Bit

Field Field

Name Type Default

Value Description

0PMCAPRWL0x1Prefetchable Memory Capability. Indicates if the bridge sup-

ports 32-bit or 64-bit prefetchable memory addressing.

0x0 - (prefmem32) 32-bit prefetchable memory addressing.

0x1 - (prefmem64) 64-bit prefetchable memory addressing.

3:1 Reserved RO 0x0 Reserved field.

15:4 PMBASE RW 0xFFF Prefetchable Memory Address Base. The PMBASE, PMBA-

SEU, PMLIMIT and PMLIMITU registers are used to control the

forwarding of prefetchable transactions between the primary and

secondary interfaces of the bridge. This field contains A[31:20] of

the lowest memory address aligned on a 1MB boundary that is

below the primary interface of the bridge. PMBASEU specifies

the remaining bits.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 17 February 22, 2012

Notes

PMLIMIT - Prefetchable Memory Limit Register (0x026)

PMBASEU - Prefetchable Memory Base Upper Register (0x028)

PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)

IOBASEU - I/O Base Upper Register (0x030)

Bit

Field Field

Name Type Default

Value Description

0PMCAPRO0x1Prefetchable Memory Capability. Indicates if the bridge sup-

ports 32-bit or 64-bit prefetchable memory addressing. This bit

always reflects the value in the PMCAP field in the PMBASE reg-

ister.

3:1 Reserved RO 0x0 Reserved field.

15:4 PMLIMIT RW 0x0 Prefetchable Memory Address Limit. The PMBASE, PMBA-

SEU, PMLIMIT and PMLIMITU registers are used to control the

forwarding of prefetchable transactions between the primary and

secondary interfaces of the bridge. This field contains A[31:20] of

the highest memory address, with A[19:0] assumed to be

0xF_FFFF, that is below the primary interface of the bridge.

PMLIMITU specifies the remaining bits

Bit

Field Field

Name Type Default

Value Description

31:0 PMBASEU RW 0xFFFF_FFF

FPrefetchable Memory Address Base Upper. This field specifies

the upper 32-bits of PMBASE when 64-bit addressing is used.

When the PMCAP field in the PMBASE register is cleared, this

field becomes read-only with a value of zero.

Bit

Field Field

Name Type Default

Value Description

31:0 PMLIMITU RW 0x0 Prefetchable Memory Address Limit Upper. This field specifies

the upper 32-bits of PMLIMIT.

When the PMCAP field in the PMBASE register is cleared, this

field becomes read-only with a value of zero.

Bit

Field Field

Name Type Default

Value Description

15:0 IOBASEU RW 0xFFFF I/O Address Base Upper. This field specifies the upper 16-bits

of IOBASE.

When the IOCAP field in the IOBASE register is cleared, this field

becomes read-only with a value of zero.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 18 February 22, 2012

Notes

IOLIMITU - I/O Limit Upper Register (0x032)

CAPPTR - Capabilities Pointer Register (0x034)

EROMBASE - Expansion ROM Base Address Register (0x038)

INTRLINE - Interrupt Line Register (0x03C)

Bit

Field Field

Name Type Default

Value Description

15:0 IOLIMITU RW 0x0 Prefetchable IO Limit Upper. This field specifies the upper 16-

bits of IOLIMIT.

When the IOCAP field in the IOBASE register is cleared, this field

becomes read-only with a value of zero.

Bit

Field Field

Name Type Default

Value Description

7:0 CAPPTR RWL 0x40 Capabilities Pointer. This field specifies a pointer to the head of

the capabilities structure.

Bit

Field Field

Name Type Default

Value Description

31:0 EROMBASE RO 0x0 Expansion ROM Base Address. The bridge does not implement

an expansion ROM. Thus, this field is hardwired to zero.

Bit

Field Field

Name Type Default

Value Description

7:0 INTRLINE RW 0x0 Interrupt Line . This register communicates interrupt line routing

information. Values in this register are programmed by system

software and are system architecture specific. The bridge does

not use the value in this register. Legacy interrupts may be imple-

mented by downstream ports.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 19 February 22, 2012

Notes

INTRPIN - Interrupt PIN Register (0x03D)

BCTL - Bridge Control Register (0x03E)

Bit

Field Field

Name Type Default

Value Description

7:0 INTRPIN RWL 0x0 Interrupt Pin. Interrupt pin or legacy interrupt messages are not

used by the bridge by default. However, they can be used for hot-

plug by the downstream ports and to report memory errors by the

upstream port.

This field should only be configured with values of 0x0 through

0x4. The PES24T3G2 bridges may only be configured to gener-

ate INTA interrupts. Therefore, correct values for this field are

only 0x0 and 0x1.

0x0 - (none) Bridge does not generate any interrupts.

0x1 - (INTA) Bridge generates INTA interrupts.

0x2 - (INTB) Bridge generates INTB interrupts.

0x3 - (INTC) Bridge generates INTC interrupts.

0x4 - (INTD) Bridge generates INTD interrupts.

Bit

Field Field

Name Type Default

Value Description

0 PERRE RW 0x0 Parity Error Response Enable. Not applicable.

1 SERRE RW 0x0 System Error Enable. This bit controls forwarding of ERR_COR,

ERR_NONFATAL, ERR_FATAL from the secondary interface of

the bridge to the primary interface.

Note that error reporting must be enabled in the Command regis-

ter or PCI Express Capability structure, Device Control register

for errors to be reported on the primary interface.

0x0 - (ignore) Do not forward errors from the secondary to the pri-

mary interface.

0x1 - (report) Enable forwarding of errors from secondary to the

primary interface.

2 ISAEN RW 0x0 ISA Enable. This bit controls the routing of ISA I/O transactions.

0 - (disable) Forward downstream all I/O addresses in the

address range defined by the I/O base and I/O limit registers

1 -(enable) Forward upstream ISA I/O addresses in the address

range defined by the I/O base and I/O limit registers that are in

the first 64 KB of PCI I/O address space (top 768 bytes of

each 1-KB block)

3 VGAEN RW 0x0 VGA Enable. Controls the routing of processor-initiated transac-

tions targeting VGA.

0 - (block) Do not forward VGA compatible addresses from the

primary interface to the secondary interface

1 - (forward) Forward VGA compatible addresses from the pri-

mary to the secondary interface.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 20 February 22, 2012

Notes

PCI Express Capability Stru cture

PCIECAP - PCI Express Capability (0x040)

4 VGA16EN RW 0x0 VGA 16-bit Enable. This bit only has an effect when the VGAEN

bit is set in this register.

This read/write bit enables system configuration software to

select between 10-bit and 16-bit I/O space decoding for VGA

transactions.

0 - (bit10) Perform 10-bit decoding. I/O space aliasing occurs in

this mode.

1 - (bit16) Perform 16-bit decoding. No I/O space aliasing occurs

in this mode.

5 Reserved RO 0x0 Reserved field.

6 SRESET RW 0x0 Secondary Bus Reset. Setting this bit triggers a secondary bus

reset.

In the upstream port, setting this bit initiates a Upstream Second-

ary Bus Re set.

In a downstream port, setting this bit initiates a Downstream Sec-

ondary Bus Reset.

Port Configuration Registers must not be changed except as

required to update port status.

15:7 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

7:0 CAPID RO 0x10 Capability ID. The value of 0x10 identifies this capability as a

PCI Express capability structure.

15:8 NXTPTR RWL 0xC0 Next Pointer. This field contains a pointer to the next capability

structure.

19:16 VER RWL 0x2 PCI Express Capability Version. This field indicates the PCI-

SIG defined PCI Express capability structure version number.

The PES24T3G2 is compliant with the Express Capabilities Reg-

ister Expansion ECN.

23:20 TYPE RO Upstream:

0x5

Downstream:

0x6

Port Type. This field identifies the type of switch port (upstream

or downstream).

24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express link

associated with this Port is connected to a slot. This field does

not apply to an upstream port and should be set to zero.

29:25 IMN RO 0x0 Interrupt Message Number. The function is allocated only one

MSI. Therefore, this field is set to zero.

31:30 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 21 February 22, 2012

Notes

PCIEDCAP - PCI Express Device Capabilities (0x044)

Bit

Field Field

Name Type Default

Value Description

2:0 MPAYLOAD RWL HWINIT Maximum Payload Size Supported. This field indicates the

maximum payload size that the device can support for TLPs.

For all bond options the default value is 0x4 which corresponds to

2048 bytes.

4:3 PFS RO 0x0 Phantom Functions Supported. This field indicates the support

for unclaimed function number to extend the number of outstand-

ing transactions allowed by logically combining unclaimed func-

tion numbers. The value is hardwired to 0x0 to indicate that no

function number bits are used for phantom functions.

5ETAGRWL0x1Extended Tag Field Support. This field indicates the maximum

supported size of the Tag field as a requester.

8:6 E0AL RO 0x0 Endpoint L0s Acceptable Latency. This field indicates the

acceptable total latency that an endpoint can withstand due to

transition from the L0s state to the L0 state. The value is hard-

wired to 0x0 as this field does not apply to a switch.

11:9 E1AL RO 0x0 Endpoint L1 Acceptable Latency. This field indicates the

acceptable total latency that an endpoint can withstand due to

transition from the L1 state to the L0 state. The value is hardwired

to 0x0 as this field does not apply to a switch.

12 ABP RO 0x0 Attention Button Present. In PCIe base 1.0a when set, this bit

indicates that an Attention Button is implemented on the card/

module.

The value of this field is undefined in PCIe base 1.1

13 AIP RO 0x0 Attention Indicator Present. In PCIe base 1.0a when set, this

bit indicates that an Attention Indicator is implemented on the

card/module.

The value of this field is undefined in PCIe base 1.1

14 PIP RO 0x0 Power Indicator Present. In PCIe base 1.0a when set, this bit

indicates that a Power Indicator is implemented on the card/mod-

ule.

The value of this field is undefined in PCIe base 1.1

15 RBERR RO 0x1 Role Based Error Reporting. This bit is set to indicate that the

PES24T3G2 supports error reporting as defined in the PCIe base

1.1 specification.

17:16 Reserved RO 0x0 Reserved.

25:18 CSPLV RO 0x0 Captur ed S lot Powe r Limi t Value . This field in combination with

the Slot Power Limit Scale value, specifies the upper limit on

power supplied by the slot. Power limit (in Watts) calculated by

multiplying the value in this field by the value in the Slot Power

Limit Scale field.

The value of this field is set by a Set_Slot_Power_Limit Message

and is only applicable for the upstream port. This field is always

zero in downstream ports.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 22 February 22, 2012

Notes

PCIEDCTL - PCI Express Device Control (0x048)

27:26 CSPLS RO 0x0 Captured Slot Power Limit Scale. This field specifies the scale

used for the Slot Power Limit Value.

The value of this field is set by a Set_Slot_Power_Limit Message

and is only applicable for the upstream port. This field is always

zero in downstream ports.

0 - (v1) 1.0x

1 - (v1p1) 0.1x

2 - (v0p01) 0.01x

3 - (v0p001x) 0.001x

31:28 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0 CEREN RW 0x0 Correctable Error Reporting Enable. This bit controls reporting

of correctable errors.

1NFERENRW 0x0Non-Fatal Erro r Repor tin g Enabl e. This bit controls reporting of

non-fatal errors.

2 FEREN RW 0x0 Fatal Error Reporting En able. This bit controls reporting of fatal

errors.

3 URREN RW 0x0 Unsupported Request Reporting Enable. This bit controls

reporting of unsupported requests.

4 ERO RO 0x0 Enable Relaxed Ordering. When set, this bit enables relaxed

ordering. This bit is not applicable to the switch, since the switch

never sets the relaxed ordering bit in transactions it initiates as a

requester. Therefore, this bit is hardwired to 0x0.

7:5 MPS RW 0x0 Max Payload Size. This field sets maximum TLP payload size for

the device.

This field should be set to a value less than that advertised by the

Maximum Payload Size Supported (MPAYLOAD) field in the PCI

Express Device Capabilities (PCIEDCAP) register. Setting this

field to a v alue larger than that advertised in the MPAYLOAD field

produces undefined results.

0x0 - (s128) 128 bytes max payload size

0x1 - (s256) 256 bytes max payload size

0x2 - (s512) 512 bytes max payload size

0x3 - (s1024) 1024 bytes max payload size

0x4 - (s2048) 2048 bytes max payload size

0x5 - (s4096) 4096 bytes max payload size

0x6 - reserved (treated as 128 bytes)

0x7 - reserved (treated as 128 bytes)

8ETFENRW0x0Extended Tag Field Enable. Since the bridge never generates a

transaction that requires a completion, this bit has no functional

effect on the device during normal operation.

To aid in debug, when the SEQTAG field is set in the TLCTL reg-

ister, this field controls whether tags are generated in the range

from 0 through 31 or from 0 through 255.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 23 February 22, 2012

Notes

PCIEDSTS - PCI Express Device Status (0x04A)

9PFENRO0x0Pha n tom Fu nction Enable. The bridge does not support phan-

tom function numbers. Therefore, this field is hardwired to zero.

10 AUXPMEN RO 0x0 Auxiliary Power PM Enable. The device does not implement

this capability.

11 ENS RO 0x0 Enable No Snoop. The bridge does not generate transactions

with the No Snoop bit set and passes transactions through the

bridge with the No Snoop bit unmodified.

14:12 MRRS RO 0x0 Maximum Read Request Size. The bridge does not generate

transactions larger than 128 bytes and passes transactions

through the bridge with the size unmodified. Therefore, this field

has no functional effect on the behavior of the bridge.

15 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0CEDRW1C0x0Correctable Error Detected. This bit indicates the status of cor-

rectable errors. Errors are logged in this register regardless of

whether error reporting is enabled or not.

1NFEDRW1C0x0Non-Fatal Error Detected. This bit indicates the status of cor-

rectable errors. Errors are logged in this register regardless of

whether error reporting is enabled or not.

2FEDRW1C0x0Fatal Error Detected. This bit indicates the status of Fatal errors.

Errors are logged in this registers regardless of whether error

reporting is enabled or not.

3 URD RW1C 0x0 Un support ed Request Detected. This bit indicates the device

received an Unsupported Request. Errors are logged in this reg-

ister regardless of whether error reporting is enabled or not.

4 AUXPD RO 0x0 Aux Power Detected. Devices that require AUX power, set this

bit when AUX power is detected.This device does not require

AUX power, hence the value is hardwired to zero.

5TPRO0x0Transactions Pending. The bridge does not issue Non-Posted

Requests on its own behalf. Therefore, this field is hardwired to

zero.

15:6 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 24 February 22, 2012

Notes

PCIELCAP - PCI Express Link Capabilities (0x04C)

Bit

Field Field

Name Type Default

Value Description

3:0 MAXLNKSPD RO 0x2 Maximum Link Speed. This field indicates the supported link

speeds of the port.

1 - (gen1) 2.5 Gbps

2 - (gen2) 5 Gbps

others - reserved

The initial value of this field is always 0x2 for the upstream and

downstream ports.

9:4 MAXLNK-

WDTH RWL HWINIT Maximum Link Width. This field indicates the maximum link

width of the given PCI Express link. This field may be overridden

to allow the link width to be forced to a smaller value.

Setting this field to an invalid or reserved value is allowed, and

results in the port operating at its default (i.e., initial) value. The

value written to this field is never modified by hardware.

The initial value of this field is x8.

0 - reserved

1 - (x1) x1 link width

2 - (x2) x2 link width

4 - (x4) x4 link width

8 - (x8) x8 link width

others - reserved

11:10 ASPMS RWL 0x3 Active State Power Management (ASPM) Support. This

default value of this field is 0x3 to indicate that L0s and L1 are

supported.

14:12 L0SEL RWL 0x6 L0s Exit Latency. This field indicates the L0s exit latency for the

given PCI Express link.

17:15 L1EL RWL 0x2 L1 Exit Latency. This field indicates the L1 exit latency for the

given PCI Express link. Transitioning from L1 to L0 always

requires 2.3 µs. Therefore, a value 2 µs to less than 4 µs is

reported with a default value of 0x2.

18 CPM RWL 0x0 Clock Power Management. This bit indicates if the component

tolerates removal of the reference clock via the “CLKREQ#”

machanism.

The PES24T3G2 does not support the removal of reference

clocks.

19 SDERR RWL Upstream:

0x0

Downstream:

0x1

Surprise Down Error Rep ort ing. The PES24T3G2 downstrem

ports support surprise down error reporting.

This field does not apply to an upstream port and should be hard-

wired to zero.

20 DLLLA RWL Upstream:

0x0

Downstream:

0x1

Data Link Layer Link Active Reporting. The PES24T3G2

downstream ports support the capability of reporting the

DL_Active state of the data link control and management state

machine.

Modification of this bit changes the advertised capability value

but does not modify the device behavior (i.e., status is always

reported regardless of this field value).

This field is not applicable for the upstream port and must be

hardwired to zero.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 25 February 22, 2012

Notes

PCIELCTL - PCI Express Link Control (0x050)

21 LBN RWL Upstream:

0x0

Downstream:

0x1

Link Bandwidth Notification Capability. When set, this bit indi-

cates support for the link bandwidth notification status and inter-

rupt mechanisms. The PES24T3G2 downstream ports support

the capability.

This field is not applicable for the upstream port and must be

zero.

23:22 Reserved RO 0x0 Reserved field.

31:24 PORTNUM RO Port 0: 0x0

Port 2: 0x2

Port 4: 0x4

Port Number. This field indicates the PCI express port number

for the corresponding link.

Bit

Field Field

Name Type Default

Value Description

1:0 ASPM RW 0x0 Active State Power Management (ASPM) Control. This field

controls the level of ASPM s upported by the link. The initial value

corresponds to disabled. The value contained in Serial EEPROM

may override this default value

0x0 - (disabled) disabled

0x1 - (l0s) L0s enable entry

0x2 - (l1) L1 enable entry

0x3 - (l0sl1) L0s and L1 enable entry

Note that “L0s enable entry” corresponds to the transmitter enter-

ing L0s (the receiver supports this function and is not affected by

this setting).

2 Reserved RO 0x0 Reserved field.

3RCBRO0x0Read Completion Boundary. This field is not applicable and is

hardwired to zero.

4LDISRW0x0Link Disable. When set in a downstream port, this bit disables

the link.

This field is not applicable for the upstream port.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 26 February 22, 2012

Notes

5LRETRW0x0Link Retrain. Writing a one to this field initiates Link retraining by

directing the Physical Layer LTSSM to the Recovery state. This

field always returns zero when read.

It is permitted to set this bit while simultaneously modifying other

fields in this register.

When this bit is set and the LTSSM is already in the Recovery or

Configuration states, all modifications that affect link retraining

are applied in the subsequent retraining. Else, if the LTSSM is

not in the Recovery or Configuration states, modifications that

affect link retraining are applied immediately.

For compliance with the PCIe specification, this bit has no effect

on the upstream port when the REGUNLOCK bit is cleared in the

SWCTL register. In this mode the field is hardwired to zero. When

the REGUNLOCK bit is set, writing a one to the LRET bit initiates

link retraining on the upstream port with a delayed effect of 1 ms.

For the upstream port, the effect of setting the LRET bit is

delayed by 1ms to allow the completion associated with the con-

figuration access that set the bit to be sent towards the root.

Therefore, for the upstream port, software must wait 1ms after

setting the LRET bit before polling the RLWS field.

Setting LRET in the upstream port does not result in the immedi-

ate setting of the LTRAIN bit in the PCIELSTS register. The

LTRAIN bit is set at a 1ms delay.

6CCLKRW0x0Common Clock Configuration. When set, this bit indicates that

this component and the component at the opposite end of the link

are operating with a distributed common reference clock.

7 ESYNC RW 0x0 Extended Sync. When set this bit forces transmission of addi-

tional ordered sets when exiting the L0s state and when in the

recovery state.

8 CLKP-

WRMGT RO 0x0 Enable Clock Power Management. The PES24T3G2 does not

support this feature.

9 HAWD RO 0x0 Hardware Autonomous Width Disable. When set, this bit disables

hardware from changing the link width for reasons other than

attempting to correct for unreliable link operation by reducing the

link width.

The PES24T3G2 ports do not have a hardware autonomous

mechanism to change link width, except due to link reliability

issues. Therefore, this bit is not applicable and is hardwired to

zero.

10 LBWINTEN RW 0x0 Link Bandwidth Management Interrupt Enable. When set, this

bit enables the generation of an interrupt to indicate that the

LBWSTS bit has been set in the PCIELSTS register.

If the LBN field in the PCIELCAP register is cleared, this field is

hardwired to zero.

This field is hardwired to zero in the upstream port.

11 LABWINTEN RW 0x0 Link Auton omous Bandw idth Int errup t Enabl e. When set, this

bit enables the generation of an interrupt to indicate that the

LABWSTS bit has been set in the PCIELSTS register.

If the LBN field in the PCIELCAP register is cleared, this field is

hardwired to zero.

This field is hardwired to zero in the upstream port.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 27 February 22, 2012

Notes

PCIELSTS - PCI Express Link Status (0x052)

15:12 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

3:0 CLS RO 0x1 Current L ink S peed. This field indicates the current link speed of

the port.

1 - (gen1) 2.5 Gbps

2 - (gen2) 5 Gbps

others-reserved

9:4 NLW RO HWINIT Nego tia t ed Li nk W idt h. This field indicates the negotiated width

of the link.

00 0001b - x1

00 0010b - x2

00 0100b - x4

00 1000b - x8

00 1100b - x12

01 0000b - x16

10 0000b - x32

When the MAXLNKWDTH field in the PCIELCAP register selects

a width not supported by the port, the value of this field corre-

sponds to the setting of the MAXLNKWDTH field, regardless of

the actual negotiated link width.

When the MAXLNKWDTH field in the PCIELCAP register selects

a width supported by the port, but the link is unable to train, the

value in this field is set to 0x0.

10 TERR RO 0x0 Training Error. In PCIe base 1.0a when set, this bit indicates

that a link training error has occurred.

The value of this field is undefined in the PCIe base 2.0 specifica-

tion.

11 LTRAIN RO 0x0 Link Training. When set, this bit indicates that link training is in

progress.

This bit is set when the Physical Layer LTSSM is in Configuration

or Recovery State, or when 0x1 is written to LRET bit in the

PCIELCTL register but Link training has not yet begun. For

upstream port, LRET has a delayed effect of 1 ms.

Hardware clears this bit when LTSSM exits Configuration/

Recovery State.

12 SCLK RWL HWINIT Slot Clock Configuration. When set, this bit indicates that the

component uses the same physical reference clock that the plat-

form provides. The initial value of this field is the state of the

CCLKUS signal for the upstream port and the CCLKDS signal for

downstream ports. The serial EEPROM may override these

default values.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 28 February 22, 2012

Notes

PCIESCAP - PCI Express Slot Capabilities (0x054)

13 DLLLA RO 0x0 Data Link Layer Link Active. This bit indicates the status for the

data link control and management state machine.

0x0 - (not_active) Data link layer not active state

0x1 - (active) Data link layer active state

This bit must never be set by hardware if the DLLLA bit in the

PCIELCAP register is cleared.

14 LBWSTS RW1C 0x0 Link Bandwidth Management Status. This bit is set to indicate

that either of the following have occurred without the link transi-

tioning through the DL_Down state.

A link retraining initiated by setting the LRET bit in the PCIELCTL

The PHY has autonomously changed link speed or width to

attempt to correct unreliable link operation either through an

LTSSM time-out or a higher level process.

This bit must be set if the Physical Layer reports a speed or width

change was initiated by the downstream component that was not

indicated as an autonomous change.

If the LBN field in the PCIELCAP register is cleared, this field is

hardwired to zero.

This field is hardwired to zero in the upstream port.

15 LABWSTS RW1C 0x0 Link Autonomous Bandwidth Status. This bit is set to indicate

that either that the PHY has autonomously changed link speed or

width for reasons other than to attempt to correct unreliable link

operation.

This bit must be set if the Physical Layer reports a speed or width

change was initiated by the downstream component that was

indicated as an autonomous change.

If the LBN field in the PCIELCAP register is cleared, this field is

hardwired to zero.

This field is hardwired to zero in the upstream port.

Bit

Field Field

Name Type Default

Value Description

0 ABP RWL 0x0 Atte nti o n Bu tt on Pr ese n t. This bit is set when the Attention But-

ton is implemented for the port.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

1 PCP RWL 0x0 Power Control Present. This bit is set when a Power Controller

is implemented for the port.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

2MRLPRWL0x0MRL Sensor Present. This bit is set when an MRL Sensor is

implemented for the port.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 29 February 22, 2012

Notes

3ATTIPRWL0x0Attention Indicator Present. This bit is set when an Attention

Indicator is implemented for the port.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

4PWRIPRWL0x0Power Indicator Present. This bit is set when an Power Indica-

tor is implemented for the port.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

5HPSRWL0x0Hot Plug Surprise. When set, this bit indicates that a device

present in the slot may be removed from the system without

notice.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

6HPCRWL0x0Hot Plug Capable. This bit is set if the slot corresponding to the

port is capable of supporting hot-plug operations.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

14:7 SPLV RW 0x0 Slot Power Limit Value. In combination with the Slot Power

Limit Scale, this field specifies the upper limit on power supplied

by the slot.

A Set_Slot_Power_Limit message is generated using this field

whenever this register is written or when the link transitions from

a non DL_Up status to a DL_Up status.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

16:15 SPLS RW 0x0 Slot Power Limit Scale. This field specifies the scale used for

the Slot Power Limit Value (SPLV).

0x0 - (x1) 1.0x

0x1 - (xp1) 0.1x

0x2 - (xp01) 0.01x

0x3 - (xp001) 0.001x

A Set_Slot_Power_Limit message is generated using this field

whenever this register is written or when the link transitions from

a non DL_Up status to a DL_Up status.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

17 EIP RWL 0x0 Electromechanical Interlock Present. This bit is set if an elec-

tromechanical interlock is implemented on the chassis for this

slot.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

18 NCCS RO 0x0 No Command Completed Support. Software notification is

always generated when an issued command is completed by the

hot-plug controller. Therefore, this field is hardwired to zero.

31:19 PSLOTNUM RWL 0x0 Physical Slot Number. This field indicate s the physical slo t num-

ber attached to this port. For devices interconnected on the sys-

tem board, this field should be initialized to zero.

This bit is read-only and has a value of zero when the SLOT bit in

the PCIECAP register is cleared.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 30 February 22, 2012

Notes

PCIESCTL - PCI Express Slot Control (0x058)

Bit

Field Field

Name Type Default

Value Description

0 ABPE RW 0x0 Attention Button Pressed Enable. This bit when set enables

generation of a Hot-Plug interrupt or wake-up event on an atten-

tion button pressed event.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

1PFDERW0x0Power Fault Detected Enable. This bit when set enables the

generation of a Hot-Plug interrupt or wake-up event on a power

fault event.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

2MRLSCERW 0x0MRL Sensor Chan ge Enable. This bit when set enables the

generation of a Hot-Plug interrupt or wake-up event on a MRL

sensor change event.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

3PDCERW0x0Presence Detected Changed Enable. This bit when set enables

the generation of a Hot-Plug interrupt or wake-up event on a

presence detect change event.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

4CCIERW0x0Command Complete Interrupt Enable. This bit when set

enables the generation of a Hot-Plug interrupt when a command

is completed by the Hot-Plug Controller.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

5HPIERW0x0Hot Plug Interrupt Enable. This bit when set enables generation

of a Hot-Plug interrupt on enabled Hot-Plug events.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

7:6 AIC RW 0x3 Attention Indicator Control. When read, this register returns the

current state of the Attention Indicator. Writing to this register sets

the indicator.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

This field is always zero if the ATTIP bit is cleared in the PCIES-

CAP register.

0x0 - (reserved) Reserved

0x1 - (on) On

0x2 - (blink) Blink

0x3 - (off) Off

IDT Configuration Registers

PES24T3G2 User Manual 8 - 31 February 22, 2012

Notes

PCIESSTS - PCI Express Slot Status (0x05A)

9:8 PIC RW 0x1 Power Indicator Control. When read, this register returns the

current state f the Power Indicator. Writing to this register sets the

indicator.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

This field is always zero if the PWRIP bit is cleared in the PCIES-

CAP register.

0x0 - (reserved) Reserved

0x1 - (on) On

0x2 - (blink) Blink

0x3 - (off) Off

This field has no effect on the upstream port.

10 PCC RW 0x0 Power Controller Control. When read, this register returns the

current state of the power applied to the slot. Writing to this regis-

ter sets the power state of the slot.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

0x0 - (on) Power on

0x1 - (off) Power off

11 EIC RW 0x0 Electromechanical Interlock Control. This field always returns

a value of zero when read. If an electromechanical interlock is

implemented, a write of a one to this field causes the state of the

interlock to toggle and a write of a zero has no effect.

This bit is read-only and has a value of zero when the corre-

sponding capability is not enabled in the PCIESCAP register.

12 DLLLASCE RW 0x0 Data Link Layer Link Active State Change Enable. This bit

when set enables generation of a Hot-Plug interrupt or wake-up

event on a data link layer active field state change.

15:13 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0 ABP RW1C 0x0 Attention Button Pressed. Set when the attention button is

pressed.

1PFDRW1C0x0Power Fault Detected. Set when the Power Controller detects a

power fault.

2 MRLSC RW1C 0x0 MRL Sensor Changed. Set when an MRL Sensor state change

is detected.

3PDCRW1C0x0Presence Detected Changed. Set when a Presence Detected

change is detected.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 32 February 22, 2012

Notes

PCIEDCAP2 - PCI Express D evice Capabilities 2 (0x064)

4CCRW1C0x0Command Completed. This bit is set when the Hot-Plug Con-

troller completes an issued command. If the bit is already set,

then it remains set.

A single write to the PCI Express Slot Control (PCIESCTL) regis-

ter is considered to be a single command even if it affects more

than one field in that register. This command completed bit is not

set until processing of all actions associated with all fields in the

PCIESCTL register have completed (i.e., all associated SMBus I/

O expander transactions have completed).

5 MRLSS RO 0x0 MRL Sensor State. This field enclosed the current state of the

MRL sensor.

0x0 -(closed) MRL closed

0x1 -(open) MRL open

6 PDS RO 0x1 Pres en ce De te ct St ate . This bit indicates the presence of a card

in the slot corresponding to the port and reflects the state of the

Presence Detect status.

0x0 -(empty) Slot empty

0x1 -(present) Card present

7EISRO0x0Electromechanical Interlock Status. When an electromechani-

cal interlock is implemented, this bit indicates the current status

of the interlock.

0x0 -(disengaged) Electromechanical interlock disengaged

0x1 -(engaged) Electromechanical interlock engaged

8 DLLLASC RW1C 0x0 Data Link Layer Link Active State Change. This bit is set when

the state of the data link layer active field in the link status regis-

ter changes state.

0x0 -(nochange) No DLLLA state change

0x1 -(changed) DLLLA state change

15:9 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

4:0 Reserved RO 0x0 Reserved field.

5 ARIFS RO 0x1 ARI Forwarding Supported. This bit is set to indicate that the

switch supports ARI Forwarding.

When this bit is cleared, the ARI Forwarding Enable (ARIFEN) bit

in the Device Control 2 register becomes read-only zero.

This bit is read-only zero in the upstream port.

31:6 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 33 February 22, 2012

Notes

PCIEDCTL2 - PCI Express Device Control 2 (0x068)

PCIEDSTS2 - PCI Express Device Status 2 (0x06A)

PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C)

PCIELCTL2 - PCI Express Link Control 2 (0x070)

Bit

Field Field

Name Type Default

Value Description

4:0 Reserved RO 0x0 Reserved field.

5ARIFENRO0x0ARI Forwarding Enable. When set, the downstream port dis-

ables its traditional Device Number field being zero enforcement

when turning a Type 1 configuration request into a Type 0 config-

uration request, permitting access to the Extended Functions in

an ARI device immediately below the port.

When the ARIFS bit in the PCIEDCAP2 register is cleared, this

bit is read-only zero.

This bit is always read-only zero in the upstream port.

15:6 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

15:0 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

31:0 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

3:0 TLS RW 0x2

Sticky Target Link Speed. For downstream ports, this field sets an

upper limit on the link operational speed by restricting the values

advertised by the upstream component in its training sequences.

For both upstream and downstream ports, this field is used to set

the target compliance mode speed when software is using the

ECOMP bit in this register to force a link into compliance mode.

The PES24T3G2 supports 2.5 Gbps and 5.0 Gbps operation.

Setting this field to an unsupported value produces undefined

results.

0x1 - (gen1) 2.5 Gbps

0x2 - (gen2) 5.0 Gbps

others - reserved

4 ECOMP RW 0x0

Sticky Enter Compliance. Software is permitted to force a link into

compliance mode at the speed indicated by the TLS field by set-

ting this bit in both components on a link and then initiating a hot

reset on the link.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 34 February 22, 2012

Notes

5 HASD RO 0x0 Hardware Autonomous Speed Disable. When set, this bit pre-

vents hardware from changing the link speed for device specific

reasons other than to correct unreliable link operation by reduc-

ing the link speed. Initial transition to the highest supported com-

mon link speed is not blocked by this bit.

The PES24T3G2 ports do not have an autonomous mechanism

to regulate link speed, except due to link reliability issues. There-

fore, this bit is not applicable to the PES24T3G2 ports.

Note that this bit does not affect link speed changes triggered by

software setting the target link speed and link-retrain bits. Refer

to section Link Speed Negotiation on page 3-4 for further details.

6 SDE RWL 0x0 Selectable De-emphasis. For switch downstream ports, this bit

sets the de-emphasis level when the link operates at 5.0 Gbps.

For the upstream port, this bit selects the de-emphasis prefer-

ence advertised via training sets (the actual de-emphasis on the

link is selected by the link partner).

0x0 - De-emphasis level = -6.0 dB

0x1 - De-emphasis level = -3.5 dB

This bit has no effect when the link operates at 2.5 Gbps, or when

the link operates in low-swing mode.

When this field is modified, the newly selected de-emphasis is

not applied until the PHY LTSSM transitions through the states in

which it is allowed to modify the de-emphasis setting on the line

(i.e., Recovery.Speed). Therefore, after modifying this field, it is

recommended that the link be fully retrained by setting the

FLRET bit in the PHYLSTATE0 register.

9:7 TM RW 0x0

Sticky Transmit Margin. This field controls the value of the non de-

emphasized voltage level at the transmitter pins. This field is

reset to 0x0 on entry to the LTSSM Polling.Configuration sub-

state.

0x0 - Normal operating range

0x1 - 900 mV for full swing and 500 mV for low-swing

0x2 - 700 mV for full swing and 400 mV for low-swing

0x3 - 500 mV for full swing and 300 mV for low-swing

0x4 - 300 mV for full swing and 200 mv for low-swing

0x5 - 200 mV for full swing and 100 mv for low-swing

0x6-0x7 - Reserved

This register is intended for debug, compliance testing purpose

only. System firmware and software is allowed to modify this reg-

ister only during debug or compliance testing. In all other cases,

the system must ensure that this register is set to the default

value.

When this field is set to “Normal Operating Range”, the SerDes

transmitter drive level is selected via the SerDes Global Transmit-

ter Control register (STXGCTL) and SerDes Transmitter Lane

Control register (STXLC TL) .

When this field is modified, the newly selected value is not

applied until the PHY LTSSM transitions through the states in

which it is allowed to modify the transmit margin setting on the

line (i.e., Recovery.RcvrLock). Therefore, after modifying this

field, it is recommended that the link be retrained by setting the

LRET bit in the PCIELCTL register.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 35 February 22, 2012

Notes

PCIELSTS2 - PCI Express Link Status 2 (0x072)

PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074)

PCIESCTL2 - PCI Express Slot Control 2 (0x078)

10 EMC RW 0x0

Sticky Enter Modified Compliance. When this bit is set to 1b, the port

transmits the modified compliance pattern if the LTSSM enters

Polling.Compliance state.

This register is intended for debug, compliance testing purposes

only. System firmware and software is allowed to modify this reg-

ister only during debug or compliance testing. In all other cases,

the system must ensure that this register is set to the default

value.

11 CSOS RW 0x0

Sticky Compliance SOS. When set to 1b, the LTSSM is required to

send SOS periodically in both the compliance and the modified

compliance patterns.

12 CDE RW 0x0

Sticky Compliance De-emphasis. This bit selects the de-emphasis

value in the Polling.Compliance state when this state was

entered as a result of setting the Enter Compliance (ECOMP) bit

in this register.

0x0 - - 6.0 dB

0x1 - - 3.5 dB

This bit is intended for debug, compliance testing purposes. Sys-

tem firmware and software is allowed to modify this bit only dur-

ing debug or compliance testing.

15:13 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0 CDE RO 0x0 Current De-emphasis. The value of this bit indicates the current

de-emphasis level when the link operates in 5.0 Gbps.

0x0 - De-emphasis level = -6.0 dB

0x1 - De-emphasis level = -3.5 dB

The value of this bit in undefined when the link operates at 2.5

Gbps.

15:1 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

31:0 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

15:0 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 36 February 22, 2012

Notes

PCIESSTS2 - PCI Express Slot Status 2 (0x07A)

Power Management Capability Structure

PMCAP - PCI Power Management Capabilities (0x0C0)

Bit

Field Field

Name Type Default

Value Description

15:0 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

7:0 CAPID RO 0x1 Capability ID. The value of 0x1 identifies this capability as a PCI

power management capability structure.

15:8 NXTPTR RWL Upstream:

0x0

Downstream:

0xD0

Next Pointer. This field contains a pointer to the next capability

structure.

For the upstream port the value of this field is 0x0 indicating that

it is the last capability.

For ports downstream ports, this field is 0xD0 and points to the

MSI capability structure.

18:16 VER RO 0x3 Power Management Capability Version. This field indicates

compliance with version two of the specification.

Complies with version the PCI Bus Power Management Interface

Specification, Revision 1.2.

19 PMECLK RO 0x0 PME Clock. Does not apply to PCI Express.

20 Reserved RO 0x0 Reserved field.

21 DEVSP RWL 0x0 Device Specific Initialization. The value of zero indicates that

no device specific initialization is required.

24:22 AUXI RO 0x0 AUX Current. not used

25 D1 RO 0x0 D1 Support. This field indicates that the PES24T3G2 does not

support D1.

26 D2 RO 0x0 D2 Support. This field indicates that the PES24T3G2 does not

support D2.

31:27 PME RWL 0b11001 PME Support. This field indicates the power states in which the

port may generate a PME.

Bits 27, 30 and 31 are set to indicate that the bridge will forward

PME messages.

The switch does not forward PME messages in D3cold. This func-

tionality may be supported in the system by routing WAKE#

around the switch.

Modification of this field modifies the advertised capability value

but does not modify the device behavior (i.e., PME is generated

in the states noted in the default value).

IDT Configuration Registers

PES24T3G2 User Manual 8 - 37 February 22, 2012

Notes

PMCSR - PCI Power Management Control and Status (0x0C4)

Message Signal ed Interrupt Capability Structure

MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)

Bit

Field Field

Name Type Default

Value Description

1:0 PSTATE RW 0x0 Power State. This field is used to determine the current power

state and to set a new power state.

0x0 - (d0) D0 state

0x1 -(d1) D1 state (not supported by the PES24T3G2 and

reserved)

0x2-(d2) D2 state (not supported by the PES24T3G2 and

reserved)

0x3 -(d3) D3hot state

2 Reserved RO 0x0

3 NOSOFTRST RWL 0x1 No Soft Reset. This bit indicates if the configuration context is

preserved by the bridge when the device transitions from a D3hot

to D0 power management state.

0x0 - (reset) State reset

0x1 - (preserved) State preserved

7:4 Reserved RO 0x0

8PMEERW0x0

Sticky PME Enable. When this bit is set, PME message generation is

enabled for the port.

If a hot plug wake-up event is desired when exiting the D3cold

state, then this bit should be set during serial EEPROM initializa-

tion.

A hot reset does not result in modification of this field.

12:9 DSEL RO 0x0 Data Select. The optional data register is not implemented.

14:13 DSCALE RO 0x0 Data Scale. The optional data register is not implemented.

15 PMES RW1C 0x0

Sticky PME Status. This bit is set if a PME is generated by the port

even if the PMEE bit is cleared. This bit is not set when the bridge

is propagating a PME message but the port is not itself generat-

ing a PME.

Since the upstream port never generates a PME, this bit will

never be set in that port.

21:16 Reserved RO 0x0 Reserved field.

22 B2B3 RO 0x0 B2 /B3 Su pport. Does not apply to PCI Express.

23 BPCCE RO 0x0 Bus Power/Clock Control Enable. Does not apply to PCI

Express.

31:24 DATA RO 0x0 Data. This optional field is not implemented.

Bit

Field Field

Name Type Default

Value Description

7:0 CAPID RO 0x5 Capability ID. The value of 0x5 identifies this capability as a MSI

capability structure.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 38 February 22, 2012

Notes

MSIADDR - Message Signaled Interrupt Address (0x0D4)

MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8)

15:8 NXTPTR RWL 0x0 Next Pointer. This field contains a pointer to the next capability

structure. This field is set to 0x0 indicating that it is the last capa-

bility.

16 EN RW 0x0 Enable. This bit enables MSI.

0x0 - (disable) disabled

0x1 - (enable) enabled

19:17 MMC RO 0x0 Multiple Message Capable. This field contains the number of

requested messages.

22:20 MME RW 0x0 Multiple Message Enable. Hardwired to one message.

23 A64 RO 0x1 64-bit Address Capable. The bridge is capable of generating

messages using a 64-bit address.

31:24 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

1:0 Reserved RO 0x0 Reserved.

31:2 ADDR RW 0x0 Message Address. This field specifies the lower portion of the

DWORD address of the MSI memory write transaction.

The PES24T3G2 assumes that all downstream port generated

MSIs are targeted to the root and routes these transactions to the

upstream port. Configuring the address contained in a down-

stream port’s MSIADDR and MSIADDRU registers to an address

that does not route to the upstream port and generating an MSI

produces undefined results.

Bit

Field Field

Name Type Default

Value Description

31:0 UADDR RW 0x0 Upper Message Address. This field specifies the upper portion

of the DWORD address of the MSI memory write transaction. If

the contents of this field are non-zero, then 64-bit address is used

in the MSI memory write transaction. If the contents of this field

are zero, then the 32-bit address specified in the MSIADDR field

is used.

The PES24T3G2 assumes that all downstream port generated

MSIs are targeted to the root and routes these transactions to the

upstream port. Configuring the address contained in a down-

stream port’s MSIADDR and MSIADDRU registers to an address

that does not route to the upstream port and generating an MSI

produces undefined results.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 39 February 22, 2012

Notes

MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)

Subsystem ID and Subsystem Vendor ID

SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0)

SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4)

Extended Configuration Space Access Registers

ECFGADDR - Extended Configuration Space Access Address (0x0F8)

Bit

Field Field

Name Type Default

Value Description

15:0 MDATA RW 0x0 Message Data. This field contains the lower 16-bits of data that

are written when a MSI is signalled.

31:16 Reserved RO 0x0 Reserved.

Bit

Field Field

Name Type Default

Value Description

7:0 CAPID RO 0xD Capability ID. The value of 0xD identifies this capability as a

SSID/SSVID capability structure.

15:8 NXTPTR RWL 0x00 Next Pointer. This field contains a pointer to the next capability

structure.

31:16 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

15:0 SSVID RWL 0x0 SubSystem Vendor ID. This field identifies the manufacturer of

the add-in card or subsystem.

SSVID values are assigned by the PCI-SIG to insure uniqueness.

31:16 SSID RWL 0x0 Subsystem ID. This field identifies the add-in card or subsystem.

SSID values are assigned by the vendor.

Bit

Field Field

Name Type Default

Value Description

1:0 Reserved RO 0x0 Reserved field.

7:2 REG RW 0x0 Register Number. This field selects the configuration register

number as defined by Section 7.2.2 of the PCI Express Base

Specification, Rev. 1.0a

11:8 EREG RW 0x0 Extended Register Number. This field selects the extended

configuration register number as defined by Section 7.2.2 of the

PCI Express Base Specification, Rev. 1.0a

31:12 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 40 February 22, 2012

Notes

ECFGDATA - Extended Configuration Space Access Data (0x0FC)

Advanced Error Reporting (AER) Enhanced Capability

AERCAP - AER Capabilities (0x100)

AERUES - AER Uncorrectable Error Status (0x104)

Bit

Field Field

Name Type Default

Value Description

31:0 DATA RW 0x0 Configuration Data. A read from this field will return the configu-

ration space register value pointed to by the ECFGADDR regis-

ter. A write to this field will update the contents of the

configuration space register pointed to by the ECFGADDR regis-

ter with the value written. For both reads and writes, the byte

enables correspond to those used to access this field.

When the ECFGADDR register points to the ECFGDATA regis-

ter, then reads from ECFGDATA return zero and writes are

ignored. When the ECFGADDR register points to itself, writes to

the ECFGDATA register modify the contents of the ECFGADDR

SMBus reads of this field return a value of zero and SMBus

writes have no effect.

Bit

Field Field

Name Type Default

Value Description

15:0 CAPID RO 0x1 Capability ID. The value of 0x1 indicates an advanced error

reporting capability structure.

19:16 CAPVER RO 0x1 Capability Version. The value of 0x1. indicates compatibility

with version 1 of the specification.

31:20 NXTPTR RWL 0x200 Next Pointer.

Bit

Field Field

Name Type Default

Value Description

0 UDEF RW1C 0x0

Sticky Undefined. This bit is no longer used in this version of the speci-

ficiation.

3:1 Reserved RO 0x0 Reserved field.

4 DLPERR RW1C 0x0

Sticky Dat a Link Prot ocol Error Sta tus. This bit is set when a data link

layer protocol error is detected.

5 SDOENERR RW1C 0x0

Sticky Surprise Down Error Status. This bit is set when a surprise

down error is detected and the SDERR bit in the PCIELCAP reg-

ister is set.

11:6 Reserved RO 0x0 Reserved field.

12 POISONED RW1C 0x0

Sticky Poisoned TLP Status. This bit is set when a poisoned TLP is

detected.

13 FCPERR RW1C 0x0

Sticky Fl ow Control Protocol Error Status. This bit is set when a flow

control protocol error is detected.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 41 February 22, 2012

Notes

AERUEM - AER Uncorrectable Error Mask (0x108)

14 COMPTO RO 0x0 Completion Time-out Status. A switch port does not initiate

non-posted requests on its own behalf. Therefore, this field is

hardwired to zero.

15 CABORT RO 0x0 Completer Abort Status. The PES24T3G2 never responds to a

non-posted request with a completer abort.

16 UECOMP RW1C 0x0

Sticky Unexpected Completion Status. This bit is set when an unex-

pected completion is detected.

17 RCVOVR RW1C 0x0

Sticky Receiver Overflow Status. This bit is set when a receiver over-

flow is detected.

18 MAL-

FORMED RW1C 0x0

Sticky Malformed TLP Status. This bit is set when a malformed TLP is

detected.

19 ECRC RW1C 0x0

Sticky ECRC Status. This bit is set when an ECRC error is detected.

20 UR RW1C 0x0

Sticky UR Status. This bit is set when an unsupported request is

detected.

21 ACSV RW1C 0x0

Sticky ACS Violation Status. This bit is set when an ACS violation is

detected on the port. The PES24T3G2 does not support ACS

and therefore this bit is hardwired to 0x0.

30:22 Reserved RO 0x0 Reserved field.

31 DBE RW1C 0x0

Sticky Double Bit Error Status. When the Double Bit Error AER Report-

ing Enable (DBEAEREN) bit is set in the Memory Error Control

(MECTL) register, this bit is set whenever a double bit error is

detected in any memory associated with the port.

When the DBEAEREN bit is cleared, this field is read-only zero.

Bit

Field Field

Name Type Default

Value Description

0 UDEF RW 0x0

Sticky Undefined. This bit is no longer used in this version of the speci-

ficiation.

3:1 Reserved RO 0x0 Reserved field.

4 DLPERR RW 0x0

Sticky Data Link Protocol Error Mask. When this bit is set, the corre-

sponding bit in the AERUES register is masked. When a bit is

masked in the AERUES register, the corresponding event is not

logged in the advanced capability structure, the First Error

Pointer field (FEPTR) in the AERCTL register is not updated, and

an error is not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 42 February 22, 2012

Notes

5 SDOENERR RW 0x0

Sticky Surprise Down Erro r Mask. When this bit is set, the corre-

sponding bit in the AERUES register is masked. When a bit is

masked in the AERUES register, the corresponding event is not

logged in the advanced capability structure, the First Error

Pointer field (FEPTR) in the AERCTL register is not updated, and

an error is not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

11:6 Reserved RO 0x0 Reserved field.

12 POISONED RW 0x0

Sticky Poison ed TLP Mask. When this bit is set, the corresponding bit

in the AERUES register is masked. When a bit is masked in the

AERUES register, the corresponding event is not logged in the

advanced capability structure, the First Error Pointer field

(FEPTR) in the AERCTL register is not updated, and an error is

not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

13 FCPERR RW 0x0

Sticky Flow Control Protocol Error Mask. When this bit is set, the cor-

responding bit in the AERUES register is masked. When a bit is

masked in the AERUES register, the corresponding event is not

logged in the advanced capability structure, the First Error

Pointer field (FEPTR) in the AERCTL register is not updated, and

an error is not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

14 COMPTO RO 0x0 Completion Time-out Mask. A switch port does not initiate non-

posted requests on its own behalf. Therefore, this field is hard-

wired to zero.

15 CABORT RO 0x0 Completer Abort Mask. The PES24T3G2 never responds to a

non-posted request with a completer abort.

16 UECOMP RW 0x0

Sticky Unexpected Completion Mask. When this bit is set, the corre-

sponding bit in the AERUES register is masked. When a bit is

masked in the AERUES register, the corresponding event is not

logged in the advanced capability structure, the First Error

Pointer field (FEPTR) in the AERCTL register is not updated, and

an error is not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

17 RCVOVR RW 0x0

Sticky Receiver Overflow Mask. When this bit is set, the corresponding

bit in the AERUES register is masked. When a bit is masked in

the AERUES register, the corresponding event is not logged in

the advanced capability structure, the First Error Pointer field

(FEPTR) in the AERCTL register is not updated, and an error is

not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 43 February 22, 2012

Notes

18 MAL-

FORMED RW 0x0

Sticky Mal form ed TLP M ask. When this bit is set, the corresponding bit

in the AERUES register is masked. When a bit is masked in the

AERUES register, the corresponding event is not logged in the

advanced capability structure, the First Error Pointer field

(FEPTR) in the AERCTL register is not updated, and an error is

not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

19 ECRC RW 0x0

Sticky ECRC Mask. When this bit is set, the corresponding bit in the

AERUES register is masked. When a bit is masked in the

AERUES register, the corresponding event is not logged in the

advanced capability structure, the First Error Pointer field

(FEPTR) in the AERCTL register is not updated, and an error is

not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

20 UR RW 0x0

Sticky UR Mask. When this bit is set, the corresponding bit in the

AERUES register is masked. When a bit is masked in the

AERUES register, the corresponding event is not logged in the

advanced capability structure, the First Error Pointer field

(FEPTR) in the AERCTL register is not updated, and an error is

not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

21 ACSV RW 0x0

Sticky ACS Violation Mask. When this bit is set, the corresponding bit

in the AERUES register is masked. When a bit is masked in the

AERUES register, the corresponding event is not logged in the

advanced capability structure, the First Error Pointer field

(FEPTR) in the AERCTL register is not updated, and an error is

not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

30:22 Reserved RO 0x0 Reserved field.

31 DBE RW 0x0

Sticky Double Bit Error Mask. When this bit is set and the Double Bit

Error AER Reporting Enable (DBEAEREN) bit is set in the Mem-

ory Error Control (MECTL) register, the corresponding bit in the

AERUES register is masked.

When a bit is masked in the AERUES register, the corresponding

event is not logged in the advanced capability structure, the First

Error Pointer field (FEPTR) in the AERCTL register is not

updated, and an error is not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERUES register.

When the DBEAEREN bit is cleared, this field is read-only zero.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 44 February 22, 2012

Notes

AERUESV - AER Uncorrectable Error Severity (0x10C)

Bit

Field Field

Name Type Default

Value Description

0 UDEF RW 0x0

Sticky Undefined. This bit is no longer used in this version of the speci-

ficiation.

3:1 Reserved RO 0x0 Reserved field.

4 DLPERR RW 0x1

Sticky Data Link Protocol Error Severity. If the corresponding event is

not masked in the AERUEM register, then when the event

occurs, this bit controls the severity of the reported error. If this bit

is set, the event is reported as a fatal error. When this bit is

cleared, the event is reported as an uncorrectable error.

5 SDOENERR RW 0x1

Sticky Surprise Down Error Severity. If the corresponding event is not

masked in the AERUEM register, then when the event occurs,

this bit controls the severity of the reported error. If this bit is set,

the event is reported as a fatal error. When this bit is cleared, the

event is reported as an uncorrectable error.

11:6 Reserved RO 0x0 Reserved field.

12 POISONED RW 0x0

Sticky Poisoned TLP Status Severity. If the corresponding event is not

masked in the AERUEM register, then when the event occurs,

this bit controls the severity of the reported error. If this bit is set,

the event is reported as a fatal error. When this bit is cleared, the

event is reported as an uncorrectable error.

13 FCPERR RW 0x1

Sticky Flow Control Protocol Error Severity. If the corresponding

event is not masked in the AERUEM register, then when the

event occurs, this bit controls the severity of the reported error. If

this bit is set, the event is reported as a fatal error. When this bit

is cleared, the event is reported as an uncorrectable error.

14 COMPTO RO 0x0 Completion Time-out Severity. A switch port does not initiate

non-posted requests on its own behalf. Therefore, this field is

hardwired to zero.

15 CABORT RO 0x0 Completer Abort Severity. The PES24T3G2 never responds to

a non-posted request with a completer abort.

16 UECOMP RW 0x0

Sticky Unexpected Completion Severity. If the corresponding event is

not masked in the AERUEM register, then when the event

occurs, this bit controls the severity of the reported error. If this bit

is set, the event is reported as a fatal error. When this bit is

cleared, the event is reported as an uncorrectable error.

17 RCVOVR RW 0x1

Sticky Receiver Overflow Severity. If the corresponding event is not

masked in the AERUEM register, then when the event occurs,

this bit controls the severity of the reported error. If this bit is set,

the event is reported as a fatal error. When this bit is cleared, the

event is reported as an uncorrectable error.

18 MAL-

FORMED RW 0x1

Sticky Ma lformed TLP Severity. If the corresponding event is not

masked in the AERUEM register, then when the event occurs,

this bit controls the severity of the reported error. If this bit is set,

the event is reported as a fatal error. When this bit is cleared, the

event is reported as an uncorrectable error.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 45 February 22, 2012

Notes

AERCES - AER Correctable Error Status (0x110)

19 ECRC RW 0x0

Sticky ECRC Severity. If the corresponding event is not masked in the

AERUEM register, then when the event occurs, this bit controls

the severity of the reported error. If this bit is set, the event is

reported as a fatal error. When this bit is cleared, the event is

reported as an uncorrectable error.

20 UR RW 0x0

Sticky UR Severity. If the corresponding event is not masked in the

AERUEM register, then when the event occurs, this bit controls

the severity of the reported error. If this bit is set, the event is

reported as a fatal error. When this bit is cleared, the event is

reported as an uncorrectable error.

21 ACSV RW 0x0

Sticky ACS Violation Severity. If the corresponding event is not

masked in the AERUEM register, then when the event occurs,

this bit controls the severity of the reported error. If this bit is set,

the event is reported as a fatal error. When this bit is cleared, the

event is reported as an uncorrectable error.

30:22 Reserved RO 0x0

31 DBE RW 0x0

Sticky Double Bit Error Severity. If the corresponding event is not

masked in the AERUEM register, then when the event occurs,

this bit controls the severity of the reported error. If this bit is set,

the event is reported as a fatal error. When this bit is cleared, the

event is reported as an uncorrectable error.

When the DBEAEREN bit is cleared, this field is read-only zero.

Bit

Field Field

Name Type Default

Value Description

0 RCVERR RW1C 0x0

Sticky Receiver Error Status. This bit is set when the physical layer

detects a receiver error.

5:1 Reserved RO 0x0 Reserved field.

6 BADTLP RW1C 0x0

Sticky Bad TLP Status. This bit is set when a bad TLP is detected.

7 BADDLLP RW1C 0x0

Sticky Bad DLLP Status. This bit is set when a bad DLLP is detected.

8 RPLYROVR RW1C 0x0

Sticky Replay Number Rollover Status. This bit is set when a replay

number rollover has occurred indicating that the data link layer

has abandoned replays and has requested that the link be

retrained.

11:9 Reserved RO 0x0 Reserved field.

12 RPLYTO RW1C 0x0

Sticky Replay Timer Time-Out Status. This bit is set when the replay

timer in the data link layer times out.

13 ADVISO-

RYNF RW1C 0x0

Sticky Advisory Non-Fatal Error Status. This bit is set when an advi-

sory non-fatal error is detected as described in Section 6.2.3.2.4

of the PCIe base 1.1 specification.

30:14 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 46 February 22, 2012

Notes

AERCEM - AER Correctable Error Mask (0x114)

31 SBE RW1C 0x0

Sticky Single Bit Error Status. When the Single Bit Error AER Reporting

Enable (SBEAEREN) bit is set in the Memory Error Control

(MECTL) register, this bit is set whenever a single bit error is

detected in any memory associated with the port.

When the SBEAEREN bit is cleared, this field is read-only zero.

Bit

Field Field

Name Type Default

Value Description

0 RCVERR RW 0x0

Sticky Receiver Error Mask. When this bit is set, the corresponding bit

in the AERCES register is masked. When a bit is masked in the

AERCES register, the corresponding event is not reported to the

root complex.

5:1 Reserved RO 0x0 Reserved field.

6 BADTLP RW 0x0

Sticky Bad TLP Mask. When this bit is set, the corresponding bit in the

AERCES register is masked. When a bit is masked in the

AERCES register, the corresponding event is not reported to the

root complex.

7 BADDLLP RW 0x0

Sticky Bad DLLP Mask. When this bit is set, the corresponding bit in

the AERCES register is masked. When a bit is masked in the

AERCES register, the corresponding event is not reported to the

root complex.

8 RPLYROVR RW 0x0

Sticky Replay Number Rollover Mask. When this bit is set, the corre-

sponding bit in the AERCES register is masked. When a bit is

masked in the AERCES register, the corresponding event is not

reported to the root complex.

11:9 Reserved RO 0x0 Reserved field.

12 RPLYTO RW 0x0

Sticky Replay Tim er Time-Out Mask. When this bit is set, the corre-

sponding bit in the AERCES register is masked. When a bit is

masked in the AERCES register, the corresponding event is not

reported to the root complex.

13 ADVISO-

RYNF RW 0x1

Sticky Advisory Non-Fatal Error Mask.When this bit is set, the corre-

sponding bit in the AERCES register is masked. When a bit is

masked in the AERCES register, the corresponding event is not

reported to the root complex.

30:14 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 47 February 22, 2012

Notes

AERCTL - AER Control (0x118)

AERHL1DW - AER Header Log 1st Doubleword (0x11C)

AERHL2DW - AER Header Log 2nd Doubleword (0x120)

31 SBE RW 0x0

Sticky Single Bit Error Mask. When this bit is set and the Single Bit Error

AER Reporting Enable (SBEAEREN) bit is set in the Memory

Error Control (MECTL) register, the corresponding bit in the

AERCES register is masked.

When a bit is masked in the AERCES register, the corresponding

event is not logged in the advanced capability structure, the First

Error Pointer field (FEPTR) in the AERCTL register is not

updated, and an error is not reported to the root complex.

This bit does not affect the state of the corresponding bit in the

AERCES register.

When the SBEAEREN bit is cleared, this field is read-only zero.

Bit

Field Field

Name Type Default

Value Description

4:0 FEPTR RO 0x0

Sticky First Error Po inter. This field contains a pointer to the bit in the

AERUES register that resulted in the first reported error.

5 ECRCGC RWL 0x1 ECRC Generation Capable. This bit indicates if the device is

capable of generating ECRC.

6 ECRCGE RW 0x0

Sticky ECRC Generation Enable. When this bit is set, ECRC genera-

tion is enabled.

7 ECRCCC RWL 0x1 ECRC Check Capable. This bit indicates if the device is capable

of checking ECRC.

8 ECRCCE RW 0x0

Sticky ECRC Check Enable. When set, this bit enables ECRC check-

ing.

31:9 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

31:0 HL RO 0x0

Sticky Header Log. This field contains the 1st doubleword of the TLP

header that resulted in the first reported uncorrectable error.

Bit

Field Field

Name Type Default

Value Description

31:0 HL RO 0x0

Sticky Header Log. This field contains the 2nd doubleword of the TLP

header that resulted in the first reported uncorrectable error.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 48 February 22, 2012

Notes

AERHL3DW - AER Header Log 3rd Doubleword (0x124)

AERHL4DW - AER Header Log 4th Doubleword (0x128)

Device Serial Nu m ber E nha nc ed Capability

SNUMCAP - Serial Number Capabilities (0x180)

SNUMLDW - Serial Number Lower Doubleword (0x184)

SNUMUDW - Serial Number Upper Doubleword (0x188)

Bit

Field Field

Name Type Default

Value Description

31:0 HL RO 0x0

Sticky Header Log. This field contains the 3rd doubleword of the TLP

header that resulted in the first reported uncorrectable error.

Bit

Field Field

Name Type Default

Value Description

31:0 HL RO 0x0

Sticky Header Log. This field contains the 4th doubleword of the TLP

header that resulted in the first reported uncorrectable error.

Bit

Field Field

Name Type Default

Value Description

15:0 CAPID RO 0x3 Capability ID. The value of 0x3 indicates a device serial number

capability structure.

19:16 CAPVER RO 0x1 Capability Version. The value of 0x1. indicates compatibility

with version 1 of the specification.

31:20 NXTPTR RWL 0x0 Next Pointer.

Bit

Field Field

Name Type Default

Value Description

31:0 SNUM RWL 0x0

Sticky Lower 32-bits of Device Serial Number. This field contains the

lower 32-bits of the IEEE defined 64-bit extended unique identi-

fier (EUI-64) assigned to the device.

Bit

Field Field

Name Type Default

Value Description

31:0 SNUM RWL 0x0

Sticky Upper 32-bits of Device Serial Number. This field contains the

upper 32-bits of the IEEE defined 64-bit extended unique identi-

fier (EUI-64) assigned to the device.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 49 February 22, 2012

Notes

PCI Expres s Virtual Channel Capabi lity

PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200)

PVCCAP1- Port VC Capability 1 (0x204)

Bit

Field Field

Name Type Default

Value Description

15:0 CAPID RO 0x2 Capability ID. The value of 0x2. indicates a virtual channel capa-

bility structure.

19:16 CAPVER RO 0x1 Capability Version. The value of 0x1. indicates compatibility

with version 1 of the specification.

31:20 NXTPTR RWL 0x0 Next Pointer. The value of 0x0 indicates that there are no

extended capabilities.

Bit

Field Field

Name Type Default

Value Description

2:0 EVCCNT RO 0x0 Extended VC Count. The value 0x0 indicates only implementa-

tion of the default VC.

3 Reserved RO 0x0 Reserved field.

6:4 LPEVCCNT RO 0x0 Low Priority Extended VC Count. The value of 0x0 indicates

only implementation of the default VC.

7 Reserved RO 0x0 Reserved field.

9:8 REFCLK RO 0x0 Reference Clock. WRR is not implemented.

11:10 PATBLSIZ RO Upstream:

0x2

Downstream:

0x0

Port Arbitration Table Entry Size. This field indicates the size of

the port arbitration table in the device. For the upstream port, the

is set to 0x2 to indicate a table with 4-bit entries. For downstream

ports, this value is set to 0x0.

0x0 - (bit1) Port arbitration table is 1-bit

0x1 - (bit2) Port arbitration table is 2-bits

0x2 - (bit4) Port arbitration table is 4-bits

0x3 - (bit8) Port arbitration table is 8-bits

31:12 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 50 February 22, 2012

Notes

PVCCAP2- Port VC Capability 2 (0x208)

PVCCTL - Port VC Control (0x20C)

PVCSTS - Port VC Status (0x20E)

Bit

Field Field

Name Type Default

Value Description

7:0 VCARBCAP RO 0x0 VC Arbitration Capability. This field indicates the type of VC

arbitration that is supported by the port for the low priority VC

group.

This field is valid for all ports that report a low priority extended

VC count greater than zero.

Each bit in this field corresponds to a VC arbitration capability.

bit 0 - hardware fixed arbitration (i.e., round robin)

bit 1 - weighted round robin (WRR) with 32 phases

bit 2 - weighted round robin (WRR) with 64 phases

bit 3 - weighted round robin (WRR) with 128 phases

bits 4 through 7 - reserved

23:8 Reserved RO 0x0 Reserved field.

31:24 VCATBLOFF RO 0x0 VC Arbitration Table Offset. This field contains the offset of the

VC arbitration table from the base address of the Virtual Channel

Capability structure in double quad words (16 bytes).

The value of zero indicates that the VC arbitration table is not

present.

Bit

Field Field

Name Type Default

Value Description

0LVCATRO0x0Load VC Arbitration Table. This bit, when set, updates the VC

arbitration logic from the VC Arbitration Table for the VC

resource.

Since the device does not implement a VC arbitration table, this

field has no functional effect.

This bit always returns 0 when read.

3:1 VCARBSEL RW 0x0 VC Arbitration Select. This field configures the VC arbitration by

selecting one of the supported arbitration schemes indicated by

the VC arbitration capability field (i.e., the VCARBCAP field in the

PVCCAP2 register).

Since the device supports only VC0, this field has no functional

effect.

15:4 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0 VCATS RO 0x0 VC Arbitration Table Status. This bit indicates the coherency

status of the VC arbitration table.

Since the device supports only VC0, this field has no functional

effect and is always zero.

15:1 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 51 February 22, 2012

Notes

VCR0CAP- VC Resource 0 Capability (0x210)

VCR0CTL- VC Resource 0 Control (0x214)

Bit

Field Field

Name Type Default

Value Description

7:0 PARBC RO Upstream:

0x3

Downstream:

0x1

Port Arbitration Capability. This field indicates the type of port

arbitration supported by the VC. Each bit corresponds to a Port

Arbitration capability. When more than one arbitration scheme is

supported, multiple bits may be set.

The upstream port supports hardware fixed round robin and

weighted round robin with 32 phases.

Downstream ports support only hardware fixed round robin.

bit 0 - hardware fixed round robin

bit 1 - weighted round robin with 32 phases

bit 2 - weighted round robin with 64 phases

bit 3 - weighted round robin with 128 phases

bit 4 - time-based weighted round robin with 128 phases

bit 5 - weighted round robin with 256 phases

13:8 Reserved RO 0x0 Reserved field.

14 APS RO 0x0 Advanced Packet Switching. Not supported.

15 RJST RO 0x0 Reject Snoop Transactions. No supported for switch ports.

22:16 MAXTS RO 0x0 Maximum Time Slot s. Since this VC does not support time-

based WRR, this field is not valid.

23 Reserved RO 0x0 Reserved field.

31:24 PATBLOFF RO Upstream:

0x2

Downstream:

0x0

Port Arbitration Table Offset. This field contains the offset of

the port arbitration table from the base address of the Virtual

Channel Capability structure in double quad words (16 bytes).

The upstream port has a port arbitration table. Downstream ports

do not have a port arbitration table.

Bit

Field Field

Name Type Default

Value Description

7:0 TCVCMAP bit 0 RO

bits 1

through

0xFF TC/VC Map. This field indicates the TCs that are mapped to the

VC resource. Each bit corresponds to a TC. When a bit is set, the

corresponding TC is mapped to the VC.

15:8 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 52 February 22, 2012

Notes

VCR0STS - VC Resource 0 Status (0x218)

16 LPAT RW 0x0 Load Port Arbitration Table. This bit, when set, updates the

Port Arbitration logic from the Port Arbitration Table for the VC

resource. In addition, this field is only valid when the Port Arbitra-

tion Table is used by the selected Port Arbitration scheme (that is

indicated by a set bit in the Port Arbitration Capability field

selected by Port Arbitration Select).

Software sets this bit to signal hardware to update Port Arbitra-

tion logic with new values stored in Port Arbitration Table; clear-

ing this bit has no effect. Software uses the Port Arbitration Table

Status bit to confirm whether the new values of Port Arbitration

Table are completely latched by the arbitration logic.

This bit only has an effect in the upstream port.

This bit always returns 0 when read.

19:17 PARBSEL RW 0x0 Port Arbitration Select. This field configures the VC resource to

provide a particular Port Arbitration service.

The permissible values of this field is a number that corresponds

to one of the asserted bits in t he Port Arbitration Capability field

of the VC resource.

23:20 Reserved RO 0x0 Reserved field.

26:24 VCID RO 0x0 VC ID. This field assigns a VC ID to the VC resource. Since the

PES24T3G2 implements only a single VC, this field is hardwired

to zero.

30:27 Reserved RO 0x0 Reserved field.

31 VCEN RO 0x1 VC Enable. This field, when set, enables a virtual channel. Since

The PES24T3G2 implements only a single VC, this field is hard-

wired to one (enabled).

Bit

Field Field

Name Type Default

Value Description

15:0 Reserved RO 0x0 Reserved field.

16 PATS RO 0x0 Port Arbitration Table Status. This bit indicates the coherency

status of the port arbitration table associated with the VC

resource and is valid only when the port arbitration table is used

by the selected arbitration algorithm.

This bit is set when any entry of the port arbitration table is written

by software and remains set until hardware finishes loading the

value after software sets the LPAT field in the VCR0CTL register.

This field is always zero for downstream ports.

17 VCNEG RO 0x0 VC Negotiation Pending. Since the PES24T3G2 implements

only a single VC (i.e., the default VC) this field indicates the sta-

tus of the process of flow control initialization. This bit is cleared

by hardware after the VC negotiation is complete (on exit from

the FC_INIT2 state).

The value of this field is defined only when the Link is in the

DL_Active state and the Virtual Channel is enabled (its VC

Enable bit is Set).

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 53 February 22, 2012

Notes

VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)

VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)

31:18 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

3:0 PHASE0 RW 0x1 Phase 0. This field contains the port ID for the corresponding port

arbitration period. Selecting an invalid port ID results in the entry

being skipped without delay.

The port arbitration behavior when this field contains an illegal

value (i.e., reserved or the egress port ID) is undefined.

0x0 - (port_0) Port 0 (upstream port)

0x1 - Reserved

0x2 - (port_2) Port 2

0x3 - Reserved

0x4 - (port_4) Port 4

0x5 through 0xF - Reserved

7:4 PHASE1 RW 0x2 Phase 1. This field contains the port ID for the corresponding port

arbitration period.

11:8 PHASE2 RW 0x3 Phase 2. This field contains the port ID for the corresponding port

arbitration period.

15:12 PHASE3 RW 0x4 Phase 3. This field contains the port ID for the corresponding port

arbitration period.

19:16 PHASE4 RW 0x5 Phase 4. This field contains the port ID for the corresponding port

arbitration period.

23:20 PHASE5 RW 0x6 Phase 5. This field contains the port ID for the corresponding port

arbitration period.

27:24 PHASE6 RW 0x7 Phase 6. This field contains the port ID for the corresponding port

arbitration period.

31:28 PHASE7 RW 0x1 Phase 7. This field contains the port ID for the corresponding port

arbitration period.

Bit

Field Field

Name Type Default

Value Description

3:0 PHASE8 RW 0x2 Phase 8. This field contains the port ID for the corresponding port

arbitration period.

7:4 PHASE9 RW 0x3 Phase 9. This field contains the port ID for the corresponding port

arbitration period.

11:8 PHASE10 RW 0x4 Phase 10. This field contains the port ID for the corresponding

port arbitration period.

15:12 PHASE11 RW 0x5 Phase 11. This field contains the port ID for the corresponding

port arbitration period.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 54 February 22, 2012

Notes

VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)

VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C)

19:16 PHASE12 RW 0x6 Phase 12. This field contains the port ID for the corresponding

port arbitration period.

23:20 PHASE13 RW 0x7 Phase 13. This field contains the port ID for the corresponding

port arbitration period.

27:24 PHASE14 RW 0x1 Phase 14. This field contains the port ID for the corresponding

port arbitration period.

31:28 PHASE15 RW 0x2 Phase 15. This field contains the port ID for the corresponding

port arbitration period.

Bit

Field Field

Name Type Default

Value Description

3:0 PHASE16 RW 0x3 Phase 16. This field contains the port ID for the corresponding

port arbitration period.

7:4 PHASE17 RW 0x4 Phase 17. This field contains the port ID for the corresponding

port arbitration period.

11:8 PHASE18 RW 0x5 Phase 18. This field contains the port ID for the corresponding

port arbitration period.

15:12 PHASE19 RW 0x6 Phase 19. This field contains the port ID for the corresponding

port arbitration period.

19:16 PHASE20 RW 0x7 Phase 20. This field contains the port ID for the corresponding

port arbitration period.

23:20 PHASE21 RW 0x1 Phase 21. This field contains the port ID for the corresponding

port arbitration period.

27:24 PHASE22 RW 0x2 Phase 22. This field contains the port ID for the corresponding

port arbitration period.

31:28 PHASE23 RW 0x3 Phase 23. This field contains the port ID for the corresponding

port arbitration period.

Bit

Field Field

Name Type Default

Value Description

3:0 PHASE24 RW 0x4 Phase 24. This field contains the port ID for the corresponding

port arbitration period.

7:4 PHASE25 RW 0x5 Phase 25. This field contains the port ID for the corresponding

port arbitration period.

11:8 PHASE26 RW 0x6 Phase 26. This field contains the port ID for the corresponding

port arbitration period.

15:12 PHASE27 RW 0x7 Phase 27. This field contains the port ID for the corresponding

port arbitration period.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 55 February 22, 2012

Notes

Power Budgeting Enhanced Capability

PWRBCAP - Power Budgeting Capabilities (0x280)

PWRBDSEL - Power Budgeting Data Select (0x284)

19:16 PHASE28 RW 0x1 Phase 28. This field contains the port ID for the corresponding

port arbitration period.

23:20 PHASE29 RW 0x2 Phase 29. This field contains the port ID for the corresponding

port arbitration period.

27:24 PHASE30 RW 0x3 Phase 30. This field contains the port ID for the corresponding

port arbitration period.

31:28 PHASE31 RW 0x4 Phase 31. This field contains the port ID for the corresponding

port arbitration period.

Bit

Field Field

Name Type Default

Value Description

15:0 CAPID RWL 0x0 Capability ID. The value of 0x4 indicates a power budgeting

capability structure.

If the power budgeting capability is used, then this field should be

initialized with data from a serial EEPROM.

19:16 CAPVER RWL 0x0 Capability Version. The value of 0x1. indicates compatibility

with version 1 of the specification.

If the power budgeting capability is used, then this field should be

initialized with data from a serial EEPROM.

31:20 NXTPTR RWL 0x0 Next Pointer.

Bit

Field Field

Name Type Default

Value Description

7:0 DVSEL RW 0x0 Data Value Select. This field selects the Power Budgeting Data

Value (PWRBDVx) register whose contents are reported in the

Data (DATA) field of the Power Budgeting Data (PWRBD) regis-

ter.

Setting this field to a value greater than 7, causes zero to be

returned in the DATA field of the PWRBD register.

31:8 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 56 February 22, 2012

Notes

PWRBD - Power Budgeting Data (0x288)

PWRBPBC - Power Budgeting Power Budget Capability (0x28C)

PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)

Switch Control and Status Registers

SWSTS - Switch Status (0x400)

Bit

Field Field

Name Type Default

Value Description

31:0 DATA RO 0x0 Data. If the Data Value Select (DVSEL) field in the Power Bud-

geting Data Select register contains a value of zero through 7,

then this field returns the contents of the corresponding Power

Budgeting Data Value (PWRBDVx) register. Otherwise, this field

contains a value of zero .

Bit

Field Field

Name Type Default

Value Description

0SARWL0x0System Allocated. When this bit is set, it indicates that the

power budget for the device is included within the system power

budget and that reported power data for this device should be

ignored.

If the power budgeting capability is used, then this field should be

initialized with data from a serial EEPROM.

31:1 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

31:0 DV RW Undefined

Sticky Data Value. This 32-bit field is used to hold power budget data in

the format described in Section 7.15.3 in the PCIe 2.0 Base

Specification.

This field may be read and written when the Power Budgeting

Data Value Unlock (PWRBDVUL) bit is set in the Switch Control

(SWCTL) register. When the PWRBDVUL bit is cleared, this reg-

ister is read-only and writes are ignored.

If the power budgeting capability is used, then this field should be

initialized with data from a serial EEPROM.

Bit

Field Field

Name Type Default

Value Description

2:0 SWMODE RO HWINIT Switch Mode. These configuration pins determine the

PES24T3G2 switch operating mode.

0x0 - Normal Switch Mode

0x1 - Normal Switch Mode with Serial EEPROM initialization

0x2 through 0x7 - reserved

4:3 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 57 February 22, 2012

Notes

SWCTL - Switch Control (0x404)

5 CCLKDS RO HWINIT Common Clock Downstream. This bit reflects the value of the

CCLKDS signal sampled during Fundamental Reset.

6 CCLKUS RO HWINIT Common Clock Upstream. This bit reflects the value of the

CCLKUS signal sampled during Fundamental Reset.

7 MSMB-

SMODE RO HWINIT Master SMBus Slow Mode. This bit reflects the value of the

MSMBSMODE signal sampled during Fundamental Reset.

8 REFCLKM RO HWINIT PCI Express Reference Clock Mode Select. This bit reflects the

value of the REFCLKM signal sampled during Fundamental

Reset.

9 RSTHALT RO HWINIT Reset Halt. This bit reflects the value of the RSTHALT signal

sampled during Fundamental Reset.

19:10 Reserved RO 0x0 Reserved field.

22:20 LOCKMODE RO 0x0 Lock Mode. This field reflects the current locked status of the

switch.

0x0 - (unlocked) Upstream port is unlocked

0x1 - Reserved

0x2 - (port2locked) Upstream port is locked with port 2.

0x3 - (Reserved

0x4 - (port4locked) Upstream port is locked with port 4.

0x5 - Reserved

27:23 Reserved RO 0x0 Reserved field.

31:28 MARKER RW 0x0

Sticky Marker. This field is preserved across a hot reset and is available

for general software use.

A hot reset does not result in modification of this field.

Bit

Field Field

Name Type Default

Value Description

0FRSTRW0x0Fundamental Reset. Writing a one to this bit initiates a Funda-

mental Reset. Writing a zero has no effect. This field always

returns a value of zero when read.

Writing of a one to this bit always results in the PES24T3G2

returning a completion to the requester before the action speci-

fied by this bit takes effect.

See section Fundamental Reset on page 2-2 for the behavior of

this bit.

1 HRST RW 0x0 Hot Reset. Writing a one to this bit initiates a hot reset. Addition-

ally, the upstream port’s PHY initiates a full link retrain.

Writing a zero has no effect. This field always returns a value of

zero when read.

Writing of a one to this bit always results in the PES24T3G2

returning a completion to the requester before the action speci-

fied by this bit takes effect.

See section Hot Reset on page 2-5 for the behavior of this bit.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 58 February 22, 2012

Notes

2 RSTHALT RW HWINIT

Sticky Reset Halt. When this bit is set, all of the switch logic except the

SMBus interface remains in a reset state. In this state, registers

in the device may be initialized by the slave SMBus interface.

When this bit is cleared, normal operation ensues.

Setting or clearing this bit has no effect following a reset opera-

tion.

This bit may be set by asserting the RSTHALT signal during a

reset operation or through initialization by the serial EEPROM.

3REGUN-

LOCK RW 0x0

Sticky Register Unlock. When this bit is set, the contents of registers

and fields of type Read and Write when Unlocked (RWL) are

modified when written to. When this bit is cleared, all registers

and fields denoted as RWL become read-only.

While the initial value of this field is cleared, it is set during a reset

operation, thus allowing serial EEPROM initialization to modify

the contents of RWL fields.

4 PWRBDVUL RWL 0x0

Sticky Power Budgeting Data Value Unlock. When this bit is set, the

Power Budgeting Data Value [7:0] (PWRBDV[7:0]) registers in all

ports may be read and written. When this bit is cleared, then the

PWRBDV registers in all ports are read-only.

5 DLDHRST RW 0x0

Sticky Disable Link Down Hot Reset. When this bit is set, hot resets

due to the data link layer of the upstream port transitioning to the

DL_Down state are disabled.

All other hot reset conditions are unaffected by this bit.

6 DHRSTSEI RW 0x0

Sticky Disable Hot Reset Serial EEPROM Initialization. When this bit

is set, step 6 “serial EEPROM initialization” is skipped in the hot

reset sequence described in section Hot Reset on page 2-5

regardless of the selected switch operating mode.

7DRORW0x0

Sticky Disable Relaxed Ordering. The switch implements relaxed

ordering for TLPs with the relaxed ordering bit set. When the

DRO bit is set, the switch strongly orders all transactions regard-

less of the state of the relaxed ordering bit in TLPs.

8DP2PRW0x0

Sticky Disable Peer-to-Peer Transactions. When this bit is set, all

peer-to-peer transactions are disabled. In this mode, transactions

received on a downstream port which are not destined to the

upstream port are treated as an unsupported requests.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 59 February 22, 2012

Notes

10:9 DDDNC RW 0x0

Sticky Disable Downstream Device Number Checking. According to

Section 7.3.1. Device Number in PCIe base 2.0, configuration

requests specifying target device 0 in a bus number associated

with a downstream link are delivered to the device attached to the

link; configuration requests specifying all other device numbers

(1-31) must be terminated by the switch downstream port with an

unsupported request.

This field controls the extent to which device numbers are

checked by downstream ports.

This field is present for backwards compatibility with earlier IDT

switches that implement a proprietary version of ARI forwarding.

This field has no functional effect on the operation of a port when

the ARI Forwarding Enable (ARIFEN) bit is set in the port’s PCI

Express Device Control 2 (PCIEDCTL2) register.

0x0 - (all) Inhibit the transmission of all TLPs that are routed by

ID, specify a bus number associated with a downstream

port link, and specify a device number other than zero.

0x1 - (cfg) Inhibit the transmission of configuration request

TLPs that are routed by ID, specify a bus number associ-

ated with a downstream port link, and specify a device

number other than zero. Non-configuration request TLPs

are delivered to the device attached to a link associated

with a downstream switch port regardless of the speci-

fied device number.

0x2 - (none) All TLPs are delivered to the device attached to a

link associated with a downstream switch port regardless

of the specified device number.

0x3 - reserved

11 EUIDC RW 0x0

Sticky Enable Upstream Port ID Checking. Normally TLPs with a non-

zero device number that target the bus number corresponding to

the upstream link and are received on a downstream port are for-

warded upstream and are emitted on the upstream link.

When this bit is set, these request TLPs are treated as unsup-

ported requests (UR) and completion TLPs are silently discarded.

This field should be documented

13:12 Reserved RO 0x0 Reserved field.

14 CTDIS RW 0x0

Sticky Disable Cut-Through Routing. When this bit is set, cut through

routing of TLPs is disabled between all ports (i.e., they are routed

in a stored and forwarded manner). When this bit is cleared,

TLPs are routed in a cut-through manner when possible.

15 LOCK-

IGNORE RW 0x0

Sticky Ignore Locked Transactions When this bit is set, all bus locking

side-effects associated with locked transactions (e.g., MRdLk)

are ignored and the TLPs are treated by the PES24T3G2 as nor-

mal TLPs (e.g., are routed normally through the switch).

18:16 Reserved RO 0x0 Reserved field.

19 BDISCARD RW 0x0

Sticky Discard Vendor Defined Broadcast Messages. When this bit is

set, vendor defined Type 1 broadcast messages received on the

upstream port are silently discarded and not forwarded down-

stream.

Silently discarding a TLP means that flow control credits are

returned, TLP contents are discarded, and no error bits are set.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 60 February 22, 2012

Notes

HPCFGCTL - Hot-Plug Configuration Control (0x408)

31:20 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0 IPXAPN RW 0x0

Sticky Invert Polarity of PxAPN. When this bit is set, the polarity of the

PxAPN input is inverted in all ports.

1 IPXPDN RW 0x0

Sticky Invert Polarity of PxPDN. When this bit is set, the polarity of the

PxPDN input is inverted in all ports.

2 IPXPFN RW 0x0

Sticky Invert Polarity of PxPFN. When this bit is set, the polarity of the

PxPFN input is inverted in all ports.

3 IPXMRLN RW 0x0

Sticky Invert Polarity of PxMRLN. When this bit is set, the polarity of

the PxMRLN input is inverted in all ports.

4 IPXAIN RW 0x0

Sticky Invert Polarity of PxAIN. When this bit is set, the polarity of the

PxAIN output is inverted in all ports.

5 IPXPIN RW 0x0

Sticky Invert Polarity of PxPIN. When this bit is set, the polarity of the

PxPIN output is inverted in all ports.

6 IPXPEP RW 0x0

Sticky Invert Polarity of PxPEP. When this bit is set, the polarity of the

PxPEP output is inverted in all ports.

7 IPXILOCKP RW 0x0

Sticky Invert Polarity of PxILOCKP. When this bit is set, the polarity of

the PxILOCKP output is inverted in all ports.

8 IPXPWRGDN RW 0x0

Sticky Invert Polarity of PxPWRGDN. When this bit is set, the polarity

of the PxPWRGDN input is inverted in all ports.

10:9 PDETECT RW 0x0

Sticky Presence Detect Control. This field controls the manner in

which presence of an adapter in a slot is reported to the hot-plug

controller associated with a downstream switch port.

0x0 -(both) Presence of an adapter in the slot is reported as the

logical “OR” of the receiver detect mechanism selected by the

RDETECT field in the PHYLCFG register and the hot-plug pres-

ence detect input (PxPDN).

0x1 - (signal) Presence of an adapter in the slot is reported as the

state of the hot-plug presence detect input (PxPDN).

0x2 - (always) When selected this mode always informs the hot-

plug controller that an adapter is present.

0x3 - (never) When selected this mode always informs the hot-

plug controller that an adapter is not present.

11 MRLP-

WROFF RW 0x1

Sticky When the MRL Automatic Power Off. When this bit is set and the

Manual Retention Latch Present (MRLP) bit is set in the PCI

Express Slot Capability (PCIESCAP) register, then power to the

slot is automatically turned off when the MRL sensor indicates

that the MRL is open. This occurs regardless of the state of the

Power Controller Control (PCC) bit in the PCI Express Slot Con-

trol (PCIESCTL) register.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 61 February 22, 2012

Notes

GPIOFUNC - General Purpose I/O Control Function (0x418)

12 RMRLWEMIL RW 0x0

Sticky Replace MRL Status with EMIL Status. When this bit is set, the

PxMRLN signal inputs are used as electromechanical lock state

inputs.

13 TEMICTL RW 0x0

Sticky Toggle Electromechanical Interlock Control. When this bit is

cleared, the Electromechanical Interlock (PxILOCKP) output is

pulsed for at least 100 ms and at most 150 ms when a one is writ-

ten to the EIC bit in the PCIESCTL register. When this bit is set,

writing a one to the EIC register inverts the state of the

PxILOCKP output.

15:14 RSTMODE RW 0x0

Sticky Reset Mode. This field controls the manner in which downstream

port reset outputs are generated.

0x0 - (pec) Power enable controlled reset output

0x1 - (pgc) Power good controlled reset output

0x2 - Reserved

0x3 - Reserved

23:16 PWR2RST RW 0x14

Sticky Slot Power to Reset Negation. This field contains the delay

from stable downstream port power to negation of the down-

stream port reset in units of 10 mS. A value of zero corresponds

to no delay.

This field may be used to meet the TPCPERL specification.

The default value corresponds to 200 mS.

31:24 RST2PWR RW 0x14

Sticky Reset Negation. This field contains the delay from negation of a

downstream port’s reset to disabling of a downstream port’s

power in units of 10 mS. A value of zero corresponds to no delay.

The default value corresponds to 200 mS.

Bit

Field Field

Name Type Default

Value Description

15:0 GPIOFUNC RW 0x0

Sticky GPIO Function. Each bit in this field controls the corresponding

GPIO pin. When set to a one, the corresponding GPIO pin oper-

ates as the alternate function as defined in Chapter 4, General

Purpose I/O. When a bit is cleared to a zero, the corresponding

GPIO pin operates as a general purpose I/O pin.

31:16 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 62 February 22, 2012

Notes

GPIOCFG - General Purpose I/O Configuration (0x41C)

GPIOD - General Purpose I/O Data (0x420)

SMBUSSTS - SMBus Status (0x424)

Bit

Field Field

Name Type Default

Value Description

15:0 GPIOCFG RW 0x0

Sticky GPIO Configuration. Each bit in this field controls the corre-

sponding GPIO pin. When a bit is configured as a general pur-

pose I/O pin and the corresponding bit in this field is set, then the

pin is configured as a GPIO output. When a bit is configured as a

general purpose I/O pin and the corresponding bit in this field is

zero, then the pin is configured as an input. When the pin is con-

figured as an alternate function, the behavior of the pin is defined

by the alternate function.

31:16 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

15:0 GPIOD RW HWINIT

Sticky GPIO Data. Each bit in this field controls the corresponding GPIO

pin. Reading this field returns the current value of each GPIO pin

regardless of GPIO pin mode (i.e., alternate function or GPIO

pin). Writing a value to this field causes the corresponding pins

which are configured as GPIO outputs to change state to the

value written.

31:16 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0 Reserved RO 0x0 Reserved field.

7:1 SSMBADDR RO HWINIT Slave SMBus Address. This field contains the SMBus address

assigned to the slave SMBus interface.

8 Reserved RO 0x0 Reserved field.

15:9 MSMBADDR RO HWINIT Master SMBus Address. This field contains the SMBus address

assigned to the master SMBus interface.

23:16 Reserved RO 0x0 Reserved field.

24 EEPROM-

DONE RO 0x0 Serial EEPROM Initialization Done. When the switch is config-

ured to operate in a mode in which serial EEPROM initialization

occurs during a Fundamental Reset, this bit is set when serial

EEPROM initialization completes or when an error is detected.

25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected NACK is

observed during a master SMBus transaction. The setting of this

bit may indicate the following: that the addressed device does not

exist on the SMBus (i.e., addressing error); data is unavailable or

the device is busy; an invalid command was detected by the

slave; or invalid data was detected by the slave.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 63 February 22, 2012

Notes

SMBUSCTL - SMBus Control (0x428)

26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus interface loses

arbitration for the SMBus, it automatically re-arbitrates for the

SMBus. If the master SMBus interface loses 16 consecutive arbi-

tration attempts, then the transaction is aborted and this bit is set.

27 OTHERERR RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP condi-

tion is detected by the master SMBus interface.

28 ICSERR RW1C 0x0 Init ializatio n Che cksu m Error. This bit is set if an invalid check-

sum is computed during Serial EEPROM initialization or when a

configuration done command is not found in the serial EEPROM.

29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is set if an

attempt is made to initialize via serial EEPROM a register that is

not defined in the corresponding PCI configuration space.

31:30 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

15:0 MSMBCP RW HWINIT

Sticky Master SMBus Clock Prescalar. This field contains a clock

prescalar value used during master SMBus transactions. The

prescalar clock period is equal to 32 ns multiplied by the value in

this field. When the field is cleared to zero or one, the clock is

stopped.

The initial value of this field is 0x0139 when the master SMBus is

configured to operate in slow mode (i.e., 100 KHz) in the boot

configuration and to 0x00531 when it is configured to operate in

fast mode (i.e., 400 KHz).

16 MSMBIOM RW 0x0

Sticky Master SMBus Ignore Other Masters. When this bit is set, the

master SMBus proceeds with transactions regardless of whether

it won or lost arbitration.

17 ICHECKSUM RW 0x0

Sticky Igno re Checksum Errors. When this bit is set, serial EEPROM

initialization checksum errors are ignored (i.e., the checksum

always passes).

19:18 SSMBMODE RW 0x0

Sticky Slave SMBus Mode. The salve SMBus contains internal glitch

counters on the SSMBCLK and SSMBDAT signals that wait

approximately 1uS before sampling or driving these signals. This

field allows the glitch counter time to be reduced or entirely

removed. In some systems, this may permit high speed slave

SMBus operation.

0x0 - (normal) Slave SMBus normal mode. Glitch counters oper-

ate with 1uS delay.

0x1 - (fast) Slave SMBus interface fast mode. Glitch counters

operate with 100nS delay.

0x2 - (disabled) Slave SMBus interface with glitch counters dis-

abled. Glitch counters operate with zero delay which effec-

tively removes them.

0x3 - reserved.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 64 February 22, 2012

Notes

EEPROMINTF - Serial EEPROM Interface (0x42C)

21:20 MSMBMODE RW 0x0

Sticky Master SMBus Mode. The master SMBus contains internal

glitch counters on the MSMBCLK and MSMBDAT signals that

wait approximately 1uS before sampling or driving these signals.

This field allows the glitch counter time to be reduced or entirely

removed. In some systems, this may permit high speed master

SMBus operation.

0x0 - (normal) Master SMBus normal mode. Glitch counters oper-

ate with 1uS delay.

0x1 - (fast) Master SMBus interface fast mode. Glitch counters

operate with 100nS delay.

0x2 - (disabled) Master SMBus interface with glitch counters dis-

abled. Glitch counters operate with zero delay which effec-

tively removes them.

0x3 - reserved.

22 SMBDTO RW 0x0 SMBus Disable Time-out. When this bit is set, SMBus time-outs

are disabled on the master and slave SMBuses.

31:23 Reserved RO 0x0 Reserved field.

1. The M SMBCLK l ow minimu m puls e widt h is eq ual to half th e perio d prog ramme d in th is field . The value of 0x53 , whic h corre -

sponds to ~37 3 KH z, allo ws the min low puls e widt h to be sa tisfi ed. In syste ms wh ere this tim ing param ete r is not cr itica l, the op -

erati ng freq uen cy ma y be increa se d.

Bit

Field Field

Name Type Default

Value Description

15:0 ADDR RW 0x0 EEPROM Address. This field contains the byte address in the

Serial EEPROM to be read or written.

23:16 DATA RW 0x0 EEPROM Data. A write to this field will initiates a serial EEPROM

read or write operation, as selected by the OP field, to the

address specified in the ADDR field.

When a write operation is selected, the value written to this field

is the value written to the serial EEPROM. When a read operation

is selected, the value written to this field is ignored and the value

read from the serial EEPROM may be read from this field when

the DONE bit is set.

24 BUSY RO 0x0 EEPROM Busy. This bit is set when a serial EEPROM read or

write operation is in progress.

0x0 - (idle) serial EEPROM interface idle

0x1 - (busy) serial EEPROM interface operation in progress

25 DONE RW1C 0x0 EEPROM Operation Completed. This bit is set when a serial

EEPROM operation has completed.

0x0 - (notdone) interface is idle or operation in progress

0x1 - (done) operation completed

26 OP RW 0x0 EEPROM Operation Select. This field selects the type of

EEPROM operation to be performed when the DATA field is writ-

ten

0x0 - (write) serial EEPROM write

0x1 - (read) serial EEPROM read

31:27 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 65 February 22, 2012

Notes

IOEXPINTF - I/O Expander Interface (0x430)

‘

Bit

Field Field

Name Type Default

Value Description

15:0 IOEDATA RW 0x0 I/O Expander Data. Each bit in this field corresponds to an I/O

expander input/output signal. Reading this field returns the cur-

rent value of the corresponding I/O pin state of the I/O expander

number selected in the Select (SEL) field in this register (i.e., the

input values last read from the I/O expander and output values

supplied to the I/O expander).

Writes to this field are ignored unless the I/O Expander Test

Mode (IOEXTM) bit is set. When the IOEXTM bit is set, the value

for outputs supplied to the I/O expander selected by the SEL field

correspond to the value written to this field instead of the value

supplied by internal logic. Bits in this field which correspond to

inputs are always read-only, even when the IOEXTM bit is set.

23:16 Reserved RO 0x0 Reserved field.

24 RELOAD-

IOEX RW 0x0 Reload I/O Expander Signals. Writing a one to this field results

in an I/O expander SMBus transaction that refreshes all I/O

expander input and output signal values in the IOEDATA field.

This bit always returns a zero when read.

25 IOEXTM RW 0x0 IO Expander Test Mode. Setting this bit puts the I/O expander

interface into a test mode. In this test mode, I/O expander output

signals generated by the PES24T3G2 core are ignored and val-

ues supplied to the I/O expander correspond to value written to

the IOEDATA field when the RELOADIOEX bit is set.

29:26 SELECT RW 0x0 I/O Expander Select. This field selects the I/O expander on

which fields in this register operates.

0x0 - (ioe0) I/O expander 0

0x1 - (ioe1) I/O expander 1

0x2 - (ioe2) I/O expander 2

0x3 - (ioe3) I/O expander 3

0x4 - (ioe4) I/O expander 4

others - reserved

30 Reserved RO 0x0 Reserved field.

31 DONE RW1C 0x0 I/O Expander Operati on Done. This bit is set when any of the

following conditions occur.

RELOADIOEX bit in this register is written, the corresponding I/O

expander is selected by the SELECT field in this register, and the

corresponding IO expander SMBus transaction completes.

The I/O expander is in test mode (i.e., IOEXTM bit set), the IOE-

DATA field is written with the RELOADIOEX bit set, the corre-

sponding I/O expander is selected by the SELECT field in this

updating the I/O expander outputs completes.

An I/O Expander Address (IOExADDR) field is written in an

SMBus I/O Expander Address (IOEXPADRy) register, the corre-

sponding I/O expander is selected by the SELECT field in this

IDT Configuration Registers

PES24T3G2 User Manual 8 - 66 February 22, 2012

Notes

IOEXPADDR0 - SMBus I/O Expander Address 0 (0x434)

IOEXPADDR1 - SMBus I/O Expander Address 1 (0x438)

GPECTL - General Purpose Event Control (0x450)

Bit

Field Field

Name Type Default

Value Description

0 Reserved RO 0x0 Reserved field.

7:1 IOE0ADDR RWL 0x0

Sticky I/O Ex pand er 0 A ddres s. This field contains the SMBus address

assigned to I/O expander 0 on the master SMBus interface.

8 Reserved RO 0x0 Reserved field.

15:9 IOE1ADDR RWL 0x0

Sticky I/O Ex pand er 1 A ddres s. This field contains the SMBus address

assigned to I/O expander 1 on the master SMBus interface.

16 Reserved RO 0x0 Reserved field.

23:17 IOE2ADDR RWL 0x0

Sticky I/O Ex pand er 2 A ddres s. This field contains the SMBus address

assigned to I/O expander 2 on the master SMBus interface.

24 Reserved RO 0x0 Reserved field.

31:25 IOE3ADDR RWL 0x0

Sticky I/O Ex pand er 3 A ddres s. This field contains the SMBus address

assigned to I/O expander 3 on the master SMBus interface.

Bit

Field Field

Name Type Default

Value Description

0 Reserved RO 0x0 Reserved field.

7:1 IOE4ADDR RWL 0x0

Sticky I/O Ex pand er 4 A ddres s. This field contains the SMBus address

assigned to I/O expander 4 on the master SMBus interface.

31:8 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0IGPERW0x0

Sticky Invert General Purpose Event Enable Signal Polarity. When

this bit is set, the polarity of all General Purpose Event (GPEN)

signals is inverted.

0x0 - (normal) GPEN signals are active low

0x1 - (invert) GPEN signals are active high

1 Reserved RO 0x0 Reserved field.

2 P2GPEE RW 0x0

Sticky Port 2 General Purpose Event Enable. When this bit is set, the

hot-plug INTx, MSI and PME event notification mechanisms

defined by the PCIe base 2.0 specification are disabled for port 2

and are instead signalled through General Purpose Event

(GPEN) signal assertions. GPEN is an alternate function of

GPIO[7].

3 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 67 February 22, 2012

Notes

GPESTS - General Purpose Event Status (0x454)

SERDESCTL- SerDes Control (0x500)

4 P4GPEE RW 0x0

Sticky Port 4 General Purpose Event Enable. When this bit is set, the

hot-plug INTx, MSI and PME event notification mechanisms

defined by the PCIe base 2.0 specification are disabled for port 4

and are instead signalled through General Purpose Event

(GPEN) signal assertions. GPEN is an alternate function of

GPIO[7].

31:5 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

1:0 Reserved RO 0x0 Reserved field.

2 P2GPES RO 0x0 Port 2 General Purpose Event Status. When this bit is set, the

corresponding port is signalling a general purpose event by

asserting the GPEN signal. This bit is never set if the correspond-

ing general purpose event is not enabled in the GPECTL register.

GPEN is an alternate function of GPIO[7] and GPIO[7] is

asserted only if enabled to operate as an alternate function.

3 Reserved RO 0x0 Reserved field.

4 P4GPES RO 0x0 Port 4 General Purpose Event Status. When this bit is set, the

corresponding port is signalling a general purpose event by

asserting the GPEN signal. This bit is never set if the correspond-

ing general purpose event is not enabled in the GPECTL register.

GPEN is an alternate function of GPIO[7] and GPIO[7] is

asserted only if enabled to operate as an alternate function.

31:5 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

7:0 Reserved RO 0x0 Reserved field.

8LSERW0x0

Sticky Low-Swing Mode Enable. When set, this bit enables Low-Swing

mode operation at the SerDes Transmit logic. Please refer to

section Low-Swing Transmitter Voltage Mode on page 3-10 for

further details.

0x0 - Full-Swing Mode

0x1 - Low-Swing Mode

31:9 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

IDT Configuration Registers

PES24T3G2 User Manual 8 - 68 February 22, 2012

Notes

PHYLCFG0 - Phy Link Configuration 0 (0x530)

Bit

Field Field

Name Type Default

Value Description

12:0 Reserved RO 0x0 Reserved field.

13 SCLINKEN RW 0x0

Sticky Self Cross Link Enable. When this bit is set, crosslink training

of a port to itself is enabled (i.e., the serial transmit lines of the

port may be connected to the serial receive lines of the same

port).

This bit has no effect when the CLINKDIS bit in this register is

set to 0x1.

Please refer to section Crosslink on page 3-10 for further

details.

14 ILSCC RW Upstream:

0x1

Down-

stream:

0x0

Sticky

Initial Link Speed Change Control. This field determines

whether a port automatically initiates a speed change to Gen2

speed, if Gen2 speed is permissible, after initial entry to L0 from

Detect.

0x0 - (automatic) Automatically initiate speed change to Gen2

speed, if permissible, after the first entry to L0 from

Detect.

0x1 - (nochange) Do not automatically initiate a speed change

to Gen2 speed, stay in Gen1 speed.

18:15 Reserved RO 0x0 Reserved field.

21:19 TLW RW 0x7 Target Link Width. This field indicates the target link width

when doing dynamic upconfiguration or downconfiguration of

the link (section Dynamic Link Width Reconfiguration on page 3-

3).

0x0 - Target LInk Width = x1

0x1 - Target Link Width = x2

0x2 - Target Link Width = x4

0x3 - Target Link Width = x8

0x4 - Reserved

0x5 - Reserved

0x6 - Reserved

0x7 - Target Link Width = Maximum Link Width (MAXLNK-

WDTH in the PCIELCAP register)

When performing link width downconfiguration, the value in this

field must be less than the Negotiated Link Width (NLW) field in

the PCIELSTS register.

When performing link width upconfiguration, the value written

into the TLW field must be greater than the NLW field and less

than the ILW field in the PCIELSTS register.

Link width upconfiguration or downconfiguration takes effect

when the Link Retrain (LRET) bit in the PCIELCTL register is

set.

Software must not simultaneously change the Target Link

Speed (TLS) field in the PCIELCTL2 together with this field

before setting the LRET bit. When this occurs, the behavior of

the PHY is undefined.

This field takes on its default value when the link is fully

retrained (i.e., the PHY LTSSM of the corresponding port transi-

tions through the DETECT state).

31:22 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 69 February 22, 2012

Notes

PHYLSTS0 - Phy Link Status 0 (0x538)

Bit

Field Field

Name Type Default

Value Description

11:0 Reserved RO 0x0 Reserved field.

13:12 RLWS RO 0x0 Reconfigure Link Width Status. This field indicates the status

of a link width upconfiguration or downconfiguration request.

0x0 - Idle (request not yet serviced)

0x1 - Success (re-configuration of the link succeeded)

0x2 - Problem (The link width was reconfigured, but did not

reach the target link width)

0x3 - Failed (The link width was not re-configured)

This field may be used by software to determine the success of

dynamic upconfiguration or downconfiguration of links. Please

refer to section Dynamic Link Width Reconfiguration on page 3-

3 for further details.

15:14 Reserved RO 0x0 Reserved field.

16 LPWUC RO 0x0 Link Partner Wid th Upconfiguration Capability. This bit indi-

cates a link partner’s ability to upconfigure link widths. This bit

reflects the state of the upconfigure_capable variable defined by

the PCIe 2.0 specification.

31:17 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 70 February 22, 2012

Notes

PHYLSTATE0 - Phy Link State 0 (0x540)

Bit

Field Field

Name Type Default

Value Description

4:0 LTSSMSTAT

ERO 0x0 Phy LTSSM State Machine State. This field contains the current

state of the Phy Link Training and Status State Machine

(LTSSM).

0x0 - XMIT_EIOS

0x1 - TMOUT_1MS

0x2 - DET_QUIET

0x3 - DET_ACTIV E

0x4 - POL_ACTIVE

0x5 - POL_COMPLIANCE

0x6 - POL_CONFIG

0x7 - RESERVE_1

0x8 - CFG_LWIDTH_START

0x9 - CFG_LWIDTH_ACCEPT

0xA - CFG_LNUM_WAIT

0xB - CFG_LNUM_ACCEPT

0xC - CFG _COMPLETE

0x D - CFG_IDLE

0xE - RESERVE_2

0xF - OVR_TMOUT

0x10 - REC_RCVR_LOCK

0x11 - REC_RCVR_CFG

0x12 - REC_IDLE

0x13 - REC_SPEED

0x14 - L0

0x15 - L0s

0x16 - L1_ENTRY

0x17 - L1_IDLE

0x18 - L2_IDLE

0x19 - L2_XMIT_WAKE

0x1A - DISABLE

0x1B- HOT_RST

0x1C - LPBK_ENTRY

0x1D - LPBK_ACTIVE

0x1E - LPBK_EXIT

0x1F - IDT_TM

30:5 Reserved RO 0x0 Reserved field.

31 FLRET RW 0x0 Full Link Retrain. Writing a one to this field initiates full link

retraining by directing the PHY LTSSM into the DETECT state.

This bit always returns zero when read.

Writing of a one to this bit always results in the PES24T3G2

returning a completion to the requester before the action speci-

fied by this bit takes effect.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 71 February 22, 2012

Notes

PHYPRBS - Phy PRBS Seed (0x55C)

Auto no mous Link Reliabili ty Management

ALRCTL - Autonomous Link Reliability Control (0x560)

Bit

Field Field

Name Type Default

Value Description

15:0 SEED RW 0xFFFF

Sticky Phy PRBS Seed Value. This field contains the PHY PRBS

seed value used for crosslink operation.

When the value in this register is modified, the PRBS counter

associated with this seed is reset to the seed value and re-starts

counting.

31:16 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

0ENRW0x0

Sticky Enable. When set, the Autonomous Link Reliability mechanism

described in section Autonomous Link Reliability Management

on page 3-6 is enabled.

0x0 - Autonomous Link Reliability Management Disabled

0x1 - Autonomous Link Reliability Management Enabled

1LETRW0x0

Sticky Link Error Type. This field can be programmed to select the

type of error monitored by the Autonomous Link Reliability Man-

agement logic.

0x0 - Individual Bit Errors (i.e., LCRC Errors)

0x1 - Link State Errors (i.e., LTSSM transitioning from the L0 to

the Recovery state due to the following link errors: clock com-

pensation FIFO underflow/overflow, electrical idle detected/

inferred on the receiver, lane de-skew aligner errors, and DL

layer errors that trigger link retraining).

Note that it is only possible to count link errors that cause the

port to initiate a link transition to Recovery. Link errors that

cause the link partner to initiate entry into the Recovery state

are not counted.

31:2 Reserved RO 0x0 Reserved field.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 72 February 22, 2012

Notes

ALRSTS - Autonomous Link Reliability Status (0x564)

ALRERT - Autonomous Link Reliability Error Rate Threshold (0x5680)

Bit

Field Field

Name Type Default

Value Description

0 ULD RW1C 0x0

Sticky Unreliable Link Detected. This bit is set by hardware to indi-

cate that the Autonomous Link Reliability logic has detected an

unreliable link. This occurs when the rate of errors in the link

matches or exceeds the threshold value specified in the ALR-

ERT register (i.e., the ENCNT field in the ALRCNT register is

greater than or equal to the ERRT field in the ALRERT register).

This bit is only set when the EN bit in the ALRCTL register is

set.

Once set, this bit is never cleared by hardware.

31:1 Reserved RO 0x0 Reserved field.

Bit

Field Field

Name Type Default

Value Description

7:0 ERRT RW 0xFF

Sticky Error Threshold. The value in this field represents the mini-

mum number of errors that must be detected by the Autono-

mous Link Reliability Management logic in order to determine

link unreliability.

The value of 0x0 is ‘Reserved’. When 0x0 is programmed into

this field, the operation is undefined.

Please refer to section Autonomous Link Reliability Manage-

ment on page 3-6 for further details.

31:8 PERIOD RW 0xFF_FFFF

Sticky Monitoring Period. The value in this field represents the time

window (in units of micro-seconds) in which a number of errors

equal to ERRT must be detected in order to determine link unre-

liability.

A value of 0x0 is ‘Reserved’. When 0x0 is programmed into this

field, the operation is undefined.

Please refer to section Autonomous Link Reliability Manage-

ment on page 3-6 for further details.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 73 February 22, 2012

Notes

ALRCNT - Autonomous Link Reliability Counter (0x56C)

Bit

Field Field

Name Type Default

Value Description

7:0 ENCNT RO 0x0 Error Number Count. This field contains the count for the num-

ber of errors detected by the Autonomous Link Reliability Man-

agement logic. The count saturates at its maximum value.

The value of this field is reset to 0x0 when the LRET bit in the

PCIELCTL register is set, or when a DL_Down event occurs

(i.e., LTSSM transitions through the Detect state).

The value of this field is also reset to 0x0 when the EN bit in the

ALRCS register transitions from zero to one.

Else, this count stops counting when the Autonomous Link Reli-

ability Management logic determines that a link is unreliable.

Else, this count is re-started from 0x0 when the value of the

MPCNT field in this register is equal to the value of the PERIOD

field in the ALRERT register.

This count remains active when the ALR mechanism is dis-

abled.

Please refer to section Autonomous Link Reliability Manage-

ment on page 3-6 for further details.

31:8 MPCNT RO 0x0 Monit or in g P er iod Coun t. This field contains the count for the

monitoring period associated with the Autonomous Link Reliabil-

ity Management Logic. The count saturates at its maximum

value.

Note that the count is in units of micro-seconds.

The value of this field is reset to 0x0 when the LRET bit in the

PCIELCTL register is set, or when a full link retrain event occurs

(i.e., LTSSM transitions through the Detect state).

The value of this field is also reset to 0x0 when the EN bit in the

ALRCS register transitions from zero to one.

Else, this count stops counting when the Autonomous Link Reli-

ability Management logic determines that a link is unreliable.

Else, this field is re-started from 0x0 when its value is equal to

the value of the PERIOD field in the ALRERT register.

This count remains active when the ALR mechanism is dis-

abled.

Please refer to section Autonomous Link Reliability Manage-

ment on page 3-6 for further details.

IDT Configuration Registers

PES24T3G2 User Manual 8 - 74 February 22, 2012

Notes

PES24T3G2 User Manual 9 - 1 February 22, 2012

Chapter 9

JTAG Boundary Scan

Introduction

The JTAG Boundary Scan interface provides a way to test the interconnections between integrated

circuit pins after they have been assembled onto a circuit board.

There are two pin types present in the PES24T3G2: AC-coupled and DC-coupled (also called AC and

DC pins). The Boundary Scan interface in the PES24T3G2 is IEEE 1149.1 compliant to allow testing of the

DC pins. The DC pins are those “normal” pins that do not require AC-coupling.

The presence of AC-coupling capacitors on some of the PES24T3G2 pins prevents DC values from

being driven between a driver and receiver. An AC Boundary Scan methodology, as described in IEEE

1149.6, is available to provide a time-varying signal to pass through the AC-coupling when in AC test mode;

however, IEEE 1149.6 is not supported in the PES24T3G2.

Test Access Point

The system logic utilizes a 16-state, TAP controller, a six-bit instruction register, and five dedicated pins

to perform a variety of functions. The primary use of the JTAG TAP Controller state machine is to allow the

five external JTAG control pins to control and access the PES24T3G2's many external signal pins. The

JTAG TAP Controller can also be used for identifying the device part number. The JTAG logic of the

PES24T3G2 is depicted in Figure 9.1.

Figure 9.1 Diagram of the JTAG Logic

Refer to the IEEE 1149.1 document for an operational description of the Boundary Scan and TAP

controller.

Signal Definitions

JTAG operations such as reset, state-transition control, and clock sampling are handled through the

signals listed in Table 9.1. A functional overview of the TAP Controller and Boundary Scan registers is

provided in the sections following the table.

Bypass Register

Instr u ct io n Registe r D e coder

6-Bit In st ruction R egister

Tap Controller

Device ID R egister

Boundary Scan Register

JTAG_TDI

JTAG_TMS

JTAG_TCK

JTAG_TRST_N

JTAG_TDO

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 2 February 22, 2012

Notes

The TAP controller transitions from state to state, according to the value present on JTAG_TMS, as

sampled on the rising edge of JTAG_TCK. The Test-Logic Reset state can be reached either by asserting

JTAG_TRST_N or by applying a 1 to JTAG_TMS for five consecutive cycles of JTAG_TCK. A state diagram

for the TAP controller appears in Figure 9.2. The value next to state represent the value that must be

applied to JTAG_TMS on the next rising edge of JTAG_TCK, to transition in the direction of the as sociated

arrow.

Figure 9.2 State Diagram of PES24T3G2’s TAP Controller

Pin Name Type Description

JTAG_TRST_N Input JTAG RESET (active low)

Asynchronous reset for JTAG TAP controller (internal pull-up)

JTAG_TCK Input JTAG Clock

Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge.

JTAG_TDO is output on the falling edge.

JTAG_TMS Input JTAG Mode Select. Requires an external pull-up.

Controls the state transitions for the TAP controller state machine (internal pull-up)

JTAG_TDI Input JTAG Input

Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS

JTAG_TDO Output JTAG Output

Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP con-

troller states.

Table 9.1 JTAG Pin Descriptions

Test- Logic

Reset

Run-Test/

Idle Select-

DR-Scan

Capture-DR

Shift-DR

Exit1 -DR

Pause-DR

Exit2-DR

Select-

IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-DR Update-IR

000

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 3 February 22, 2012

Notes

Boundary Scan Chain

Function Pin Name Type1

1. I = Input, O = Output

Boundary Cell2

2. O = Observe, C = Control

PCI Express Interface PE0RN[3:0] I O

PE0RP[3:0] I O

PE0TN[3:0] O C

PE0TP[3:0] O

PE2RN[3:0] I O

PE2RP[3:0] I O

PE2TN[3:0] O C

PE2TP[3:0] O

PE4RN[3:0] I O

PE4RP[3:0] I O

PE4TN[3:0] O C

PE4TP[3:0] O

PEREFCLKN I —

PEREFCLKP I —

REFCLKM I O

SMBus MSMBADDR[4:1] I O

MSMBCLK I/O O/C

MSMBDAT I/O O/C

SSMBADDR[5,3:1] I O

SSMBCLK I/O O/C

SSMBDAT I/O O/C

General Purpose I/O GPIO[7:0] I/O O/C

System Pins CCLKDS I O

CCLKUS I O

MSMBSMODE I O

PERSTN I O

RSTHALT I O

SWMODE[2:0] I —

EJTAG / JTAG JTAG_TCK I —

JTAG_TDI I —

JTAG_TDO O —

JTAG_TMS I —

JTAG_TRST_N I —

SerDes Reference

Resistors REFRES0 I/O —

REFRES1 I/O —

REFRES2 I/O —

REFRES3 I/O —

REFRES4 I/O —

REFRES5 I/O —

Table 9.2 Boundary Scan Chain

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 4 February 22, 2012

Notes

Test Data Register (DR)

The Test Data register contains the following:

Bypass register

Boundary Scan registers

Device ID register

These registers are connected in parallel between a common serial input and a common serial data

output and are described in the following sections. For more detailed descriptions, refer to IEEE Standard

Test Access Port (IEEE Std. 1149.1).

Boundary Scan Registers

This boundary scan chain is connected between JTAG_TDI and JTAG_TDO when EXTEST or

SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes

through the UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output

latches is immediately transferred to the corresponding outputs or output enables.

Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the

boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the

boundary scan cells feature a negative edge latch, which guarantees that clock s kew cannot cause incor-

rect data to be latched into a cell. The input cells are sample-only cells. The simplified logic configuration is

shown in Figure 9.3.

Figure 9.3 Diagram of Observe-only Input Cell

The simplified logic configuration of the output cells is shown in Figure 9.4.

Input

shift_dr

From previous cell

clock_dr

DQ To next cell

To core logic

MUX

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 5 February 22, 2012

Notes

Figure 9.4 Diagra m of Output Cell

The output enable cells are also output cells. The simplified logi c is shown in Figure 9.5.

Figure 9.5 Diagram of Bidirectional Cell

The bidirectional cells are composed of only two boundary sc an cells. They contain one output enable

cell and one capture cell, which contains only one register. The input to this single register is selected via a

mux that is selected by the output enable cell when EXTEST is disabled. When the Output Enable Cell is

driving a high out to the pad (which enables the pad for output) and EXTEST is disabled, the Capture Cell

will be configured to capture output data from the core to the pad.

However, in the case where the Output Enable Cell is low (signifying a tri-state condition at the pad) or

EXTEST is enabled, the Capture Cell will c apture input data from the pad to the core. The configuration is

shown graphically in Figure 9.5.

Data from Core

Data from Previous Cell

shift_dr

To Next Cell

To Output Pad

clock_dr update_dr

MUX

DQDQ

EXTEST

MUX

DQ DQ

Data fro m c ore

shift_dr

MUX

DQ DQ

clock_dr

shift_dr

update_dr

MUX

MUX MUX

OEN to pad

I/O pin

Output enable from core

EXTEST

Data from previous cell

To next cell

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 6 February 22, 2012

Notes

Instruction Register (IR)

The Instruction register allows an instruction to be shifted serially into the device at the rising edge of

JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be

accessed, or both. The instruction shifted into the register is latched at the completion of the shifting

process, when the TAP controller is at the Update-IR state.

The Instruction register contains six shift-register-based cells that can hold instruction data. This register

is decoded to perform the following functions:

–To select test data registers that may operate while the instruction is current. The other test data

registers should not interfere with chip operation and selected data registers.

–To define the serial test data register path used to shift data between JTAG_TDI and JTAG_TDO

during data register scanning.

The Instruction register is comprised of 6 bits to decode instructions, as shown in Table 9.3.

EXTEST

The external test (EXTEST) instruction is used to control the boundary scan register, once it has been

initialized using the SAMPLE/PRELOAD instruction. Using EXTEST, the user can then sample inputs from

or load values onto the external pins of the PES24T3G2. Once this instruction is selected, the user then

uses the SHIFT-DR TAP controller state to shift values into the boundary scan chain. When the TAP

controller passes through the UPDATE-DR state, these values will be latched onto the output pins or into

the output enables.

Instruction Definition Opcode

EXTEST Mandatory instruction allowing the testing of board level interconnec-

tions. Data is typically loaded onto the latched parallel outputs of the

boundary scan shift register using the SAMPLE/PRELOAD instruction

prior to use of the EXTEST instruction. EXTEST will then hold these

values on the outputs while being executed. Also see the CLAMP

instruction for similar capability.

000000

SAMPLE/

PRELOAD Mandatory instruction that allows data values to be loaded onto the

latched parallel output of the boundary scan shift register prior to

selection of the other boundary scan test instruction. The Sample

instruction allows a snaps hot of data flowing from the system pins to

the on-chip logic or vice versa.

000001

IDCODE Provided to select Device Identification to read out manufacturer’s

identity, part, and version number. 000010

HIGHZ Tri-states all output and bidirectional boundary scan cells. 000011

RESERVED 000100 —

101100

VALIDATE Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits

‘01’ are mandated by the IEEE Std. 1149.1 specification.

101101

RESERVED 101110 —

111101

CLAMP Provides JTAG users with the option to bypass the part’s JTAG con-

troller while keeping the part outputs controlled similar to EXTEST. 111110

BYPASS The BYPASS instruction is used to truncate the boundary scan regis-

ter as a single bit in length. 111111

Table 9.3 Instructions Supported by PES24T3G2’s JTAG Boundary Scan

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 7 February 22, 2012

Notes

SAMPLE/PRELOAD

The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the

boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown

random data being driven onto the output pins when EXTEST is selected. The secondary function of

SAMPLE/PRELOAD is for sampling the system state at a particular moment. Using the SAMPLE function,

the user can halt the device at a certain state and shift out the status of all of the pins and output enables at

that time.

BYPASS

The BYPAS S instruction is used to truncate the boundary scan register to a single bit in length. During

system level use of the JTAG, the boundary scan chains of all the devices on the board are connected in

series. In order to facilitate rapid testing of a given device, all other devices are put into BYPASS mode.

Therefore, instead of having to shift many times to get a value through the PES24T3G2, the user only

needs to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes

through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.

CLAMP

This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan

chain outputs to be clamped to fixed values. When the clamp instruction is issued, the bypass register is

selected between TDI and TDO and the scan chain passes through this register to devices further down-

stream.

IDCODE

The IDCODE instruction is automatically loaded when the T AP controller state machine is reset either by

the use of the JTAG_TRST_N signal or by the application of a ‘1’ on JTAG_TMS for five or more cycles of

JTAG_TCK as per the IEEE Std. 1149.1 specification. The least significant bit of thi s value must always be

1. Therefore, if a device has a Device ID register, it will shift out a 1 on the first shift if it is brought directly to

the SHIFT-DR TAP controller state after the TAP controller is reset. The board- level tester can then

examine this bit and determine if the device contains a Device ID register (the first bit is a 1) , or if the de vice

only contains a BYPASS register (the first bit is 0).

However, even if the device contains a Device ID register, it must also contain a BYPASS register. The

only difference is that the BYPASS register will not be the default register selected during the TAP controller

reset. When the IDCODE i nstruction is active and the TAP controller is in the Shift-DR state, the thirty-two

bit value that will be shifted out of the Device ID register is shown in Figure 9.6.

Bit(s) Mnemonic Description R/W Reset

0 Reserved Reserved R 0x1

11:1 Manuf_ID Manufacturer Identity (11 bits)

This field identifies the manufacturer as IDT. R0x33

27:12 Part_number Part Number (16 bits)

This field identifies the silicon as PES24T3G2. R 0x806A

31:28 Version Version (4 bits)

This field identifies the silicon revision of the PES24T3G2. R silicon-

dependent

Table 9.4 System Controller Device Identification Register

Version Part Number Mnfg. ID LSB

xxxx 1000|0000|0110|1010 0000|0011|011 1

Figure 9.6 Device ID Register Format

IDT JTAG Boundary Scan

PES24T3G2 User Manual 9 - 8 February 22, 2012

Notes

VALIDATE

The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std.

1149.1 specification.

RESERVED

Reserved instructions implement various test modes used in the device manufacturing process. The

user should not enable these instructions.

Usage Considerations

As previously stated, there are internal pull-ups on JTAG_TRST_N, JTAG_TMS, and JTAG_TDI.

However, JTAG_TCK also needs to be driven to a known value. It is best to either drive a zero on the

JTAG_TCK pin when it is not being used or to use an external pull-down resistor. In order to guarantee that

the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test-

Logic-Reset controller state by continuously holding JTA G_TRST_N low and/or JTAG_TMS high when the

chip is in normal operation. If JTAG will not be used, externally pull-down JTAG_TRST_N low to disable it.