SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 * * * * * SN54ALS169B, SN54AS169A . . . J PACKAGE SN74ALS169B, SN74AS169A . . . D OR N PACKAGE (TOP VIEW) Fully Synchronous Operation for Counting and Programming Internal Carry Look-Ahead Circuitry for Fast Counting Carry Output for n-Bit Cascading Fully Independent Clock Circuit Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs U/D CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD description These synchronous 4-bit up/down binary presettable counters feature an internal carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. CLK U/D NC VCC RCO SN54ALS169B, SN54AS169A . . . FK PACKAGE (TOP VIEW) 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QA QB NC QC QD ENP GND NC LOAD ENT A B NC C D These counters are fully programmable; that is, they may be preset to either level. The load-input circuitry allows loading with the carry-enable output of cascaded counters. Because loading is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. NC - No internal connection The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range of -55C to 125C. The SN74ALS169B and SN74AS169A are characterized for operation from 0C to 70C. Copyright 1994, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- * DALLAS, TEXAS 75265 * HOUSTON, TEXAS 77251-1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2-1 SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 logic symbol LOAD 9 1 U/D ENT ENP CLK 10 7 2 CTRDIV16 M1 [LOAD] M2 [COUNT] M3 [UP] M4 [DOWN] 3,5CT=15 4,5CT=0 G5 15 RCO G6 2,3,5,6+/C7 2,4,5,6 - A B C D 3 1 1, 7D 4 2 5 4 6 8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 2-2 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 14 13 12 11 QA QB QC QD SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 logic diagram (positive logic) LOAD U/D ENT ENP 9 1 15 RCO 10 7 C1 CLK A 2 1D 14 QA 3 C1 1D B 13 QB 4 C1 1D C 12 QC 5 C1 1D D 11 QD 6 Pin numbers shown are for the D, J, and N packages. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 2-3 SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 typical load, count, and inhibit sequences The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 LOAD A Data Inputs B C D CLK U/D ENP and ENT QA Data Outputs QB QC QD RCO 13 14 15 0 1 2 Count Up 2 2 Inhibit 1 0 15 14 13 Count Down Load absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C SN74ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2-4 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 recommended operating conditions SN54ALS169B SN74ALS169B MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current -0.4 -0.4 mA IOL fclock Low-level output current 4 8 mA 40 MHz tw Pulse duration, CLK high or low High-level input voltage 2 Clock frequency 2 0 tsu Setup time before CLK th TA Hold time, data after CLK 22 12.5 A, B, C, or D 20 15 ENP or ENT 25 15 LOAD 20 15 U/D 28 15 0 Operating free-air temperature V 0 14 ns ns 0 -55 125 V ns 0 70 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54ALS169B MIN TYP MAX TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = - 18 mA IOH = - 0.4 mA VOL VCC = 4.5 V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V SN74ALS169B MIN TYP MAX -1.5 VCC - 2 -1.5 VCC - 2 0.25 -20 0.4 UNIT V V 0.25 0.4 0.35 0.5 V 0.1 0.1 20 20 A -0.2 -0.2 mA -112 mA -112 -30 mA ICC VCC = 5.5 V 15 25 15 25 mA All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 2-5 SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX TO (OUTPUT) SN54ALS169B MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH SN74ALS169B MAX MIN 22 CLK RCO CLK Any Q ENT RCO U/D RCO UNIT MAX 40 MHz 3 20 3 20 6 25 6 20 2 20 2 15 5 23 5 20 2 16 2 13 3 24 3 16 4 22 5 19 5 19 tPHL 5 26 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ns ns ns ns absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C SN74AS169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS169A SN74AS169A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current -2 -2 mA IOL fclock* Low-level output current tw* Pulse duration, CLK high or low High-level input voltage 2 20 Clock frequency tsu* Setup time before CLK th* TA Hold time, data after CLK 2 0 60 0 7.7 6.7 A, B, C, or D 10 8 ENP or ENT 10 8 LOAD 10 8 U/D 14 11 2 0 Operating free-air temperature -55 125 0 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. 2-6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * V V 20 mA 75 MHz ns ns ns 70 C SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54AS169A TYP MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = - 18 mA IOH = - 2 mA VOL VCC = 4.5 V, IOL = 20 mA VCC = 5.5 V, VI = 7 V VCC = 5.5 V, VI = 2.7 V VCC = 5.5 V, VI = 0.4 V -1.2 VCC - 2 All others 0.25 LOAD, ENT, U/D IIH All others LOAD, ENT, U/D IIL All others -1.2 VCC - 2 LOAD, ENT, U/D II SN74AS169A TYP MAX MIN 0.5 UNIT V V 0.25 0.5 0.2 0.2 0.1 0.1 40 40 20 20 -1 -1 -0.5 -0.5 V mA A A mA IO VCC = 5.5 V, VO = 2.25 V -30 -112 -30 -112 mA ICC VCC = 5.5 V 41 63 41 63 mA All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX SN54AS169A MIN fmax* tPLH tPHL tPLH tPHL tPLH tPHL tPLH MAX 60 CLK RCO (LOAD high or low) CLK Any Q ENT RCO UNIT SN74AS169A MIN MAX 75 MHz 3 17.5 3 16.5 2 14 2 13 1 7.5 1 7 2 14 2 13 1.5 10 1.5 9 1.5 10 1.5 9 2 14 2 12 U/D RCO tPHL 2 14.5 2 13 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * ns ns ns ns 2-7 SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point From Output Under Test LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ 3.5 V Input tPZH 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output VOL 0.3 V 1.3 V 1.3 V VOL tPLH tPHL VOH 1.3 V 1.3 V [3.5 V 1.3 V tPHZ Waveform 2 S1 Open (see Note B) 1.3 V VOH Out-of-Phase Output (see Note C) 0.3 V [0 V 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 2-8 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD Call TI Call TI 8302501EA ACTIVE CDIP J 16 1 TBD Call TI Call TI Call TI Call TI 8302501FA OBSOLETE CFP W 16 JM38510/38003B2A ACTIVE LCCC FK 20 1 TBD JM38510/38003BEA ACTIVE CDIP J 16 1 TBD M38510/38003B2A ACTIVE LCCC FK 20 1 TBD M38510/38003BEA ACTIVE CDIP J 16 1 TBD SN54ALS169BJ ACTIVE CDIP J 16 1 SN54AS169AJ OBSOLETE CDIP J 16 SN74ALS169BD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BDE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BDRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type TBD A42 N / A for Pkg Type TBD Call TI Call TI SN74ALS169BN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS169BNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS169BNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS169BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS169AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AS169ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SNJ54ALS169BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type Addendum-Page 1 Samples (Requires Login) 83025012A TBD (3) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Jan-2012 Status (1) Package Type Package Drawing Pins SNJ54ALS169BJ ACTIVE CDIP J 16 SNJ54AS169AFK OBSOLETE LCCC FK SNJ54AS169AJ OBSOLETE CDIP J Package Qty Eco Plan 1 (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TBD A42 N / A for Pkg Type 20 TBD Call TI Call TI 16 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A : * Catalog: SN74ALS169B, SN74AS169A * Military: SN54ALS169B, SN54AS169A NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALS169BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74ALS169BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS169BDR SN74ALS169BNSR SOIC D 16 2500 333.2 345.9 28.6 SO NS 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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