1
FEATURES
D, DCT, DGK, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
VCC
SCL1
SDA1
EN
NC
SCL0
SDA0
GND
8
7
6
5
NC No internal connection–
DRG PACKAGE
(TOP VIEW)
1
2
3
4
VCC
SCL1
SDA1
EN
NC
SCL0
SDA0
GND
8
7
6
5
DESCRIPTION/ORDERING INFORMATION
PCA9515ADUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007www.ti.com
•Two-Channel Bidirectional Buffers•I
2
C Bus and SMBus Compatible•Active-High Repeater-Enable Input•Open-Drain I
2
C I/O•5.5-V Tolerant I
2
C I/O and Enable Input SupportMixed-Mode Signal Operation•Lockup-Free Operation•Accommodates Standard Mode and Fast ModeI
2
C Devices and Multiple Masters•Supports Arbitration and Clock StretchingAcross the Repeater•Powered-Off High-Impedance I
2
C Pins•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)
This dual bidirectional I
2
C buffer is operational at 2.3-V to 3.6-V V
CC
.
The PCA9515A is a BiCMOS integrated circuit intended for I
2
C bus and SMBus systems applications. Thedevice contains two identical bidirectional open-drain buffer circuits that enable I
2
C and similar bus systems to beextended without degradation of system performance. Both buffers specifically are designed to support thestandard low-level-contention arbitration of the I
2
C bus and support clock stretching.
The PCA9515A buffers both the serial data (SDA) and serial clock (SCL) signals on the I
2
C bus, while retainingall the operating modes and features of the I
2
C system. This enables two buses of 400-pF bus capacitance to beconnected in an I
2
C application.
The I
2
C bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515Aenables the system designer to isolate two halves of a bus, accommodating more I
2
C devices or longer tracelengths.
The PCA9515A has an active-high enable (EN) input with an internal pullup, which allows the user to selectwhen the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It nevershould change state during an I
2
C operation, because disabling during a bus operation hangs the bus, andenabling part way through a bus cycle could confuse the I
2
C parts being enabled. The EN input should changestate only when the global bus and the repeater port are in an idle state, to prevent system failures.
The PCA9515A also can be used to run two buses: one at 5-V interface levels and the other at 3.3-V interfacelevels, or one at 400-kHz operating frequency and the other at 100-kHz operating frequency. If the two buses areoperating at different frequencies, the 100-kHz bus must be isolated when the 400-kHz operation of the other busis required. If the master is running at 400 kHz, the maximum system operating frequency may be less than400 kHz, because of the delays that are added by the repeater.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
PCA9515A
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
MSOP – DGK Reel of 2500 PCA9515ADGKR 7B_Tube of 75 PCA9515ADSOIC – D Reel of 2500 PCA9515ADR PD515AReel of 250 PCA9515ADTSON – DRG TBD PCA9515ADRGR PREVIEW– 40 °C to 85 °C
Reel of 3000 PCA9515ADCTRSSOP – DCT 7BG_ _ _Reel of 250 PCA9515ADCTTTube of 150 PCA9515APWTSSOP – PW Reel of 2000 PCA9515APWR PD515AReel of 250 PCA9515APWT
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.DGK: The actual top-side marking has one additional character that designates the assembly/test site.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internalbuffer must be 70 mV or more below the output low level, when the output internally is driven low. This preventsa lockup condition from occurring when the input low condition is released.
Two or more PCA9515A devices cannot be used in series. The PCA9515A design does not allow thisconfiguration. Because there is no direction pin, slightly different valid low-voltage levels are used to avoid lockupconditions between the input and the output of each repeater. A valid low applied at the input of a PCA9515A ispropagated as a buffered low with a slightly higher value on the enabled outputs. When this buffered low isapplied to another PCA9515A-type device in series, the second device does not recognize it as a valid low anddoes not propagate it as a buffered low again.
The device contains a power-up control circuit that sets an internal latch to prevent the output circuits frombecoming active until V
CC
is at a valid level (V
CC
= 2.3 V).
As with the standard I
2
C system, pullup resistors are required to provide the logic high levels on the buffered bus.The PCA9515A has standard open-collector configuration of the I
2
C bus. The size of these pullup resistorsdepends on the system, but each side of the repeater must have a pullup resistor. The device is designed towork with Standard Mode and Fast Mode I
2
C devices in addition to SMBus devices. Standard Mode I
2
C devicesonly specify 3 mA in a generic I
2
C system where Standard Mode devices and multiple masters are possible.Under certain conditions, high termination currents can be used.
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Product Folder Link(s): PCA9515A
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SDA0 3 6 SDA1
SCL0 2 7 SCL1
EN 5
VCC
Pullup
Resistor
PCA9515A
8
4
PCA9515ADUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
TERMINAL FUNCTIONS
NO. NAME DESCRIPTION
1 NC No internal connection2 SCL0 Serial clock bus 03 SDA0 Serial data bus 04 GND Supply ground5 EN Active-high repeater enable input6 SDA1 Serial data bus 17 SCL1 Serial clock bus 18 V
CC
Supply power
FUNCTION TABLE
INPUT
FUNCTIONEN
L Outputs disabled
SDA0 = SDA1,H
SCL0 = SCL1
LOGIC DIAGRAM (POSITIVE LOGIC)
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): PCA9515A
www.ti.com
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
PCA9515A
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 7 VV
I
Enable input voltage range
(2)
– 0.5 7 VV
I/O
I
2
C bus voltage range
(2)
– 0.5 7 VI
IK
Input clamp current V
I
< 0 – 50 mAI
OK
Output clamp current V
O
< 0 – 50 mAI
O
Continuous output current ± 50 mAContinuous current through V
CC
or GND ± 100 mAD package 97DCT package 220
θ
JA
Package thermal impedance
(3)
DGK package 172 °C/WDRG package TBDPW package 149T
stg
Storage temperature range – 65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 VSDA and SCL inputs 0.7 ×V
CC
5.5V
IH
High-level input voltage VEN input 2 5.5SDA and SCL inputs – 0.5 0.3 ×V
CCV
IL
(1)
Low-level input voltage VEN input – 0.5 0.8V
ILc
(1)
SDA and SCL low-level input voltage contention – 0.5 0.4 VV
CC
= 2.3 V 6I
OL
Low-level output current mAV
CC
= 3 V 6T
A
Operating free-air temperature – 40 85 °C
(1) V
IL
specification is for the EN input and the first low level seen by the SDAx and SCLx lines. V
ILc
is for the second and subsequent lowlevels seen by the SDAx and SCLx lines. V
ILc
must be at least 70 mV below V
OL
.
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Product Folder Link(s): PCA9515A
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Electrical Characteristics
Timing Requirements
Switching Characteristics
PCA9515ADUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= – 18 mA 2.3 V to 3.6 V – 1.2 VSDAx,V
OL
Low-level output voltage I
OL
= 20 μA or 6 mA 2.3 V to 3.6 V 0.47 0.52 0.6 VSCLxLow-level input voltage below SDAx,V
OL
– V
ILc
I
I
= 10 μA 2.3 V to 3.6 V 70 mVlow-level output voltage SCLx
2.7 V 0.5 3Both channels high,SDAx = SCLx = V
CC
3.6 V 0.5 3Both channels low, 2.7 V 1 4SDA0 = SCL0 = GND andI
CC
Quiescent supply current SDA1 = SCL1 = open; or mA3.6 V 1 4SDA0 = SCL0 = open andSDA1 = SCL1 = GND
2.7 V 1 4In contention,
SDAx = SCLx = GND
3.6 V 1 4V
I
= 3.6 V ± 1SDAx,
SCLx
V
I
= 0.2 V 3I
I
Input current 2.3 V to 3.6 V μAV
I
= V
CC
± 1EN
V
I
= 0.2 V – 10 – 20V
I
= 3.6 V 0.5SDAx,I
off
Leakage current EN = L or H 0 V μASCLx
V
I
= GND 0.5Leakage current during SDAx,I
I(ramp)
V
I
= 3.6 V EN = L or H 0 V to 2.3 V 1 μApower up SCLx
EN 3.3 V 7 9C
in
Input capacitance V
I
= 3 V or GND pFSDAx,
EN = H 3.3 V 7 9SCLx
(1) All typical values are at nominal supply voltage (V
CC
= 2.5 V or 3.3 V) and T
A
= 25 °C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 2.5 V V
CC
= 3.3 V± 0.2 V ± 0.3 V
UNITMIN MAX MIN MAX
t
su
Setup time, EN ↑before Start condition 100 100 nst
h
Hold time, EN ↓after Stop condition 130 100 ns
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted)
V
CC
= 2.5 V ± 0.2 V V
CC
= 3.3 V ± 0.3 VFROM TOPARAMETER UNIT(INPUT) (OUTPUT)
MIN TYP
(1)
MAX MIN TYP
(1)
MAX
t
PZL
45 82 130 45 68 120SDA0, SCL0 or SDA1, SCL1 orPropagation delay time
(2)
nsSDA1, SCL1 SDA0, SCL0t
PLZ
33 113 190 33 102 180t
tHL
80% 20% 57 58Output transition time
(2)
ns(SDAx, SCLx)t
tLH
20% 80% 148 147
(1) All typical values are at nominal supply voltage (V
CC
= 2.5 V or 3.3 V) and T
A
= 25 °C.(2) Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): PCA9515A
www.ti.com
PARAMETER MEASUREMENT INFORMATION
20%
tPLZ/tPZL VCC
TEST S1
CL= 50 pF
(see Note B)
S1
GND
RL= 1.35 kΩ
VCC
Output
PULSE
GENERATOR DUT
RT
(see Note A)
VCC
VIN VOUT
VOL
ttHL ttLH
VCC
tPLZ
tPZL
1.5 V 1.5 V
VCC
0 V
Input
1.5 V 1.5 V
20%
80% 80%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
PCA9515A
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
A. R
T
termination resistance should be equal to Z
OUT
of pulse generators.B. C
L
includes probe and jig capacitance.C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω,slew rate ≥1 V/ns.D. The outputs are measured one at a time, with one transition per measurement.E. t
PLH
and t
PHL
are the same as t
pd
.F. t
PLZ
and t
PHZ
are the same as t
dis
.G. t
PZL
and t
PZH
are the same as t
en
.
Figure 1. Test Circuit and Voltage Waveforms
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Product Folder Link(s): PCA9515A
www.ti.com
APPLICATION INFORMATION
I2C BUS SLAVE
100 kHz
3.3 V
PCA9515A
5 V
SDA
SCL
I2C BUS MASTER
400 kHz
SDA1
SCL1
SDA0
SCL0
EN
SDA
SCL
BUS 0 BUS 1
9th Clock Pulse
VOL of PCA9515AVOL of Master
SCL
SDA
PCA9515ADUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
A typical application is shown in Figure 2 . In this example, the system master is running on a 3.3-V bus, while theslave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then themaster bus can run at 400 kHz. Master devices can be placed on either bus.
Figure 2. Typical Application
The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the differentbus voltages.
When one side of the PCA9515A is pulled low by a device on the I
2
C bus, a CMOS hysteresis-type input detectsthe falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to golow. The side driven low by the PCA9515A typically is at V
OL
= 0.5 V.
Figure 3 and Figure 4 show the waveforms that are seen in a typical application. If the bus master in Figure 2writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 3 . This looks like a normalI
2
C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line(SDA) while the slave pulls it low through the PCA9515A. Because the V
OL
of the PCA9515A typically is around0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases thedata line.
Figure 3. Bus 0 Waveforms
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): PCA9515A
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9th Clock Pulse
VOL of PCA9515A VOL of Slave
SCL
SDA
PCA9515A
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
Figure 4. Bus 1 Waveforms
On the Bus 1 side of the PCA9515A, the clock and data lines have a positive offset from ground equal to the V
OLof the PCA9515A. After the eighth clock pulse, the data line is pulled to the V
OL
of the slave device, which is veryclose to ground in the example.
It is important to note that any arbitration or clock-stretching events on Bus 1 require that the V
OL
of the deviceson Bus 1 be 70 mV below the V
OL
of the PCA9515A (see V
OL
– V
ILc
in Electrical Characteristics) to berecognized by the PCA9515A and transmitted to Bus 0.
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Product Folder Link(s): PCA9515A
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9515AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADRGR ACTIVE SON DRG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9515ADT ACTIVE SOIC D 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515ADTG4 ACTIVE SOIC D 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PCA9515APW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515APWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515APWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515APWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9515APWT ACTIVE TSSOP PW 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9515APWTG4 ACTIVE TSSOP PW 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9515ADGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
PCA9515ADGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PCA9515ADGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PCA9515ADGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
PCA9515ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCA9515ADRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PCA9515ADT SOIC D 8 250 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCA9515APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9515ADGKR VSSOP DGK 8 2500 346.0 346.0 35.0
PCA9515ADGKR VSSOP DGK 8 2500 358.0 335.0 35.0
PCA9515ADGKT VSSOP DGK 8 250 358.0 335.0 35.0
PCA9515ADGKT VSSOP DGK 8 250 220.0 205.0 50.0
PCA9515ADR SOIC D 8 2500 367.0 367.0 35.0
PCA9515ADRGR SON DRG 8 3000 367.0 367.0 35.0
PCA9515ADT SOIC D 8 250 367.0 367.0 35.0
PCA9515APWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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