82C87H CMOS Octal Inverting Bus Transceiver March 1997 Features Description * Full Eight Bit Bi-Directional Bus Interface The Intersil 82C87H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C87H provides a full eight-bit bi-directional bus interface in a 20 pin package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C87H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. The 82C87H provides inverted data at the outputs. * Industry Standard 8287 Compatible Pinout * High Drive Capability - B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA - A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA * Three-State Inverting Outputs * Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. * Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors Ordering Information PART NUMBERS * Single 5V Power Supply 5MHz * Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10A * Operating Temperature Range - C82C87H . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC - I82C87H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C87H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC CP82C87H-5 IP82C87H-5 CS82C87H-5 IS82C87H-5 8MHz PACKAGE CP82C87H 20 Ld PDIP IP82C87H CS82C87H 20 Ld PLCC IS82C87H CD82C87H-5 CD82C87H 20 Ld CERDIP ID82C87H-5 ID82C87H MD82C87H-5/B - 59628757702RA - MR82C87H-5/B - 596287577022A - CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 4-325 TEMP. RANGE 0oC to +70oC -40oC 0oC to -40oC 0oC to +70oC to to +85oC +85oC +70oC PKG. NO. E20.3 E20.3 N20.35 N20.35 F20.3 -40oC to +85oC F20.3 -55oC to +125oC SMD # 20 Pad CLCC F20.3 F20.3 -55oC to +125oC SMD # J20.A J20.A File Number 2978.1 82C87H Pinouts A1 A0 VCC B0 82C87H (PLCC, CLCC) TOP VIEW A2 82C87H (PDIP, CERDIP) TOP VIEW 3 2 1 20 19 TRUTH TABLE A0 1 20 VCC A1 2 19 B0 A2 3 18 B1 A3 4 17 B2 A3 4 18 B1 A4 5 16 B3 A4 5 17 B2 A5 6 15 B4 A5 6 16 B3 A6 7 14 B5 A7 8 13 B6 A6 7 15 B4 OE 9 12 B7 A7 8 14 B5 OE A B X H Hi-Z Hi-Z H L I O L L O I = Logic One = Logic Zero = Input Mode = Output Mode = Don't Care = High Impedance PIN NAMES 11 12 13 PIN B7 B6 10 T 9 GND 11 T OE GND 10 H L I O X Hi-Z T A0-A7 Local Bus Data I/O Pins B0-B7 System Bus Data I/O Pins T OE 4-326 DESCRIPTION Transmit Control Input Active Low Output Enable 82C87H Functional Diagram Decoupling Capacitors B0 The transient current required to charge and discharge the 300pF load capacitance specified in the 82C86H/87H data sheet is determined by: A1 B1 I = C L ( dv dt ) A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A0 (EQ. 4) Assuming that all outputs change state at the same time and that dv/dt is constant; (V CC x 80% ) I = C L ------------------------------------tR tF (EQ. 5) where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight outputs. I = ( 80 x 300 x 10 = 480mA OE T Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance ("float" condition), it could create an indeterminate logic state at the inputs and cause a disruption in device operation. - 12 ) x ( 5.0V x 0.8 ) ( 20 x 10 -9 ) (EQ. 6) This current spike may cause a large negative voltage spike on VCC which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1F ceramic disc capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible. The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C87H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-Channel and lower N-Channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. VCC VCC P P N STB P INTERNAL DATA DATA IN N N FIGURE 3. 82C82/83H VCC P OE P D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10A during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices. 4-327 INTERNAL DATA DATA IN VCC N P N N FIGURE 4. 82C86H/87H GATED INPUTS 82C87H Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 70 16 CLCC Package . . . . . . . . . . . . . . . . . . 80 20 PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature Hermetic Package . . . . . . . +175oC Maximum Junction Temperature Plastic Package. . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC (PLCC - Lead Tips Only) Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC I82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications SYMBOL VIH VCC = 5.0V 10%; TA = 0oC to +70oC (C82C87H); TA = -40oC to +85oC (I82C87H); TA = -55oC to +125oC (M82C87H) PARAMETER MIN MAX UNITS 2.0 - V C82C87H, I82C87H 2.2 - V M82C87H (Note 1) - 0.8 V B Outputs 3.0 - V IOH = -8mA A Outputs 3.0 - V IOH = -4mA VCC -0.4 - V IOH = -100A B Outputs - 0.45 V IOL = 20mA A Outputs - 0.45 V IOL = 12mA Logical One Input Voltage VIL Logical Zero Input Voltage VOH Logical One Output Voltage A or B Outputs VOL TEST CONDITIONS Logical Zero Output Voltage II Input Leakage Current -10.0 10.0 A VIN = GND or VCC DIP Pins 9, 11 IO Output Leakage Current -10.0 10.0 A VO = GND or VCC, OE VCC -0.5V DIP Pins 1 - 8, 12 - 19 VIN = VCC or GND, VCC = 5.5V, Outputs Open ICCSB Standby Power Supply Current - 10 A ICCOP Operating Power Supply Current - 1 mA/MHz TA = +25oC, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for a valid logical "1" during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4. 2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0s read/write cycle time = 1mA). Capacitance SYMBOL CIN TA = +25oC PARAMETER TYPICAL UNITS B Inputs 18 pF A Inputs 14 pF TEST CONDITIONS Input Capacitance 4-328 Freq = 1MHz, all measurements are referenced to device GND 82C87H AC Electrical Specifications VCC = 5.0V 10%; Freq = 1MHz TA = 0oC to +70oC (C82C87H); TA = -40oC to +85oC (I82C87H); TA = -55oC to +125oC (M82C87H) NOTE 4 SYMBOL (1) PARAMETER TIVOV MIN 82C87H MAX 82C87H-5 MAX UNITS Input to Output Delay TEST CONDITIONS Notes 1, 2 Inverting 5 30 35 ns Non-Inverting 5 32 35 ns (2) TEHTV Transmit/Receive Hold Time 5 - - ns Notes 1, 2 (3) TTVEL Transmit/Receive Setup Time 10 - - ns Notes 1, 2 (4) TEHOZ Output Disable Time 5 30 35 ns Notes 1, 2 (5) TELOV Output Enable Time 10 50 65 ns Notes 1, 2 (6) TR, TF Input Rise/Fall Times - 20 20 ns Notes 1, 2 (7) TEHEL Minimum Output Enable High Time Note 3 82C87H 30 - - ns 82C87H-5 35 - - ns NOTES: 1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven at 1ns/V. 2. Input test signals must switch between VIL - 0.4V and VIH +0.4V. 3. A system limitation only when changing direction. Not a measured parameter. 4. 82C87H is available in commercial and industrial temperature ranges only. 82C87H-5 is available in commercial, industrial and military temperature ranges. Timing Waveform TR, TF (6) INPUTS 2.0V 0.8V TEHEL (7) OE (4) TEHOZ (1) TIVOV TELOV (5) VOH -0.1V OUTPUTS VOL +0.1V TEHTV (2) T 4-329 3.0V 0.45V TTVEL (3) 82C87H Test Load Circuits A SIDE OUTPUTS TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH ENABLE LOAD CIRCUIT TELOV OUTPUT LOW ENABLE LOAD CIRCUIT 1.5V 1.5V 2.36V 160 375 TEST POINT OUTPUT 100pF (SEE NOTE) 2.36V 91 TEST POINT OUTPUT TEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUIT TEST POINT OUTPUT 100pF (SEE NOTE) 160 TEST POINT OUTPUT 100pF (SEE NOTE) 50pF (SEE NOTE) B SIDE OUTPUTS TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH ENABLE LOAD CIRCUIT TELOV OUTPUT LOW ENABLE LOAD CIRCUIT 1.5V 1.5V 2.27V 91 OUTPUT 180 TEST POINT 300pF (SEE NOTE) 2.27V 51 TEST POINT OUTPUT TEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUIT TEST POINT OUTPUT 300pF (SEE NOTE) 91 OUTPUT 300pF (SEE NOTE) 50pF (SEE NOTE) NOTE: Includes jig and stray capacitance. Burn-In Circuits MD82C87H CERDIP VCC C1 R1 F2 1 20 2 19 A 3 18 A 4 17 A 5 16 A 6 15 A 7 14 A 8 13 A 9 12 A 10 11 R1 F2 R1 F2 R1 F2 R1 F2 R1 F2 VCC R1 F2 R2 R1 F2 R1 R1 4-330 A R3 VCC TEST POINT 82C87H Burn-In Circuits (Continued) MR82C87H CLCC C1 VCC F2 R5 3 F2 F2 F2 F2 F2 R5 R5 R5 R5 R5 F2 F2 R5 R5 2 F3 1 R5 20 19 18 4 17 5 R5 R5 R5 16 6 R5 15 7 R5 14 8 9 10 R4 F0 11 R4 F1 NOTES: 1. VCC = 5.5V 0.5V, GND = 0V 2. VIH = 4.5V 10% 3. VIL = -0.2V to 0.4V 4. R1 = 47k 5% 5. R2 = 2.4k 5% 6. R3 = 1.5k 5% 7. R4 = 1k 5% 8. R5 = 5k 5% 9. C1 = 0.01F minimum 10. F0 = 100kHz 10% 11. F1 = F0/2, F2 = F1/2, F3 = F2/2 4-331 12 R5 F3 13 R5 F3 F3 F3 F3 F3 F3 82C87H Die Characteristics DIE DIMENSIONS: 138.6 x 155.5 x 19 1mils GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA METALLIZATION: Type: Si - Al Thickness: 11kA 1kA WORST CASE CURRENT DENSITY: 1.47 x 105 A/cm2 Metallization Mask Layout 82C87H A2 A1 A0 VCC B0 B1 B2 A3 B3 A4 B4 A5 B5 A6 A7 OE GND T B7 B6 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-332