85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
1
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
GENERAL DESCRIPTION
The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-
to-Differential HSTL translator and a member of
the HiPerClocks™ family of High Performance
Clock Solutions from ICS. The ICS85222-02 has
one single ended clock input. The single ended
clock input accepts LVCMOS or LVTTL input levels and trans-
lates them to HSTL levels. The small outline 8-pin SOIC pack-
age makes this device ideal for applications where space,
high performance and low power are important.
FEATURES
•Two differential HSTL outputs
•One LVCMOS/LVTTL clock input
•CLK input can accept the following input levels:
LVCMOS or LVTTL
•Maximum output frequency: 350MHz
•Part-to-part skew: TBD
•Propagation delay: 1ns (typical)
•VOH: 1.4V (maximum)
•Full 3.3V operating supply voltage
•0°C to 70°C ambient operating temperature
•Industrial temperature information available upon request
•Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS85222-02
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
Q0
nQ0
CLK
HiPerClockS™
ICS
VDD
CLK
nc
GND
8
7
6
5
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
Q1
nQ1
Pullup
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
2
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
3
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
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85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
4
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
PROPAGATION DELAY
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
HSTL
Qx
nQx
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
CLK
nQ0, nQ1
Q0, Q1
t
PD
V
DD
2
VDD
0V
3.3V ± 5%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
nQ0, nQ1
Q0, Q1
GND
OUTPUT RISE/FALL T IME
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
5
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
OUTPUTS:
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
APPLICATION INFORMATION
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
6
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85222-02.
Equations and example calculations are also provided.
1. P ower Dissipation.
The total power dissipation for the ICS85222-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW
•Power (outputs)MAX = 73.8mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 73.8mW = 147.6mW
Total Power_MAX (3.465V, with all outputs switching) = 121.3mW + 147.6mW = 459.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total device power dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.460W * 103.3°C/W = 117.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 5. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN SOIC, FORCED CONVECTION
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
7
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 1.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DD_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1V/50Ω) * (3.465V - 1V) = 49.3mW
Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 73.8mW
FIGURE 1. HSTL DRIVER CIRCUIT AND T ERMINATION
VDD
VOUT
RL
50Ω
Q1
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
8
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS85222-02 is: 411
TABLE 6. θJAVS. AIR FLOW T ABLE 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
9
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
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MUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
10
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-TO-2 LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
PRELIMINARY
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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