DATASHEET 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI 9ZX21201 General Description Features/Benefits The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express * Gen3 or QPI applications. The part is backwards compatible to PCIe Gen1 and Gen2. A fixed external feedback maintains low drift * for critical QPI applications. In bypass mode, the IDT9ZX21201 can * provide outputs up to 150MHz. * Recommended Application * 12-output PCIe Gen3/ QPI differential buffer for Romley and newer * platforms * Key Specifications * * * * * Cycle-to-cycle jitter <50ps Output-to-output skew < 65 ps Input-to-output delay variation <50ps PCIe Gen3 phase jitter < 1.0ps RMS QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS * * Space-saving 64-pin packages Fixed feedback path/ 0ps input-to-output delay 9 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment 12 OE# pins/Hardware control of each output PLL or bypass mode/PLL can dejitter incoming clock 100MHz or 133MHz PLL mode operation/supports PCIe and QPI applications Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI Software control of PLL Bandwidth and Bypass Settings/ PLL can dejitter incoming clock (B Rev only) Output Features * 12 - 0.7V differential HCSL output pairs Functional Block Diagram OE(11:0)# DFB_OUT Z-PLL (SS Compatible) DIF_IN DIF_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri DIF(11:0) Logic SMBDAT SMBCLK IREF Note: Even though the feedback is fixed, DFB_OUT still needs a termination network for the part to function. IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D - 11/19/15 1 VDD DIF_8 DIF_8# vOE8# vOE9# DIF_9 DIF_9# VDD VDD GND DIF_10 DIF_10# vOE10# vOE11# DIF_11# Pin Configuration DIF_11 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA GNDA IREF 100M_133M# HIBW_BYPM_LOBW# CKPWRGD_PD# GND VDDR DIF_IN DIF_IN# SMB_A0_tri SMBDAT SMBCLK SMB_A1_tri DFB_OUT# DFB_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 9ZX21201 GND DIF_7# DIF_7 vOE7# vOE6# DIF_6# DIF_6 GND VDD DIF_5# DIF_5 vOE5# vOE4# DIF_4# DIF_4 GND VDD DIF_3 DIF_3# vOE3# vOE2# DIF_2# DIF_2 VDD VDD GND DIF_1# DIF_1 vOE1# vOE0# DIF_0 DIF_0# 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes: Pins with ^ prefix have internal ~100K pullup Pins with v prefix have internal ~100K pulldown. Tri-level Input Thresholds Level Voltage <0.8V Low Mid 1.2<Vin<1.8V High Vin > 2.2V MLF Power Connections Pin Number Functionality at Power Up (PLL Mode) DIF_IN 100M_133M# (MHz) 1 100.00 0 133.33 DIF_IN DIF_IN PLL Operating Mode Readback Table HiBW_BypM_LoBW# Byte0, bit 7 Low (Low BW) 0 Mid (Bypass) 0 High (High BW) 1 Byte 0, bit 6 0 1 1 PLL Operating Mode HiBW_BypM_LoBW# DIF PLL Lo BW Mid Bypass High PLL Hi BW VDD 24,40,57 25,32,49,56 GND 2 7 23,33,41,48, 58 Description Analog PLL Analog Input DIF clocks 9ZX21201 SMBus Addressing Pin SMBus Address SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0) 0 D8 0 0 M DA 1 0 DE M 0 C2 M C4 M 1 M C6 0 1 CA M 1 CC 1 1 CE MODE Low VDD 1 8 NOTE: PLL is OFF in Bypass Mode IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 2 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Pin Description PIN # 1 2 PIN NAME VDDA GNDA 3 IREF 4 100M_133M# 5 H IBW_BYPM_LOBW# 6 C KPWRGD_PD# 7 GND 8 VDDR 9 10 D IF_IN D IF_IN# 11 SMB_A0_tri 12 13 SMBDAT SMBCLK 14 SMB_A1_tri 15 D FB_OUT# 16 D FB_OUT 17 18 D IF_0 D IF_0# 19 vOE0# 20 vOE1# 21 22 23 24 25 26 27 D IF_1 D IF_1# GND VDD VDD D IF_2 D IF_2# 28 vOE2# 29 vOE3# 30 31 32 D IF_3 D IF_3# VDD TYPE DESCR IPTION PWR 3.3V power for the PLL core. PWR Ground pin for the PLL core. This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision OUT resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. 3.3V Input to select operating frequency IN See Functionality Table for Definition Trilevel input to select High BW, Bypass or Low BW mode. IN See PLL Operating Mode Table for Details. Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on IN subsequent assertions. Low enters Power Down Mode. PWR Ground pin. 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and PWR filtered appropriately. IN 0.7 V Differential TR UE input IN 0.7 V Differential Complementary Input SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMBus IN Addresses. I/O Data pin of SMBUS circuitry, 5V tolerant IN Clock pin of SMBUS circuitry, 5V tolerant SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMBus IN Addresses. Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization OUT with input clock to eliminate phase error. True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input OUT clock to eliminate phase error. OUT 0.7V differential true clock output OUT 0.7V differential C omplementary clock output Active low input for enabling DIF pair 0. IN 1 =disable outputs, 0 = enable outputs Active low input for enabling DIF pair 1. IN 1 =disable outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential C omplementary clock output PWR Ground pin. PWR Power supply, nominal 3.3V PWR Power supply, nominal 3.3V OUT 0.7V differential true clock output OUT 0.7V differential C omplementary clock output Active low input for enabling DIF pair 2. IN 1 =disable outputs, 0 = enable outputs Active low input for enabling DIF pair 3. IN 1 =disable outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential C omplementary clock output PWR Power supply, nominal 3.3V IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 3 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Pin Description (continued) 33 34 35 GND DIF_4 DIF_4# PWR OUT OUT 36 vOE4# IN 37 vOE5# IN 38 39 40 41 42 43 DIF_5 DIF_5# VDD GND DIF_6 DIF_6# OUT OUT PWR PWR OUT OUT 44 vOE6# IN 45 vOE7# IN 46 47 48 49 50 51 DIF_7 DIF_7# GND VDD DIF_8 DIF_8# OUT OUT PWR PWR OUT OUT 52 vOE8# IN 53 vOE9# IN 54 55 56 57 58 59 60 DIF_9 DIF_9# VDD VDD GND DIF_10 DIF_10# OUT OUT PWR PWR PWR OUT OUT 61 vOE10# IN 62 vOE11# IN 63 64 DIF_11 DIF_11# OUT OUT Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 4 1 =disable outputs, 0 = enable outputs Active low input for enabling DIF pair 5. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 6. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs Active low input for enabling DIF pair 7. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 8. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs Active low input for enabling DIF pair 9. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 10. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs Active low input for enabling DIF pair 11. This pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 4 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage VDD, VDDA Input Low Voltage VIL Input High Voltage VIH Input High Voltage VIHSMB Storage Temperature Junction Temperature Input ESD protection MIN TYP VDD for core logic and PLL MAX 4.6 GND-0.5 Except for SMBus interface SMBus clock and data pins Ts Tj ESD prot VDD+0.5V 5.5V -65 Human Body Model 150 125 2000 UNITS NOTES V V V V C C V 1,2 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temperature TCOM Commmercial range 0 70 C 1 Input High Voltage VIH 2 VDD + 0.3 V 1 Input Low Voltage VIL GND - 0.3 0.8 V 1 Input Frequency Pin Inductance Capacitance MAX UNITS NOTES -5 5 uA 1 Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 VDD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode VDD = 3.3 V, 133.33MHz PLL mode 33 90 120 CINDIF_IN Logic Inputs, except DIF_IN DIF_IN differential clock inputs 1.5 1.5 150 110 147 7 5 2.7 MHz MHz MHz nH pF pF 2 2 2 1 1 1,4 COUT Output pin capacitance 6 pF 1 1 ms 1,2 33 kHz 1 6 12 clocks 1 16 300 us 1,3 10 10 0.8 5.5 1000 300 ns ns V V V mA V ns ns 1,2 1,2 1 1 1 1 1 1 1 100 kHz 1,5 IIN Input Current Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, VIN = GND, VIN = VDD TYP IINP Fibyp Fipll Fipll Lpin CIN Clk Stabilization TSTAB Input SS Modulation Frequency fMODIN OE# Latency t LATOE# Tdrive_PD# t DRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of control inputs Rise time of control inputs VILSMB VIHSMB VOLSMB I PULLUP VDDSMB tRSMB tFSMB @ IPULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) f MAXSMB Maximum SMBus operating frequency 100.00 133.33 0.300 30 4 2.1 4 2.7 VDDSMB 0.4 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 5 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Electrical Characteristics - DIF_IN Clock Input Parameters TAMB=TCOM unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER Input Crossover Voltage DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN SYMBOL CONDITIONS MIN VCROSS Cross Over Voltage 150 VSWING Differential value 300 dv/dt Measured differentially 0.4 TYP MAX UNITS NOTES 900 mV 1 mV 1 8 V/ns 1,2 uA Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 Input Duty Cycle dtin Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle J DIFIn Differential Measurement 0 125 ps 1 1 2 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP Slew rate Slew rate matching Trf Trf Scope averaging on Slew rate matching, Scope averaging on 1 2 8 4 20 Voltage High VHigh 660 705 850 Voltage Low VLow Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs -Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns % 1, 2, 3 1, 2, 4 1 mV -150 1 150 725 -22 1407 309 22 1150 -300 300 250 550 140 1 mV mV mV mV 1 1 1, 2 1, 5 1, 6 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 412 (1%), IREF = 2.7mA. IOH = 6.4 x IREF and VOH = 0.7V @ ZO=85 differential impedance. 1 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS I DDVDD 133MHz, CL = Full load; VDD rail, Zo=85 Operating Current 133MHz, CL = Full load; VDD rail, Zo=85 IDDVDDA Power Down, VDD rail, Zo=85 I DDVDDPD Powerdown Current Power Down, VDD rail, Zo=85 I DDVDDAPD 1 MIN TYP 260 13 2 1.3 MAX 275 20 6 2 UNITS mA mA mA mA NOTES 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 6 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Electrical Characteristics - Skew and Differential Jitter Parameters TA = TCOM; Supply Voltage VDD/ V DDA = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input-to-Output Skew in PLL mode CLK_IN, DIF[x:0] t SPO_PLL nominal value @ 25C, 3.3V Input-to-Output Skew in Bypass mode CLK_IN, DIF[x:0] t PD_BYP nominal value @ 25C, 3.3V Input-to-Output Skew Varation in PLL mode CLK_IN, DIF[x:0] t DSPO_PLL across voltage and temperature MIN TYP MAX UNITS NOTES -100 29 100 ps 1,2,4,5,8 2.5 3.7 4.5 ns 1,2,3,5,8 -50 50 ps 1,2,3,5,8 -250 250 ps 1,2,3,5,8 CLK_IN, DIF[x:0] t DSPO_BYP Input-to-Output Skew Varation in Bypass mode across voltage and temperature CLK_IN, DIF[x:0] t DTE Random Differential Tracking error beween two 9ZX devices in Hi BW Mode 2.9 5 ps (rms) 1,2,3,5,8 CLK_IN, DIF[x:0] t DSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode 14 75 ps 1,2,3,5,8 DIF{x:0] t SKEW_ALL 32 65 ps 1,2,3,8 PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Duty Cycle jpeak-hibw jpeak-lobw pllHIBW pllLOBW t DC 0 0 2 0.7 45 1.8 0.7 3.1 1.1 49.6 2.5 2 4 1.4 55 dB dB MHz MHz % 7,8 7,8 8,9 8,9 1 Duty Cycle Distortion t DCD -2 -0.2 2 % 1,10 Jitter, Cycle to cycle t jcyc-cyc 15.7 0.1 50 50 ps ps 1,11 1,11 Output-to-Output Skew across all outputs (Common to Bypass and PLL mode) LOBW#_BYPASS_HIBW = 1 LOBW#_BYPASS_HIBW = 0 LOBW#_BYPASS_HIBW = 1 LOBW#_BYPASS_HIBW = 0 Measured differentially, PLL Mode Measured differentially, Bypass Mode @100MHz PLL mode Additive Jitter in Bypass Mode Notes for preceding table: Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 1 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. 6. t is the period of the input clock 3 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not 100% tested in production. 9 Measured at 3 db down or half power point. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 10 11 Measured from differential waveform IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 7 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5% PARAMETER SYMBOL t jphPCIeG1 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) t jphPCIeG2 Phase Jitter, PLL Mode t jphPCIeG3 t jphQPI_SMI t jphPCIeG1 t jphPCIeG2 Additive Phase Jitter, Bypass mode t jphPCIeG3 t jphQPI_SMI MIN TYP 32 MAX 86 0.8 3 1.9 3.1 0.45 1 0.20 0.5 0.14 0.3 0.12 0.2 0.10 10 0.13 0.3 0.10 0.7 0.10 0.3 0.09 0.3 0.09 0.1 0.09 0.1 UNITS ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) Notes 1,2,3 1,2 1,2 1,2,4 1,5 1,5 1,5 1,2,3 1,2,6 1,2,6 1,2,4,6 1,5,6 1,5,6 1,5,6 1 Applies to all outputs. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4 6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2 2 Power Management Table Inputs CKPWRGD*/PD# 0 1 DIF_IN/ DIF_IN# SMBus EN bit X X 0 1 1 Running Control Bits/Pins DIF(11:0)/ OE# Pin DIF(11:0)# X X 0 1 Hi-Z1 Hi-Z1 Running Hi-Z1 Outputs DFB_OUT/ DFB_OUT# PLL State Hi-Z1 Running Running Running OFF ON ON ON NOTE: 1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 8 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Clock Periods - Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 133.33 1 Clock 1us 0.1s - ppm -SSC -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 9.94900 9.99900 7.44925 7.49925 Measurement Window 0.1s 0.1s + ppm 0 ppm Long-Term Period Average Nominal Max 10.00000 10.00100 7.50000 7.50075 1us +SSC Short-Term Average Max 1 Clock +c2c jitter AbsPer Max 10.05100 7.55075 Units Notes ns ns 1,2,3 1,2,4 Clock Periods - Differential Outputs with Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 133.00 1 Clock 1us 0.1s -SSC - ppm -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 9.94906 9.99906 10.02406 7.44930 7.49930 7.51805 Measurement Window 0.1s 0.1s + ppm 0 ppm Long-Term Period Average Nominal Max 10.02506 10.02607 7.51880 7.51955 1us +SSC Short-Term Average Max 10.05107 7.53830 1 Clock +c2c jitter AbsPer Max 10.10107 7.58830 Units Notes ns ns 1,2,3 1,2,4 Notes: Guaranteed by design and characterization, not 100% tested in production. 1 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy requirements (+/-100ppm). The 9ZX21201 itself does not contribute to ppm error. 3 4 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode Differential Output Termination Table DIF Zo () Iref () Rs () Rp () 100 475 33 50 85 412 27 42.2 or 43.2 9ZX21201 Differential Test Loads Rs DIF Zo=85ohms,10" 2pF Rs Rp 2pF Rp HCSL Output Buffer IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 9 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI General SMBus serial interface information for the 9ZX21201 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address XX (H) IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 * IDT clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * * * * * * * * * * * * * * * * Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Controller (host) will send start bit. Controller (host) sends the write address XX (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read addressYY (H) IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N + X -1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) T Controller (Host) starT bit IDT (Slave/Receiver) Slave Address XX (H) WR WRite Slave Address XX(H) WR WRite ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Data Byte Count = X ACK Repeat starT Slave Address YY (H) RD ReaD Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Note: XX(H) is defined by SMBus address select pins. Byte N + X - 1 N P IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Not acknowledge stoP bit 1682D- 11/19/15 10 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI SMBusTable: PLL Mode, Byte 0 Pin # 5 Bit 7 5 Bit 6 Bit 5 Bit 4 These bits Bit 3 Bit 2 available in B Bit 1 rev only. 4 Bit 0 and Frequency Select Register Name Control Function PLL Mode 1 PLL Operating Mode Rd back 1 PLL Mode 0 PLL Operating Mode Rd back 0 Reserved Reserved PLL_SW_EN Enable S/W control of PLL BW PLL Mode 1 PLL Operating Mode 1 PLL Mode 0 PLL Operating Mode 1 100M_133M# Frequency Select Readback SMBusTable: Output Control Register Pin # Name Byte 1 47/46 DIF_7_En Bit 7 43/42 DIF_6_En Bit 6 39/38 DIF_5_En Bit 5 35/34 DIF_4_En Bit 4 DIF_3_En 30/31 Bit 3 26/27 DIF_2_En Bit 2 21/22 DIF_1_En Bit 1 17/18 DIF_0_En Bit 0 SMBusTable: Output Control Register Byte 2 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 64/63 DIF_11_En Bit 3 DIF_10_En 59/60 Bit 2 DIF_9_En 54/55 Bit 1 DIF_8_En 50/51 Bit 0 Output Output Output Output Output Output Output Output Control Function Control - '0' overrides Control - '0' overrides Control - '0' overrides Control - '0' overrides Control - '0' overrides Control - '0' overrides Control - '0' overrides Control - '0' overrides Output Output Output Output Control Function Reserved Reserved Reserved Reserved Control - '0' overrides OE# pin Control - '0' overrides OE# pin Control - '0' overrides OE# pin Control - '0' overrides OE# pin SMBusTable: Reserved Register Byte 3 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OE# pin OE# pin OE# pin OE# pin OE# pin OE# pin OE# pin OE# pin Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Type R R 0 1 See PLL Operating Mode Readback Table RW RW RW R HW Latch S/W Control See PLL Operating Mode Readback Table 133MHz 100MHz Type RW RW RW RW RW RW RW RW 0 1 Low/Low Enable Type 0 1 RW RW RW RW Low/Low Enable Type 0 1 Default Latch Latch 0 0 0 1 1 Latch Default 1 1 1 1 1 1 1 1 Default 0 0 0 0 1 1 1 1 Default 0 0 0 0 0 0 0 0 1682D- 11/19/15 11 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI SMBusTable: Reserved Register Pin # Name Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBusTable: DEVICE ID Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SMBusTable: Byte Count Register Byte 7 Pin # Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 Control Function Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Type R R R R R R R R 0 REVISION ID VENDOR ID Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Control Function Reserved Reserved Reserved Writing to this register configures how many bytes will be read back. SMBusTable: Reserved Register Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Type RW RW RW RW RW Type A rev = 0000 B rev = 0001 0001 for IDT/ICS 1 1201 is 201 decimal or C9 hex 0 1 Default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. 0 1 Default 1 1 0 0 1 0 0 1 Default 0 0 0 0 1 0 0 0 Default 0 0 0 0 0 0 0 0 1682D- 11/19/15 12 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI PCI Express Add-in Board REF_CLK Input L3 1682D- 11/19/15 13 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 F Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI PCIe Device REF_CLK Input 1682D- 11/19/15 14 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL N ND NE DIMENSIONS (mm) SYMBOL A A1 A3 b e D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 64L 64 16 16 MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC 9.00 x 9.00 6.00 6.25 6.00 6.25 0.30 0.50 Ordering Information Part / Order Number 9ZX21201AKLF 9ZX21201AKLFT 9ZX21201BKLF 9ZX21201BKLFT Shipping Package Trays Tape and Reel Trays Tape and Reel Package 64-pin MLF 64-pin MLF 64-pin MLF 64-pin MLF Temperature 0 to +70C 0 to +70C 0 to +70C 0 to +70C Difference W/O Byte 0 PLL Control With Byte 0 PLL Mode Control "LF" designates PB-free configuration, RoHS compliant. "A and B" are the device revision designators (will not correlate with the datasheet revision). IDT(R) 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15 15 9ZX21201 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI Revision History Rev. A B C D E Issuer Issue Date Description Page # 1. Updated electrical tables with char data RDW 9/13/2011 2. Fixed minor typographical errors Various 3. Moved to final 1. Added B rev functionality description to Features, Benefits 2. Updated tDSPO_BYP parameter from +/-350ps to +/-250ps RDW 12/8/2011 1,7,11,15 3.Updated SMBus Byte 0 with B rev functionality 4. Updated ordering information to include B rev 1. Updated Power connections table to be consistent with 9ZXL1231. RDW 4/18/20112 2. Updated Rp value for 85 ohm differential Zo from 43.2ohms to 42.2 OR 2,9 43.2 ohms to be consistent with Intel recommendations. RDW 5/5/2014 1. Fixed error in feedback path on block diagram 1 1. Updated the DIF_IN Input clock specification to align with the PCIe SIG RDW 11/19/2015 6 specification. Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 (c) 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 16