9ZX21201
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D - 11/19/15
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI
1
General Description
The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express
Gen3 or QPI applications. The part is backwards compatible to
PCIe Gen1 and Gen2. A fixed external feedback maintains low drift
for critical QPI applications. In bypass mode, the IDT9ZX21201 can
provide outputs up to 150MHz.
Key Specifications
Features/Benefits
• Space-saving 64-pin packages
• Fixed feedback path/ 0ps input-to-output delay
• 9 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• 100MHz or 133MHz PLL mode operation/supports PCIe
and QPI applications
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• Software control of PLL Bandwidth and Bypass Settings/
PLL can dejitter incoming clock (B Rev only)
Functional Block Diagram
DATASHEET
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and newer
platforms
Output Features
• 12 - 0.7V differential HCSL output pairs
Logic
DIF(11:0)
HIBW_BYPM_LOBW#
SMBDAT
SMBCLK
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
100M_133M#
Z-PLL
(SS Compatible)
DFB_OUT
DIF_IN
DIF_IN#
OE(11:0)#
IREF
Note: Even though the feedback is fixed, DFB_OUT still needs a
termination network for the part to function.
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 65 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
2
Pin Configuration
Functionality at Power Up (PLL Mode)
100M_133M# DIF_IN
(
MHz
)
DIF
1 100.00 DIF_IN
0 133.33 DIF_IN
PLL Operating Mode Readback Table
HiBW_BypM_LoBW# Byte0, bit 7 Byte 0, bit 6
Low (Low BW) 0 0
Mid (Bypass) 0 1
High (High BW) 1 1
PLL Operating Mode
HiBW_BypM_LoBW# MODE
Low PLL Lo BW
Mid Bypass
High PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
Tri-level Input Thresholds
Level Voltage
Low <0.8V
Mid 1.2<Vin<1.8V
High Vin > 2.2V
SMB_A1_tri SMB_A0_tri
00D8
0M DA
01DE
M0 C2
MMC4
M1C6
10CA
1MCC
11 CE
9ZX21201 SMBus Addressin
g
Pin SMBus Address
(Rd/Wrt bit = 0)
DIF_11#
DIF_11
vOE11#
vOE10#
DIF_10#
DIF_10
GND
VDD
VDD
DIF_9#
DIF_9
vOE9#
vOE8#
DIF_8#
DIF_8
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 148
GND
GNDA 247
DIF_7#
IREF 346
DIF_7
100M_133M# 445
vOE 7#
HIBW_BYPM_LOBW# 544
vOE 6#
CKPWRGD_PD# 643
DIF_6#
GND 742
DIF_6
VDDR 841
GND
DIF_IN 940
VDD
DIF_IN# 10 39 DIF_5#
SMB_A0_tri 11 38 DIF_5
SMBDAT 12 37 vOE 5#
SMBCLK 13 36 vOE 4#
SMB_A1_tri 14 35 DIF_4#
DFB_OUT# 15 34 DIF_4
DFB_OUT 16 33 GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DIF_0
DIF_0#
vOE0
#
vOE1
#
DIF_1
DIF_1#
GND
VDD
VDD
DIF_2
DIF_2#
vOE2
#
vOE3
#
DIF_3
DIF_3#
VDD
Notes: Pins with ^ prefix have internal ~100K pullup
Pins with v prefix have internal ~100K pulldown.
9ZX21201
MLF Power Connections
VDD VDD GND
1 2 Analog PLL
8 7 Analog Input
24,40,57 25,32,49,56 23,33,41,48,
58 DIF clocks
Pin Number Description
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
3
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GNDA PWR Ground pin for the PLL core.
3 IREF OUT
This pin establishe s the referen ce for the differential current-mode output pairs. It requires a fixed precision
resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require
different values. See data sheet.
4 100M_133M # IN 3.3V Input to select operating frequency
See Functionality Table for Definition
5 H IBW _BYPM _LOBW# IN Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
6CKPWRGD_PD# IN
Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
7 GND PWR Ground pin.
8 VDDR PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered a
pp
ro
p
riatel
y
.
9 DIF_IN IN 0.7 V Differential TRUE in
p
ut
10 DIF_IN# IN 0.7 V Differential Com
p
lementar
y
In
p
ut
11 SMB_A0_tri IN SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to d ecode 1 of 9 SMBus
Addresses.
12 SMBDAT I/
O
Data
p
in of SMBUS circuitr
y
, 5V tolerant
13 SMBCLK IN Clock
in of SMBUS circuitr
, 5V tolerant
14 SMB_A1_tri IN SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to d ecode 1 of 9 SMBus
Addresses.
15 DFB_OUT# OUT Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization
with in
p
ut clock to e lim ina te
p
hase error.
16 DFB_OUT OUT True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input
clock t o el imi nate
p
hase error.
17 DIF_0 OUT 0.7V differential true clock output
18 DIF_0# OUT 0.7V differential Complementary clock output
19 vOE0# IN Active low input for enabling DIF pair 0.
1 =disable out
p
uts, 0 = enable out
p
uts
20 vOE1# IN Active low input for enabling DIF pair 1.
1 =disable out
p
uts, 0 = enable out
p
uts
21 DIF_1 OUT 0.7V differential true clock output
22 DIF_1# OUT 0.7V differential Complementary clock output
23 GND PWR Ground pin.
24 VDD PWR Power supply, nominal 3.3V
25 VDD PWR Power supply, nominal 3.3V
26 DIF_2 OUT 0.7V differential true clock output
27 DIF_2# OUT 0.7V differential Complementary clock output
28 vOE2# IN Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outp uts
29 vOE3# IN Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outp uts
30 DIF_3 OUT 0.7V differential true clock output
31 DIF_3# OUT 0.7V differential Complementary clock output
32 VDD PWR Power supply, nominal 3.3V
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
4
Pin Description (continued)
33 GND PWR Ground pin.
34 DIF_4 OUT 0.7V differential true clock output
35 DIF_4# OUT 0.7V differential Complementary clock output
36 vOE4# IN Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
37 vOE5# IN Active low input for enabling DIF pair 5. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
38 DIF_5 OUT 0.7V differential true clock output
39 DIF_5# OUT 0.7V differential Complementary clock output
40 VDD PWR Power supply, nominal 3.3V
41 GND PWR Ground pin.
42 DIF_6 OUT 0.7V differential true clock output
43 DIF_6# OUT 0.7V differential Complementary clock output
44 vOE6# IN Active low input for enabling DIF pair 6. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
45 vOE7# IN Active low input for enabling DIF pair 7. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
46 DIF_7 OUT 0.7V differential true clock output
47 DIF_7# OUT 0.7V differential Complementary clock output
48 GND PWR Ground pin.
49 VDD PWR Power supply, nominal 3.3V
50 DIF_8 OUT 0.7V differential true clock output
51 DIF_8# OUT 0.7V differential Complementary clock output
52 vOE8# IN Active low input for enabling DIF pair 8. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
53 vOE9# IN Active low input for enabling DIF pair 9. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
54 DIF_9 OUT 0.7V differential true clock output
55 DIF_9# OUT 0.7V differential Complementary clock output
56 VDD PWR Power supply, nominal 3.3V
57 VDD PWR Power supply, nominal 3.3V
58 GND PWR Ground pin.
59 DIF_10 OUT 0.7V differential true clock output
60 DIF_10# OUT 0.7V differential Complementary clock output
61 vOE10# IN Active low input for enabling DIF pair 10. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
62 vOE11# IN Active low input for enabling DIF pair 11. This pin has an internal pull-down
1 =disable outputs, 0 = enable outputs
63 DIF_11 OUT 0.7V differential true clock output
64 DIF_11# OUT 0.7V differential Complementary clock output
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
5
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDD, VDDA VDD for core logic and PLL 4.6 V 1,2
Input Low Voltage VIL GND-0.5 V 1
Input High Voltage VIH Except for SMBus interface VDD+0.5V V 1
Input High Voltage VIHSMB SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150 °C1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature TCOM Commmercial range 0 70 °C 1
Input High Voltage VIH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs 2V
DD + 0.3 V 1
Input Low Voltage VIL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs GND - 0.3 0.8 V 1
IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200 200 uA 1
Fib
yp
VDD = 3.3 V, Bypass mode 33 150 MHz 2
Fi
p
ll VDD = 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2
Fi
p
ll VDD = 3.3 V, 133.33MHz PLL mode 120 133.33 147 MHz 2
Pin Inductance L
p
in 7nH1
CIN Logic Inputs, except DIF_IN 1.5 5 pF 1
CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,4
COUT Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock 0.300 1 ms 1,2
Input SS Modulation
Frequency fMODI N
Allowable Frequency
(Triangular Modulation) 30 33 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion 4612clocks1
Tdrive_PD# tDRVPD
DIF output enable after
PD# de-assertion 16 300 us 1,3
Tfall tFFall time of control inputs 10 ns 1,2
Trise tRRise time of control inputs 10 ns 1,2
SMBus Input Low Voltage VILSMB 0.8 V 1
SMBus Input High Voltage VIHSMB 2.1 VDDSMB V1
SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1
SMBus Sink Current IPULLUP @ VOL 4mA1
Nominal Bus Voltage VDDSMB 3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1,5
1Guaranteed by desi
g
n and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
5The differential in
p
ut clock must be runnin
g
for the SMBus to be active
Input Current
3Time from deassertion until out
p
uts are >200 mV
4DIF_IN input
Capacitance
Input Frequency
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
6
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1 2 4 V/ns 1, 2, 3
Slew rate matching ∆Trf Slew rate matching, Scope averaging on 8 20 %1, 2, 4
Voltage High VHigh 660 705 850 1
Voltage Low VLow -150 1 150 1
Max Voltage Vmax 725 1150 1
Min Voltage Vmin -300 -22 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1407 mV 1, 2
Crossin
g
Volta
g
e (abs) Vcross_abs Scope avera
g
in
g
off 250 309 550 mV 1, 5
Crossing Voltage (var) ∆-Vcross Scope averaging off 22 140 mV 1, 6
2 Measured from differential waveform
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off) mV
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 412Ω (1%), IREF = 2.7mA.
IOH = 6.4 x IREF and VOH = 0.7V @ ZO=85Ω differential impedance.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope uses for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
IDDVDD 133MHz, CL = Full load; VDD rail, Zo=85Ω260 275 mA 1
IDDVDDA 133MHz, CL = Full load; VDD rail, Zo=85Ω13 20 mA 1
IDDVDDPD Power Down, VDD rail, Zo=85Ω26mA1
IDDVDDAPD Power Down, VDD rail, Zo=85Ω1.3 2mA1
1Guaranteed by design and characterization, not 100% tested in production.
Operating Current
Powerdown Current
Electrical Characteristics - DIF_IN Clock Input Parameters
TAMB=TCOM unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN VCROSS Cross Over Voltage 150 900 mV 1
Input Swing - DIF_IN VSWING Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA
Input Duty Cycle dtin Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle JDI FI n Differential Measurement 0 125 ps 1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
7
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] tSPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V -100 29 100 ps 1,2,4,5,8
CLK_IN, DIF[x:0] tPD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V 2.5 3.7 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0] tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
across volta
g
e and temperature -50 50 ps 1,2,3,5,8
CLK_IN, DIF[x:0] tDSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature -250 250 ps 1,2,3,5,8
CLK_IN, DIF[x:0] tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode 2.9 5 ps
(rms) 1,2,3,5,8
CLK_IN, DIF[x:0] tDSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode 14 75 ps 1,2,3,5,8
DIF{x:0] tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode) 32 65 ps 1,2,3,8
PLL Jitter Peaking j
p
eak-hibw LOBW#_BYPASS_HIBW = 1 0 1.8 2.5 dB 7,8
PLL Jitter Peaking j
p
eak-lobw LOBW#_BYPASS_HIBW = 0 0 0.7 2 dB 7,8
PLL Bandwidth pllHI BW LOBW#_BYPASS_HIBW = 1 2 3.1 4 MHz 8,9
PLL Bandwidth pllLOBW LOBW#_BYPASS_HIBW = 0 0.7 1.1 1.4 MHz 8,9
Duty Cycle tDC Measured differentially, PLL Mode 45 49.6 55 % 1
Duty Cycle Distortion tDCD
Measured differentially, Bypass Mode
@100MHz -2 -0.2 2 % 1,10
PLL mode 15.7 50 ps 1,11
Additive Jitter in Bypass Mode 0.1 50 ps 1,11
Notes for preceding table:
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by desi
g
n and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
3 All B
yp
ass Mode In
p
ut-to-Out
p
ut s
p
ecs refer to the timin
g
between an in
p
ut ed
g
e and the s
p
ecific out
p
ut ed
g
e created b
y
it.
4 This
p
arameter is deterministic for a
g
iven device
5 Measured with sco
p
e avera
g
in
g
on to find mean value.
Jitter, Cycle to cycle tjcyc-cyc
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2 Measured from differential cross-
p
oint to differential cross-
p
oint. This
p
arameter can be tuned with external feedback
p
ath
,
if
p
resent.
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
8
Power Management Table
Outputs
CKPWRGD•/PD#
DIF_IN/
DIF_IN#
SMBus
EN bit OE# Pin
DIF(11:0)/
DIF(11:0)#
DFB_OUT/
DFB_OUT#
0XXX
Hi-Z1Hi-Z1OFF
0X
Hi-Z1Running ON
1 0 Running Running ON
11
Hi-Z1Running ON
NOTE:
1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs
Inputs
PLL State
1 Running
Control Bits/Pins
Electrical Characteristics - Phase Jitter Parameters
TA = TCOM; Supply Voltage VDD/ VDDA = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jp
hPCIeG1 PCIe Gen 1 32 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz 0.8 3 ps
(rms) 1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 1.9 3.1 ps
(rms) 1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 0.45 1ps
(rms) 1,2,4
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.20 0.5 ps
(rms) 1,5
QPI & SMI
(100MHz, 8.0Gb/s, 12UI) 0.14 0.3 ps
(rms) 1,5
QPI & SMI
(100MHz, 9.6Gb/s, 12UI) 0.12 0.2 ps
(rms) 1,5
t
jp
hPCIeG1 PCIe Gen 1 0.10 10 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz 0.13 0.3 ps
(rms) 1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 0.10 0.7 ps
(rms) 1,2,6
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 0.10 0.3 ps
(rms) 1,2,4,6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.09 0.3 ps
(rms) 1,5,6
QPI & SMI
(100MHz, 8.0Gb/s, 12UI) 0.09 0.1 ps
(rms) 1,5,6
QPI & SMI
(100MHz, 9.6Gb/s, 12UI) 0.09 0.1 ps
(rms) 1,5,6
1 Applies to all outputs.
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
4 Sub
j
ect to final radification b
y
PCI SIG.
5 Calculated from Intel-su
pp
lied Clock Jitter Tool v 1.6.4
2 See htt
p
://www.
p
cisi
g
.com for com
p
lete s
p
ecs
Additive Phase Jitter,
Bypass mode
tjphPCIeG2
tjphQPI_SMI
tjphQPI_SMI
Phase Jitter, PLL Mode
tjphPCIeG2
3 Sam
p
le size of at least 100K c
y
cles. This fi
g
ures extra
p
olates to 108
p
s
p
k-
p
k @ 1M c
y
cles for a BER of 1-12.
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
9
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3
133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3
133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4
Notes:
1Guaranteed by design and characterization, not 100% tested in production.
3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
SSC OFF
Center
Freq.
MHz
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+
accuracy requirements (+/-100ppm). The 9ZX21201 itself does not contribute to ppm error.
DIF
DIF
Measurement Window
Units Notes
Notes
Differential Output Termination Table
DIF Zo (Ω)Iref (
Ω)Rs (
Ω)Rp (
Ω)
100 475 33 50
85 412 27 42.2 or 43.2
DIF Zo=85ohms,10"
Rp Rp
HCSL Output
Buffer
9ZX21201 Differential Test Loads
Rs
Rs
2pF 2pF
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
10
General SMBus serial interface information for the 9ZX21201
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address XX (H)
• IDT clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will
acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• IDT clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address XX (H)
• IDT clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read addressYY (H)
• IDT clock will
acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends
Byte N + X -1
• IDT clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
IDT (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Be
g
innin
g
Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address XX
(
H
)
Beginning Byte = N
WRite
starT bit
Controller (Host)
TstarT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
IDT
(
Slave/Receiver
)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address YY
(
H
)
Index Block Read Operation
Slave Address XX
(
H
)
Beginning Byte = N
ACK
ACK
Note: XX(H) is defined by SMBus address select pins.
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
11
SMBusTable: PLL Mode, and Frequency Select Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 PLL Mode 1 PLL O
p
eratin
g
Mode Rd back 1 RLatch
Bit 6 PLL Mode 0 PLL O
p
eratin
g
Mode Rd back 0 RLatch
Bit 5 0
Bit 4 0
Bit 3 PLL_SW_EN Enable S/W control of PLL B
W
RW HW Latch S/W Control 0
Bit 2 PLL Mode 1 PLL O
p
eratin
g
Mode 1 RW 1
Bit 1 PLL Mode 0 PLL O
p
eratin
g
Mode 1 RW 1
Bit 0 100M_133M# Fre
q
uenc
y
Select Readback R 133MHz 100MHz Latch
SMBusTable: Output Control Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 DIF_7_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 6 DIF_6_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 5 DIF_5_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 4 DIF_4_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 3 DIF_3_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 2 DIF_2_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 1 DIF_1_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 0 DIF_0_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
SMBusTable: Output Control Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 DIF_11_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 2 DIF_10_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 1 DIF_9_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
Bit 0 DIF_8_En Out
p
ut Control - '0' overrides OE#
p
in RW 1
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
See PLL Operating Mode
Readback Table
See PLL Operating Mode
Readback Table
Low/Low Enable
30/31
B
y
te 3
50/51
59/60
54/55
B
y
te 2
B
y
te 0
5
5
4
These bits
available in B
rev onl
y
.
B
y
te 1
47/46
64/63
26/27
21/22
17/18
43/42
39/38
35/34
Low/Low Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
12
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
SMBusTable: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 RID3 R X
Bit 6 RID2 R X
Bit 5 RID1 R X
Bit 4 RID0 R X
Bit 3 VID3 R 0
Bit 2 VID2 R 0
Bit 1 VID1 R 0
Bit 0 VID0 R 1
SMBusTable: DEVICE ID
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 R1
Bit 6 R1
Bit 5 R0
Bit 4 R0
Bit 3 R1
Bit 2 R0
Bit 1 R0
Bit 0 R1
SMBusTable: Byte Count Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 BC4 RW 0
Bit 3 BC3 RW 1
Bit 2 BC2 RW 0
Bit 1 BC1 RW 0
Bit 0 BC0 RW 0
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e 0 1 Default
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Device ID 5
Device ID 6
Device ID 0
Default value is 8 hex, so 9
bytes (0 to 8) will be read back
by default.
Reserved
Reserved
-
Reserved
1201 is 201 decimal or C9 hex
Device ID 7
(
MSB
)
B
y
te 7
-
-
-
-
-
-
-
-
B
y
te 5
B
y
te 6
B
y
te 4
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
B
y
te 8
-
-
-
-
-
Device ID 2
Device ID 1
Device ID 4
REVISION ID A rev = 0000
B rev = 0001
-
Reserved
VENDOR ID
Device ID 3
0001 for IDT/ICS
Writing to this register configures how
many bytes will be read back.
Reserved
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
13
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
DI F Re fe rence Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
14
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Al terna tive Term i nati on for LVDS and othe r Comm on Diffe rential Si gnal s (figure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cabl e Conne cte d AC Coupled Appli ca ti on (fi gure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
15
DIMENSIONS DIMENSIONS (mm)
SYMBOL MIN. MAX.
A0.81.0
N64 A1 00.05
ND16 A3
NE16 b 0.18 0.3
e
D x E BASIC
D2 MIN. / MAX. 6.00 6.25
E2 MIN. / MAX. 6.00 6.25
L MIN. / MAX. 0.30 0.50
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
SYMBOL 64L
0.25 Reference
0.50 BASIC
9.00 x 9.00
Orderi ng Inf orm ation
Part / Orde r Num ber S hi ppi ng Packa ge Packa ge Tem pera ture Diffe rence
9ZX21201AKLF Trays 64-pin MLF 0 to +70°C
9ZX21201AKLFT Tape and Reel 64-pin MLF 0 to +70°C
9ZX21201BKLF Trays 64-pin MLF 0 to +70°C
9ZX21201BKLFT Tape and Reel 64-pin MLF 0 to +70°C
"LF" desi gnates P B-free configurati on, RoHS com pl i a nt.
"A a nd B" a re the device revision designa tors (w ill not correla te w ith the datashee t revision).
W/O Byte 0 PLL Control
With Byte 0 PLL Mode
Control
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
16
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www.IDT.com
For Sales
800-345-7015
408-284-8200
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408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
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United States
800 345 7015
+408 284 8200 (outside U.S.)
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1 Kallang Sector #07-01/06
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KT22 7TU
England
Phone: 44-1372-363339
Fax: 44-1372-378851
© 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
Revision History
Rev. Issuer Issue Date Description Page #
A RDW 9/13/2011
1. Updated electrical tables with char data
2. Fixed minor typographical errors
3. Moved to final
Various
B RDW 12/8/2011
1. Added B rev functionality description to Features, Benefits
2. Updated tDSPO_BYP parameter from +/-350ps to +/-250ps
3.Updated SMBus Byte 0 with B rev functionality
4. Updated ordering information to include B rev
1,7,11,15
C RDW 4/18/20112
1. Updated Power connections table to be consistent with 9ZXL1231.
2. Updated Rp value for 85 ohm differential Zo from 43.2ohms to 42.2 OR
43.2 ohms to be consistent with Intel recommendations.
2,9
D RDW 5/5/2014 1. Fixed error in feedback path on block diagram 1
E RDW 11/19/2015 1. Updated the DIF_IN Input clock specification to align with the PCIe SIG
specification. 6