LTC6602CUF#TRPBF - Linear Technology Corporation

LTC6602

6602fc

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual Matched, High

Frequency Bandpass/Lowpass Filters

The LTC

6602 is a dual, matched, programmable bandpass

or lowpass ﬁlter and differential driver. The selectivity of the

LTC6602, combined with its phase matching and dynamic

range, make it ideal for ﬁltering in RFID systems. With two

degree phase matching between channels, the LTC6602 can

be used in applications requiring highly matched ﬁlters,

such as transceiver I and Q channels. Gain programmabil-

ity, and the fully differential inputs and outputs, simplify

implementation in most systems.

Both channels of the LTC6602 consist of a programmable

lowpass and highpass ﬁlter. For bandpass functionality,

the lowpass ﬁlters are programmed for the upper cutoff

frequency. For lowpass functionality, the highpass ﬁlters

can be bypassed. The ﬁlter cutoff frequencies can be set

with a guaranteed accuracy of 3% with the use of a single

resistor. Alternatively, the ﬁlter cutoff frequencies can be

controlled with an external clock.

The LTC6602 operates on a single 2.7V to 3.6V supply

and features a low power shutdown mode.

UHF RFID Reader Dual Baseband Filter and Dual ADC

n Matched Dual Filter/Driver, Ideal for RFID Readers

n Guaranteed Phase Matching to Within 2 Degrees

n Guaranteed Gain Matching to Within 0.2dB

n Conﬁgurable as Lowpass or Bandpass:

– Programmable 5th Order Lowpass: 42kHz to 900kHz

– Programmable 4th Order Highpass: 4.2kHz to 90kHz

n Programmable Gain: 1×, 4×, 16×, 32×

n Simple Pin Programming or SPI Interface

n Low Noise: –145dBm/Hz (Input Referred)

n Low Distortion: –75dBc at 200kHz

n Differential, Rail-to-Rail Inputs and Outputs

n Input Range Extends from 0V to 5V

n Low Voltage Operation: 2.7V to 3.6V

n Shutdown Mode

n 4mm × 4mm QFN Package

n Multiprotocol RFID Readers: EPC-GEN2, ISD and IPX

n IDEN, PHS, GSM Basestations

n Repeaters, Radio Links, and Modems

n Wireless Telemetry

n JTRS

6602 TA01

LTC6602

V+IN

+INA

–INA

+INB

–INB

RBIAS

VOCM

MUTE

GAIN0(D0)

GAIN1

GND

–OUTA

+OUTA

–OUTB

+OUTB

CLKIO

SER

CLKCNTL

HPF0(SDO)

HPF1(SDI)

LPF0(SCLK)

LPF1(CS)

V+AV+D

MUTE

INPUT

FROM

TRANSMITTER

38.3k 0.1µF

LTC2297

CLK IN

0.1µF 0.1µF

CS SCLK SDI

SPI CONTROL INPUT

I INPUT

Q INPUT

I OUTPUT

Q OUTPUT 2.2µF

AIN+

AIN–

BIN+

BIN–

VCM

÷4

CLOCK INPUT

24MHz TO 128MHz

(COVERS THE TAG BACKSCATTER LINK FREQUENCY RANGE OF 40kHz to 640kHz

OF THE CLASS 1 GENERATION 2 UHF RFID COMMUNICATION PROTOCOL)

100pF

14-BIT

ADC

14-BIT

ADC

100Ω

Gain vs Frequency

FREQUENCY (Hz)

GAIN (dB)

6602 TA01b

–40

–30

–20

–10

–50

–601k 1M 10M100k10k

EXTERNAL CLOCK = 90MHz

90kHz-900kHz BPF

15kHz-150kHz BPF

45kHz-300kHz BPF

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

LTC6602

6602fc

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

V+IN to GND ................................................................6V

V+A, V+D to GND .........................................................4V

Filter Inputs to GND ....................... –0.3V to V+IN + 0.3V

All Other Pins to GND .............. –0.3V to V+A, V+D + 0.3V

Output Short-Circuit Duration .......................... Indeﬁnite

Operating Temperature Range (Note 2)

LTC6602CUF ........................................ –40°C to 85°C

LTC6602IUF ......................................... –40°C to 85°C

Speciﬁed Temperature Range (Note 3)

LTC6602CUF ............................................ 0°C to 70°C

LTC6602IUF ......................................... –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

(Note 1)

24 23 22 21 20 19

789

TOP VIEW

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

10 11 12

V+IN

V+A

VOCM

RBIAS

CLKCNTL

LPF1(CS)

–OUTA

SER

V+D

CLKIO

GND

+OUTB

+INA

–INA

GAIN1

GAIN0(D0)

MUTE

+OUTA

+INB

–INB

LPFO(SCLK)

HPF1(SDI)

HPFO(SDO)

–OUTB

TJMAX = 150°C, θJA = 37°C/W

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO THE PCB.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Filter Gain Either Channel

Gain = 0dB

External Clock = 90MHz, Highpass Filter Cutoff = 45kHz,

Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P

fIN = 22.5kHz

fIN = 45kHz

fIN = 150kHz

fIN = 300kHz

fIN = 900kHz

–1.8

0.1

–2.7

–32

–1.2

0.5

–2

–44

–30

–0.8

0.8

–1.2

–43

Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 45kHz,

Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P

fIN = 45kHz

fIN = 150kHz

fIN = 300kHz

±0.2

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6602CUF#PBF LTC6602CUF#TRPBF 6602 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C

LTC6602IUF#PBF LTC6602IUF#TRPBF 6602 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =

300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.

LTC6602

6602fc

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =

300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Filter Phase

Either Channel

External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz,

Lowpass Filter Cutoff = 300kHz

fIN = 50kHz

fIN = 250kHz

125

–134

130

–130

134

–126

deg

Matching of Filter Phase External Clock = 90MHz, VIN = 3.6VP-P , Highpass Filter Cutoff = 45kHz,

Lowpass Filter Cutoff = 300kHz

fIN = 50kHz

fIN = 250kHz

±2

±1.5

deg

Filter Gain Either Channel

Gain = 0dB

External Clock = 90MHz, Highpass Filter Cutoff = 15kHz,

Lowpass Filter Cutoff = 150kHz, VIN = 3.6VP-P

fIN = 7.5kHz

fIN = 15kHz

fIN = 50kHz

fIN = 150kHz

fIN = 450kHz

–1.6

0.4

–2.3

–32

–1.2

0.7

–1.9

–44

–30

–0.8

0.9

–1.3

–43

Matching of Filter Gain External Clock = 90MHz, VIN = 3.6VP-P , Highpass Filter Cutoff = 15kHz,

Lowpass Filter Cutoff = 150kHz

fIN = 15kHz

fIN = 50kHz

fIN = 150kHz

±0.2

Filter Phase Either

Channel

External Clock = 90MHz, VIN = 3.6VP-P , Highpass Filter Cutoff = 15kHz,

Lowpass Filter Cutoff = 150kHz

fIN = 16.5kHz

fIN = 125kHz

137

–143

142

–138

146

–134

deg

Matching of Filter Phase External Clock = 90MHz, VIN = 3.6VP-P , Highpass Filter Cutoff = 15kHz,

Lowpass Filter Cutoff = 150kHz

fIN = 16.5kHz

fIN = 125kHz

±2

±1

deg

Filter Gain Either Channel

Gain = 0dB

External Clock = 90MHz, Highpass Filter Cutoff = 90kHz,

Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P

fIN = 45kHz

fIN = 90kHz

fIN = 300kHz

fIN = 900kHz

fIN = 2700kHz

–1.8

–0.1

–2.1

–29

–1.2

0.6

–1.1

–45

–27

–0.7

1.2

–0.5

–44

Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 90kHz,

Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P

fIN = 90kHz

fIN = 300kHz

fIN = 900kHz

±0.3

±0.6

±0.4

Filter Phase Either Chanel External Clock = 90MHz, VIN = 3.6VP-P , Highpass Filter Cutoff = 90kHz,

Lowpass Filter Cutoff = 900kHz

fIN = 100kHz

fIN = 750kHz

136

–136

141

–131

145

–127

deg

Matching of Filter Phase External Clock = 90MHz, VIN = 3.6VP-P , Highpass Filter Cutoff = 90kHz,

Lowpass Filter Cutoff = 900kHz

fIN = 100kHz

fIN = 750kHz

±2

±1.5

deg

Filter Cutoff Accuracy

when Self Clocked

CLKCNTL = 3V (Note 4)

RBIAS = 200k, Output Clock = 24.705MHz

RBIAS = 54.9k, Output Clock = 90MHz

±3

LTC6602

6602fc

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =

300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

PGA Gain Lowpass Cutoff = 150kHz, Highpass Filter Bypassed,

Measured at DC, 0.6V to 2.4V Each Output

Gain Setting = 0dB

Gain Setting = 12dB

Gain Setting = 24dB

Gain Setting = 30dB

0.4

11.6

23.5

29.1

0.8

23.8

29.6

1.2

12.4

24.1

30.1

PGA Gain Matching Lowpass Cutoff = 150kHz, Highpass Filter Bypassed,

Measured at DC, 0.6V to 2.4V Each Output

Gain Setting = 0dB

Gain Setting = 12dB

Gain Setting = 24dB

Gain Setting = 30dB

±0.2

±0.3

Noise At 200kHz Voltage Noise Referred to the Input

Gain = 0dB

Gain = 12dB

Gain = 24dB

Gain = 30dB

–119

–131

–142

–146

dBm/Hz

Integrated Noise Noise Bandwidth = 1.57MHz (Note 5), Referred to the Input

Gain = 0dB

Gain = 12dB

Gain = 24dB

Gain = 30dB

–62

–74

–85

–89

dBm

THD VIN = 1.5VP-P , fIN = 100kHz –75 dB

Input Impedance Differential

Common Mode

kΩ

VOS Differential Differential Offset Voltage at Either Output

Differential Offset Voltage at Either Output HPF Bypassed, Lowest LPF Cutoff

Differential Offset Voltage at Either Output HPF Bypassed, Highest LPF Cutoff

±7

±10

±15

±30

VOSCM Common Mode Offset Voltage

VOCM = 1.5V, Supplies = 3V

VOSCM = VOUT-CM – VOCM

–40

±20

CMR Differential

ΔVINCM/ΔVOUTDIFF

Common Mode Input from 0 to 3V

V+IN = 3V

Common Mode Input from 0 to 5V

V+IN = 5V

VOCM Pin Voltage V+A = V+D = 3V, Pin 3 Open l1.2 1.4 1.6 V

VOCM Pin Input

Impedance

V+A = V+D = 3V, Pin 3 Open l300 400 700 Ω

Output Swing Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC

Source 1mA, VOUT High, Relative to V+A

Sink 1mA, VOUT Low, Relative to GND

200

500

Short-Circuit Current Lowpass Cutoff = 150kHz, Highpass Filter Bypassed

Sourcing

Sinking

Supply Current Internal Clock (RBIAS = 54.9k); Sum of the Currents into V+D, V+A, and

V+IN All Supplies Set to 3V

HPF = 15k, LPF = 150k

HPF = 45k, LPF = 300k

HPF = 90k, LPF = 900k

100

105

133

138

LTC6602

6602fc

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =

300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Current,

Shutdown Mode

Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V

Shutdown Via Serial Interface, Control Bit D1 = 1.

170

235

µA

Supply Voltage V+D, V+A Relative to GND

V+IN Relative to GND

2.7

3.6

5.5

PSR V+D = V+A = V+IN, All from 2.7V to 3.6V

V+D = V+A = 3.0V, V+IN from 4.5V to 5.5V

RBIAS Resistor Range Clock Frequency Error ≤ ±3%, CLKCNTL = 3V l54.9 200 kΩ

RBIAS Pin Voltage 54.9k < RBIAS < 200k 1.17 V

Clock Frequency Drift

Over Temperature

RBIAS = 54.9k, CLKCNTL Pin Open 40 ppm/ºC

Clock Frequency Change

Over Supply

V+A, V+D from 2.7V to 3.6V, RBIAS = 54.9k, CLKCNTL Pin Open l–0.6 0.1 0.6 %/V

Output Clock Duty Cycle RBIAS = 54.9k l25 50 75 %

CLKIO Pin High Level

Input Voltage

CLKCNTL = 0V (Note 6) V+D – 0.3 V

CLKIO Pin Low Level

Input Voltage

CLKCNTL = 0V (Note 6) 0.3 V

CLKIO Pin Input Current CLKCNTL = 0V

CLKIO = 0V (Note 7)

CLKIO = V+D

–1

µA

CLKIO Pin High Level

Output Voltage

V+A = V+D = 3V, CLKCNTL = 3V

IOH = –1mA

IOH = –4mA

2.95

2.9

CLKIO Pin Low Level

Output Voltage

V+A = V+D = 3V, CLKCNTL = 3V

IOL = 1mA

IOL = 4mA

0.05

0.1

CLKIO Rise Time V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF 0.3 ns

CLKIO Fall Time V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF 0.3 ns

SER, MUTE

High Level Input Voltage

Pins 17, 20 lV+D – 0.3 V

SER, MUTE

Low Level Input Voltage

Pins 17, 20 l0.3 V

SER, MUTE

Input Current

Pin 17 or Pin 20 = 0V (Note 7)

Pin 17 or Pin 20 = V+D

–10

µA

CLKCNTL High Level

Input Voltage

Pin 5 lV+D – 0.5 V

CLKCNTL Low Level

Input Voltage

Pin 5 0.5 V

CLKCNTL Input Current CLKCNTL = 0V (Note 7)

CLKCNTL = V+D

–25 –15

µA

LTC6602

6602fc

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. Speciﬁcations apply to pins 6, 9-11, 21 and 22.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V+D = 2.7V to 3.6V

VIH Digital Input High Voltage Pins 6, 9-11, 21, 22 l2 V

VIL Digital Input Low Voltage Pins 6, 9-11, 21, 22 l0.8 V

IIN Digital Input Current Pins 6, 9-11, 21, 22 (Note 7) l–1 1 µA

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V+D = 2.7V to 3.6V

VIH Digital Input High Voltage Pins 6, 9, 10 l2 V

VIL Digital Input Low Voltage Pins 6, 9, 10 l0.8 V

IIN Digital Input Current Pins 6, 9, 10 (Note 7) l–1 1 µA

VOH Digital Output High Voltage Pins 11, 21 Sourcing 500µA lVSUPPLY – 0.3 V

VOL Digital Output Low Voltage Pins 11, 21 Sinking 500µA l0.3 V

t1SDI Valid to SCLK Setup (Note 6) l60 ns

t2SDI Valid to SCLK Hold (Note 6) l0 ns

t3SCLK Low l100 ns

t4SCLK High l100 ns

t5CS Pulse Width l60 ns

t6LSB SCLK to CS (Note 6) l60 ns

t7CS Low to SCLK (Note 6) l30 ns

t8SDO Output Delay CL = 15pF l125 ns

t9SCLK Low to CS Low (Note 6) l0 ns

Pin Programmable Control Mode Speciﬁcations

Serial Port DC and Timing Speciﬁcations

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: LTC6602C and LTC6602I are guaranteed functional over the

operating temperature range of –40°C to 85°C.

Note 3: LTC6602C is guaranteed to meet speciﬁed performance from

0°C to 70°C. The LTC6602C is designed, characterized and expected to

meet speciﬁed performance from –40°C to 85°C but is not tested or QA

sampled at these temperatures. The LTC6602I is guaranteed to meet the

speciﬁed performance limits from –40°C to 85°C.

Note 4: This test measures the internal oscillator accuracy (deviation from

the fCLK equation). Variations in the internal oscillator frequency cause

variations in the ﬁlter cutoff frequency. See the “Applications Information”

section.

Note 5: 1.57MHz is the equivalent noise bandwidth of a 1MHz 1st order

RC lowpass ﬁlter.

Note 6: Guaranteed by design, not subject to test.

Note 7: To conform to the Logic IC standard, current out of a pin is

arbitrarily given a negative value.

LTC6602

6602fc

TYPICAL PERFORMANCE CHARACTERISTICS

Gain vs Frequency

Distortion vs Input Frequency

Distortion vs Output Voltage

Distortion vs Gain

Distortion vs Highpass

Cutoff Frequency

Distortion vs Lowpass

Cutoff Frequency

Filter Cutoff Accuracy

vs Supply Voltage

Filter Cutoff Accuracy

vs Temperature

Common Mode Rejection

FREQUENCY (Hz)

GAIN (dB)

6602 G01

–40

–30

–20

–10

–50

–601k 1M 10M100k10k

TA = 25°C

VS = 3V

EXTERNAL CLOCK

RBIAS = 54.9k

GAIN = 0dB

Gain vs Frequency

-60

-50

-40

-30

-20

-10

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Gain (dB)

TA = 25oC

VS = 3V

External Clock

RBIAS = 54.9k

Gain = 0dB

15-150kHz BPF

45-300kHz BPF

90-900kHz BPF

90kHz-900kHz BPF

15kHz-150kHz BPF

45kHz-300kHz BPF

INPUT FREQUENCY (kHz)

DISTORTION (dBc)

66062 G02

–70

–75

–80

–85

–90 0 50 100 250 300200150

TA = 25°C, VS = 3V, DIFFERENTIAL INPUT,

VIN = 1.5VP-P, 12.4-82.4kHz BPF, RBIAS = 200k

45kHz-300kHz BPF, RBIAS = 54.9k, GAIN = 0dB

HD3

12kHz-82kHz BPF

HD2

12kHz-82kHz BPF

HD2

45kHz-300kHz BPF

HD3

45kHz-300kHz BPF

OUTPUT VOLTAGE (VP-P)

DISTORTION (dBc)

66062 G03

–30

–40

–50

–60

–70

–80

–90

–100 0 1 2 5 643

TA = 25°C

VS = 3V

fIN = 100kHz

DIFFERENTIAL INPUT

RBIAS = 54.9k

RBIAS = 45kHz-300kHz BPF

GAIN = 0dB

HD3

HD2

GAIN (dB)

DISTORTION (dBc)

6602 G04

–70

–75

–80

–85

–90 0 6 24 301812

TA = 25°C

VS = 3V

fIN = 100kHz

DIFFERENTIAL INPUT, VOUT = 1.5VP-P

RBIAS = 54.9k

45kHz-300kHz BPF

HD3

HD2

HIGHPASS CUTOFF FREQUENCY (kHz)

DISTORTION (dBc)

6602 G05

–70

–75

–80

–85

–90 0 15 75 90604530

TA = 25°C

VS = 3V

fIN = 100kHz

DIFFERENTIAL INPUT, VIN = 1.5VP-P

RBIAS = 54.9k

fLP = 300kHz

GAIN = 0dB

HD3

HD2

LOWPASS CUTOFF FREQUENCY (kHz)

DISTORTION (dBc)

6602 G06

–70

–75

–80

–85

–90 0 150 750 900600450300

TA = 25°C

VS = 3V

fIN = 100kHz

DIFFERENTIAL INPUT, VIN = 1.5VP-P

RBIAS = 54.9k

fHP = 45kHz

GAIN = 0dB

HD3

HD2

SUPPLY VOLTAGE (V)

FILTER CUTOFF FREQUENCY DEVIATION (%)

6602 G07

0.10

0.05

0.00

–0.052.7 2.8 3.5 3.63.43.33.23.13.02.9

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

–40°C

85°C

25°C

TEMPERATURE (°C)

FILTER CUTOFF FREQUENCY DEVIATION (%)

6602 G08

0.4

0.3

0.0

0.1

0.2

–0.4

–0.3

–0.2

–0.1

–40 806040200–20

VS = 3V

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

5 TYPICAL UNITS

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

6602 G09

120

110

100

201k 1M 10M100k10k

TA = 25°C

VS = 3V

VIN-CM = 0V

ΔVIN-CM = 1.25VP-P

RBIAS = 54.9k

45kHz-300kHz BPF

CMR = ΔVIN-CM /ΔVOUT-DIFF

GAIN = 30dB

GAIN = 24dB

GAIN = 0dB

GAIN = 12dB

LTC6602

6602fc

TYPICAL PERFORMANCE CHARACTERISTICS

Common Mode Rejection Ratio

OIP3 vs Average Signal

Frequency, fC

OIP3 vs Average Signal

Frequency, fC

OIP3 vs Average Signal

Frequency, fC

OIP3 vs Temperature

Common Mode Rejection

Common Mode Rejection Ratio

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

6602 G10

120

110

100

201k 1M100k10k

TA = 25°C

VS = 3V

VIN-CM = 0V

ΔVIN-CM = 1.25VP-P

RBIAS = 54.9k

15kHz-150kHz BPF

CMR = ΔVIN-CM /ΔVOUT-DIFF

GAIN = 24dB

GAIN = 30dB

GAIN = 12dB

GAIN = 0dB

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

6602 G11

120

110

100

10k 10M1M100k

TA = 25°C, VS = 3V,

VIN-CM = 0V, ΔVIN-CM = 1.25VP-P,

RBIAS = 54.9k, 90kHz-900kHz BPF

CMR = ΔVIN-CM /ΔVOUT-DIFF

GAIN = 24dB

GAIN = 0dB

GAIN = 30dB

GAIN = 12dB

FREQUENCY (Hz)

CMRR (dB)

6602 G12

120

110

100

201k 10M1M100k10k

TA = 25°C, VS = 3V,

VIN-CM = 0V, ΔVIN-CM = 1.25VP-P,

RBIAS = 54.9k, 45kHz-300kHz BPF

GAIN = 0dB

GAIN = 12dB

GAIN = 24dB

GAIN = 30dB

FREQUENCY (Hz)

CMRR (dB)

6602 G13

120

110

100

201k 1M100k10k

TA = 25°C, VS = 3V,

VIN-CM = 0V, ΔVIN-CM = 1.25VP-P,

RBIAS = 54.9k, 15kHz-150kHz BPF

GAIN = 0dB

GAIN = 30dB

GAIN = 12dB

GAIN = 24dB

FREQUENCY (Hz)

CMRR (dB)

6602 G14

120

110

100

10k 10M1M100k

TA = 25°C

VS = 3V

VIN-CM = 0V

ΔVIN-CM = 1.25VP-P

RBIAS = 54.9k

90kHz-900kHz BPF

GAIN = 30dB

GAIN = 0dB

GAIN = 12dB GAIN = 24dB

CENTER SIGNAL FREQUENCY, fC (kHz)

OIP3 (dBm)

6602 G15

38 0 50 300 350250200150100

TA = 25°C

VS = 3V

f1 = fC –5kHz, f2 = fC +5kHz

VOUT = 6dBm PER TONE FOR 2-TONE TEST

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

GAIN = 24dB

GAIN = 30dB

GAIN = 12dB

CENTER SIGNAL FREQUENCY, fC (kHz)

OIP3 (dBm)

6602 G16

38 0 20 140 160100 120806040

TA = 25°C

VS = 3V

f1 = fC –5kHz

f2 = fC +5kHz

VOUT = 6dBm PER TONE

FOR 2-TONE TEST

RBIAS = 54.9k

15kHz-150kHz BPF

GAIN = 0dB

GAIN = 30dB

GAIN = 12dB

GAIN = 24dB

CENTER SIGNAL FREQUENCY, fC (kHz)

OIP3 (dBm)

6602 G17

38 0 200100 300 9001000700 800600500400

TA = 25°C, VS = 3V

f1 = fC –10kHz, f2 = fC +10kHz

VOUT = 6dBm PER TONE

FOR 2-TONE TEST

RBIAS = 54.9k

90kHz-900kHz BPF

GAIN = 0dB

GAIN = 30dB

GAIN = 12dB

GAIN = 24dB

TEMPERATURE (°C)

OIP3 (dBm)

6602 G18

–40–30–20 100–10 20 80 9060 70504030

VS = 3V

VOUT = 6dBm PER TONE

FOR 2-TONE TEST

RBIAS = 54.9k

GAIN = 30dB fIN = 95kHz, 105kHz

15kHz-150kHz BPF

fIN = 145kHz, 155kHz

45kHz-300kHz BPF

fIN = 590kHz, 610kHz

90kHz-900kHz BPF

LTC6602

6602fc

TYPICAL PERFORMANCE CHARACTERISTICS

Output Impedance vs Frequency

Supply Current vs Supply Voltage

Supply Current vs Temperature

Clock Output Operating at 90MHz

RBIAS Pin Voltage vs IRBIAS

Input Referred Noise Density

FREQUENCY (Hz)

OUTPUT IMPEDANCE (Ω)

6602 G19

100

0.11k 1M 10M100k10k

TA = 25°C

VS = 3V

RBIAS = 54.9k

900kHz LPF

45kHz-300kHz BPF

90kHz-900kHz BPF

15kHz-150kHz BPF

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

6602 G20

110

105

100

902.7 2.8 3.5 3.63.43.33.23.13.02.9

CLKCNTL PIN FLOATING

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

85°C

25°C

–40°C

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

6602 G21

120

100

–40–30–20 100–10 20 80 9060 70504030

VS = 3V

CLKCNTL PIN FLOATING

RBIAS = 54.9k

GAIN = 0dB

15kHz-150kHz BPF

45kHz-300kHz BPF

90kHz-900kHz BPF

6602 G22

1V/DIV

2.5ns/DIV IRBIAS (µA)

RBIAS PIN VOLTAGE (V)

6602 G23

1.25

1.20

1.15

1.10 0 5 20 251510

TA = 25°C

VS = 3V

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

6602 G24

1000

100

11k 1M100k10k

TA = 25°C, VS = 3V, EXTERNAL CLOCK

RBIAS = 54.9k, 45kHz-300kHz BPF

INTEGRATED NOISE BW = 1.57MHz

GAIN = 0dB

INTEGRATED

NOISE = 186.5µVRMS

GAIN = 30dB

INTEGRATED

NOISE = 7.5µVRMS

GAIN = 24dB

INTEGRATED

NOISE = 12.6µVRMS

GAIN = 12dB

INTEGRATED NOISE

= 47.1µVRMS

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

6602 G25

1000

100

11k 1M100k10k

TA = 25°C, VS = 3V, EXTERNAL CLOCK

RBIAS = 54.9k, 15kHz-150kHz BPF

INTERNAL NOISE BW = 400kHz

GAIN = 30dB INTEGRATED NOISE = 7.2µVRMS

GAIN = 24dB

INTEGRATED NOISE = 12.5µVRMS

GAIN = 0dB INTEGRATED NOISE = 189µVRMS

GAIN = 12dB

INTEGRATED

NOISE= 47.8µVRMS

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

6602 G26

1000

100

10k 10M1M100k

TA = 25°C, VS = 3V, EXTERNAL CLOCK

RBIAS = 54.9k, 90kHz-900kHz BPF

INTERNAL NOISE BW = 2.5MHz

GAIN = 24dB

INTEGRATED

NOISE = 20.7µVRMS

GAIN = 30dB

INTEGRATED NOISE = 17.5µVRMS

GAIN = 0dB INTEGRATED NOISE = 304.2µVRMS

GAIN = 12dB INTEGRATED NOISE

= 77.6µVRMS

LTC6602

6602fc

PIN FUNCTIONS

V+IN (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This

supply must be kept free from noise and ripple. It should

be bypassed directly to a ground plane with a 0.1µF ca-

pacitor unless it is tied to V+A (Pin 2). The bypass should

be as close as possible to the IC, but is not as critical as

the bypassing of V+A and V+D (Pin16).

V+A (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This

supply must be kept free from noise and ripple. It should be

bypassed directly to a ground plane with a 0.1µF capacitor.

The bypass should be as close as possible to the IC.

VOCM (Pin 3): Output common mode voltage reference. If

ﬂoated, an internal resistive divider sets the voltage on this

pin to half the supply voltage (typically 1.5V), maximizing

the dynamic range of the ﬁlter. If this pin is ﬂoated, it must

be bypassed with a quality 0.1µF capacitor to ground.

This pin has a typical input impedance of 400Ω and may

be overdriven. Driving this pin to a voltage other than the

default value will reduce the signal range the ﬁlter can

handle before clipping.

RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input.

The value of the resistor connected between this pin and

ground determines the frequency of the master oscillator,

and sets the bias currents for the ﬁlter networks. The volt-

age on this pin is held by the LTC6602 to approximately

1.17V. For best performance, use a precision metal ﬁlm

resistor with a value between 54.9k and 200k and limit the

capacitance on this pin to less than 10pF. This resistor is

necessary even if an external clock is used.

CLKCNTL (Pin 5): Clock Control Input. This three-state

input selects the function of CLKIO (Pin 15). Tying the

CLKCNTL pin to ground allows the CLKIO pin to be driven

by an external clock (CLKIO is the master clock input).

If the CLKCNTL pin is ﬂoated, the internal oscillator is

enabled, but the master clock is not present at the CLKIO

pin (CLKIO is a no-connect). If the CLKCNTL pin is tied

to V+D (Pin 16), the internal oscillator is enabled and the

master clock is present at the CLKIO pin (CLKIO is the

master clock output). To detect a ﬂoating CLKCNTL pin,

the LTC6602 attempts to pull the pin toward mid-supply.

This is realized with two internal current sources, one tied

to V+D and CLKCNTL and the other one tied to ground

and CLKCNTL. Therefore, driving the CLKCNTL pin high

requires sourcing approximately 15µA. Likewise, driving

the CLKCNTL pin low requires sinking 15µA. When the

CLKCNTL pin is ﬂoated, preferably it should be bypassed

by a 1nF capacitor to ground or it should be surrounded

by a ground shield to prevent excessive coupling from

other PCB traces.

LPF1(CS) (Pin 6): Logic Input. When in pin programmable

control mode, this pin is the MSB of the lowpass cutoff

frequency control code; in serial control mode, this pin is

the chip select input (active low).

+INB, –INB (Pins 7, 8): Channel B differential inputs.

The input range and input resistance are described in the

Applications Information section. Input voltages which

exceed V+IN (Pin 1) should be avoided.

LPF0(SCLK) (Pin 9): Logic Input. When in pin program-

mable control mode, this pin is the LSB of the lowpass

cutoff frequency control code; in serial control mode, this

pin is the clock of the serial interface.

HPF1(SDI) (Pin 10): Logic Input. When in pin program-

mable control mode, this pin is the MSB of the highpass

cutoff frequency control code; in serial control mode, this

pin is the serial data input.

HPF0(SDO) (Pin 11): Logic Input. When in pin program-

mable control mode, this pin is the LSB of the highpass

cutoff frequency control code; in serial control mode, this

pin is the serial data output.

–OUTB, +OUTB (Pins 12, 13): Channel B differential ﬁlter

outputs. These pins can drive 1k and/or 50pF loads. For

larger capacitive loads, an external 100Ω series resistor

is recommended for each output. The common mode

voltage of the ﬁlter outputs is the same as the voltage at

VOCM (Pin 3).

GND (Pin 14): Ground. Connect to a ground plane for

best performance.

LTC6602

6602fc

PIN FUNCTIONS

CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground,

CLKIO is the master clock input. When CLKCNTL is ﬂoated,

CLKIO is pulled to ground by a weak, 5µA pulldown. When

CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock

output. When conﬁgured as a clock output, this pin can

drive 1k and/or 5pF loads. Heavier loads may cause inac-

curacies due to supply bounce at high frequencies.

V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V).

This supply must be kept free from noise and ripple. It

should be bypassed directly to a ground plane with a 0.1µF

capacitor. The bypass should be as close as possible to

the IC.

SER (Pin 17): Interface Selection Input. When tied to V+D

(Pin 16), the interface is in pin programmable control mode,

i.e. the ﬁlter gain and cutoff frequencies are programmed

by the GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0 pin

connections. When SER is tied to ground, the ﬁlter gain,

the ﬁlter cutoff frequencies and shutdown mode are pro-

grammed by the serial interface.

–OUTA, +OUTA (Pins 18, 19): Channel A differential ﬁlter

outputs. These pins can drive 1k and/or 50pF loads. For

larger capacitive loads, an external 100Ω series resistor

is recommended for each output. The common mode

voltage of the ﬁlter outputs is the same as the voltage at

VOCM (Pin 3).

MUTE (Pin 20): MUTEX input. Drive to ground to discon-

nect and mute the inputs. Float or drive to V+D (Pin 16)

for normal operation.

GAIN0(D0) (Pin 21): Logic Input. When in pin program-

mable control mode, this pin is the LSB of the gain control

code; in serial control mode, this pin is the LSB of the

serial control register, an output.

GAIN1 (Pin 22): Logic Input. When in pin programmable

control mode, this pin is the MSB of the gain control code;

in serial control mode, this pin is a no-connect.

–INA, +INA (Pins 23, 24): Channel A differential inputs.

The input range and input resistance are described in the

Applications Information section. Input voltage levels can

range from GND to the V+IN supply rail.

Exposed Pad (Pin 25): Ground. The Exposed Pad must

be soldered to PCB.

LTC6602

6602fc

Timing Diagram of the Serial Interface

BLOCK DIAGRAM

D3D3 D2 D1 D0 D7 • • • • D4

D3D3D4 D2 D1 D0 D7 • • • • D4

PREVIOUS BYTE CURRENT BYTE

SCLK

SDI

SDO

6602 TD

VDDA

GND

V+A

V+IN

RBIAS 4

VOCM 3

CLKCNTL

LPF1(CS)

6602 BD

20 19

22 21

2324

11 12

9 10

–INB

+INB HPF1(SDI)

LPF0(SCLK) HPF0(SDO) –OUTB

–INA

+INA GAIN0(D0)GAIN1 MUTE +OUTA

SER

–OUTA

CLKIO

V+D

GND

+OUTB

LPF HPF

CONTROL BIAS CLK

CONTROLBIAS CLK

BIAS/OSC CLOCK

GENERATOR

CONTROL

LOGIC

CHANNEL A

CHANNEL B

PGA

1.6k

PGA

TIMING DIAGRAM

LTC6602

6602fc

APPLICATIONS INFORMATION

Theory of Operation (Refer to Block Diagram)

The LTC6602 features two matched ﬁlter channels, each

containing gain control, lowpass, and highpass networks

that are controlled by a single control block and clocked by

a single clock generator. The gain, lowpass and highpass

sections can be independently programmed. The two

channels are not independent, i.e. if the gain is set to 24dB,

then both channels have a gain of 24dB. The ﬁlter can also

be programmed to bypass the highpass ﬁlter networks,

giving a lowpass response. The ﬁlter can be clocked with

an external clock source, or using the internal oscillator. A

resistor connected to the RBIAS pin sets the bias currents

for the ﬁlter networks and the internal oscillator frequency

(unless driven by an external clock). Altering the clock

frequency changes the ﬁlter bandwidths. This allows the

ﬁlters to be “tuned” to many different bandwidths.

Pin Programmable Interface

As shown in Figure 1, connecting SER to V+D allows the

ﬁlter to be directly controlled through the pin programmable

control lines GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0.

The HPF0(SDO) and GAIN0(D0) pins are bidirectional (in-

puts in pin programmable control mode, outputs in serial

mode). In pin programmable control mode, the voltages

at HPF0(SDO) and GAIN0(D0) cannot exceed V+D; oth-

erwise, large currents can be injected to V+D through the

internal diodes (see Figure 2). Connecting a 10k resistor

at the HPF0(SDO) and GAIN0(D0) pins (see Figure 1) is

recommended for current limiting, to less than 10mA. SER

has an internal pull-up to V+D. None of the logic inputs

have an internal pull-up or pull-down.

Figure 1. Filter in Pin Programmable Control Mode

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

HPF1(SDI)

HPF0(SDO)

GAIN1

GAIN0(D0)

GND

LTC6602

VOUT

VIN

0.1µF

LOWPASS CUTOFF = 900kHz (fCLK = 90MHz)

HIGHPASS CUTOFF = 90kHz (fCLK = 90MHz)

GAIN = 16

GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.

10k RESISTORS ON HPF0(SDO) AND GAIN0(D0)

PROTECT THE DEVICE IF VHPF0 > V+D OR

VGAIN0 > V+D

µP

–

10k

6602 F01

+OUTA

–OUTA

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

HPF1(SDI)

HPF0(SDO)

GAIN1

GAIN0(D0)

GND

VOUT

VIN

+OUTA

–OUTA

3.3V

0.1µF

3.3V

LTC6602

LPF1

LPF0

HPF1

HPF0

GAIN1

GAIN0

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 2. Bidirectional Design of

HPFO(SDO) and GAIN0(D0) Pins Figure 3. Diagram of Serial Interface (MSB First Out)

Figure 4. Two Filters in a Daisy Chain

Serial Control Register Deﬁnition

D7 D6 D5 D4 D3 D2 D1 D0

GAIN0 GAIN1 LPF0 LPF1 HPF0 HPF1 SHDN OUT

µP

6602 F04

LPF1(CS)

SCLK

SDI

SCLK

SDI

D15 D11 D10 D9 D8 D7 D3 D2 D1 D0

GAIN, BW CONTROL WORD FOR #2 GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1SHUTDOWN FOR #2

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

HPF1(SDI)

GND

LTC6602

VOUT1

VIN1

0.1µF

–

VIN2

3.3V

+OUTA

–OUTA

OUT1

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

HPF1(SDI)

GND

LTC6602

VOUT2

0.1µF

3.3V

+OUTA

–OUTA

OUT2

GAIN0(D0)

HPF0(SDO)

GAIN0(D0)

HPF0(SDO) SDO

V+D

HPF0(SDO)

6602 F02

(INTERNAL

NODE)

6-BIT GAIN, BW

CONTROL CODE

8-BIT LATCH

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

8-BIT

SHIFT-REGISTER

SDO

SCLK

DIN

6602 F03

OUT

SHUTDOWN

LTC6602

6602fc

APPLICATIONS INFORMATION

Serial Interface

Connecting SER to ground allows the ﬁlter to be controlled

through the SPI serial interface. When CS is low, the serial

data on SDI is shifted into an 8-bit shift-register on the

rising edge of the clock (SCLK), with the MSB transferred

ﬁrst (see Figure 3). Serial data on SDO is shifted out on

the clock’s falling edge. A high CS will load the 8 bits of

the shift-register into an 8-bit D-latch, which is the serial

control register. The clock is disabled internally when

CS is pulled high. Note: SCLK must be low before CS is

pulled low to avoid an extra internal clock pulse. SDO is

always active in serial mode (never tri-stated) and cannot

be “wire-or’ed” to other SPI outputs. In addition, SDO is

not forced to zero when CS is pulled high.

An LTC6602 may be daisy chained with other LTC6602s

or other devices having serial interfaces. Daisy chain-

ing is accomplished by connecting the SDO of the lead

chip to the SDI of the next chip, while SCLK and CS

remain common to all chips in the daisy chain. The se-

rial data is clocked to all the chips then the CS signal

is pulled high to update all of them simultaneously.

Figure 4 shows an example of two LTC6602s in a daisy

chained SPI conﬁguration.

GAIN1 and GAIN0 are the gain control bits (register bits

D6 and D7 when in serial mode). Their function is shown

in Table 1. In serial mode, register bit D1 can be set to

‘1’ to put the device into a low power shutdown mode.

in serial mode.

Table 1. Gain Control

GAIN 1

GAIN 0

PASSBAND GAIN

(dB)

0 0 0

0 1 12

1 0 24

1 1 30

Self-Clocking Operation

The LTC6602 features a unique internal oscillator which sets

the ﬁlter cutoff frequency using a single external resistor

connected to the RBIAS pin. The clock frequency is deter-

mined by the following simple formula (see Figure 5):

fCLK = 494.1MHz • 10k/RBIAS

Note: RBIAS ≤ 200k.

Figure 5. RBIAS vs Desired Clock Frequency

The design is optimized for V+A, V+D = 3V, fCLK = 90MHz,

where the ﬁlter cutoff frequency error is typically <3%

when a 0.1% external 54.9k resistor is used. With differ-

ent resistor values and cutoff frequency control settings

(HPF1, HPF0, LPF1 and LPF0), the highpass and lowpass

cutoff frequencies can be accurately varied from 4.1175kHz

to 90kHz and from 41.175kHz to 900kHz, respectively.

Table 2 summarizes the cutoff frequencies that can be

obtained with an external resistor (RBIAS) value of 54.9k.

Note that the cutoff frequencies scale with the clock fre-

quency. For example, if HPF1, HPF0, LPF1 and LPF0 are

all equal to zero, and RBIAS is increased from 54.9k to

200k, fCLK will decrease from 90MHz to 24.705MHz, the

lowpass cutoff frequency will be reduced from 150kHz

to 41.175kHz, and the highpass cutoff frequency will be

reduced from 15kHz to 4.1175Hz. The cutoff frequencies

that can be obtained with an external resistor value of 200k

DESIRED CLOCK FREQUENCY (MHz)

RBIAS (kΩ)

6602 F05

200

175

150

125

100

5020 80 9060 70504030

LTC6602

6602fc

APPLICATIONS INFORMATION

Gain and Group Delay vs Frequency

(45kHz to 300kHz Bandpass Response)

Gain and Group Delay vs Frequency

(15kHz to 150kHz Bandpass Response)

Gain and Group Delay vs Frequency

(90kHz to 900kHz Bandpass Response)

Gain and Group Delay vs Frequency

(900kHz Lowpass Response)

are shown in Table 3. When the LTC6602 is programmed

for the lowest lowpass cutoff frequency (LPF1, LPF0 = ‘0’),

the power is automatically reduced by about 35%.

Table 2. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 90MHz

LPF1

LPF0

LOWPASS

BW (kHz)

HPF1

HPF0

HIGHPASS

BW (kHz)

0 0 150 0 0 15

0 1 300 0 1 45

1 0 900 1 0 90

1 1 900 1 1 Bypass HPF

Table 3. Cutoff Frequency Control, RBIAS = 200k, fCLK = 24.705MHz

LPF1

LPF0

LOWPASS

BW (kHz)

HPF1

HPF0

HIGHPASS

BW (kHz)

0 0 41.175 0 0 4.1175

0 1 82.35 0 1 12.3525

1 0 247.05 1 0 24.705

1 1 247.05 1 1 Bypass HPF

The following graphs show a few of the possible combina-

tions of highpass and lowpass ﬁlters.

FREQUENCY (Hz)

GAIN (dB)

GROUP DELAY (µs)

6602 G28

–60

–50

–40

–30

–20

–10

1k 1M 10M100k10k

TA = 25°C

VS = 3V

EXTERNAL

CLOCK

RBIAS = 54.9k

GAIN = 30dB

GROUP

DELAY

GAIN = 24dB

GAIN = 0dB

GAIN = 12dB

FREQUENCY (Hz)

GAIN (dB)

GROUP DELAY (µs)

6602 G29

–60

–50

–40

–30

–20

–10

1k 1M100k10k

TA = 25°C

VS = 3V

EXTERNAL

CLOCK

RBIAS = 54.9k

GAIN = 30dB

GROUP

DELAY

GAIN = 24dB

GAIN = 0dB

GAIN = 12dB

FREQUENCY (Hz)

GAIN (dB)

GROUP DELAY (µs)

6602 G30

–60

–50

–40

–30

–20

–10

10k 10M1M100k

TA = 25°C

VS = 3V

EXTERNAL

CLOCK

RBIAS = 54.9k

GAIN = 30dB

GAIN = 24dB

GAIN = 12dB

GAIN = 0dB

GROUP

DELAY

FREQUENCY (Hz)

GAIN (dB)

GROUP DELAY (µs)

6602 G28

–60

–50

–40

–30

–20

–10

1.0

0.7

0.8

0.9

0.6

0.0

0.1

0.2

0.3

0.4

0.5

1k 1M 10M100k10k

TA = 25°C

VS = 3V

EXTERNAL CLOCK

RBIAS = 54.9k

GAIN = 30dB

GROUP DELAY

GAIN = 24dB

GAIN = 0dB

GAIN = 12dB

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 6. Current Controlled Clock Frequency Figure 7. Voltage Controlled Clock Frequency

RBIAS

6602 F06

ICONTROL

fCLK = 10k • (494.1MHz/1.17V) • ICONTROL(A)

RBIAS

6602 F07

VCONTROL

fCLK = 494.1MHz • (10k/RBIAS) • (1 – VCONTROL/1.17V)

RBIAS

–

Preserving Oscillator Accuracy

The oscillator is sensitive to transients on the positive

supply. The IC should be soldered to the PC board and

the PCB layout should include a 0.1µF ceramic capacitor

between V+A (Pin 2) and ground, as close as possible to

the IC to minimize inductance. The PCB layout should also

include an additional 0.1µF ceramic capacitor between

V+D (Pin 16) and ground. Avoid parasitic capacitance on

RBIAS (Pin 4) and avoid routing noisy signals near RBIAS.

Use a ground plane connected to Pin 14 and the Exposed

Pad (Pin 25).

Alternative Methods of Setting the Clock Frequency of

the LTC6602

The oscillator may be programmed by any method that

sinks a current out of the RBIAS pin. The circuit in Figure 6

sets the clock frequency by using a programmable current

source and in the expression for fCLK, the resistor RBIAS

is replaced by the ratio of 1.17V/ICONTROL. Because the

voltage of the RBIAS pin is approximately 1.17V ±5%, the

Figure 6 circuit is less accurate than if a resistor controls

the clock frequency.

Figure 7 shows the LTC6602’s oscillator conﬁgured as

a VCO. A voltage source is connected in series with the

RBIAS resistor. The clock frequency, fCLK, will vary with

VCONTROL. Again, this circuit decouples the relationship

between the current out of the RBIAS pin and the voltage

of the RBIAS pin; the frequency accuracy will be degraded.

The clock frequency, however, will increase monotonically

with decreasing VCONTROL.

Operation Using an External Clock

The LTC6602 may be clocked by an external oscillator

for tighter bandwidth control by pulling CLKCNTL (Pin 5)

to ground and driving a clock into CLKIO (Pin 15). If an

external clock is used, the RBIAS resistor is still necessary.

The value of RBIAS must be no larger than the value that

would be required for using the internal oscillator. For

example, a 100k resistor would program the internal oscil-

lator for 49.41MHz, so an external oscillator frequency of

49.41MHz would require an RBIAS resistance of no more

than 100k. If the value of RBIAS is too large, the ﬁlters will

not receive a large enough bias current, possibly causing

errors due to insufﬁcient settling.

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 8. Distortion vs Common Mode Input Voltage (3V) Figure 9. Distortion vs Common Mode Input Voltage (5V)

Input Common Mode and Differential Voltage Range

The input signal range extends from zero to the V+IN sup-

ply voltage. This input supply can be tied to V+A and V+D,

or driven up to 5.5V for increased input common mode

voltage range. Figures 8 and 9 show the distortion of the

ﬁlter versus common mode input voltage with a 1.5VP-P

differential input signal.

For best performance, the inputs should be driven dif-

ferentially. For single ended signals, connect the unused

input to VOCM (Pin 3) or to a quiet DC reference voltage.

To achieve the best distortion performance, the input

signal should be centered around the DC voltage of the

unused input.

Refer to the Typical Performance Characteristics section

to estimate the distortion for a given input level.

Dynamic Input Impedance

The unique input sampling structure of the LTC6602 has a

dynamic input impedance which depends on the conﬁgura-

tion and the clock frequency. This dynamic input impedance

has both a differential component and a common mode

component. The common mode input impedance is a

function of the clock frequency and the control bit LPF1.

The differential input impedance is a function of the clock

frequency and the control bits LPF1, GAIN1 and GAIN0.

Table 4 shows the typical input impedances for a clock

frequency of 90MHz. These input impedances are all pro-

portional to 1/fCLK, so if the clock frequency were reduced

by half to 45MHz, the impedances would be doubled. The

typical part to part variation in dynamic input impedance

for a given clock frequency is –20% to +35%.

Table 4. Differential, Common Mode Input Impedances,

fCLK = 90MHz

GAIN1

GAIN0

LPF1

DIFFERENTIAL INPUT

IMPEDANCE (kΩ)

COMMON MODE INPUT

IMPEDANCE (kΩ)

0 0 0 16 20

0 0 1 6 6.7

0 1 0 8 20

0 1 1 2.8 6.7

1 0 0 2.6 20

1 0 1 1.8 6.7

1 1 0 2.4 20

1 1 1 1.3 6.7

Output Common Mode and Differential Voltage Range

The output voltage is a fully differential signal with a

common mode level equal to the voltage at VOCM. Any of

the ﬁlter outputs may be used as single-ended outputs,

although this will degrade the performance. The output

voltage range is typically 0.5V to V+A – 0.5V (V+A = 2.7V

to 3.6V).

The common mode output voltage can be adjusted by

overdriving the voltage present on VOCM. To maximize

the undistorted peak-to-peak signal swing of the ﬁlter,

the VOCM voltage should be set to V+A/2. Note that the

COMMON MODE INPUT VOLTAGE (V)

DISTORTION (dBc)

6602 F08

–70

–75

–80

–85

–90 0 2.5 3.01.5 2.01.00.5

TA = 25°C

fIN = 100kHz

DIFFERENTIAL INPUT, VIN = 1.5VP-P

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

HD3

HD2

COMMON MODE INPUT VOLTAGE (V)

DISTORTION (dBc)

6602 F09

–70

–75

–80

–85

–90 0 3 4 521

TA = 25°C

fIN = 100kHz

DIFFERENTIAL INPUT, VIN = 1.5VP-P

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

HD3

HD2

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 10. Distortion vs Common Mode Output Voltage

output common mode voltages of the two channels are

not independent as they are both set by the VOCM pin.

Figure 10 illustrates the distortion versus output common

mode voltage for a 1.5VP-P differential input voltage and a

common mode input voltage that is equal to mid-supply.

Interfacing to the LTC6602

The input and output common mode voltages of the

LTC6602 are independent. The input common mode volt-

age is set by the signal source if DC coupled, as shown in

Figure 11. If the inputs are AC coupled, the input com-

mon mode voltage will pulled to ground by an equivalent

resistance of RCM, shown in Table 4. This does not affect

the ﬁlter’s performance as long as the input amplitude

is less than 0.5VP-P . At low ﬁlter gain settings, a larger

input voltage swing may be desired. Figure 12 shows two

circuits with AC coupled inputs. In a ﬁxed lowpass cutoff

frequency, connecting resistors between each input and

V+IN will pull the input common mode voltage up, increas-

ing the input signal swing (Figure 12a). The resistance,

RPULL-UP , necessary to set the input common mode

voltage, VICM, to any desired level can be calculated by

RPULL −UP =RCM

VSUPPLY

ICM

−1











where

RCM = 20k • 90MHz/fCLK for LPFI = 0

RCM = 6.7k • 90MHz/fCLK for LPFI = 1

For example, if the lowpass cutoff frequency is set to

300kHz, 20k resistors connected between each input

and V+IN will set the input common mode voltage to

mid-supply.

Figure 11. DC Coupled Inputs

Figure 12. AC Coupled Inputs

COMMON MODE OUTPUT VOLTAGE (V)

DISTORTION (dBc)

6602 F10

–20

–60

–50

–40

–30

–70

–80

–900.5 2.51.5 2.01.0

TA = 25°C

fIN = 100kHz

VIN = 1.5VP-P

RBIAS = 54.9k

45kHz-300kHz BPF

GAIN = 0dB

HD3

HD2

V+IN

V+A

V+D

+INA

–INA

VOCM

GND

LTC6602

0.1µF

DC COUPLED INPUT

VIN (COMMON MODE) = (VIN+ + VIN–)/2

VOUT (COMMON MODE) = (VOUT+ + VOUT–)/2 = VSUPPLY/2

6602 F11

+OUTA

–OUTA

VSUPPLY

–

–1µF

VOUT+

VOUT–

VIN+VIN–

AC COUPLED INPUT

VIN (COMMON MODE) = VSUPPLY/2

6602 F12a

VSUPPLY

–

–0.1µF

0.1µF

RPULL-UP RPULL-UP

V+IN

V+A

V+D

+INA

–INA

VOCM

GND

LTC6602

0.1µF

–OUTA

–OUTB

VSUPPLY

1µF

VIN+VIN–

(a) Fixed Lowpass Cutoff Frequency

6602 F12b

AC COUPLED INPUT COMMON MODE AT +INA AND –INA

VSUPPLY

–

–0.1µF

0.1µF

1.87k 1.87k1.87k

1.87k

V+IN

V+A

V+D

+INA

–INA

VOCM

GND

LTC6602

0.1µF

–OUTA

–OUTB

VSUPPLY

1µF

VIN+VIN–

RCM • VSUPPLY

2 • RCM + 1.87k

= =

1.87k

(b) Variable Lowpass Cutoff Frequency

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 13. Two Filters in a Master/Slave Conﬁguration

If the lowpass cutoff frequency varies then the Figure 12b

circuit must be used.

The output common mode voltage is equal to the voltage

of the VOCM pin. The VOCM pin is biased to one half of the

supply voltage by an internal resistive divider (see Block

Diagram). To alter the common mode output voltage, VOCM

can be driven with an external voltage source or resistor

network. If external resistors are used, it is important to

note that the internal 1.6k resistors can vary ±30% (their

ratio varies only ±1%). The ﬁlter outputs can also be AC

coupled.

The LTC6602 can be interfaced to an A/D converter by pull-

ing CLKCNTL (Pin 5) to V+D. This conﬁgures CLKIO (Pin 15)

as a clock output, which can be used to drive the clock

input of the A/D converter. This allows the A/D converter

to be synchronized with the ﬁlter sampling clock, avoiding

“beat frequencies” and simplifying the board layout. Any

routing attached to the CLKIO pin should be as short as

possible, in order to minimize ringing.

Similarly, two LTC6602s can be connected in a master/

slave conﬁguration as shown in Figure 13. This results

in four matched ﬁlter channels, all synchronized to the

same clock. The master has its CLKCNTL pin pulled to

V+D, conﬁguring its CLKIO pin as an output, while the

slave has its CLKCNTL pin pulled to ground, conﬁguring

its CLKIO pin as an input.

Output Drive

The ﬁlter outputs can drive 1k and/or 50pF loads connected

to AC ground with a 0.5V to 2.5V signal (corresponding

to a 4VP-P differential signal). For differential loads (loads

connected between +OUTA and –OUTA or +OUTB and

–OUTB) the outputs can produce a 4VP-P signal across 2k

and/or 25pF. For smaller signal amplitudes, the outputs can

drive correspondingly heavier loads. For larger capacitive

loads, an external 50Ω series resistor is recommended

for each output.

V+IN

V+A

V+D

+INA

–INA

CLKCNTL

CLKIO

GND

LTC6602

MASTER

VOUT1

VIN1

0.1µF

–

6602 F13

+OUTA

–OUTA

RBIAS

3.3V

LTC6602

SLAVE

VOUT2

VIN2

0.1µF

+OUTA

–OUTA

3.3V

V+IN

V+A

V+D

+INA

–INA

CLKCNTL

CLKIO

GND

RBIAS

LTC6602

6602fc

Figure 14. Mute Function Recovery Time

APPLICATIONS INFORMATION

Mute Function

The LTC6602 features a mute function which is asserted

by pulling MUTE (Pin 20) to ground. This breaks the signal

path that leads from the input pins to the ﬁlter networks,

attenuating the input signal by at least 20dB. The mute

function can be used to protect the ﬁlter inputs from large

transients. The ﬁlter clock continues to run when the ﬁlter

is muted, allowing for a fast recovery time when MUTE

is deasserted. Typically, the recovery time is less than

5µs, as shown in Figure 14. When the mute function is

asserted, the differential input impedance becomes very

high, but the common mode input impedance to ground

remains the same. This keeps the input common mode

voltage stable when muted, even when the inputs are

AC coupled. Connecting GAIN0(D0) to MUTE allows for

serial control of the mute function. MUTE has an internal

pull-up to V+D.

A ground plane should be used. Noisy signals should be

isolated from the ﬁlter input pins.

The output DC offset typically changes less than ±2mV when

the clock frequency varies from 24.705MHz to 90MHz. The

offset is measured by connecting the inputs to VOCM and

measuring the differential voltage at the ﬁlter’s output.

Aliasing

Aliasing is an inherent phenomenon of sampled data ﬁlters.

Signiﬁcant aliasing only occurs when the frequency of the

input signal approaches the sampling frequency or mul-

tiples of the sampling frequency. The ratio of the LTC6602

input sampling frequency to the clock frequency, fCLK, is

determined by the state of control bit LPF1. If LPF1 is set

to ‘0’, the input sampling frequency is equal to fCLK/3. If

LPF1 is set to ‘1’, the input sampling frequency is equal to

fCLK. Input signals with frequencies near the input sampling

frequency will be aliased to the passband of the ﬁlter and

appear at the output unattenuated.

A simple LC anti-aliasing ﬁlter is recommended at the ﬁlter

inputs to attenuate frequencies near the input sampling

frequency that will be aliased to the passband. For example,

if the clock frequency is set to 90MHz and the lowpass

cutoff frequency of the ﬁlter is set to it’s maximum (LPF1

= ‘1’), the lowest frequency that would be aliased to the

passband would be fCLK – fCUTOFF , i.e. 90MHz – 900kHz =

89.1MHz. In order to attenuate this frequency by 40dB, an

LC ﬁlter with a cutoff frequency of 8.91MHz or lower would

be required at the ﬁlter inputs. The capacitor connected

between the LTC6602 ﬁlter inputs should be at least 150pF

to provide sufﬁcient charge to the input sampler. If there

is no anti-aliasing ﬁlter, the LTC6602 ﬁlter inputs should

be driven by a low impedance source (<100Ω).

Wideband Noise

The wideband noise of the ﬁlter is the RMS value of the

device’s output noise spectral density. The wideband noise

voltage is used to determine the operating signal-to-noise

ratio at a given distortion level. The wideband noise is

nearly independent of the value of the clock frequency

and excludes the clock feedthrough. Most of the wideband

noise is concentrated in the ﬁlter passband and cannot be

removed with post ﬁltering.

6602 F14

MUTE (2V/DIV)

VOUT (1V/DIV)

4µs/DIV

Clock Feedthrough

Clock feedthrough is deﬁned as the RMS value of the clock

frequency and its harmonics that are present at the ﬁlter’s

output. The clock feedthrough is measured with +INA and

–INA (or +INB, –INB) tied to VOCM and depends on the PC

board layout and the power supply decoupling. The clock

feedthrough can be reduced with a simple RC post ﬁlter.

DC Offset

The output DC offset of the LTC6602 is less than ±15mV.

To obtain optimum DC offset performance, appropriate

PC board layout techniques should be used. The ﬁlter

IC should be soldered to the PC board. The power sup-

plies should be well decoupled including 0.1µF ceramic

capacitors from V+D (Pin 16) and V+A (Pin 2) to ground.

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 15. fCLK vs Filter Cutoff Frequencies Figure 16. Supply Current vs Lowpass Cutoff Frequency

Table 5. Total Input Referred Integrated Noise Voltage (Passband Gain = 30dB)

LPF1 LPF0 HPF1 HPF0 Noise Voltage

0 0 0 0 –90dBm

0 1 0 1 –89dBm

1 X 1 0 –82dBm

Power Supply Current

The power supply current depends on the state of the

lowpass cutoff frequency controls (LPF1, LPF0) and the

value of RBIAS. When the LTC6602 is programmed for the

lowest lowpass cutoff frequency (LPF1 = LPF0 = ‘0’), the

supply current is reduced by about 35% relative to the

supply current for the higher bandwidth settings. Power

supply current vs. cutoff frequency for various bandwidth

settings is shown in the Typical Performance Characteris-

tics section. The LTC6602 can be programmed through the

serial interface to enter into a low power shutdown mode

as described in the Serial Interface section. The power

supply current during shutdown is less than 235µA.

Supply Current Versus Noise Tradeoff

The passband of the LTC6602 is determined by the master

clock frequency (which is set by RBIAS when the internal

oscillator is used), HPF1, HPF0, LPF1 and LPF0. The

LTC6602 is optimized for use with RBIAS having a value

between 200k and 54.9k to set the internal oscillation

frequency from 24.705MHz to 90MHz. Both lowpass

and highpass corner frequencies are proportional to the

clock frequency (internal or external). To extend the ﬁlter’s

operational frequency range, the master clock is divided

down before reaching the ﬁlter. LPF1 and LPF0 set the divi-

sion ratio of the lowpass clock while HPF1 and HPF0 set

the division ratio of the highpass clock. Figure 15 shows

the possible cutoff frequencies versus fCLK, HPF1, HPF0,

LPF1 and LPF0. Overlapping frequency ranges allow more

than one possible choice of bandwidth settings for some

cutoff frequencies. Figure 16 shows supply current as a

function of the lowpass cutoff frequency, LPF1 and LPF0.

Note that the higher bandwidth setting always gives the

minimum supply current for a given cutoff frequency. The

total integrated noise voltage for a passband gain of 30dB

is shown in Table 5. Note that the noise is higher for the

higher bandwidth settings. This creates a tradeoff between

supply current and noise. For a given cutoff frequency,

using the highest possible bandwidth setting gives the

minimum supply current at the expense of higher noise.

FILTER CUTOFF FREQUENCY (Hz)

fCLK (MHz)

6602 F15

100

101k 100k 1M10k

HPF1 = 0

HPF0 = 0 HPF1 = 0

HPF0 = 1

HPF1 = 1

HPF0 = 0 LPF1 = 0

LPF0 = 0

LPF1 = 0

LPF0 = 1

LPF1 = 1

LOWPASS CUTOFF FREQUENCY (Hz)

SUPPLY CURRENT (mA)

6602 F16

120

100

10k 100k 1M

TA = 25°C

VS = 3V

CLKCNTL PIN FLOATING

HPF1 = 0

HPF0 = 1

GAIN = 0dB

LPF1 = 0

LPF0 = 1

LPF1 = 0

LPF0 = 0

LPF1 = 1

LTC6602

6602fc

APPLICATIONS INFORMATION

The LTC6602, an Adaptable Baseband Filter for an

RFID Reader

A radio-frequency identiﬁcation (RFID) system is an auto-id

technology that identiﬁes any object that contains a coded

tag. An RFID system consists of a reader (or interrogator)

and a tag. An RFID system capable of identifying multiple

tags at a maximum operating distance operates in the

UHF frequency range. A UHF reader transmits informa-

tion to a tag by modulating an RF signal in the 860MHz

to 960MHz frequency range. Typically a tag is passive,

meaning that it receives all of its operating energy from a

reader that transmits a continuous wave (CW) RF signal

to power a tag. A tag responds by modulating the reﬂec-

tion coefﬁcient of its antenna, thereby backscattering an

information signal to the reader. Reliable detection of a

tag signal requires communication protocols that deﬁne

the physical and operating interaction between readers

and tags. The latest UHF RFID protocol, the Electronic

Product Code™ (EPC) global class-1 generation 2 standard

(C1G2), have been accepted worldwide and is also known

as ISO 18000-6C. The C1G2 standard deﬁnes a reader to

tag and a tag to reader communication using a ﬂexible

set of signal modulation, data encoding, data rates and

command procedures. C1G2 speciﬁes reader and tag data

symbols using pulse-interval encoding. Tag signal detec-

tion requires measuring the time interval between signal

transitions (a data “1” symbol has a longer interval than

a data “0” symbol). The reader initiates a tag inventory by

sending a signal that instructs a tag to set its backscatter

data rate and encoding. C1G2 certiﬁed RFID readers can

operate in an RF environment where many readers are in

close proximity. The three operating modes of C1G2, single

interrogator, multiple interrogator and dense interrogator,

deﬁne the spectral limits of reader and tag signals for an

optimum balance of reliable multitag detection and high

data throughput (for more information on C1G2, consult

the references at the end of this design note). The advan-

tages of C1G2 complex protocols can be realized by using

a reader whose receiver contains a high linearity direct

conversion I and Q demodulator, a low noise ampliﬁer, a

dual baseband ﬁlter with variable gain and bandwidth and

a dual analog to digital converter (ADC).

Certiﬁed C1G2 UHF RFID readers can adapt to a great

variety of operating conditions. To achieve operating

ﬂexibility a reader’s baseband circuits must include an

adaptable bandwidth ﬁlter. Figure 17 shows an LTC6602

based ﬁlter circuit that uses SPI control to vary the ﬁlter’s

bandwidth to adjust for the C1G2 complex set of data rates,

encoding and modulation. The ﬁlter’s clock frequency is

set by the SPI control of 8-bit LTC2630 DAC (digital to

analog converter). The DAC voltage through a resistive

divider sets the current into the LTC6602 RBIAS pin. The

resistive divider sets the clock frequency range for a DAC

voltage range 0V to 3V. For the resistor values in Figure 17

(191k and 61.9k) the clock frequency range is 40MHz to

100MHz (234.4kHz per bit). The lowpass and highpass

division ratio is set by the SPI control of the LTC6602. The

cutoff range for the highpass ﬁlter is 6.7kHz to 100kHz and

for the lowpass ﬁlter is 66.7kHz to 1MHz. The optimum

ﬁlter bandwidth setting can be adjusted by a software

algorithm and is a function of the reader’s data clock, data

rate, encoding and modulation. The ﬁlter bandwidth must

be sufﬁciently narrow to maximize the dynamic range to

the ADC input and wide enough to preserve signal transi-

tions and pulse width. If the ﬁlter setting is optimum then

a DSP algorithm can reliably detect tag data. Figure 18a

shows the ﬁlter’s time response to a typical tag symbol

sequence (a “short” pulse interval followed by a “long”

pulse interval). The lowpass cutoff frequency is set equal

to the reciprocal of the shortest interval (fCUTOFF = 1/10µs

= 100kHz). If the lowpass cutoff frequency is lower the

signal transition and time interval will be distorted beyond

recognition by any tag signal detection algorithm. The set-

ting of the highpass cutoff frequency is more qualitative

than speciﬁc. The highpass cutoff frequency must be lower

than the reciprocal of the longest interval (for Figure 18

example, highpass fCUTOFF < 1/20µs < 50kHz) and as

high as possible to decrease the receiver’s low frequency

noise (baseband ampliﬁer and down-converted phase and

amplitude noise). Figures 18a and 18b show the ﬁlter’s

total response (lowpass plus highpass ﬁlter). The ﬁlter’s

output is shown with 30kHz and a 10kHz highpass cutoff

frequency setting. Comparing the ﬁlter outputs with a

10kHz and a 30kHz highpass setting, the signal transitions

and time intervals of the 10kHz output are adequate for

LTC6602

6602fc

APPLICATIONS INFORMATION

Figure 18. Filter Transient Response to a Tag Symbol Sequence

detecting the symbol sequence (in an RFID environment,

noise will be superimposed on the output signal). In

general, increasing the lowpass fCUTOFF and/or decreasing

Figure 17. An Adaptable RFID Baseband Filter with SPI Control

6602 F17

LTC6602

V+IN

+INA

–INA

+INB

–INB

RBIAS

VOCM

MUTE

GAIN0(D0)

GAIN1

GND

–OUTA

+OUTA

–OUTB

+OUTB

CLKIO

SER

CLKCNTL

HPFO(SDO)

HPFI(SDI)

LPFO(SCLK)

LPF1(CS)

V+AV+D

68.1k

0.1µF 0.1µF

5V 3V

1 2 16

24 18

CS1 CS2SCK SDI

SPI CONTROL OF LTC6602

SETS THE FILTER GAIN AND THE

LOWPASS AND HIGHPASS

DIVISION RATIO

0.1µF

174k

SCLK

SDI

VOUT

GND

V+

I CHANNEL INPUT

Q CHANNEL INPUT I CHANNEL OUTPUT

Q CHANNEL OUTPUT

SPI CONTROL OF DAC

SETS THE LTC6602

CLOCK FREQUENCY

40MHz TO 100MHz

TRANSMITTER MUTE INPUT

ADC VCOM INPUT

LTC2630

8-BIT DAC

DAC VOUT

RANGE 0V TO 2.5V

(USING THE LTC2630

INTERNAL REFERENCE)

0.1µF

the highpass fCUTOFF “enhances” signal transitions and

intervals and increases ﬁlter output noise.

(µs)

(a)

6602 F19a

0 10 20 30 40 50 60 70 80 90 100110120

TYPICAL TAG

SYMBOL

SEQUENCE

100kHZ

LOWPASS

LOWPASS ONLY FILTER

6602 F19b

(µs)

(b)

0 10 20 30 40 50 60 70 80 90 100110120

100kHz LOWPASS + 30kHz HIGHPASS FILTER

6602 F19c

(µs)

(c)

0 10 20 30 40 50 60 70 80 90 100110120

100kHz LOWPASS + 10kHz HIGHPASS FILTER

LTC6602

6602fc

TYPICAL APPLICATIONS

Switching the RBIAS Resistor

6602 TA02

LTC6602

V+IN

+INA

–INA

+INB

–INB

RBIAS

VOCM

MUTE

GAIN0(D0)

GAIN1

GND

–OUTA

+OUTA

–OUTB

+OUTB

CLKIO

SER

CLKCNTL

HPF0(SDO)

HPF1(SDI)

LPF0(SCLK)

LPF1(CS)

V+AV+D

0.1µF

1 2 16

24 18

VOCM

MUTE

HPF0HPF1LPF0LPF1

DIODES INC

DMN2004DMK

0.1µF

R2 R1R3

SOT-363

GAIN0GAIN1CLK0CLK1

CLK1 CLK0

0 0 RBIAS1 fCLK1

0 1 RBIAS2 fCLK2

1 0 RBIAS3 fCLK3

1 1 RBIAS4 fCLK4

RBIAS1 > RBIAS2 OR RBIAS3

DESIGN PROCEDURE

1. CHOOSE fCLK1, fCLK2 AND fCLK3

2. CALCULALTE RBIAS1, RBIAS2 AND RBIAS3

3. CALCULATE R2, R3 AND RBIAS4

RBIAS1 IN k

fCLK IN MHz

RBIAS = 4941

fCLK

R1 = RBIAS1 R2 = RBIAS1 • RBIAS2

RBIAS1 – RBIAS2

R3 = RBIAS1 • RBIAS3

RBIAS1 – RBIAS3

RBIAS4 = R1 • R2 • R3

R1 • (R2 + R3) + R2 • R3

LTC6602

V+IN

+INA

–INA

+INB

–INB

RBIAS

VOCM

MUTE

GAIN0(D0)

GAIN1

GND

–OUTA

+OUTA

–OUTB

+OUTB

CLKIO

SER

CLKCNTL

HPF0(SDO)

HPF1(SDI)

LPF0(SCLK)

LPF1(CS)

V+AV+D

0.1µF

1 2 16

24 18

VOCM

MUTE

SDOSCLK SDI CS2CS1

LTC2630

8-BIT DAC

0.1µF

R2 = 1.056 • 1013

fCLKHI – fCLKLO

R1 = 1.056 • 1013

1.137 • fCLKHI + fCLKLO

VOUT

GND

V+

SCLK

SDI

0.1µF

DAC VOUT LTC6602 fCLK

0V fCLKHI

2.5V fCLKLO

DAC VOUT RANGE, 0V TO 2.5V

(USING LTC2630 INTERNAL REFERENCE)

PARALLEL CONTROL

SERIAL CONTROL

LTC6602

6602fc

PACKAGE DESCRIPTION

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

4.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.45 ± 0.05

(4 SIDES)

3.10 ± 0.05

4.50 ± 0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

LTC6602

6602fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

C 10/10 Updated Filter Phase Either Channel Min value for fIN = 125kHz to –143 in Electrical Characteristics section

Updated all Max values for Supply Current in Electrical Characteristics section

(Revision history begins at Rev C)

LTC6602

6602fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2008

LT 1010 REV C • PRINTED IN USA

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6602 TA03

LTC6602

V+IN

+INA

–INA

+INB

–INB

RBIAS

VOCM

MUTE

GAIN0(D0)

GAIN1

GND

–OUTA

+OUTA

–OUTB

+OUTB

CLKIO

SER

CLKCNTL

HPF0(SDO)

HPF1(SDI)

LPF0(SCLK)

LPF1(CS)

V+AV+D

38.3k

0.1µF 0.1µF

5V 3V

1 2 16

24 18

CS SCLK SDI

SPI CONTROL INPUT

0.1µF

CLOCK

INPUT

VCC

GND

GND GNDLO VCC

GND GND

LT5575

270pF

10pF

270nH*

10pF

121110917

4 3 2 1

4.7pF

RF IN

4.7pF

LO IN

1µF 0.1µF 1000pF

1000pF

*COILCRAFT 0603HP-R27X

MUTE INPUT FROM TRANSMITTER

VOCM INPUT FROM ADC

I OUTPUT

Q OUTPUT

I INPUT

Q INPUT