Hot Swap Controller and
Digital Power Monitor with ALERTB Output
Data Sheet
ADM1178
Rev. D
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FEATURES
Allows safe board insertion and removal from a live
backplane
Controls supply voltages from 3.15 V to 16.5 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
Charge-pumped gate drive for external N-channel FET
Adjustable analog current limit with circuit breaker
±3% accurate hot swap current limit level
Fast response limits peak fault current
Automatic retry or latch-off on current fault
Programmable hot swap timing via TIMER pin
Active high ON pin
ALERTB output for overcurrent interrupt
I2C fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
APPLICATIONS
Power monitoring/power budgeting
Central office equipment
Telecommunications and data communications equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1178 is an integrated hot swap controller and current
sense amplifier that offers digital current and voltage monitoring
via an on-chip 12-bit analog-to-digital converter (ADC),
communicated through an I2C® interface.
An internal current sense amplifier measures voltage across the
sense resistor in the power path via the VCC pin and the SENSE pin.
The ADM1178 limits the current through this resistor by control-
ling the gate voltage (via the GATE pin) of an external N-channel
FET in the power path. The voltage across the sense resistor (and
therefore the inrush current) is kept below a preset maximum.
The ADM1178 protects the external FET by limiting the time that
the maximum current runs through it. This current limit period
is set by the value of the capacitor attached to the TIMER pin.
Additionally, the device provides protection from overcurrent
events that may occur after the hot swap event is complete. In
case of a short-circuit event, the current in the sense resistor
exceeds an overcurrent trip threshold, and the FET is switched
off immediately by pulling down the GATE pin.
FUNCTIONAL BLOCK DIAGRAM
V
I
0
1
ADM1178
SENSE
ON
VCC
1.3V
MUX
I
2
C
12-BIT
ADC
FET DRIVE
CONTROLLER
GND
CURRENT
SENSE
AMPLIFIER
UNDERVOLTAGE
COMPARATOR
A
SDA
SCL
ADR
ALERTB
GATE
TIMER
ALERT
06048-001
Figure 1.
R
SENSE
N-CHANNEL FE T
P = VI
CONTROLLER
ADM1178
SENSEVCC
SDA
SCL SDA
SCL
GND
GATE
INTERRUPT
ALERTB
ADR
TIMER
3.15V TO 16.5V
ON
06048-002
Figure 2. Applications Diagram
A 12-bit ADC can measure the current seen in the sense
resistor, as well as the supply voltage on the VCC pin. An alert
output can be set to trigger when the ADC current reading
exceeds a programmed overcurrent limit threshold.
An industry-standard I2C interface allows a controller to read
current and voltage data from the ADC. Measurements can be
initiated by an I2C command. Alternatively, the ADC can run
continuously, and the user can read the latest conversion data
whenever it is required. Up to four unique I2C addresses can be
created, depending on how the ADR pin is connected.
The ADM1178 is packaged in a 10-lead MSOP.
ADM1178 Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Overview of the Hot Swap Function ............................................ 12
Undervoltage Lockout ............................................................... 12
ON Function ............................................................................... 12
TIMER Function ........................................................................ 12
GATE and TIMER Functions During a Hot Swap Operation
....................................................................................................... 13
Calculating Current Limits and Fault Current Limit Time .. 13
Initial Timing Cycle ................................................................... 13
Hot Swap Retry Cycle on the ADM1178-1 ............................. 14
Voltage and Current Readback ..................................................... 15
Serial Bus Interface..................................................................... 15
Identifying the ADM1178 on the I2C Bus ............................... 15
General I2C Timing .................................................................... 15
Write and Read Operations ........................................................... 17
Quick Command ........................................................................ 17
Write Command Byte ................................................................ 17
Write Extended Command Byte .............................................. 18
Read Voltage and/or Current Data Bytes ................................ 19
Applications Information .............................................................. 21
Applications Waveforms ............................................................ 21
ALERTB Output ......................................................................... 22
Kelvin Sense Resistor Connection ........................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
6/12—Rev. C to Rev. D
Changes to Low Level Input Voltage, VIL Parameter, Test
Conditions/Comments Column, Table 1 and High Level Input
Voltage, VIH Parameter, Test Conditions/Comments Column,
Table 1 ................................................................................................ 3
Changes to ALERTB Output Section and Kelvin Sense Resistor
Connection Section ........................................................................ 22
Deleted Figure 50; Renumbered Sequentially............................. 23
Updated Outline Dimensions ....................................................... 23
5/09—Rev. B to Rev. C
Changes to Figure 1 .......................................................................... 1
2/08—Rev. A to Rev. B
Changed VVCC to VCC Throughout ................................................. 3
Changes to Input Current for 11 Decode, IADRHIGH, Parameter ... 3
Changes to Input Current for 00 Decode, IADRLOW, Parameter ... 3
Added ADC Conversion Time Parameter .................................... 5
Added Fast Overcurrent Response Time Parameter ................... 5
Added Endnote 2 and Endnote 3 ................................................... 5
Changes to Figure 14 ........................................................................ 9
Changes to Figure 15 Caption ......................................................... 9
Changes to Figure 24 ...................................................................... 11
Changes to TIMER Function Section .......................................... 13
Changes to General I2C Timing Section, Step 3 ......................... 16
Changes to Table 5 .......................................................................... 16
Changes to Quick Command Section ......................................... 18
Changes to Figure 38 ...................................................................... 18
Changes to Table 7 .......................................................................... 18
Changes to Write Extended Command Byte Section ................ 19
Changes to Figure 40 ...................................................................... 19
Changes to Table 9 and Table 11 .................................................. 19
Changes to Converting ADC Codes to Voltage and
Current Readings Section .............................................................. 20
4/07—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 3
Changes to GATE and TIMER Functions During
a Hot Swap Section ......................................................................... 14
Changes to Calculating Current Limits and
Fault Current Limit Time Section ................................................ 14
Changes to Initial Timing Cycle Section ..................................... 15
Changes to Table 5 .......................................................................... 16
Changes to Figure 35 and Figure 36 ............................................ 17
Changes to Figure 40 ...................................................................... 19
Changes to Figure 42 and Figure 43 ............................................ 20
Added Applications Information Heading ................................. 22
9/06—Revision 0: Initial Version
Data Sheet ADM1178
Rev. D | Page 3 of 24
SPECIFICATIONS
VCC = 3.15 V to 16.5 V, TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter Min
Typ
Max
Unit
Test Conditions/Comments
VCC PIN
Operating Voltage Range, VCC 3.15
16.5
V
Supply Current, ICC 1.7
2.5
mA
Undervoltage Lockout, VUVLO 2.8
V
VCC rising
Undervoltage Lockout Hysteresis, VUVLOHYST 80
mV
ON PIN
Input Current, IINON −100 +100 nA ON < 1.5 V
−2 +2 µA
Rising Threshold, VONTH 1.26 1.3
1.34 V
ON rising
Trip Threshold Hysteresis, VONHYST 35 50
65 mV
Glitch Filter Time 3
µs
ALERTB PIN
Output Low Voltage, V
ALERTOL
0.05
0.1
V
I
ALERT
= −100 µA
1 1.5 V IALERT = −2 mA
Input Current, IALERT −1 +1 µA VALERT = VCC; ALERTB not asserted
SENSE PIN
Input Leakage, ISENSE −1
+1
µA
VSENSE = VCC
Overcurrent Fault Timing Threshold, VOCTRIM 92
mV
VOCTRIM = (VCC − VSENSE), fault timing
starts on the TIMER pin
Overcurrent Limit Threshold, VLIM 97
100
103
mV
VLIM = (VCC − VSENSE), closed-loop
regulation to a current limit
Fast Overcurrent Trip Threshold, VOCFAST 115
mV
VOCFAST = (VCC − VSENSE), gate pull-down
current turned on
GATE PIN
Drive Voltage, VGATE 3
6 9 V
VGAT E − VCC, VCC = 3.15 V
9
11
13
V
VGAT E − VCC, VCC = 5 V
7
10 13 V
VGAT E − VCC, VCC = 16.5 V
Pull-Up Current 8
12.5
17
µA
VGAT E = 0 V
Pull-Down Current
1.5
mA
V
GAT E
= 3 V, V
CC
= 3.15 V
5 mA VGATE = 3 V, VCC = 5 V
7 mA
VGAT E = 3 V, VCC = 16.5 V
TIMER PIN
Pull-Up Current (Power-On Reset), ITIMERUPPOR −3.5
−5
−6.5
µA
Initial cycle, VTIMER = 1 V
Pull-Up Current (Fault Mode), ITIMERUPFAULT −40
−60
−80
µA
During current fault, VTIMER = 1 V
Pull-Down Current (Retry Mode), ITIMERDNRETRY 2
3
µA
After current fault and during a cooldown
period on a retry device, VTIMER = 1 V
Pull-Down Current, I
TIMERDN
100
µA
Normal operation, V
TIMER
= 1 V
Trip Threshold High, V
TIMERH
1.26
1.3
1.34
V
TIMER rising
Trip Threshold Low, VTIMERL 0.175
0.2
0.225
V
TIMER falling
ADR PIN
Set Address to 00, VADRLOWV 0
0.8
V
Low state
Set Address to 01, RADRLOWZ 135
150
165
kΩ
Resistor to ground state, load pin with
specified resistance for 01 decode
Set Address to 10, IADRHIGHZ −1
+1
µA
Open state, maximum load allowed on
ADR pin for 10 decode
Set Address to 11, VADRHIGHV 2
5.5
V
High state
Input Current for 11 Decode, IADRHIGH 3
10
µA
VADR = 2.0 V to 5.5 V
Input Current for 00 Decode, IADRLOW −40
−22
µA
VADR = 0 V to 0.8 V
ADM1178 Data Sheet
Rev. D | Page 4 of 24
Parameter Min
Typ
Max
Unit
Test Conditions/Comments
MONITORING ACCURACY1
Current Sense Absolute Accuracy
0°C to +70°C −1.45 +1.45 % VSENSE = 75 mV
−1.8 +1.8 % VSENSE = 50 mV
−2.8 +2.8 % VSENSE = 25 mV
−5.7 +5.7 % VSENSE = 12.5 mV
0°C to +85°C −1.5 +1.5 % VSENSE = 75 mV
−1.8 +1.8 % VSENSE = 50 mV
−2.95 +2.95 % VSENSE = 25 mV
−6.1
+6.1
%
V
SENSE
= 12.5 mV
−40°C to +85°C
−1.95
+1.95
%
V
SENSE
= 75 mV
−2.45 +2.45 % VSENSE = 50 mV
−3.85 +3.85 % VSENSE = 25 mV
−6.7 +6.7 % VSENSE = 12.5 mV
VSENSE for ADC Full Scale2 105.84
mV
Voltage Sense Accuracy
0°C to +70°C −0.85 +0.85 % VCC = 3 V minimum (low range)
−0.9 +0.9 % VCC = 6 V minimum (high range)
0°C to +85°C −0.85 +0.85 % VCC = 3 V minimum (low range)
−0.9 +0.9 % VCC = 6 V minimum (high range)
−40°C to +85°C −0.9 +0.9 % VCC = 3 V minimum (low range)
−1.15
+1.15
%
V
CC
= 6 V minimum (high range)
VCC for ADC Full Scale3
Low Range (VRANGE = 1) 6.65
V
High Range (VRANGE = 0) 26.35
V
I2C TIMING
Low Level Input Voltage, VIL
0.3 VBUS V VBUS = 3.0 V to 5.5 V
High Level Input Voltage, VIH
0.7 VBUS V VBUS = 3.0 V to 5.5 V
Low Level Output Voltage on SDA, VOL
0.4 V IOL = 3 mA
Output Fall Time on SDA from VIHMIN to VILMAX 20 + 0.1 CBUS
250 ns CBUS = bus capacitance from SDA to GND
Maximum Width of Spikes Suppressed by
Input Filtering on SDA and SCL Pins
50 250 ns
Input Current, II, on SDA/SCL When Not
Driving a Logic Low Output
−10 +10 µA
Input Capacitance on SDA/SCL
5 pF
SCL Clock Frequency, fSCL
400 kHz
Low Period of the SCL Clock
600 ns
High Period of the SCL Clock
1300 ns
ADC Conversion Time4 150 µs
Fast Overcurrent Response Time5 4 10 µs
Setup Time for a Repeated Start Condition, tSU;STA
600 ns
SDA Output Data Hold Time, t
HD;DAT
100
900
ns
Setup Time for a Stop Condition, tSU;STO
600 ns
Bus Free Time Between a Stop and a Start
Condition, tBUF
1300 ns
Capacitive Load for Each Bus Line
400 pF
1 Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
2 This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see
the Specifications for the Current Sense Absolute Accuracy parameter).
3 These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the
Specifications for the Voltage Sense Accuracy parameter).
4 Time between the receipt of the command byte and the actual ADC result being placed in the register.
5 Guaranteed by design; not production tested.
Data Sheet ADM1178
Rev. D | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC Pin 20 V
SENSE Pin 20 V
TIMER Pin −0.3 V to +6 V
ON Pin −0.3 V to +20 V
ALERTB Pin 30 V
GATE Pin 30 V
SDA Pin, SCL Pin −0.3 V to +6 V
ADR Pin
−0.3 V to +7 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
10-Lead MSOP 137.5 °C/W
ESD CAUTION
ADM1178 Data Sheet
Rev. D | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
1
SENSE
2
ON
3
GND
4
TIMER
5
ALERTB
10
GATE
9
ADR
8
SDA
7
SCL
6
ADM1178
TOP VIEW
(Not t o Scale)
06048-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1178 when a low supply voltage is detected.
2 SENSE Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1178 controls the external FET gate to maintain the (VCC − VSENSE)
voltage at or below 100 mV.
3 ON Undervoltage Input Pin. Active high pin. An internal undervoltage comparator has a trip threshold of 1.3 V,
and the output of this comparator is used as an enable for the hot swap operation. With an external resistor
divider from VCC to GND, the ON pin can be used to enable the hot swap operation for a specific voltage on
VCC, providing an undervoltage function.
4 GND Chip Ground Pin.
5 TIMER Timer Pin. An external capacitor, CTIMER, sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault delay.
The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection
with an external Zener can be used to force this pin high.
6 SCL I2C Clock Pin. Open-drain input requires an external resistive pull-up.
7 SDA I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
8 ADR I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C
addresses.
9 GATE GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which utilizes a charge pump to provide a 12.5 µA pull-up current to charge the FET
GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)
by modulating the GATE pin.
10 ALERTB Alert Output Pin. Active low, open-drain configuration. This pin asserts when an overcurrent condition is
present. The overcurrent level that causes an alert to be asserted is digitally programmable via the I2C
interface. This function can also be enabled/disabled via I2C.
Data Sheet ADM1178
Rev. D | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
06048-021
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00246810 14 1812 16
I
CC
(mA)
V
CC
(V)
Figure 4. Supply Current vs. Supply Voltage
12
10
8
6
4
2
0018161412108642
DRIVE VOLTAGE (V)
VCC (V)
06048-029
Figure 5. Drive Voltage (VGATE − VCC) vs. Supply Voltage
0
–14
–12
–10
–8
–6
–4
–2
01810 12 16148642
I
GATE
(µA)
V
CC
(V)
06048-027
Figure 6. Gate Pull-Up Current vs. Supply Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40 806040200–20
I
CC
(mA)
TEMPERATURE (°C)
06048-022
Figure 7. Supply Current vs. Temperature (Gate On)
06048-030
12
10
8
6
4
2
0
–40 806040200–20
DRIVE VOLTAGE (V)
TEMPERATURE (°C)
5V V
CC
3.15V V
CC
Figure 8. Drive Voltage (VGATE − VCC) vs. Temperature
0
–2
–4
–6
–8
–10
–12
–14
–40 806040200–20
I
GATE
(µA)
TEMPERATURE (°C)
06048-028
Figure 9. Gate Pull-Up Current vs. Temperature
ADM1178 Data Sheet
Rev. D | Page 8 of 24
12
10
8
6
4
2
0018161412108642
I
GATE
(mA)
V
CC
(V)
06048-031
Figure 10. Gate Pull-Down Current vs. Supply Voltage at VGATE = 5 V
2
–14
–12
–10
–8
–6
–4
–2
0
0161412108642
I
GATE
(µA)
V
GATE
(V)
06048-040
Figure 11. Gate Pull-Up Current vs. Gate Voltage at VCC = 5 V
06048-043
0
5
10
15
20
0252015105
IGATE (mA)
VGATE (V)
VCC = 3V
VCC = 5V
VCC = 12V
Figure 12. Gate Pull-Down Current vs. Gate Voltage
06048-038
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TIMER THRESHOLD (V)
V
CC
(V)
01810 12 16148642
HIGH
LOW
Figure 13. Timer Threshold vs. Supply Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40 80
HIGH
LOW
6040200–20
TIMER THRESHOLD (V)
TEMPERATURE (°C)
06048-039
Figure 14. Timer Threshold vs. Temperature
0
100
80
60
40
20
90
70
50
30
10
05.04.54.03.53.02.52.01.51.00.5
GATE ON TIME (ms)
C
TIMER
(µF)
06048-050
Figure 15. Gate On Time vs. Timer Capacitance,
During Current Limiting Condition
Data Sheet ADM1178
Rev. D | Page 9 of 24
06048-032
01810 12 16148642
0
–1
–2
–3
–4
–5
–6
I
TIMER
(µA)
V
CC
(V)
Figure 16. Timer Pull-Up Current (Initial Cycle) vs. Supply Voltage
06048-034
0
–80
–70
–60
–50
–40
–30
–20
–10
I
TIMER
(µA)
V
CC
(V)
01810 12 16148642
Figure 17. Timer Pull-Up Current (Circuit Breaker Delay) vs. Supply Voltage
06048-036
3.0
2.5
2.0
1.5
1.0
0.5
0
I
TIMER
(µA)
V
CC
(V)
01810 12 16148642
Figure 18. Timer Pull-Down Current (Cooldown/FET Off Cycle) vs. Supply Voltage
0
–1
–2
–3
–4
–5
–6
–40 806040200–20
I
TIMER
(µA)
TEMPERATURE (°C)
06048-033
Figure 19. Timer Pull-Up Current (Initial Cycle) vs. Temperature
0
–10
–20
–30
–40
–50
–80
–70
–60
–40 806040200–20
I
TIMER
(µA)
TEMPERATURE (°C)
06048-035
Figure 20. Timer Pull-Up Current (Circuit Breaker Delay) vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 806040200–20
I
TIMER
(µA)
TEMPERATURE (°C)
06048-037
Figure 21. Timer Pull-Down Current (Cooldown/FET Off Cycle) vs. Temperature
ADM1178 Data Sheet
Rev. D | Page 10 of 24
120
80
85
90
95
100
105
110
115
21816141210864
V
LIM
(mV)
V
CC
(V)
06048-041
Figure 22. Circuit Breaker Limit Voltage vs. Supply Voltage
06048-042
110
90
92
94
96
98
100
102
104
106
108
–40 806040200–20
VOLT AGE (mV)
TEMPERATURE (°C)
V
OCTRIM
V
LIM
V
OCFAST
Figure 23. VOCTRIM, VLIM, VOCFAST vs. Temperature
06048-026
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–35 –30 –25 –20 –15 –10 –5 0 5 10
V
ADR
I
ADR
(µA)
00 DECODE 01 DECODE 10 DECODE 11 DECO DE
Figure 24. Address Pin Voltage vs. Address Pin Current
for Four Addressing Options on Each Address Pin
0
1000
900
800
700
600
500
400
300
200
100
HITS PE R CODE ( 1000 RE ADS )
CODE
06048-060
2047 2048 2049 20502046
Figure 25. ADC Noise with Current Channel, Midcode Input, and 1000 Reads
0
1000
900
800
700
600
500
400
300
200
100
HITS PE R CODE ( 1000 RE ADS )
CODE
06048-061
780 781 782 783779
Figure 26. ADC Noise with 14:1 Voltage Channel, 5 V Input, and 1000 Reads
0
1000
900
800
700
600
500
400
300
200
100
HITS PE R CODE ( 1000 RE ADS )
CODE
06048-062
3079 3080 3081 30823078
Figure 27. ADC Noise with 7:1 Voltage Channel, 5 V Input, and 1000 Reads
Data Sheet ADM1178
Rev. D | Page 11 of 24
4
3
2
1
0
–1
–2
–3
–4 040002500 3000 3500200015001000500
INL (LSB)
CODE
06048-023
Figure 28. INL for ADC
4
3
2
1
0
–1
–2
–3
–4 040002500 3000 3500200015001000500
DNL ( LSB)
CODE
06048-024
Figure 29. DNL for ADC
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
–40 806040200–20
ALERTB OUTPUT LOW (V)
TEMPERATURE (°C)
06048-047
Figure 30. ALERTB Output Low Voltage vs. Temperature @ 1 mA
0
1.0
0.8
0.6
0.4
0.2
2161514131211109876543
ALERTB OUTPUT LOW (V)
VCC (V)
06048-048
Figure 31. ALERTB Output Low Voltage vs. Supply @ 1 mA
0
2.0
1.6
1.2
0.8
0.4
1.8
1.4
1.0
0.6
0.2
03.02.82.62.42.22.01.81.61.41.21.00.80.60.40.2
ALERTB OUTPUT LOW (V)
I
LOAD
(mA)
06048-049
Figure 32. ALERTB Output Low Voltage vs. Load Current
ADM1178 Data Sheet
Rev. D | Page 12 of 24
OVERVIEW OF THE HOT SWAP FUNCTION
When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. Such transient currents can
cause permanent damage to connector pins, as well as dips on
the backplane supply that can reset other boards in the system.
The ADM1178 is designed to turn a circuit board supply
voltage on and off in a controlled manner, allowing the circuit
board to be safely inserted into or removed from a live backplane.
The ADM1178 can reside either on the backplane or on the
circuit board itself.
The ADM1178 controls the inrush current to a fixed maximum
level by modulating the gate of an external N-channel FET placed
between the live supply rail and the load. This hot swap function
protects the card connectors and the FET itself from damage
and limits any problems that can be caused by the high current
loads on the live supply rail.
The ADM1178 holds the GATE pin down (and therefore holds
off the FET) until certain conditions are met. An undervoltage
lockout circuit ensures that the device is provided with an adequate
input supply voltage. After the input supply voltage is successfully
detected, the device goes through an initial timing cycle to
provide a delay before it attempts a hot swap. This delay ensures
that the board is fully seated in the backplane before the board
is powered up.
After the initial timing cycle is complete, the hot swap function
is switched on under control of the ON pin. When the ON pin
is asserted high, the hot swap operation starts.
The ADM1178 charges up the gate of the FET to turn on the
load. It continues to charge up the GATE pin until the linear
current limit (set to 100 mV/RSENSE) is reached. For some
combinations of low load capacitance and high current limit,
this limit may not be reached before the load is fully charged
up. If the current limit is reached, the ADM1178 regulates the
GATE pin to keep the current at this limit. For currents above
the overcurrent fault timing threshold, nominally 100 mV/RSENSE,
the current fault is timed by sourcing a current to the TIMER pin.
If the load becomes fully charged before the fault current limit
time elapses (when the TIMER pin reaches 1.3 V), the current
drops below the overcurrent fault timing threshold. The ADM1178
then continues to further charge up the GATE pin to fully enhance
the FET for lowest RON, and the TIMER pin is pulled down again.
If the fault current limit time is reached before the load drops
below the current limit, a fault has been detected, and the hot
swap operation is aborted by pulling down the GATE pin to
turn off the FET.
The ADM1178-2 is immediately latched off and attempts a hot
swap only when the ON pin is deasserted and then asserted again.
The ADM1178-1, however, retries the hot swap operation
indefinitely, keeping the FET in its safe operating area (SOA) by
using the TIMER pin to time a cooldown period between hot swap
attempts.
The current and voltage threshold combinations on the TIMER pin
set the retry duty cycle to 3.8%. The ADM1178 is designed to
operate over a range of supplies from 3.15 V to 16.5 V.
UNDERVOLTAGE LOCKOUT
An internal undervoltage lockout (UVLO) circuit resets the
ADM1178 if the voltage on the VCC pin is too low for normal
operation. The UVLO has a low-to-high threshold of 2.8 V, with
80 mV hysteresis. When there is a supply voltage greater than 2.8 V,
the ADM1178 starts the initial timing cycle.
ON FUNCTION
The ADM1178 has an active high ON pin. The ON pin is the
input to a comparator that has a low-to-high threshold of 1.3 V,
an 50 mV hysteresis, and a glitch filter of 3 μs. A low input on the
ON pin turns off the hot swap operation by pulling the GATE pin
to ground, turning off the external FET. The TIMER pin is also
reset by turning on a pull-down current on this pin. A low-to-
high transition on the ON pin starts the hot swap operation. A
10 kΩ pull-up resistor connecting the ON pin to the supply is
recommended.
Alternatively, an external resistor divider at the ON pin can be
used to program an undervoltage lockout value that is higher
than the internal UVLO circuit, thereby setting the hot swap
operation to start at a specific voltage level on the VCC pin. An
RC filter can be added at the ON pin to increase the delay time
at card insertion if the initial timing cycle delay is insufficient.
TIMER FUNCTION
The TIMER pin handles several timing functions with an
external capacitor, CTIMER. There are two comparator thresholds:
VTIMERH (1.3 V) and VTIMERL (0.2 V). The four timing current
sources are a 5 µA pull-up, a 60 µA pull-up, a 2 µA pull-down,
and a 100 µA pull-down. The 100 µA pull-down is a nonideal
current source, approximating a 7 kΩ resistor below 0.4 V.
These current and voltage levels, together with the value of CTIMER
chosen by the user, determine the initial timing cycle time, the
fault current limit time, and the hot swap retry duty cycle.
Data Sheet ADM1178
Rev. D | Page 13 of 24
GATE AND TIMER FUNCTIONS DURING A HOT
SWAP OPERATION
During hot insertion of a board onto a live supply rail at VCC,
the abrupt application of supply voltage charges the external
FET drain/gate capacitance, which can cause an unwanted gate
voltage spike. An internal circuit holds GATE low before the
internal circuitry wakes up. This substantially reduces the FET
current surges at insertion. The GATE pin is also held low during
the initial timing cycle until the ON pin is taken high to start
the hot swap operation.
During a hot swap operation, the GATE pin is first pulled up by
a 12.5 μA current source. If the current through the sense resistor
reaches the overcurrent fault timing threshold (VOCTRIM), a pull-up
current of 60 µA on the TIMER pin, is turned on and the GATE
pin starts charging up. At a slightly higher voltage in the sense
resistor, the error amplifier servos the GATE pin to maintain a
constant current to the load by controlling the voltage across the
sense resistor to the linear current limit, VLIM.
A normal hot swap operation is complete when the board supply
capacitors near full charge and the current through the sense
resistor drops to eventually reach the level of the board load
current. As soon as the current drops below the overcurrent
fault timing threshold, the current into the TIMER pin switches
from being a 60 μA pull-up to being a 100 μA pull-down. The
ADM1178 then drives the GATE voltage as high as it can to
fully enhance the FET and reduce RON losses to a minimum.
A hot swap operation fails if the load current does not drop
below the overcurrent fault timing threshold, VOCTRIM, before the
TIMER pin has charged up to 1.3 V. In this case, the GATE pin
is then pulled down with a 1.5 mA to 7 mA current sink (this
varies with supply voltage). The GATE pull-down stays on until
a hot swap retry starts, which can be forced by deasserting and
then reasserting the ON pin. On the ADM1178-1, the device retries
a hot swap operation automatically after a cooldown period.
The ADM1178 also features a method of protection from sudden
load current surges, such as a low impedance fault, when the
current seen across the sense resistor may go well beyond the
linear current limit. If the fast overcurrent trip threshold,
VOCFA ST , is exceeded, the 1.5 mA to 7 mA GATE pull-down is
turned on immediately. This pulls the GATE voltage down quickly
to enable the ADM1178 to limit the length of the current spike
that passes through the external FET and to bring the current
through the sense resistor back into linear regulation as quickly as
possible. This process protects the backplane supply from
sustained overcurrent conditions that may otherwise cause the
backplane supply to droop during the overcurrent event.
CALCULATING CURRENT LIMITS AND FAULT
CURRENT LIMIT TIME
The nominal linear current limit is determined by a sense
resistor connected between the VCC pin and the SENSE pin,
as given by Equation 1.
ILIMIT(NOM) = VLIM(NOM)/RSENSE = 100 mV/RSENSE (1)
The minimum linear fault current is given by Equation 2.
ILIMIT(MIN) = VLIM(MIN)/RSENSE(MAX) = 97 mV/RSENSE(MAX) (2)
The maximum linear fault current is given by Equation 3.
ILIMIT(MAX) = VLIM(MAX)/RSENSE(MIN) = 103 mV/RSENSE(MIN) (3)
The power rating of the sense resistor should be rated at the
maximum linear fault current level.
The minimum overcurrent fault timing threshold current is
given by Equation 4.
IOCTRIM(MIN) = VOCTRIM(MIN)/RSENSE(MAX) = 90 mV/RSENSE(MAX) (4)
The maximum fast overcurrent trip threshold current is given
by Equation 5.
IOCFAST(MAX) = VOCFAST(MAX)/RSENSE(MIN) = 115 mV/RSENSE(MIN) (5)
The fault current limit time is the time that a device spends timing
an overcurrent fault. The fault current limit time is given by
Equation 6.
tFAULT ≈ 21.7 × CTIMER ms/μF (6)
INITIAL TIMING CYCLE
When VCC is first connected to the backplane supply, the
internal supply (Time Point 1 in Figure 33) of the ADM1178
must be charged up. A very short time later (significantly less
than 1 ms), the internal supply is fully up and, because the
undervoltage lockout voltage is exceeded at VCC, the device
comes out of reset. During this first short reset period, the
GATE pin is held down with a 25 mA pull-down current, and
the TIMER pin is pulled down with a 100 µA current sink.
The ADM1178 then goes through an initial timing cycle. At
Time Point 2, the TIMER pin is pulled high with 5 µA. At Time
Point 3, the TIMER reaches the VTIMERL threshold, and the first
portion of the initial cycle ends. The 100 µA current source then
pulls down the TIMER pin until it reaches 0.2 V at Time Point 4.
The initial cycle delay (Time Point 2 to Time Point 4) is related
to CTIMER as shown in Equation 7.
tINITIAL ≈ 270 × CTIMER ms/μF (7)
ADM1178 Data Sheet
Rev. D | Page 14 of 24
When the initial timing cycle terminates, the device is ready to
start a hot swap operation (assuming that the ON pin is asserted).
In the example shown in Figure 33, the ON pin is asserted at the
same time as VCC is applied; therefore, the hot swap operation
starts immediately after Time Point 4. At this point, the FET
gate is charged up with a 12.5 µA current source.
At Time Point 5, the threshold voltage of the FET is reached and
the load current begins to flow. The FET is controlled to keep
the sense voltage at 100 mV (this corresponds to a maximum load
current level defined by the value of RSENSE).
At Time Point 6, VGATE and VOUT have reached their full potential,
and the load current has settled to its nominal level. Figure 34
illustrates the situation where the ON pin is asserted after VCC is
applied.
VCC
(1)
INITIAL TIMING
CYCLE
(2) (3)(4)(5) (6)
VON
VTIMER
VGATE
VSENSE
VOUT
06048-004
Figure 33. Startup (ON Asserts as Power Is Applied)
INITIAL TIMING
CYCLE
VCC
VON
VTIMER
VGATE
VSENSE
VOUT
(1) (2) (3)(4) (5)(6) (7)
06048-005
Figure 34. Startup (ON Asserts After Power Is Applied)
HOT SWAP RETRY CYCLE ON THE ADM1178-1
With the ADM1178-1, the device turns off the FET after an
overcurrent fault and then uses the TIMER pin to time a delay
before automatically retrying to hot swap.
As with all ADM1178 devices, an overcurrent fault is timed by
charging the TIMER capacitor with a 60 μA pull-up current.
When the TIMER pin reaches 1.3 V, the fault current limit time
is reached, and the GATE pin is pulled down. On the ADM1178-1,
the TIMER pin is then pulled down with a 2 μA current sink.
When the TIMER pin reaches 0.2 V, it automatically restarts the
hot swap operation.
The cooldown period is related to CTIMER by Equation 8.
tCOOL ≈ 550 × CTIMER ms/μF (8)
Therefore, the retry duty cycle is as given by Equation 9.
tFAULT/(tCOOL + tFAULT) × 100% = 3.8% (9)
Data Sheet ADM1178
Rev. D | Page 15 of 24
VOLTAGE AND CURRENT READBACK
In addition to providing hot swap functionality, the ADM1178
contains the components to allow voltage and current readback
over an I2C bus. The voltage output of the current sense
amplifier and the voltage on the VCC pin are fed into a 12-bit
ADC via a multiplexer. The device can be instructed to convert
voltage and/or current at any time during operation via an I2C
command. When all conversions are complete, the voltage
and/or current values can be read back with 12-bit accuracy in
two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1178 is carried out via the I2C bus. This
interface is compatible with the I2C fast mode (400 kHz
maximum). The ADM1178 is connected to this bus as a slave
device, under the control of a master device.
IDENTIFYING THE ADM1178 ON THE I2C BUS
The ADM1178 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The three MSBs of the address are set to 111, and the two MSBs
are set to 10, resulting in an address of 111x10. Bit A2 and Bit
A3 are determined by the state of the ADR pin. There are four
configurations available on the ADR pin that correspond to four
I2C addresses for these bits (see Table 5). This scheme allows
four ADM1178 devices to operate on a single I2C bus.
GENERAL I2C TIMING
Figure 35 and Figure 36 show timing diagrams for general write
and read operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I2C protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit that determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowl-
edge bit, and holding it low during the high period of this
clock pulse. All other devices on the bus remain idle while
the selected device waits for data to be read from it or written
to it. If the R/W bit is 0, the master writes to the slave device.
If the R/W bit is 1, the master reads from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-high
transition when the clock is high can be interpreted as a
stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a
no acknowledge. The master then takes the data line low
during the SCL low period before the 10th clock pulse and
then high during the 10th clock pulse to assert a stop condition.
Table 5. Setting I2C Addresses via the ADR Pin
Base Address ADR Pin State ADR Pin Logic State Address in Binary1 Address in Hex
111AA10 Ground 00 1110010X 0xE4
Resistor to ground 01 1110110X 0xEC
Floating 10 1111010X 0xF4
High 11 1111110X 0xFC
1 X = don’t care.
ADM1178 Data Sheet
Rev. D | Page 16 of 24
SCL
START BY MASTER
1919
R/W D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLE DGE BY
SLAVE
ACKNOWLE DGE BY
SLAVE ACKNOWLE DGE BY
SLAVE
ACKNOWLE DGE BY
SLAVE
FRAM E 1
SL AV E ADDRE S S FRAM E 2
COM M AND CODE
SCL
(CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1919
STOP
BY
MASTER
SDA
(CONTINUED)
FRAM E 3
DATA BY TE FRAM E N
DATA BY TE
06048-006
SDA 1 0
ADRBADRA
11
1
Figure 35. General I2C Write Timing Diagram
SCL
START BY MASTER
1919
R/W D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLE DGE BY
SLAVE
ACKNOWLE DGE BY
MASTER NO ACKNOWLEDG E
ACKNOWLE DGE BY
MASTER
FRAM E 1
SL AV E ADDRE S S FRAM E 2
DATA BY TE
SCL
(CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1919
STOP
BY
MASTER
SDA
(CONTINUED)
FRAM E 3
DATA BY TE FRAM E N
DATA BY TE
06048-007
SDA 1 0
ADRBADRA
11
1
Figure 36. General I2C Read Timing Diagram
SCLSCL
SDA
PS
tHD;STA tHD;DAT
tHIGH tSU;DAT
tSU;STA
t
HD;STA
tF
tR
tLOW
tBUF
tSU;STO
P
S
06048-008
Figure 37. Serial Bus Timing Diagram
Data Sheet ADM1178
Rev. D | Page 17 of 24
WRITE AND READ OPERATIONS
The I2C specification defines several protocols for different types of
read and write operations. The operations used in the ADM1178
are discussed in this section. Table 6 shows the abbreviations
used in the command diagrams (see Figure 38 to Figure 43).
Table 6. I2C Abbreviations
Abbreviation Condition
S Start
P Stop
R Read
W Write
A
Acknowledge
N No acknowledge
QUICK COMMAND
The quick command operation allows the master to check if the
slave is present on the bus, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master asserts a stop condition on SDA to end the
transaction.
06048-009
SSLAVE
ADDRESS W A
1 2 3
P
4
Figure 38. Quick Command
WRITE COMMAND BYTE
In the write command byte operation, the master device sends
a command byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends the command byte. The command byte is
identified by an MSB = 0. An MSB = 1 indicates an extended
register write (see the Write Extended Command Byte
section).
5. The slave asserts an acknowledge on SDA.
6. The master asserts a stop condition on SDA to end the
transaction.
SSLAVE
ADDRESS W A COMMAND
BYTE A P
1 2 3 4 5 6
06048-010
Figure 39. Write Command Byte
The seven LSBs of the command byte are used to configure and
control the ADM1178. Table 7 provides details of the function
of each bit.
Table 7. Command Byte Operations
Bit Default Name Function
C0 0 V_CONT LSB, set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1178 asserts an acknowledge and returns all 0s in the returned data.
C1 0 V_ONCE Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
C2
0
I_CONT
Set to convert current continuously. If readback is attempted before the first conversion is complete, the
ADM1178 asserts an acknowledge and returns all 0s in the returned data.
C3 0 I_ONCE Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
C4 0 VRANGE Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1
voltage divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the
VCC pin for an ADC full-scale result is 26.35 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
C5 0 Not applicable Unused.
C6 0 STATUS_RD Status read. When this bit is set, the data byte read back from the ADM1178 is the status byte. This
contains the status of the device alerts. See Table 15 for full details of the status byte.
ADM1178 Data Sheet
Rev. D | Page 18 of 24
WRITE EXTENDED COMMAND BYTE
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends the register address byte. The MSB of
this byte is set to 1 to indicate an extended register write.
The two LSBs indicate which of the three extended registers
is written to (see Table 8). All other bits should be set to 0.
5. The slave asserts an acknowledge on SDA.
6. The master sends the extended command byte (refer to
Table 9, Table 10, and Table 11).
7. The slave asserts an acknowledge on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
SSLAVE
ADDRESS W A REGISTER
ADDRESS A P
EXTENDED
COMMAND
BYTE
A
1 2 3 4 5 6 7 8
06048-011
Figure 40. Write Extended Byte
Table 9, Table 10, and Table 11 provide the details of each
extended register.
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0 Extended Register
0 0 0 0 0 0 1 ALERT_EN
0 0 0 0 0 1 0 ALERT_TH
0 0 0 0 0 1 1 CONTROL
Table 9. ALERT_EN Register Operations
Bit Default Name Function
0 0 EN_ADC_OC1 LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
1 0 EN_ADC_OC4 Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
2 1 EN_HS_ALERT Enabled if the hot swap operation either has latches off or enters a cooldown cycle because of an
overcurrent event.
3 0 EN_OFF_ALERT Enables an alert if the hot swap operation is turned off by a transition that deasserts the ON pin or by
an operation that writes the SWOFF bit high.
4 0 CLEAR Clears the OFF_ALERT, HS_ALERT, and ADC_ALERT status bits in the STATUS register. The value of these
bits may immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Table 10. ALERT_TH Register Operations
Bit Default Function
[7:0] FF The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit value
corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit Default Name Function
0
0
SWOFF LSB, forces the hot swap operation off. Equivalent to deasserting the ON pin.
Data Sheet ADM1178
Rev. D | Page 19 of 24
READ VOLTAGE AND/OR CURRENT DATA BYTES
Depending on how the device is configured, ADM1178 can be
set up to provide information in three ways after a conversion
(or conversions): voltage and current readback, voltage only
readback, and current only read back. See the Write Command
Byte section for more details.
Voltage and Current Readback
The ADM1178 digitizes both voltage and current. Three bytes
are read back in the format shown in Table 12.
Table 12. Voltage and Current Readback Format
Byte Contents B7 B6 B5 B4 B3 B2 B1 B0
1 Voltage MSBs V11 V10 V9 V8 V7 V6 V5 V4
2 Voltage MSBs I11 I10 I9 I8 I7 I6 I5 I4
3 Voltage LSBs V3 V2 V1 V0 I3 I2 I1 I0
Voltage Readback
The ADM1178 digitizes voltage only. Two bytes are read back in
the format shown in Table 13.
Table 13. Voltage Only Readback Format
Byte Contents B7 B6 B5 B4 B3 B2 B1 B0
1 Voltage MSBs V11 V10 V9 V8 V7 V6 V5 V4
2 Voltage LSBs V3 V2 V1 V0 0 0 0 0
Current Readback
The ADM1178 digitizes current only. Two bytes are read back
in the format shown in Table 14.
Table 14. Current Only Readback Format
Byte Contents B7 B6 B5 B4 B3 B2 B1 B0
1 Current MSBs I11 I10 I9 I8 I7 I6 I5 I4
2 Current LSBs I3 I2 I1 I0 0 0 0 0
The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the first data byte.
5. The master asserts an acknowledge on SDA.
6. The master receives the second data byte.
7. The master asserts an acknowledge on SDA.
8. The master receives the third data byte.
9. The master asserts a no acknowledge on SDA.
10. The master asserts a stop condition on SDA, and the
transaction ends.
For cases where the master is reading voltage only or current
only, two data bytes are read and Step 7 and Step 8 are not required.
SSLAVE
ADDRESS R A DATA 1 DATA 2 N PDATA 3A
A
1 2 3 4 5 6 7 8 9 10
06048-012
Figure 41. Three-Byte Read from ADM1178
06048-013
SSLAVE
ADDRESS R A DATA 1 N PDATA 2
A
1 2 3 4 5 6 7 8
Figure 42. Two-Byte Read from ADM1178
Converting ADC Codes to Voltage and Current Readings
Equation 10 and Equation 11 can be used to convert ADC codes
representing voltage and current from the ADM1178 12-bit
ADC into actual voltage and current values.
Voltage = (VFULLSCALE/4096) × Code (10)
where:
VFULLSCALE = 6.65 V (7:2 range) or 26.35 V (14:1 range).
Code is the ADC voltage code read from the device
(Bit V11 to Bit V0).
Current = ((IFULLSCALE/4096) × Code)/Sense Resistor (11)
where:
IFULLSCALE = 105.84 mV.
Code is the ADC current code read from the device
(Bit I11 to Bit I0).
Read Status Register
A single register of status data can also be read from the
ADM1178 as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the status byte.
5. The master asserts an acknowledge on SDA.
06048-014
SSLAVE
ADDRESS STATUS
BYTE
R A A
1 2 3 4 5
Figure 43. Status Read from ADM1178
Table 15 shows the ADM1178 STATUS registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 (the
CLEAR bit) of the ALERT_EN register.
ADM1178 Data Sheet
Rev. D | Page 20 of 24
Table 15. Status Byte Operations
Bit Name Function
0 ADC_OC An ADC-based overcurrent comparison is detected on the last three conversions.
1 ADC_ALERT An ADC-based overcurrent trip has occurred, causing the alert. Cleared by writing to Bit 4 of the ALERT_EN register.
2 HS_OC The hot swap operation is off due to an analog overcurrent event. On parts that latch off, this is the same as the
HS_ALERT status bit (if EN_HS_ALERT = 1). On the retry parts, this indicates the current state: a 0 can indicate that the
data was read during a period when the device was retrying or that it has successfully hot swapped by retrying after at
least one overcurrent timeout.
3 HS_ALERT The hot swap operation has failed since the last time this was reset. Cleared by writing to Bit 4 of the ALERT_EN register.
4 OFF_STATUS The state of the ON pin. Set to 1 if the input pin is deasserted. Can also be set to 1 by writing to the SWOFF bit of the
CONTROL register.
5
OFF_ALERT
An alert has been caused by either the ON pin or the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
Data Sheet ADM1178
Rev. D | Page 21 of 24
APPLICATIONS INFORMATION
APPLICATIONS WAVEFORMS
06048-070
CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V M40.0ms
4
3
2
1
Figure 44. Inrush Current Control into 220 µF Load
(Channel 1 = ILOAD, Channel 2 = VTIMER, Channel 3 = VGATE, Channel 4 = VOUT)
06048-071
CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V M10.0ms
4
3
2
1
Figure 45. Overcurrent Condition at Startup (ADM1178-1 Model)
(Channel 1 = ILOAD, Channel 2 = VTIMER, Channel 3 = VGATE, Channel 4 = VOUT)
06048-072
CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V M20.0ms
4
3
2
1
Figure 46. Overcurrent Condition at Startup (ADM1178-2 Model)
(Channel 1 = ILOAD, Channel 2 = VTIMER, Channel 3 = VGATE, Channel 4 = VOUT)
06048-073
CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V M10.0ms
4
3
2
1
Figure 47. Overcurrent Condition During Operation (ADM1178-1 Model)
(Channel 1 = ILOAD, Channel 2 = VTIMER, Channel 3 = VGATE, Channel 4 = VOUT)
06048-074
CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V M20.0ms
4
3
2
1
Figure 48. Overcurrent Condition During Operation (ADM1178-2 Model)
(Channel 1 = ILOAD, Channel 2 = VTIMER, Channel 3 = VGATE, Channel 4 = VOUT)
ADM1178 Data Sheet
Rev. D | Page 22 of 24
ALERTB OUTPUT
The ALERTB output is an open-drain pin with 30 V tolerance.
This output can be used as an overcurrent flag by connecting it
to the general-purpose logic input of a controller. During normal
operation, this output is pulled high. (An external pull-up resistor
should be used because this is an open-drain pin.) When an over-
current condition occurs, the ADM1178 pulls this output low.
If any of the enabled latched alerts in the status byte (ADC_ALERT,
HS_ALERT, and OFF_ALERT) are triggered, the ALERTB output
asserts. For a programmable ADC-based overcurrent limit level
point, the ADC_ALERT latch must be enabled. The overcurrent
threshold that triggers an alert is then programmed via the
ALERT_TH register. This pin is disabled by default at power up.
See the ALERT_EN register to enable.
R
SENSE
N-CHANNEL FE T
P = VI
CONTROLLER
ADM1178
SENSEVCC
SDA
SCL SDA
SCL
GND
GATE
INTERRUPT
ALERTB
ADR
TIMER
3.15V TO 16.5V
ON
06048-100
Figure 49. Using the ALERTB Output as an Interrupt
KELVIN SENSE RESISTOR CONNECTION
When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance can arise.
The pad and solder resistance can be a substantial fraction of
the rated resistance, making the total resistance larger than
expected. This error problem can be largely avoided by using a
Kelvin sense connection. This type of connection separates the
high current path through the resistor and the voltage drop across
the resistor. A four pad resistor can be used or a split pad layout
can be used with a two pad sense resistor to achieve Kelvin sensing.
Data Sheet ADM1178
Rev. D | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Hot Swap Retry Option Temperature Range Package Description Package Option Branding
ADM1178-1ARMZ-R7 Automatic Retry Version −40°C to +85°C 10-Lead MSOP RM-10 M62
ADM1178-2ARMZ-R7 Latched Off Version −40°C to +85°C 10-Lead MSOP RM-10 M64
EVAL-ADM1178EBZ Evaluation Board
1 Z = RoHS Compliant Part.
ADM1178 Data Sheet
Rev. D | Page 24 of 24
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06048-0-6/12(D)
