Enpirion(R) Power Datasheet ES1022SI Adjustable Quad Sequencer ES1022SI Datasheet The ES1022SI IC provides four delay adjustable sequenced outputs while monitoring an input voltage all with a minimum of external components. Features High performance DSP, FPGA, P and various subsystems require input power sequencing for proper functionality at initial power up and the ES1022SI provides this function while monitoring the distributed voltage for over and undervoltage compliance. * Adjustable Delay to Sequence Auto Start * Adjustable Delay to Subsequent EN Signal * Adjustable Distributed Voltage Monitoring * Under and Overvoltage Adjustable Delay to Auto Start Sequence * I/O Options: EN and SEQ_EN This IC operates over the +3.3V to +24V nominal voltage range. It has a user adjustable time from UV and OV voltage compliance to sequencing start via an external capacitor when in auto start mode and adjustable time delay to subsequent EN output signal via external resistors. * Voltage Compliance Fault Output * Pb-Free Plus Anneal Available (RoHS Compliant) Applications * Power Supply Sequencing Additionally, the ES1022SI provides I/O for sequencing on and off operation (SEQ_EN) and for voltage window compliance reporting (FAULT) over the +3.3V to +24V nominal voltage range. * System Timing Function Easily daisy chained for more than 4 sequenced signals. Altogether, the ES1022SI provides these adjustable features with a minimum of external BOM. See Figure 1 for typical implementation. 3.3-24V EN Ru VIN SEQ_EN EN_A EN_B EN_C EN_D UV Rm OV TDLY_BC TDLY_AB GND DC/DC Vo1 DC/DC Vo2 DC/DC Vo3 DC/DC V04 EN FAULT TDLY_CD TIME EN Rl EN FIGURE 1. ES1022SI IMPLEMENTATION 101 Innovation Drive San Jose, CA 95134 www.altera.com May 2014 (c) 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe 10037 May 28, 2014 Rev A Page 2 Ordering Information PART NUMBER (Note 1) TEMP. RANGE (C) PART MARKING ES1022SI* ES1022SI EVB-ES1022SI Evaluation Platform -40 to +85 PACKAGE (Pb-free) 14 Ld SOIC PKG. DWG. # M14.15 *Add "-T" suffix for tape and reel. Please refer to Packing and Marking Information: www.altera.com/support/reliability/packing/relpacking-and-marking.html NOTES: 1. Altera Enpirion Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 May 28, 2014 May 2014 Altera Corporation Rev A Page 3 Pinout ES1022SI (14 LD SOIC) TOP VIEW EN_D 1 14 VIN EN_C 2 13 TDLY_CD EN_B 3 12 TDLY_BC EN_A 4 11 TDLY_AB OV 5 10 TIME UV 6 9 SEQ_EN GND 7 8 FAULT Pin Descriptions Pin Number PIN NAME FUNCTION DESCRIPTION 1 EN_D EN output D. Active high open drain sequenced output. Sequenced on after EN_C and first output to sequence off. Pulls low with VIN < 1V. 2 EN_C EN output C. Active high open drain sequenced output. Sequenced on after EN_B and sequenced off after EN_D. Pulls low with VIN < 1V. 3 EN_B EN output B. Active high open drain sequenced output. Sequenced on after EN_A and sequenced off after EN_C. Pulls low with VIN < 1V. 4 EN_A EN output A. Active high open drain sequenced output. Sequenced on after CTIME period and sequenced off after EN_B. Pulls low with VIN < 1V. 5 OV The voltage on this pin must be under its 1.22V Vth or the four EN outputs will be immediately pulled down. 6 UV The voltage on this pin must be over its 1.22V Vth or the four EN outputs will be immediately pulled down. 7 GND 8 FAULT IC ground. The VIN voltage when not within the desired UV to OV window will cause FAULT to be released to be pulled high to a voltage equal to or less than VIN via an external resistor. 9 SEQ_EN 10 TIME This pin provides a 2.6A current output so that an adjustable VIN valid to sequencing on and off start delay period is created with a capacitor to ground. 11 TDLY_AB A resistor connected from this pin to ground determines the time delay from EN_A being active to EN _B being active on turnon and also going inactive on turn-off via the SEQ_EN input. 12 TDLY_BC A resistor connected from this pin to ground determines the time delay from EN_B being active to EN _C being active on turnon and also going inactive on turn-off via the SEQ_EN input. 13 TDLY_CD A resistor connected from this pin to ground determines the time delay from EN_C being active to EN _D being active on turnon and also going inactive on turn-off via the SEQ_EN input. 14 VIN May 2014 10037 This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V. IC Bias Pin Nominally 3.3V to 24V This pin requires a 1F decoupling capacitor close to IC pin. Altera Corporation Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer May 28, 2014 Rev A Page 4 Absolute Maximum Ratings Thermal Information VIN, EN, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V TIME, TDLY_AB, TDLY_BC, TDLY_CD, UV, OV .+6V, to -0.3V SEQ_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN+0.3V, to -0.3V EN Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Thermal Resistance (Typical, Note 2) . . . . . . . . . . . JA (C/W) 14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package) +125C Maximum Storage Temperature Range . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . +300C (SOIC Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltage Range (Nominal) . . . . . . . . . . . . . . 3.3V to 24V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Electrical Specifications PARAMETER Nominal VIN = 3.3V to +24V, TA = TJ = -40C to+85C, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 1.16 1.21 1.28 V 1.06 1.10 1.18 V - 104 - mV - 10 - nA UV AND OV INPUTS UV/OV Rising Threshold VUVRvth UV/OV Falling Threshold VUVFvth UV/OV Hysteresis VUVhys UV/OV Input Current VUVRvth - VUVFvth IUV TIME, EN OUTPUTS ITIME - 2.6 - A TIME Pin Threshold VTIME_VTH 1.9 2.0 2.25 V Time from VIN Valid to EN_A tVINSEQpd SEQ_EN = high, CTIME = open - 30 - s tVINSEQpd_10 SEQ_EN = high, CTIME = 10nF - 7.7 - ms tVINSEQpd500 SEQ_EN = high, CTIME = 500nF - 435 - ms UV or OV to simultaneous shutdown - - 1 s TIME Pin Charging Current Time from VIN Invalid to Shutdown tshutdown EN Output Resistance REN IEN = 1mA - 100 - EN Output Low Vol IEN = 1mA - 0.1 - V EN Pull-down Current Ipulld EN = 1V 10 15 - mA Delay to Subsequent EN Turn-on/off RTX = 120k 155 195 240 ms tdel_3 RTX = 3k 3.5 4.7 6 ms tdel_0 RTX = 0 - 0.5 - ms tdel_120 SEQUENCE EN AND FAULT I/O VIN Valid to FAULT Low tFLTL 15 30 50 s VIN Invalid to FAULT High tFLTH - 0.5 - s 10 15 - mA - 2.4 - V FAULT Pull-down Current SEQ_EN Pull-up Voltage FAULT = 1V VSEQ SEQ_EN open SEQ_EN Low Threshold Voltage VilSEQ_EN - - 0.3 V SEQ_EN High Threshold Voltage VihSEQ_EN 1.2 - - V Delay to EN_A Deasserted tSEQ_EN_ENA - 0.2 1 s SEQ_EN low to EN_A low Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 May 28, 2014 May 2014 Altera Corporation Rev A Page 5 Electrical Specifications Nominal VIN = 3.3V to +24V, TA = TJ = -40C to+85C, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT BIAS IC Supply Current VIN Power On Reset IVIN_3.3V VIN = 3.3V - 191 - A IVIN_12V VIN = 12V - 246 400 A IVIN_24V VIN = 24V - 286 - A VIN_POR VIN low to high - 2.3 2.8 V Functional Block Diagram VIN (2.8V MIN - 27V MAX) VIN VREF VOLTAGE REFERENCE 1.17V VIN 3.5V SEQ_EN UV + eo + OV INTERNAL VOLTAGE REGULATOR 2.0V VIN POR LOGIC - EN_A EN_B FAULT 30s GND EN_C VTIME_VTH EN_D PROGRAMMABLE DELAY TIMER VIN 2.6A TIME TDLY_AB TDLY_BC TDLY_CD Functional Description ES1022SI provides four delay adjustable sequenced outputs while monitoring a single distributed voltage in the nominal range of 3.3V to 24V for both under and overvoltage. Only when the voltage is in compliance will the ES1022SI initiate the pre-programmed A-B-C-D sequence of the EN outputs. Although this IC has a bias range of 3.3V to 24V it can monitor any voltage >1.22V via the external divider if a suitable bias voltage is otherwise provided. During initial bias voltage (VIN) application the ES1022SI EN outputs are held low once VIN = 1V. Once VIN > the V bias power on reset threshold (POR) of 2.8V, VIN is constantly monitored for compliance via the input voltage resistor divider and the voltages on the UV and OV pins and reported by the FAULT output. Internally, voltage regulators generate 3.5V and 1.17V 5% voltage rails for internal usage once VIN > POR. Once UV > 1.22V and with the SEQ_EN pin high or open, the auto sequence of the four EN outputs begins as the TIME pin charges its external capacitor with a 2.6A current source. The voltage on TIME is compared to the internal reference (VTIME_VTH) comparator input and when greater than VTIME_VTH the EN_A is released to go high via an external pull-up resistor or a pull-up in a DC/DC convertor EN input, for example. The time delay generated by the external capacitor is to assure continued voltage compliance within the programmed limits, as during this time any OV or UV condition will halt the start-up process. TIME cap is discharged once VTIME_VTH is met. May 2014 10037 Altera Corporation Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer May 28, 2014 Rev A Page 6 Once EN_A is active (released high on the ES1022SI) a counter is started and using the resistor on TDLY_AB as a timing component a delay is generated before EN_B is activated. At this time, the counter is restarted using the resistor on TDLY_BC as its timing component for a separate timed delay until EN_C is activated. This process is repeated for the resistor on TDLY_CD to complete the A-B-C-D sequencing order of the EN outputs. At any time during sequencing if an OV or UV event is registered, all four EN outputs will immediately return to their low reset state. CTIME is immediately discharged after initial ramp up thus waiting for subsequent voltage compliance to restart. Once sequencing is complete, any subsequently registered UV or OV event will trigger an immediate and simultaneous reset of all EN outputs. On the ES1022SI, enabling of on or off sequencing can also be signaled via the SEQ_EN input pin once voltage compliance is met. Initially, the SEQ_EN pin should be held low and released when sequence start is desired. SEQ_EN is internally pulled high and sequencing is enabled unless it is pulled low. The on sequence of the EN outputs is as previously described. The off sequence is D off, then C off, then B off and finally A off. Once SEQ_EN is signaled low, the TIME cap is charged to 2V once again. Once this Vth is reached, EN_D transitions to its reset state and CTIM is discharged. A delay and subsequent sequence off is then determined by TDLY_CD resistor to EN_C. Likewise, a delay to EN_B and then EN_A turn-off is determined by TDLY_BC and TDLY_AB resistor values respectively. The FAULT signal is always valid at operational voltages and can be used as justification for SEQ_EN release or even controlled with an RC timer for sequence on. Programming the Under and Overvoltage Limits When choosing resistors for the divider remember to keep the current through the string bounded by power loss at the top end and noise immunity at the bottom end. For most applications, total divider resistance in the 10k to1000k range is advisable with high precision resistors being used to reduce monitoring error. Although for the ES1022SI, two dividers of two resistors each can be employed to separately monitor the OV and UV levels for the VIN voltage. We will discuss using a single three resistor string for monitoring the VIN voltage, referencing Figure 1. In the three resistor divider string with Ru (upper), Rm (middle) and Rl (lower), the ratios of each in combination to the other two is balanced to achieve the desired UV and OV trip levels. Although this IC has a bias range of 3.3V to 24V, it can monitor any voltage >1.22V. The ratio of the desired overvoltage trip point to the internal reference is equal to the ratio of the two upper resistors to the lowest (gnd connected) resistor. The ratio of the desired undervoltage trip point to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. These assumptions are true for both rising (turn-on) or falling (shutdown) voltages. The following is a practical example worked out. For detailed equations on how to perform this operation for a given supply requirement please see the next section. 1. Determine if turn-on or shutdown limits are preferred. In this example, we will determine the resistor values based on the shutdown limits. 2. Establish lower and upper trip level: 12V 10% or 13.2V (OV) and 10.8V (UV) 3. Establish total resistor string value: 100k, Ir = divider current 4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV 5. Rm+Rl = 1.1V/Ir @ UV = Rm+Rl = 1.1V/(10.8V/100k) = 10.370k 6. Rl = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100k) = 9.242k 7. Rm = 10.370k - 9.242k = 1.128k 8. Ru = 100k - 10.370k = 89.630k 9. Choose standard value resistors that most closely approximate these ideal values. Choosing a different total divider resistance value may yield a more ideal ratio with available resistor's values. In our example, with the closest standard values of Ru = 90.9k, Rm = 1.13k and Rl = 9.31k, the nominal UV falling and OV rising will be at 10.9V and 13.3V respectively. Programming the EN Output Delays The delay timing between the four sequenced EN outputs are programmed with four external passive components. The delay from SEQ_EN being valid to EN_A is determined by the value of the capacitor on the TIME pin to GND. The external TIME pin capacitor is charged with a 2.6A current source. Once the voltage on TIME is charged up to the internal Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 May 28, 2014 May 2014 Altera Corporation Rev A Page 7 reference voltage, (VTIME_VTH) the EN_A output is released out of its reset state. The capacitor value for a desired delay (10%) to EN_A once VIN and SEQ_EN where applicable has been satisfied is determined by: CTIME = tVINSEQpd/770k Once EN_A reaches VTIME_VTH, the TIME pin is pulled low in preparation for a sequenced off signal via SEQ_EN. At this time, the sequencing of the subsequent outputs is started. EN_B is released out of reset after a programmable time, then EN_C, then EN_D, all with their own programmed delay times. The subsequent delay times are programmed with a single external resistor for each EN output providing maximum flexibility to the designer through the choice of the resistor value connected from TDLY_AB, TDLY_BC and TDLY_CD pins to GND. The resistor values determine the charge and discharge rate of an internal capacitor comprising an RC time constant for an oscillator whose output is fed into a counter generating the timing delay to EN output sequencing. The RTX value for a given delay time is defined as: RTX = tdel/1667nF An Advanced Tutorial on Setting UV and OV Levels This section discusses in additional detail the nuances of setting the UV and OV levels, providing more insight into the ES1022SI than the earlier text. The following equation set can alternatively be used to work out ideal values for a 3 resistor divider string of Ru, Rm and Rl. These equations assume that VREF is the center point between VUVRvth and VUVFvth (i.e. (VUVRvth + VUVFvth)/2 = 1.17V), Iload is the load current in the resistor string (i.e. VIN /(Ru + Rm + Rl)), VIN is the nominal input voltage and Vtol is the acceptable voltage tolerance, such that the UV and OV thresholds are centered at VIN Vtol. The actual acceptable voltage window will also be affected by the hysteresis at the UV and OV pins. This hysteresis is amplified by the resistor string such that the hysteresis at the top of the string is: Vhys = VUVhys x VOUT/VREF This means that the VIN Vtol thresholds will exhibit hysteresis resulting in thresholds of VIN + Vtol Vhys/2 and VIN - Vtol Vhys/2. There is a window between the VIN rising UV threshold and the VIN falling OV threshold where the input level is guaranteed not to be detected as a fault. This window exists between the limits VIN (Vtol - Vhys/2). There is an extension of this window in each direction up to VIN (Vtol + Vhys/2), where the voltage may or may not be detected as a fault, depending on the direction from which it is approached. These two equations may be used to determine the required value of Vtol for a given system. For example, if VIN is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If VIN must remain within 12V 1.5V, Vtol = 1.5 - 1.03/2 = 0.99V. This will give a window of 12 0.48V where the system is guaranteed not to be in fault and a limit of 12 1.5V beyond which the system is guaranteed to be in fault. It is wise to check both these voltages, for if the latter is made to tight, the former will cease to exist. This point comes when Vtol < Vhys/2 and results from the fact that the acceptable window for the OV pin no longer aligns with the acceptable window for the UV pin. In this case, the application will have to be changed such that UV and OV are provided separate resistor strings. In this case, the UV and OV thresholds can be individually controlled by adjusting the relevant divider. The previous example will give voltage thresholds of: with VIN rising UVr = VIN - Vtol + Vhys/2 = 11.5V and OVr = VIN + Vtol + Vhys/2 = 13.5V with VIN falling Ovf = VIN + Vtol - Vhys/2 = 12.5V and UVf = VIN - Vtol - Vhys/2 = 10.5V. So with a single three resistor string, the resistor values can be calculated as: Rl = (VREF/Iload) (1 - Vtol/VIN) Rm = 2(VREF x Vtol)/(VIN x Iload) Ru = 1/Iload x (VIN - VREF (1+Vtol/VIN)) May 2014 10037 Altera Corporation Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer May 28, 2014 Rev A Page 8 For the above example, with Vtol = 0.99V, assuming a 100A Iload at VIN = 12V: Rl = 10.7k Rm = 1.9k Ru = 107.3k FAULT SEQ_EN TIME A EN OUTPUTS B C D D C B A FIGURE 2. ES1022SI OPERATIONAL DIAGRAM OVERVOLTAGE LIMIT tFLTH tFLTL <tFLTH UNDERVOLTAGE LIMIT MONITORED VOLTAGE RAMPING UP AND DOWN tFLTL tFLTH FAULT OUTPUT FIGURE 3. ES1022SI FAULT OPERATIONAL DIAGRAM Typical Performance Curves 1.208 310 1.207 290 1.204 250 VIN = 2.5V VIN = 12V 1.203 1.202 1.201 VIN = 12V 230 210 190 1.200 VIN = 24V 1.199 VIN = 2.5V 170 150 1.198 -40 -10 0 25 60 85 100 -40 -10 0 25 60 85 100 TEMP (C) TEMP (C) FIGURE 5. VIN CURRENT FIGURE 4. UV/OV RISING THRESHOLD Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 VIN = 24V 270 1.205 IVIN (A) UV/OV THRESHOLD (V) 1.206 May 28, 2014 May 2014 Altera Corporation Rev A Page 9 Applications Usage Using the EVB-ES1022SI Platform The EVB-ES1022SI platform is the primary evaluation board for this family of sequencers. See Figure 15 for photograph and schematic. The evaluation board is shipped with an ES1022SI mounted in the left position and with the other device variants loose packed. In the following discussion, test points names are bold on initial occurrence for identification. The VIN test point is the chip bias and can be biased from 3.3V to 24V. The VHI test point is for the EN and FAULT pull-up voltage which are limited to a maximum of 24V independent of VIN. The UV/OV resistor divider is set so that a nominal 12V on the VMONITOR test point is compliant and with a rising OV set at 13.2V and a falling UV set at 10.7V. These three test points (VIN,VHI and VMONITOR) are brought out separately for maximum flexibility in evaluation. VMONITOR ramping up and down through the UV and OV levels will result in the FAULT output signaling the out of bound conditions by being released to pull high to the VHI voltage as shown in Figures 6 and 7. Once the voltage monitoring FAULT is resolved and where applicable, the SEQ_EN is satisfied, sequencing of the EN_X outputs begins. When sequence enabled the EN_A, EN_B, EN_C and lastly EN_D are asserted in that order and when SEQ_EN is disabled the order is reversed. See Figures 8 and 9 demonstrating the sequenced enabling and disabling of the EN outputs. The timing between EN outputs is set by the resistor values on the TDLY_AB, TDLY_BC, TDLY_CD pins as shown. Figure 10 illustrates the timing from either SEQ_EN and/or VMONITOR being valid to EN_A being asserted with a 10nF TIME capacitor. Figure 11 shows that EN_X outputs are pulled low even before VIN = 1V. This is critical to ensure that a false EN is not signaled. Figure 12 shows the time from SEQ_EN transition with the voltage ramping across the TIME capacitor to TIME Vth being met. This results in the immediate pull down of the TIME pin and simultaneous EN_A enabling. VMON FALLING VMON RISING VMON > UV LEVEL VMON > OV LEVEL VMON > OV LEVEL FAULT OUTPUT FAULT OUTPUT FIGURE 6. VMONITOR RISING TO FAULT May 2014 10037 VMON > UV LEVEL FIGURE 7. VMONITOR FALLING TO FAULT Altera Corporation Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer May 28, 2014 Rev A Page 10 RTDLY_AB = 3k RTDLY_AB = 3k DELAY = 5ms DELAY = 5ms RTDLY_BC = 51k RTDLY_CD = 120k DELAY = 196ms DELAY = 86ms RTDLY_BC = 51k DELAY = 86ms RTDLY_CD = 120k DELAY = 196ms FIGURE 9. EN_X TO EN_X DISABLING FIGURE 8. EN_X TO EN_X ENABLING VIN RISING CTIME = 10nF DELAY = 8.5ms EN OUTPUTS TRACKS VIN TO < 0.8V 1V/DIV 10ms/DIV FIGURE 11. EN AS VIN RISES FIGURE 10. VIN/SEQ_EN VALID TO EN_A VMONITOR OV SEQ_EN EN_A VMONITOR UV TIME 0.5V/DIV FAULT = LOW 8s/DIV FIGURE 13. OV AND UV TRANSIENT IMMUNITY FIGURE 12. SEQ_EN TO EN_A Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 May 28, 2014 May 2014 Altera Corporation Rev A Page 11 Application Recommendations Best practices VIN decoupling is required, a 1F capacitor is recommended. Coupling from the EN_X pins to the sensitive UV and OV pins can cause false OV/UV events to be detected. This is relevant due to the EN_A and OV pins being adjacent. This coupling can be reduced by adding a ground trace between UV and the EN/FAULT signals, as shown in Figure 14. The PCB traces on OV and UV should be kept as small as practical and the EN_X and FAULT traces should ideally not be routed under/over the OV/UV traces on different PCB layers unless there is a ground or power plane in between. Other methods that can be used to eliminate this issue are by reducing the value of the resistors in the network connected to UV and OV (R2, R3, R5 in Figure 15) or by adding small decoupling capacitors to OV and UV (C2 and C7 in Figure 15). Both these methods act to reduce the AC impedance at the nodes, although the latter method acts to filter the signals which will also cause an increase in the time that a UV/OV fault takes to be detected. When the ES1022SI is implemented on a hot swappable card that is plugged into an always powered passive back plane an RC filter is required on the VIN pin to prevent a high dv/dt transient. With the already existing 1F decoupling capacitor the addition of a small series R (>50) to provide a time constant >50s is all that is necessary. PIN 4 GND PIN 5 FIGURE 14. LAYOUT DETAIL OF GND BETWEEN PINS 4 AND 5 May 2014 10037 Altera Corporation Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer May 28, 2014 Rev A Page 12 . PULL-UP RESISTORS TIMING COMPONENTS UV/OV SET RESISTORS EN_A EN_B EN_C EN_D TDLY_CD TDLY_BC TDLY_AB ES1022SI FIGURE 15. EVB-ES1022SI PHOTOGRAPH AND SCHEMATIC OF LEFT CHANNEL TABLE 1. EVB-ES1022SI LEFT CHANNEL COMPONENT LISTING COMPONENT DESIGNATOR COMPONENT FUNCTION COMPONENT DESCRIPTION U1 ES1022SI, Quad Under/Overvoltage Sequencer Altera Enpirion, ES1022SI, Quad Under/Overvoltage Sequencer R3 UV Resistor for Divider String 1.1k 1%, 0603 R2 VMONITOR Resistor for Divider String 88.7k 1%, 0603 R5 OV Resistor for Divider String 9.1k 1%, 0603 C1 CTIME Sets Delay from Sequence Start to First EN 0.01F, 0603 R1 RTDLY_CD Sets Delay from Third to Fourth EN 120k 1%, 0603 R9 RTDLY_AB Sets Delay from First to Second EN 3.01k 1%, 0603 R7 RTDLY_BC Sets Delay from Second to Third EN 51k 1%, 0603 R4, R6, R8, R10, R11 EN_X and FAULT Pull-up Resistors C3 4k 10%, 0402 Decoupling Capacitor 1F, 0603 Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 May 28, 2014 May 2014 Altera Corporation Rev A Page 13 Revision History The table lists the revision history for this document. DATE REVISION May, 2014 1.0 May 2014 10037 CHANGE Initial Release. Altera Corporation Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer May 28, 2014 Rev A Page 14 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC N INDEX AREA H 0.25(0.010) M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- A1 B C 0.10(0.004) C A M B S MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 N a NOTES: MILLIMETERS SYMBOL e e 0.25(0.010) M MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M 14 0o 1.27 6 14 8o 0o 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. Enpirion Power Datasheet ES1022SI Adjustable Quad Sequencer 10037 May 28, 2014 May 2014 Altera Corporation Rev A