MPC8308CVMAGD - Freescale Semiconductor, Inc.

Freescale Semiconductor

This document provides an overview of the MPC8308

features and its hardware specifications, including a block

diagram showing the major functional components. The

MPC8308 is a cos t -effective, low-power, highly integrated

host processor. The MPC8308 extends the PowerQUICC

family, adding higher CPU performance, additional

functionality, and faster interfaces while addressing the

requirements related to time-to-market, price, power

consumption, and package size.

NOTE

The information provided in this document is

preliminary and is based on estimates only and refers to

the pre-silicon phase, with no device characterization

done. Freescale reserves the right to change the

contents of this document as appropriate.

1Overview

Figure 1 shows the major functional units within the

MPC8308. The e300 core in the MPC8308, with its 16

Kbytes of instruction and 16 Kbytes of data cache,

implem ents the Power Architec ture user instruction set

architecture and provides hardware and software debugging

Document Number: MPC8308EC

Rev. 1, 07/2010

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 2

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8. Ethernet: Three-Speed Ethernet, MII Management . 15

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10. High-Speed Seri al Int erfaces ( H SSI) . . . . . . . . . . . . 24

11. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

12. Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 43

13. Enhanced Secure Digital H ost Cont ro ller (eSDHC) . 47

14. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

18. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

19. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

20. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 62

21. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

22. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

23. System Design Information . . . . . . . . . . . . . . . . . . . 81

24. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 85

25. Document Revision History . . . . . . . . . . . . . . . . . . . 86

MPC8308 PowerQUICC II Pro

Processor Hardware Specification

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

2Freescale Semiconductor

Electrical Characteristics

support. In addition, the MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps

Ethernet controllers (eTSEC), a DDR2 SDRAM memory controller, a SerDes block, an enhanced local

bus controller (eLBC), an integrated programmabl e interrupt controller (IPIC), a general purpose DMA

controller, two I2C controllers, dual UART (DUART), GPIOs, USB, general purpose timers, and an SPI

controller . The high level of integration in the MPC8308 helps simplify board design and offers significant

bandwidth and performance.

A block diagram of the device is shown in Figure 1.

Figure 1. MPC8308 Block Diagram

2 Electrical Characteristics

This section provides th e AC and DC electrical specif i cati ons and the rmal charact er isti cs f or the

MPC8308. The device is currently targeted to these specifi cations. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings .

Table 1. Absolute Maximum Ratings1

Characteristic Symbol Max Value Unit Notes

Core supply voltage VDD –0.3 to 1.26 V —

PLL supply voltage AVDD1, AVDD2 –0.3 to 1.26 V —

DDR2 DRAM I/O voltage GVDD –0.3 to 1.9 V —

eTSEC1

DUART

Interrupt

I2C

Timers

GPIO, SPI

Enhanced DDR2

Controller

Controller Local Bus

PCI

Express

DMA

RGMII,MII

16-Kbyte

D-Cache

16-Kbyte

I-Cache

e300c3 Core with

Power Management

FPU

Enhanced

Secure

Digital Host

Controller

USB 2.0 HS

Host/Device/OTG eTSEC2

RGMII,MII

ULPI

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 3

Electrical Characteristics

2.1.2 Power Supply Voltage Specification

Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are

the recommended and tested operating conditions. Proper device operation outside of these conditions is

not guaranteed.

Local bus, DUART, system control and power management,

eSDHC, I2C, USB, Interrupt, Ethernet management, SPI,

Miscellaneous and JTAG I/O voltage

NVDD –0.3 to 3.6 V 7

SERDES PHY XCOREVDD,

XPADVDD,

SDAVDD

–0.3 to 1.26 V —

eTSEC I/O Voltage LVDD1, LVDD2 –0.3 to 2.75 or

–0.3 to 3.6

V6,8

Input voltage DDR2 DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5

DDR2 DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5

eTSEC LVIN –0.3 to (LVDD + 0.3) V 4, 5,8

Local bus, DUART, system control and power

management, eSDHC, I2C, Interrupt,

Ethernet management, SPI, Miscellaneous

and JTAG I/O voltage

OVIN –0.3 to (NVDD + 0.3) V 3, 5,7

Storage temperature range TSTG –55 to 150 °C—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OVIN must not exceed NVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: LV IN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

5. (M, L, O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2

6. The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.

7. NVDD here refers to NVDDA, NVDDB,NVDDG, NVDDH, NVDDP_K from the ball map.

8. LVDD1 here refers to NVDDC and LVDD2 refers to NVDDF from the ball map

Table 2. Recommended Operating Conditions

Characteristic Symbol Recommended Value1Unit

SerDes internal digital power XCOREVDD 1.0 V ± 50 mV V

SerDes internal digital power XCOREVSS 0.0 V

SerDes I/O digital power XPADVDD 1.0 V ± 50 mV V

SerDes analog power for PLL SDAVDD 1.0 V ± 50 mV V

Table 1. Absolute Maximum Ratings1 (continued)

Characteristic Symbol Max Value Unit Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

4Freescale Semiconductor

Electrical Characteristics

SerDes analog power for PLL SDAVSS 0V

SerDes I/O digital power XPADVSS 0V

Core supply voltage VDD 1.0V±50mV V

Analog supply for e300 core APLL AVDD1 1.0V±50mV V

Analog supply for system APLL AVDD2 1.0V±50mV V

DDR2 DRAM I/O voltage GVDD 1.8 V ± 100 mV V

Differential reference voltage for DDR controller MVREF GVDD/2 (0.49 ×GVDD to

0.51 ×GVDD)

Standard I/O voltage (Local bus, DUART, system control and power

management, eSDHC, USB, I2C, Interrupt, Ethernet management,

SPI, Miscellaneous and JTAG I/O voltage)2

NVDD 3.3 V ± 300 mV V

eTSEC IO supply3,4 LVDD1, LVDD2 2.5 V ± 125 mV

3.3 V ± 300 mV

Analog and digital ground VSS 0.0 V

Junction temperature5TA/TJ0 to 105 °C

Notes:

1GVDD, NVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative

direction.

2NVDD here refers to NVDDA, NVDDB,NVDDG, NVDDH and NVDDP_K from the ball map.

3The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.

4LVDD1 here refers to NVDDC and LVDD2 refers to NVDDF from the ball map.

5Minimum temperature is specified with TA; Maximum temperature is specified with TJ.

Table 2. Recommended Operating Conditions (continued)

Characteristic Symbol Recommended Value1Unit

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 5

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device

Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD

2.1.3 Output Driver Characteristics

Table 3 provides information on the characteristics of th e output driver strengths.

2.1.4 Power Sequencing

The device does not r equir e the core supply voltage (V DD) and I/O supply voltages (GVDD, LVDD, and

NVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies

are stable and if the I/O voltages are supplied before the core vol tage, there might be a period of time that

all input and output pins are actively dri ven and cause contention and excessive current. In order to avoid

actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before

the I/O voltage (GVDD, LVDD, and NVDD) and assert PORESET before the power supplies fully ramp up.

In the case where the core volt age is applied f irst, the core voltage supply mus t rise to 90% of its nominal

value before the I/O supplies reach 0.7 V; see Figure 3.

Table 3. Output Driver Capability

Driver Type Output Impedance (Ω) Supply Voltage

Local bus interface utilities signals 42 NVDD = 3.3 V

DDR2 signals1

1Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).

For more information, see the

MPC8308 PowerQUICC II Pro Processor Reference Manual

18 GVDD = 1.8 V

DUART, system control, I2C, JTAG, eSDHC, GPIO,SPI, USB 42 NVDD = 3.3 V

eTSEC signals 42 LVDD = 2.5/3.3 V

VSS

VSS – 0.3 V

VSS – 0.7 V Not to Exceed 10%

G/L/NVDD + 20%

G/L/NVDD

G/L/NVDD + 5%

of tinterface1

1. Note that tinterface refers to the clock period associated with the bus clock interface.

VIH

VIL

Note:

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

6Freescale Semiconductor

Power Characteristics

The I/O power supply ramp-up slew rate should be slower than 4V/100 μs; this requirement is for ESD

circuit.

Note that there is no specific power-down sequence requirement for the device. I/O voltage supplies

(GVDD, LVDD, and NVDD) do not have any orderi ng requirements with respect to one another.

Figure 3. Power-Up Sequencing Example

3 Power Characteristics

The estimated typical power dissipation, not including I/O supply power for the device is shown in Table 4.

Table 5 shows the estimated typical I/O power dissipation.

Table 4. MPC8308 Power Dissipation1

1The values do not include I/O supply power but do include core (AVDD) and PLL (AVDD1,

AVDD2, XCOREVDD

, XPADVDD, SDAVDD)

Core Frequency (MHz) CSB Frequency (MHz) Typical2

2Typical power is based on best process, a voltage of VDD = 1.0V and ambient temperature

of TA = 25° C

Maximum3

3Maximum power is estimated based on best process, a voltage of VDD = 1.05 V and

ambient temperature of TJ = 105° C

Unit

266 133 530 900 mW

333 133 565 950 mW

400 133 600 1000 mW

Notes:

90%

Core Voltage (VDD)

I/O Voltage (GVDD, LVDD, and NVDD)

0.7 V

PORESET

>= 32 ×tSYS_CLK_IN

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 7

Clock Input Timing

Table 5 describes a typical scenario where blocks with the stated percentage of utilization and impedances

consume the amount of power described.

4 Clock Input Timing

This section provides the clock input DC and AC electrical character istics for the device.

4.1 DC Electrical Characteristics

Table 6 provides the system clock input (SYS_CLK_IN) DC electrical specifications for the device.

Table 7 provides the RTC clock input ( RTC_PIT_CLOCK) DC electrical specifications for the device.

Table 5. MPC8308 Typical I/O Power Dissipation

Interface Parameter GVDD

(1.8 V)

NVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V) Unit Comments

DDR2

Rs = 22 Ω

Rt = 75 Ω

250 MHz

32 bits+ECC

266 MHz

32 bits+ECC

0.302

0.309

—— —W—

Local bus I/O load = 20 pF 62.5 MHz

66 MHZ

— 0.038

0.040

——W—

TSEC I/O load = 20 pF MII,

25 MHz

— — 0.008 — W 2 controllers

RGMII,

125 MHz

— — 0.078 0.044 W

eSDHC IO Load = 40 pF 50 MHz — — 0.008 — W —

USB IO Load = 20 pF 60 MHz — — 0.012 W —

Other I/O — — 0.017 — — W —

Table 6. SYS_CLK_IN DC Electrical Characteristics

Parameter Condition Symbol Min Max Unit

Input high voltage — VIH 2.4 NVDD +0.3 V

Input low voltage — VIL –0.3 0.4 V

SYS_CLK_IN input current 0 V ≤VIN ≤NVDD IIN —±10μA

Table 7. RTC_PIT_CLOCK DC Electrical Characteristics

Parameter Condition Symbol Min Max Unit

Input high voltage — VIH 3.3V – 400 mV V

Input low voltage — VIL 00.4V

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

8Freescale Semiconductor

RESET Initialization

4.2 AC Electrical Characteristics

The primary clock source for the device is SYS_CLK_IN. Table 8 provides the system clock input

(SYS_CLK_IN) AC timing specifications for the device.

Table 9. RTC_PIT_CLOCK AC Timing Specifications

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electri cal requir ement s of the device.

5.1 RESET DC Electrical Characteristics

Table 10 provides the DC electrical characteristics for the RESET pins.

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter Symbol Min Typ Max Unit Notes

SYS_CLK_IN frequency fSYS_CLK_IN 24 — 66.67 MHz 1, 6

SYS_CLK_IN period tSYS_CLK_IN 15 — 41.67 ns —

SYS_CLK_IN rise and fall time tKH, tKL 0.6 1.2 ns 2

SYS_CLK_IN duty cycle tKHK/tSYS_CLK_IN 40 — 60 % 3

SYS_CLK_IN Jitter — — — ±150 ps 4, 5

Notes:

1. Caution: The system and core must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYS_CLK_IN are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread @ 33 kHz (max rate).

Parameter Symbol Min Typ Max Unit Notes

RTC_PIT_CLOCK frequency fRTC_PIT_CLOCK 1 32768 — Hz —

RTC_PIT_CLOCK rise and fall time tRTCH, tRTCL 1.5 — 3 μs—

RTC_PIT_CLOCK duty cycle tRTCHK/tRTC_PIT_CLO

45 — 55 % —

Table 10. RESET Pins DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage VIH —2.0NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN 0 V ≤ VIN ≤ NVDD ±5 μA

Output high voltage VOH IOH = –8.0 mA 2.4 — V

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 9

RESET Initialization

5.2 RESET AC Electrical Characteristics

Table 11 provides the reset initializa tion AC timing specifications .

Table 12 provides the PLL lock times.

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Table 11. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET (input) to activate reset flow 32 — tSYS_CLK_IN 1

Required assertion time of PORESET with stable power and clock applied to

SYS_CLK_IN

32 — tSYS_CLK_IN —

HRESET assertion (output) 512 — tSYS_CLK_IN 1

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with

respect to negation of PORESET

4—t

SYS_CLK_IN —

Input hold time for POR configuration signals with respect to negation of HRESET 0— ns —

Time for the device to turn off POR configuration signal drivers with respect to the

assertion of HRESET

—4 ns 2

Time for the device to turn on POR configuration signal drivers with respect to the

negation of HRESET

1 — ns 1, 2

Notes:

1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN

2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]

Table 12. PLL Lock Times

Parameter/Condition Min Max Unit Notes

System PLL lock time — 100 μs—

e300 core PLL lock time — 100 μs—

Table 10. RESET Pins DC Electrical Characteristics (continued)

Characteristic Symbol Condition Min Max Unit

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

10 Freescale Semiconductor

DDR2 SDRAM

6 DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface. Note that

DDR2 SDRAM is GVDD(typ) = 1.8 V.

6.1 DDR2 SDRAM DC Electrical Characteristics

Table 13 provides the recommended operating conditions for t he DDR2 SDRAM component(s) when

GVDD(typ) = 1.8 V.

Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 1.7 1.9 V 1

I/O reference voltage MVREF 0.49 ×GVDD 0.51 × GVDD V2

I/O termination voltage VTT MVREF –0.04 MV

REF + 0.04 V 3

Input high voltage VIH MVREF +0.125 GV

DD +0.3 V —

Input low voltage VIL –0.3 MVREF – 0.125 V —

Output leakage current IOZ –9.9 9.9 μA4

Output high current (VOUT = 1.420 V) IOH –13.4 — mA —

Output low current (VOUT = 0.280 V) IOL 13.4 — mA —

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, V

OUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 11

DDR2 SDRAM

Table 15 provides the current draw character i stics f or MV REF.

6.2 DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR2 S DRAM interface.

6.2.1 DDR2 SDRAM Input AC Timing Specifications

Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8V.

Table 17 provides the input AC timing specifications for the DDR2 SDRAM interface.

Table 15. Current Draw Characteristics for MVREF

Parameter/Condition Symbol Min Max Unit Note

Current draw for MVREF IMVREF — 500 μA1

Note:

1. The voltage regulator for MVREF must be able to supply up to 500 μA current.

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface

At recommended operating conditions with GVDD of 1.8 ± 100 mV

Parameter Symbol Min Max Unit Notes

AC input low voltage VIL —MV

REF – 0.45 V —

AC input high voltage VIH MVREF + 0.45 — V —

Table 17. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions. with GVDD of 1.8± 100 mV

Parameter Symbol Min Max Unit Notes

Controller skew for MDQS—MDQ/MECC @266 MHz tCISKEW –875 875 ps 1, 2,3

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called tDISKEW. This can

be determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is

the absolute value of tCISKEW.

3. Memory controller ODT value of 150 Ω is recommended

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

12 Freescale Semiconductor

DDR2 SDRAM

Figure 4 illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter.

Figure 4. Timing Diagram for tDISKEW

6.2.2 DDR2 SDRAM Output AC Timing Specifications

Table 18. DDR2 SDRAM Output AC Timing Specifications

Parameter Symbol 1Min Max Unit Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 7.5 10 ns 2

ADDR/CMD output setup with respect to MCK tDDKHAS ns 3

266 MHz 2.9 —

ADDR/CMD output hold with respect to MCK tDDKHAX ns 3

266 MHz 2.33 —

MCS[n] output setup with respect to MCK tDDKHCS ns 3

266 MHz 3.15 —

MCS[n] output hold with respect to MCK tDDKHCX ns 3

266 MHz 3.15 —

MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4

MDQ//MDM/MECC output setup with respect to

MDQS

tDDKHDS,

tDDKLDS

ps 5

266 MHz 900 —

MDQ//MDM/MECC output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

ps 5

266 MHz 1100 —

MCK[n]

MCK[n] tMCK

MDQ[x]/

MDQS[n]

tDISKEW

D1D0

tDISKEW

MECC[x]

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 13

DDR2 SDRAM

Figure 5 s hows the DDR2 SDRAM output timing for the MCK to MDQS skew meas urement (tDDKHMH).

Figure 5. Timing Diagram for tDDKHMH

MDQS preamble start tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK + 0.6 ns 6

MDQS epilogue end tDDKHME –0.6 0.6 ns 6

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH

describes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. For a description and understanding of the timing modifications enabled by use of these bits, see the

MPC8308 PowerQUICC II Pro Processor Reference Manual

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the

symbol conventions described in note 1.

Table 18. DDR2 SDRAM Output AC Timing Specifications (continued)

Parameter Symbol 1Min Max Unit Notes

MDQS

MCK[n]

tMCK

tDDKHMHmax) = 0.6 ns

tDDKHMH(min) = –0.6 ns

MDQS

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

14 Freescale Semiconductor

DUART

Figure 6 shows the DDR2 SDRAM output timing diagram.

Figure 6. DDR2 SDRAM Output Timing Diagram

Figure 7 provides the AC test load for the DDR2 bus.

Figure 7. DDR2 AC Test Load

7DUART

This section describes the DC and AC electrical specifi cations for the DUART interface.

7.1 DUART DC Electrical Characteristics

Table 19 provides the DC electrical characteristics for the DUART interface.

Table 19. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2.1 NVDD + 0.3 V

Low-level input voltage NVDD VIL –0.3 0.8 V

High-level output voltage, IOH = –100 μAV

OH NVDD – 0.2 — V

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]/

MDQS[n]

MCK[n]

MCK[n] tMCK

tDDKLDX

tDDKHDX

D1D0

tDDKHAX ,tDDKHCX

Write A0 NOOP

tDDKHME

tDDKHMP

MECC[x]

Output Z0 = 50 Ω

RL = 50 Ω

GVDD/2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 15

Ethernet: Three-Speed Ethernet, MII Management

7.2 DUART AC Electrical Specifications

Table 20 provides the AC timing parameters for the DUART interface.

8 Ethernet: Three-Speed Ethernet, MII Management

This section provides the AC and DC electrical c hara cteristics for three-speed, 10/100/1000, and MII

management. MP C8308 supports dual Ethernet controllers.

8.1 Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII Electrical Characteristics

The electrical characteristics specified here apply to all the media independent interface (MII) and reduced

gigabit media independent interface (RGMII) signals except management data input/output (MDIO) and

management data clock (MDC). The RGMII interface is defined for 2.5 V, while t he MII interface can be

operated at 3.3 V. The RGMII interface follows the Hewlett-Packard reduced pin-count interface for

Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical

characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface

Electri cal Char act er i stics.”

Low-level output voltage, IOL = 100 μAV

OL —0.2 V

Input current (0 V ≤VIN ≤ NVDD)I

IN —± 5μA

Table 20. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate 256 baud —

Maximum baud rate > 1,000,000 baud 1

Oversample rate 16 — 2

Notes:

1. Actual attainable baud rate is limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit.

Subsequent bit values are sampled each 16th sample.

Table 19. DUART DC Electrical Characteristics (continued)

Parameter Symbol Min Max Unit

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

16 Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.1.1 eTSEC DC Electrical Characteristics

All MI I a nd R GM II drivers and receivers co mply with the DC pa rame tric attributes spe ci fied in Table 21

and Table 22. The RGMII signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC

EIA/JESD8-5.

8.2 MII and RGMII AC Timing Specifications

The AC timing specifications for MII a nd RGMII are presented in this section.

8.2.1 MII AC Timing Specifications

This section describes the MII transm it and recei ve AC timing specificati ons.

Table 21. MII DC Electrical Characteristics

Parameter Symbol Conditions Min Max Unit

Supply voltage 3.3 V LVDD —3.03.6V

Output high voltage VOH IOH = –4.0 mA LVDD = Min 2.40 LVDD + 0.3 V

Output low voltage VOL IOL = 4.0 mA LVDD= Min VSS 0.50 V

Input high voltage VIH ——2.1LV

DD + 0.3 V

Input low voltage VIL — — –0.3 0.90 V

Input high current IIH VIN 1 = LVDD —40μA

Input low current IIL VIN 1 = VSS –600 — μA

Note:

1. The symbol VIN, in this case, represents the LVIN symbol referenced in Ta b le 1 and Ta b le 2 .

Table 22. RGMII DC Electrical Characteristics

Parameters Symbol Conditions Min Max Unit

Supply voltage 2.5 V LVDD — 2.37 2.63 V

Output high voltage VOH IOH = –1.0 mA LVDD = Min 2.00 LVDD + 0.3 V

Output low voltage VOL IOL = 1.0 mA LVDD= Min VSS – 0.3 0.40 V

Input high voltage VIH —LV

DD = Min 1.7 LVDD + 0.3 V

Input low voltage VIL —LV

DD = Min –0.3 0.70 V

Input high current IIH VIN 1 = LVDD —15μA

Input low current IIL VIN 1 = VSS –15 — μA

Note:

1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Ta b l e 1 and Ta b l e 2 .

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 17

Ethernet: Three-Speed Ethernet, MII Management

8.2.1.1 MII Transmit AC Timing Specifications

Table 23 provides the MII transmit AC timing specifications.

Figure 8 s hows the MII transmit AC timing diagram.

Figure 8. MII Transmit AC Timing Diagram

8.2.1.2 MII Receive AC Timing Specifications

Table 24 provides the MII recei ve AC timing specificati ons.

Table 23. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 0.3V.

Parameter/Condition Symbol 1Min Typ Max Unit

TX_CLK clock period 10 Mbps tMTX —400— ns

TX_CLK clock period 100 Mbps tMTX —40—ns

TX_CLK duty cycle tMTXH/tMTX 35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1 5 15 ns

TX_CLK data clock rise VIL(min) to VIH(max) tMTXR 1.0—4.0ns

TX_CLK data clock fall VIH(max) to VIL(min) tMTXF 1.0—4.0ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 24. MII Receive AC Timing Specifications

At recommended operating conditions with LVDD /NVDD of 3.3 V ± 0.3V.

Parameter/Condition Symbol 1Min Typ Max Unit

RX_CLK clock period 10 Mbps tMRX —400— ns

RX_CLK clock period 100 Mbps tMRX —40—ns

RX_CLK duty cycle tMRXH/tMRX 35 — 65 %

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

18 Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 9 shows the MII rec eive AC timing diagram.

Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications

Figure 10 provides the AC test load.

Figure 10. AC Test Load

8.2.2 RGMII AC Timing Specifications

Table 25 presents the RGMII AC timing specifica tions .

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns

RX_CLK clock rise VIL(min) to VIH(max) tMRXR 1.0—4.0ns

RX_CLK clock fall time VIH(max) to VIL(min) tMRXF 1.0—4.0ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII

receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference

(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 25. RGMII AC Timing Specifications

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter/Condition Symbol 1Min Typ Max Unit

Data to clock output skew (at transmitter) tSKRGT –0.6 — 0.6 ns

Data to clock input skew (at receiver) 2tSKRGT 1.0 — 2.6 ns

Table 24. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD /NVDD of 3.3 V ± 0.3V.

Parameter/Condition Symbol 1Min Typ Max Unit

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω or

LVDD/2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 19

Ethernet: Three-Speed Ethernet, MII Management

Figure 11 shows the RGMII AC timing and multiplexing diagrams.

Figure 11. RGMII AC Timing and Multiplexing Diagrams

Clock cycle duration 3tRGT 7.2 8.0 8.8 ns

Duty cycle for 1000Base-T 4, 5 tRGTH/tRGT 45 50 55 %

Duty cycle for 10BASE-T and 100BASE-TX 3, 5 tRGTH/tRGT 40 50 60 %

Rise time (20%–80%) tRGTR — — 0.75 ns

Fall time (20%–80%) tRGTF — — 0.75 ns

GTX_CLK125 reference clock period tG12 6—8.0—ns

GTX_CLK125 reference clock duty cycle tG125H/tG125 47 — 53 %

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII timing. For example, the subscript of tRGT represents the RGMII receive (RX) clock. Note also that the notation for rise

(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is

added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Duty cycle reference is 0.5*LVDD

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

Table 25. RGMII AC Timing Specifications (continued)

At recommended operating conditions with LVDD of 2.5 V ± 5%.

GTX_CLK

tRGT

tRGTH

tSKRGT

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKRGT

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

20 Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.3 Ethernet Management Interface Electrical Characteristics

The electrical char acter i stics specified here apply to MII management interf ace si gnals MDI O

(management data input/output) and MDC (management data clock). The electrical characteristics for MII

and RGMII are specified in Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII Electri cal Characteristics.”

8.3.1 MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. Table 26 provides the DC

electr ical chara ct er ist ics for MDI O and MDC.

8.3.2 MII Management AC Electrical Specifications

Table 27 provides the MII management AC timing specifi cations.

Table 26. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter Symbol Conditions Min Max Unit

Supply voltage (3.3 V) NVDD —3.03.6V

Output high voltage VOH IOH = –1.0 mA NVDD = Min 2.10 NVDD +0.3 V

Output low voltage VOL IOL = 1.0 mA LVDD = Min VSS 0.50 V

Input high voltage VIH —2.0—V

Input low voltage VIL ——0.80V

Input high current IIH NVDD = Max VIN 1 = 2.1 V — 40 μA

Input low current IIL NVDD = Max VIN = 0.5 V –600 — μA

Note:

1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Ta b le 1 and Ta b l e 2 .

Table 27. MII Management AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V

Parameter/Condition Symbol 1Min Typ Max Unit Notes

MDC frequency fMDC —2.5—MHz2

MDC period tMDC — 400 — ns —

MDC clock pulse width high tMDCH 32 — — ns —

MDC to MDIO delay tMDKHDX 10 — 170 ns 3

MDIO to MDC setup time tMDDVKH 5——ns—

MDIO to MDC hold time tMDDXKH 0——ns—

MDC rise time tMDCR — — 10 ns —

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 21

Ethernet: Three-Speed Ethernet, MII Management

Figure 12 shows the MII management AC timing diagram.

Figure 12. MII Management Interface Timing Diagram

8.4 IEEE Std 1588™ Timer Specifications

This section describes the DC and AC electrical specifications for the 1588 timer.

8.4.1 IEEE 1588 Timer DC Specifications

Table 28 provides the IEEE 1588 timer DC specifications.

MDC fall time tMDHF — — 10 ns —

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency

of the Mgmt Clock EC_MDC.)

3. This parameter is dependent on the cbs_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns).

Table 28. GPIO DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Input high voltage VIH — 2.0 NVDD + 0.3 V

Table 27. MII Management AC Timing Specifications (continued)

At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V

Parameter/Condition Symbol 1Min Typ Max Unit Notes

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

22 Freescale Semiconductor

USB

8.4.2 IEEE 1588 Timer AC Specifications

Table 29 provides the IEEE 1588 timer AC specifications.

9USB

9.1 USB Dual-Role Controllers

This section provides the AC and DC electrical specifications for the USB-ULPI interface.

9.1.1 USB DC Electrical Characteristics

Table 30 lists the DC electr ic al charac te ris t ics for the USB inte rf ace.

Input low voltage VIL — –0.3 0.8 V

Input current IIN 0 V ≤ VIN ≤ NVDD — ± 5 μA

Table 29. IEEE 1588 Timer AC Specifications

Parameter Symbol Min Max Unit Notes

Timer clock cycle time tTMRCK 070MHz1

Input setup to timer clock tTMRCKS ———2, 3

Input hold from timer clock tTMRCKH ———2, 3

Output clock to output valid tGCLKNV 06ns—

Timer alarm to output valid tTMRAL ——— 2

Notes:

1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected.

2. Asynchronous signals.

3. Inputs need to be stable at least one TMR clock.

Table 30. USB DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2 LVDD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current IIN —±5 μA

High-level output voltage, IOH = –100 μAV

OH LVDD – 0.2 — V

Low-level output voltage, IOL = 100 μAV

OL —0.2V

Note:

1. The symbol VIN, in this case, represents the NVIN symbol referenced in Ta bl e 1 and Table 2.

Table 28. GPIO DC Electrical Characteristics (continued)

Characteristic Symbol Condition Min Max Unit

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 23

USB

9.1.2 USB AC Electrical Specifications

Table 31 lists the general timing para mete rs of the USB-ULPI interface.

Figure 13 and Figure 14 provide the AC test load and signals for the USB, respectively.

Figure 13. USB AC Test Load

Figure 14. USB Signals

Table 31. USB General Timing Parameters

Parameter Symbol 1Min Max Unit Notes

USB clock cycle time tUSCK 15 — ns 1, 2

Input setup to USB clock—all inputs tUSIVKH 4—ns1, 4

Input hold to USB clock—all inputs tUSIXKH 1—ns1, 4

USB clock to output valid—all outputs tUSKHOV —9ns1

Output hold from USB clock—all outputs tUSKHOX 1—ns1

Notes:

1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing

(US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX

symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X)

or output hold time.

2. All timings are in reference to USB clock.

3. All signals are measured from NVDD/2 of the rising edge of USB clock to 0.4 ×NVDD of the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

Output Signals

tUSKHOV

USBDR_CLK

Input Signals

tUSIXKH

tUSIVKH

tUSKHOX

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

24 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

10 High-Speed Serial Interfaces (HSSI)

This section describes the common portion of SerDes DC electric al specificat ions, which is the DC

requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits

are also shown.

10.1 Signal Terms Definition

The SerDes utilizes dif ferential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of diffe rential signals.

Figure 15 shows how the signals are defined. For illus tration purpos e, only one SerD es lane is used for

description. The fi gure shows waveform f or either a tr ansmitte r output (T Xn and TXn) or a receiver input

(RXn and RXn) . Each signal swings between A Volts and B Volts where A > B .

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

1. Si ngle-Ended Swing

The transmitter output s ignals and the r eceiver input signals TXn, TXn, RXn, and RX n each have

a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’ s single-ended swing.

2. Differential Output Voltage, V OD (or Differential Output Swing)

The differential output voltage (or s wing) of the transmitter, VOD, is defined as the diff er ence of

the two complimentary output voltages: VTXn – VTXn. The VOD value can be either positive or

negative.

3. Differential Input Voltage, VID (or Dif ferential Input Swing )

The differential input voltage (or swing) of the receiver , VID, is defined as the difference of the two

complimentary input voltages: VRXn – VRXn. The VID value can be either positive or negative.

4. Differential Peak Voltage, VDIFFp

The peak value of the differential transmitter output signal or the diff erential r eceiver input s ignal

is defined as differential peak voltage, VDIFFp = |A – B| Volts.

5. Differential Peak-to-Peak, VDIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter

output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,

VDIFFp-p = 2*VDIFFp = 2 * |(A – B)| Volts, which is twice of differ ential swing in amplitude, or

twice of the diff erential peak. For example, the output differential peak–peak voltage can also be

calculated as VTX-DIFFp-p = 2*|VOD|.

6. Differential Waveform

The differential waveform is constructed by subtracting the inverting signal (TXn, for example)

from the non-inverting signal (TXn, for example) within a differential pair. There is only one signal

tra ce curve in a diff erentia l waveform. The voltag e represented in the diff erential wavef orm is not

referenced to ground. Refer to Figure 24 as an example for dif ferential waveform.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 25

High-Speed Serial Interfaces (HSSI)

7. Common Mode Voltage, Vcm

The common mode voltage is equal to one-half of the sum of the voltages between each conductor

of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VTXn

+ VTXn )/2 = (A + B) / 2, which is the arithmetic mean of the two complimenta ry output voltages

within a differentia l pair. In a system, the common mode voltage may often differ from one

component’s output to the other’ s input. Sometimes, it may be even dif ferent between the receiver

input and driver output circuits within the same component . It is also referred as the DC offset in

some occasion.

Figure 15. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these defini tions using real values, consider the case of a CML (curre nt mode logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Us ing these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p, which is referred as the singl e-ended swing for each sig nal. In this example, since

the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges

between 500 mV and –500 mV; in other words, VOD is 500 mV in one phase and –500 mV in the other

phase. The peak dif ferential voltage (VDIFFp) i s 500 mV. The peak-to-peak dif ferential voltage (VDIFFp-p)

is 1000 mV p-p.

10.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_RE F_CLK

for PCI Expr e ss.

The following sections describe the SerDes reference clock requirements and some application

information.

10.2.1 SerDes Reference Clock Receiver Characteristics

Figure 16 shows a receiver reference diagram of the SerDes reference clocks.

Differential Swing, VID or VOD = A – B

A Volts

B Volts

or RX

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak–Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)

Vcm = (A + B) / 2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

26 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

• The supply voltage r equirements for XCOREVDD are specified in Table 1 and Table 2.

• SerDes refer ence clock re cei ver refere nce circuit str u cture

— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown

in Figure 16. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω

termination to XCOREVSS followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single ended. Refer to the

Dif ferential Mode and Single-ended Mode description below for further detailed requirements.

• The maximum average curr ent requir ement that also determine s the common mode voltage range

— When th e SerDes reference clock differential inputs are DC-coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to th e following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V/50 = 8 mA) while the minimum common mode input level i s 0.1 V above XCOREVSS.

For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output

driven by its current source from 0 mA to 16 m A (0–0.8 V), such that each phase of the

differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage

at 400 mV.

— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to

XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be

AC-coupled off - chip.

• The input amplitude requirement

— This requirement is described in detail in the following sections.

Figure 16. Receiver of SerDes Reference Clocks

Input

Amp

50 Ω

SD_REF_CLK

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 27

High-Speed Serial Interfaces (HSSI)

10.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

• Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV

differential peak–peak (or between 200 mV and 800 mV dif ferential peak). In other words,

each signal wire of the differential pair must have a single-ended swing less than 800 mV and

greater than 200 mV. This requirement is the same for both external DC-coupled or

AC-coupled connection.

— For external DC-coupled connection, as described in Section 10.2.1, “SerDes Reference

Clock Rece ive r Charact er i stics,” the maximum average curr ent requirements sets the

requirement for average voltage (common m ode voltage) t o be between 100 mV and 400 mV.

Figure 17 shows the SerDes reference clock input requirement for DC-coupled connection

scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupl ing capac itor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

XCOREVSS. Each signal wire of the dif ferential inputs is allowed to swing below and above

the common mode voltage (XCOR EVSS). Figure 18 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

• Si ngle-E nde d Mo de

— The reference clock can also be single ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 mV and 800 mV peak–peak (from Vmin to Vmax)

with SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 19 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC - or

AC-coupled externally . For the best noise performance, the reference of the clock could be DC-

or AC-coupled i nto the unused phase (SD_REF_CLK) through the s ame source impedance as

the clock input (SD_REF_CLK) in use.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

28 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 18. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 19. Single-Ended Reference Clock Input DC Requirements

10.2.3 Interfacing with Other Differential Signaling Levels

With on-chip termination to XCOREVSS, the diff erential reference clocks inputs are high-speed current

steering logic (HCSL)-compatible and DC-coupled.

Many other low-volt age differential type outputs like low-voltage differential signaling (LVDS) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100–400 mV)

for DC-coupled connection.

LVPEC L outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

SD_REF_CLK

Vmax < 80 0mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vcm

200mV < Input Amplitude or Differential Peak < 800mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

SD_REF_CLK

400 mV < SD_REF_CLK Input Amplitude < 800 mV

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 29

High-Speed Serial Interfaces (HSSI)

NOTE

Figure 20 to Figure 23 below are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance, and

termination requirements are diff erent between various clock driver chip

manufacturers, it is very possible that the clock circuit reference designs

provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefor e,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8308 SerDes reference clock receiver requirement

provided in this document.

Figure 20 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8308 SerDes reference clock

input’s DC requirement.

Figure 20. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

50 Ω

SD_REF_CLK

Clock Driver 100 Ω differential PWB trace

Clock driver vendor dependent

source termination resistor

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

HCSL CLK Driver Chip

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

MPC8308

CLK_Out

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

30 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 21 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8308’s SerDes reference clock

input’s allowed range (100–400 mV), AC-coupled connection scheme must be used. It assumes the LVDS

output driver features 50-Ω termination resi stor. It also assumes th at the LVDS transmitter es tablishes its

own common mode level without relying on the receiver or other external component.

Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

50 Ω

SD_REF_CLK

Clock Driver 100 Ω differential PWB trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8308

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 31

High-Speed Serial Interfaces (HSSI)

Figure 22 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’ s DC levels (both common mode voltages and output swing) are incompatible with

MPC8308 SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 22

assumes that the LVPECL clock driver ’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupli ng. Its value could be ranged from 140 Ω to 240 Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination

resistor to attenuate the LVPECL output’ s differential peak level such that it meets the MPC8308’s SerDes

reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential

peak). For example, if the L VPECL output’ s differential peak is 900 mV and the desired SerDes reference

clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω.

Consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a

particular clock driver chip.

Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

50 Ω

SD_REF_CLK

Clock Driver 100 Ω differential PWB trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

MPC8308

10nF

10 nF

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

32 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 23 s hows the SerDes reference clock connection reference circuits for a single-ended clock driver .

It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock

input’s DC requirement.

Figure 23. Single-Ended Connection (Reference Only)

10.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high-quality reference clock with low-phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops, and

is less of a problem. Phase noise above 15 MHz is filter ed by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

Table 32 describes some AC parameters for PCI Express protocol.

Table 32. SerDes Reference Clock AC Parameters

At recommended operating conditions with XCOREVDD= 1.0V ± 5%

Parameter Symbol Min Max Unit Notes

Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3

Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3

Differential Input High Voltage VIH +200 — mV 2

Differential Input Low Voltage VIL — –200 mV 2

50 Ω

SD_REF_CLK

100 Ω differential PWB trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip MPC8308

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 33

High-Speed Serial Interfaces (HSSI)

Figure 24. Differential Measurement Points for Rise and Fall Time

Figure 25. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerD es re ference clocks is defined by each interface protocol

based on application usage. For detailed information, see Section 11.2, “AC Requirements for PCI Express

SerDes Clocks.”

Rising edge rate (SD_REF_CLK) to falling edge rate

(SD_REF_CLK) matching

Rise-Fall

Matching

—20%1, 4

Notes:

1. Measurement taken from single-ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered

on the differential zero crossing (Figure 24).

4. Matching applies to rising edge rate for SD_REF_CLK and falling edge rate for SD_REF_CLK. It is measured using a 200 mV

window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross point

is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of

SD_REF_CLK should be compared to the Fall Edge Rate of SD_REF_CLK, the maximum allowed difference should not exceed

20% of the slowest edge rate (See Figure 25).

Table 32. SerDes Reference Clock AC Parameters (continued)

At recommended operating conditions with XCOREVDD= 1.0V ± 5%

Parameter Symbol Min Max Unit Notes

VIH = +200

VIL = -200 mV

0.0 V

SD_REF_CLK

minus

SD_REF_CLK

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

34 Freescale Semiconductor

PCI Express

10.2.4.1 Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread

spectrum clock source.

10.3 SerDes Transmitter and Receiver Reference Circuits

Figure 26 shows the reference ci rcuits for SerDes dat a lane’s transm itter and receiver.

Figure 26. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in Section 11, “PCI Express.”

Note that external AC-coupling capacitor is required for the PCI Express serial transmission protocol with

the capacitor value defined in specification of PCI Express protocol section.

11 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus.

11.1 DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

Fo r more i nform a t i on, se e Section 10.2, “SerDes Reference Clocks.”

11.2 AC Requirements for PCI Express SerDes Clocks

Table 33 lists the PCI Express SerDes clock AC requirements.

Table 33. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol Parameter Description Min Typ Max Units Notes

tREF REFCLK cycle time (for 125 MHz and 100 MHz) 8 10 — ns —

tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period

of any two adjacent REFCLK cycles.

——100ps—

tREFPJ Phase jitter. Deviation in edge location with respect to

mean edge location.

–50 — 50 ps —

50 Ω

50 ΩReceiver

Transmitter

50 Ω

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 35

PCI Express

11.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is withi n 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

11.4 Physical Layer Specifications

Following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer, use the PCI Exp ress Base

Specification, Rev. 1.0a.

11.4.1 Differential Transmitter (TX) Output

Table 34 defines the specifications for the dif fere ntial output at all tra nsmitters (TXs). The parameters are

specified at the component pins .

Table 34. Differential Transmitter (TX) Output Specifications

Parameter Symbol Comments Min Typical Max Units Notes

Unit interval UI Each UPETX is 400 ps ±

300 ppm. UPETX does not

account for Spread

Spectrum Clock dictated

variations.

399.88 400 400.12 ps 1

Differential peak-to-peak

output voltage

VTX-DIFFp-p VPEDPPTX = 2*|VTX-D+ -

VTX-D-|

0.8 — 1.2 V 2

De-emphasized

differential output voltage

(ratio)

VTX-DE-RATIO Ratio of the VPEDPPTX of

the second and following

bits after a transition

divided by the VPEDPPTX

of the first bit after a

transition.

–3.0 –3.5 –4.0 dB 2

Minimum TX eye width TTX-EYE The maximum Transmitter

jitter can be derived as

TTX-MAX-JITTER = 1 -

UPEEWTX= 0.3 UI.

0.70——UI2, 3

Maximum time between

the jitter median and

maximum deviation from

the median

TTX-EYE-MEDIAN-t

MAX-JITTER

Jitter is defined as the

measurement variation of

the crossing points

(VPEDPPTX = 0 V) in

relation to a recovered TX

UI. A recovered TX UI is

calculated over 3500

consecutive unit intervals

of sample data. Jitter is

measured using all edges

of the 250 consecutive UI

in the center of the 3500

UI used for calculating the

TX UI.

— — 0.15 UI 2, 3

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

36 Freescale Semiconductor

PCI Express

D+/D- TX output rise/fall

time

TTX-RISE,

TTX-FALL

— 0.125 — — UI 2, 5

RMS AC peak common

mode output voltage

VTX-CM-ACp VPEACPCMTX =

RMS(|VTXD+ + VTXD-|/2 -

VTX-CM-DC)

VTX-CM-DC = DC(avg) of

|VTX-D+ + VTX-D-|/2

——20mV2

Absolute delta of DC

common mode voltage

during L0 and electrical

idle

VTX-CM-DC-

ACTIVE-

IDLE-DELTA

|VTX-CM-DC (during L0) -

VTX-CM-Idle-DC (During

Electrical Idle)|<=100 mV

VTX-CM-DC = DC(avg) of

|VTX-D+ + VTX-D-|/2 [L0]

VTX-CM-Idle-DC = DC(avg) of

|VTX-D+ + VTX-D-|/2

[Electrical Idle]

0—100mV2

Absolute delta of DC

common mode between

D+ and D–

VTX-CM-DC-LINE-

DELTA

|VTX-CM-DC-D+ -

VTX-CM-DC-D-| <= 25 mV

VTX-CM-DC-D+ = DC(avg) of

|VTX-D+|

VTX-CM-DC-D- = DC(avg) of

|VTX-D-|

0—25mV2

Electrical idle differential

peak output voltage

VTX-IDLE-DIFFp VPEEIDPTX = |VTX-IDLE-D+

-VTX-IDLE-D-| <= 20 mV

0—20mV2

Amount of voltage change

allowed during receiver

detection

VTX-RCV-DETECT The total amount of

voltage change that a

transmitter can apply to

sense whether a low

impedance Receiver is

present.

—600—mV 6

TX DC common mode

voltage

VTX-DC-CM The allowed DC Common

Mode voltage under any

conditions.

—3.6— V 6

TX short circuit current

limit

ITX-SHORT The total current the

Transmitter can provide

when shorted to its ground

——90mA—

Minimum time spent in

electrical idle

TTX-IDLE-MIN Minimum time a

Transmitter must be in

Electrical Idle Utilized by

the Receiver to start

looking for an Electrical

Idle Exit after successfully

receiving an Electrical Idle

ordered set

50——UI—

Table 34. Differential Transmitter (TX) Output Specifications (continued)

Parameter Symbol Comments Min Typical Max Units Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 37

PCI Express

Maximum time to

transition to a valid

electrical idle after

sending an electrical idle

ordered set

TTX-IDLE-SET-TO-I

DLE

After sending an Electrical

Idle ordered set, the

Transmitter must meet all

Electrical Idle

Specifications within this

time. This is considered a

debounce time for the

Transmitter to meet

Electrical Idle after

transitioning from L0.

——20UI—

Maximum time to

transition to valid TX

specifications after leaving

an electrical idle condition

TTX-IDLE-TO-DIFF-

DATA

Maximum time to meet all

TX specifications when

transitioning from

Electrical Idle to sending

differential data. This is

considered a debounce

time for the TX to meet all

TX specifications after

leaving Electrical Idle

——20UI—

Differential return loss RLTX-DIFF Measured over 50 MHz to

1.25 GHz.

12 — — dB 4

Common mode return

loss

RLTX-CM Measured over 50 MHz to

1.25 GHz.

6——dB4

DC differential TX

impedance

ZTX-DIFF-DC TX DC Differential mode

Low Impedance

80 100 120 Ω—

Transmitter DC

impedance

ZTX-DC Required TX D+ as well as

D- DC Impedance during

all states

40 — — Ω—

Lane-to-Lane output skew LTX-SKEW Static skew between any

two Transmitter Lanes

within a single Link

— — 500 + 2

ps —

AC-coupling capacitor CTX All Transmitters are

AC-coupled. The

AC-coupling is required

either within the media or

within the transmitting

component itself. An

external capacitor of

100nF is recommended.

75 — 200 nF —

Table 34. Differential Transmitter (TX) Output Specifications (continued)

Parameter Symbol Comments Min Typical Max Units Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

38 Freescale Semiconductor

PCI Express

11.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 27 is specified using the passive compliance/test measurement load

(Figure 29) in place of any real PCI Express interconnect + RX component. There are two eye diagrams

that must be met for the transmitter . Both diagrams must be aligned in time using the jit ter median to locate

the center of the eye diagram. The different eye diagrams dif fer in voltage depending on whether it is a

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always

rel ative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

It is recommended that the recovered TX UI be calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

Crosslink random timeout Tcrosslink This random timeout helps

resolve conflicts in

crosslink configuration by

eventually resulting in only

one Downstream and one

Upstream Port.

0—1ms7

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 29 and measured over

any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 27.)

3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the

transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total

TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as

opposed to the averaged time value.

4. The transmitter input impedance results in a differential return loss greater than or equal to 12 dB and a common mode return

loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies

to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and D– line

(that is, as measured by a vector network analyzer with 50-Ω probes, see Figure 29). Note that the series capacitors, CTX,

is optional for the return loss measurement.

5. Measured between 20% and 80% at transmitter package pins into a test load as shown in Figure 29 for both VTX-D+ and

VTX-D-.

6. See Section 4.3.1.8 of the

PCI Express Base Specifications

, Rev 1.0a.

7. See Section 4.2.6.3 of the

PCI Express Base Specifications

, Rev 1.0a.

Table 34. Differential Transmitter (TX) Output Specifications (continued)

Parameter Symbol Comments Min Typical Max Units Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 39

PCI Express

Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications

11.4.3 Differential Receiver (RX) Input Specifications

Table 35 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins .

Table 35. Differential Receiver (RX) Input Specifications

Parameter Symbol Comments Min Typical Max Units Notes

Unit interval UI Each UPERX is 400 ps ±

300 ppm. UPERX does not

account for Spread

Spectrum Clock dictated

variations.

399.88 400 400.12 ps 1

Differential peak-to-peak

output voltage

VRX-DIFFp-p VPEDPPRX = 2*|VRX-D+ -

VRX-D-|

0.175 — 1.200 V 2

Minimum receiver eye

width

TRX-EYE The maximum

interconnect media and

Transmitter jitter that can

be tolerated by the

Receiver can be derived

as TRX-MAX-JITTER = 1 -

UPEEWRX= 0.6 UI.

0.4——UI2, 3

[De-emphasized Bit]

566 mV (3 dB) >= V

TX-DIFFp-p-MIN

>= 505 mV (4 dB)

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

0.7 UI = UI – 0.3 UI(J

TX-TOTAL-MAX

)

TX-DIFF

= 0 mV

(D+ D– Crossing Point)

TX-DIFF

= 0 mV

(D+ D– Crossing Point)

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

40 Freescale Semiconductor

PCI Express

Maximum time between

the jitter median and

maximum deviation from

the median.

TRX-EYE-MEDIAN-t

o-MAX-JITTER

Jitter is defined as the

measurement variation of

the crossing points

(VPEDPPRX = 0 V) in

relation to a recovered TX

UI. A recovered TX UI is

calculated over 3500

consecutive unit intervals

of sample data. Jitter is

measured using all edges

of the 250 consecutive UI

in the center of the 3500

UI used for calculating the

TX UI.

— — 0.3 UI 2, 3, 7

AC peak common mode

input voltage

VRX-CM-ACp VPEACPCMRX = |VRXD+ +

VRXD-|/2 - VRX-CM-DC

VRX-CM-DC = DC(avg) of

|VRX-D+ + VRX-D-|/2

——150mV2

Differential return loss RLRX-DIFF Measured over 50 MHz to

1.25 GHz with the D+ and

D- lines biased at +300

mV and -300 mV,

respectively.

15 — — dB 4

Common mode return

loss

RLRX-CM Measured over 50 MHz to

1.25 GHz with the D+ and

D- lines biased at 0 V.

6——dB4

DC differential input

impedance

ZRX-DIFF-DC RX DC differential mode

impedance.

80 100 120 Ω5

DC Input Impedance ZRX-DC Required RX D+ as well

as D- DC Impedance (50

± 20% tolerance).

40 50 60 Ω2, 5

Powered down DC input

impedance

ZRX-HIGH-IMP-DC Required RX D+ as well

as D- DC Impedance

when the Receiver

terminations do not have

power.

200 k — — Ω

Electrical idle detect

threshold

VRX-IDLE-DET-DIF

Fp-p

VPEEIDT = 2*|VRX-D+

-VRX-D-|

Measured at the package

pins of the Receiver

65 — 175 mV

—

Unexpected Electrical Idle

Enter Detect Threshold

Integration Time

TRX-IDLE-DET-DIFF

ENTERTIME

An unexpected Electrical

Idle (Vrx-diffp-p <

Vrx-idle-det-diffp-p) must

be recognized no longer

than

Trx-idle-det-diff-entertime

to signal an unexpected

idle condition.

——10ms

—

Table 35. Differential Receiver (RX) Input Specifications (continued)

Parameter Symbol Comments Min Typical Max Units Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 41

PCI Express

11.5 Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 28 is specif ied usi ng the passive comp lia nce/t est m easur ement lo ad

(Figure 29) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram

measured with the compliance/test measurement load (Figure 29) is larger than the minimum receiver eye

diagram measured over a range of systems at the input receiver of any real PCI Express component. The

degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon

parasitic characteristics that cause the real PCI Express component to vary in impedance from the

compliance/test measurement load. The input receiver eye diagram is implementation specific and is not

specified. RX component designer should provide additional margin to adequately compensate for the

degraded minimum receiver eye diagram (shown in Figure 28) expected at the input receiver based on an

adequate combination of system simulations and the r eturn loss measured looking into the RX package

To t a l S ke w L RX-SKEW Skew across all lanes on a

Link. This includes

variation in the length of

SKP ordered set (for

example, COM and one to

five SKP Symbols) at the

RX as well as any delay

differences arising from

the interconnect itself.

— — 20 ns

—

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 29 should be used

as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 28). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in

which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any

250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point

in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as the reference for the eye diagram.

4. The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300

mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over

a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference

impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by a vector

network analyzer with 50-Ω probes, see Figure 29). Note that the series capacitors, CTX, is optional for the return loss

measurement.

5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and

simulated data.

Table 35. Differential Receiver (RX) Input Specifications (continued)

Parameter Symbol Comments Min Typical Max Units Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

42 Freescale Semiconductor

PCI Express

and silic on. The RX e ye diagram mus t be aligned in tim e using t he jitter median to locate th e center of the

eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50 Ω to ground for

both the D+ and D– line ( that is, as measured by a Vector Network Analyzer

with 50 Ω probes—see Figure 29). Note that the serie s capacitor s,

CPEACCTX, are optional for the return loss measurement.

Figure 28. Minimum Receiver Eye Timing and Voltage Compliance Specification

11.5.1 Compliance Test and Measurement Load

The AC timing and voltage parame ters must be verifie d at the measuremen t point, as specif ied within

0.2 inches of the package pins, into a test/measurement load shown in Figure 29.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in le ngth at the package

pin boundary.

RX-DIFFp-p-MIN

> 175 mV

0.4 UI = T

RX-EYE-MIN

RX-DIFF

= 0 mV

(D+ D– Crossing Point)

RX-DIFF

= 0 mV

(D+ D– Crossing Point)

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 43

Enhanced Local Bus

Figure 29. Compliance Test/Measurement Load

12 Enhanced Local Bus

This section describes the DC and AC electrical speci f icat ions for the enhance d local bus in terface.

12.1 Enhanced Local Bus DC Electrical Characteristics

Table 36 provides the DC electrical characteristics for the local bus interface.

Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned.

12.2 Enhanced Local Bus AC Electrical Specifications

Table 37 describes the general timing parameters of the local bus interface.

Table 36. Local Bus DC Electrical Characteristics at 3.3 V

Parameter Symbol Min Max Unit

High-level input voltage VIH 2.0 NVDD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current, (VIN1 = 0 V or VIN = LVDD)I

IN — ±5μA

High-level output voltage, (LVDD = min, IOH = –2 mA) VOH NVDD – 0.2 — V

Low-level output voltage, (LVDD = min, IOH = 2 mA) VOL —0.2V

Table 37. Local Bus General Timing Parameters

Parameter Symbol 1Min Max Unit Notes

Local bus cycle time tLBK 15 — ns 2

Input setup to local bus clock (Note: to be revisited) tLBIVKH 7 — ns 3, 4

Input hold from local bus clock (Note: to be revisited) tLBIXKH 1 — ns 3, 4

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

44 Freescale Semiconductor

Enhanced Local Bus

Figure 30 provides the AC test load for the local bus.

Figure 30. Local Bus AC Test Load

Local bus clock to output valid (Note: to be revisited) tLBKHOV —3 ns 3

Local bus clock to output high impedance for LD (Note: to be

revisited)

tLBKHOZ —4 ns 5

Notes:

1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case

for clock one(1).

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 ×NVDD of the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

Table 37. Local Bus General Timing Parameters (continued)

Parameter Symbol 1Min Max Unit Notes

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 45

Enhanced Local Bus

Figure 31 through Figure 33 show the local bus signals.

In what follows, T1, T2, T3, and T4 are internal clock reference phase signals corresponding to

LCCR[CLKDIV].

Figure 31. Local Bus Signals, Non-Special Signals Only

Output Signals:

LBCTL//LOE/

tLBKHOV

LCLK0

Input Signals:

LD[0:15]

Output Signals:

LA[0:25]

tLBIXKH

tLBIVKH

tLBKHOZ

Input Signal:

LGTA

tLBIXKH

tLBIVKH

tLBIXKH

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

46 Freescale Semiconductor

Enhanced Local Bus

Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2

LCLK0

UPM Mode Input Signal:

LUPWAIT

tLBIXKH

tLBIVKH

tLBIXKH

tLBKHOZ

Input Signals:

LD[0:15]

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:3]/LWE

tLBKHOV

tLBKHOZ

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 47

Enhanced Secure Digital Host Controller (eSDHC)

Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4

13 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC/SDI O) interface

of the MPC8308.

The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the

SD_DAT[0:3]/CMD as outputs and rising edge to sample the SD_DA T[0:3], CMD, CD, and WP as inputs.

This behavior is true for both full- and high-speed modes.

13.1 eSDHC DC Electrical Characteristics

Table 38 provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device,

compatible with SDHC specifications . The eSDHC NVDD range is between 3.0 V and 3.6 V.

Table 38. eSDHC interface DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

LCLK

UPM Mode Input Signal:

LUPWAIT

tLBIXKH

tLBIVKH

tLBIXKH

tLBKHOZ

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:3]/LWE

tLBKHOV

tLBKHOZ

Input Signals:

LD[0:15]

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

48 Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

13.2 eSDHC AC Timing Specifications (Full-Speed Mode)

This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.

Table 39 provides the eSDHC AC timing specificati ons for full-speed mode as defined in Figure 35 and

Figure 36.

Output low voltage VOL IOL =3.2mA — 0.4 V

Input high voltage VIH —2.1NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Table 39. eSDHC AC Timing Specifications for Full-Speed Mode

At recommended operating conditions NVDD = 3.3 V ± 300 mV.

Parameter Symbol 1Min Max Unit Notes

SD_CLK clock frequency—full-speed mode fSFSCK 025MHz—

SD_CLK clock cycle tSFSCK 40 — ns —

SD_CLK clock frequency—identification mode fSIDCK 0 400 kHz —

SD_CLK clock low time tSFSCKL 15 — ns 2

SD_CLK clock high time tSFSCKH 15 — ns 2

SD_CLK clock rise and fall times tSFSCKR/

tSFSCKF

—5ns2

Input setup times: SD_CMD, SD_DATx to SD_CLK tSFSIVKH 3—ns2

Input hold times: SD_CMD, SD_DATx to SD_CLK tSFSIXKH 2—ns2

Output valid: SD_CLK to SD_CMD, SD_DAT

valid tSFSKHOV —3ns2

Output hold: SD_CLK to SD_CMD, SD_DAT

valid tSFSKHOX –3 — — —

SD card input setup tISU 5—ns3

SD card input hold tIH 5—ns3

SD card output valid tODLY —14ns3

SD card output hold tOH 0—ns3

Notes:

1The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC

full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also

tSFSKHOV symbolizes eSDHC full-speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O)

going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2Measured at capacitive load of 40 pF.

3For reference only, according to the SD card specifications.

4Average, for reference only.

Table 38. eSDHC interface DC Electrical Characteristics (continued)

Characteristic Symbol Condition Min Max Unit

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 49

Enhanced Secure Digital Host Controller (eSDHC)

Figure 34 provides the eSDHC clock input timing diagram.

Figure 34. eSDHC Clock Input Timing Diagram

13.2.1 Full-Speed Output Path (Write)

Figure 35 provides the data and command output timing diagram.

Figure 35. Full-Speed Output Path

eSDHC

tSFSCKR

External Clock VMVMVM

tSFSCK

tSFSCKF

VM = Midpoint Voltage (NVDD/2)

operational mode tSFSCKL tSFSCKH

Input at the

MPC8308 Pins

SD CLK at the

MPC8308 Pin

Output Valid Time: tSFSKHOV

Output Hold Time: tSFSKHOX

tIH (5 ns)

tCLK_DELAY

SD CLK at

Driving

Edge

Sampling

Edge

the Card Pin

tISU (5 ns)

tDATA_DELAY

tSFSCKL

tSFSCK (Clock Cycle)

Output from the

MPC8308 Pins

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

50 Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

13.2.2 Full-Speed Input Path (Read)

Figure 36 provides the data and command input timing diagram.

Figure 36. Full-Speed Input Path

13.3 eSDHC AC Timing Specifications

Table 40 provides the eSDHC AC timing specificati ons.

Table 40. eSDHC AC Timing Specifications for High-Speed Mode

At recommended operating conditions NVDD = 3.3 V ± 300 mV.

Parameter Symbol 1Min Max Unit Notes

SD_CLK clock frequency—high-speed mode fSHSCK 050MHz3

SD_CLK clock cycle tSHSCK 20 — ns —

SD_CLK clock frequency—identification mode fSIDCK 0400kHz—

SD_CLK clock low time tSHSCKL 7—ns2

SD_CLK clock high time tSHSCKH 7—ns2

SD_CLK clock rise and fall times tSHSCKR/

tSHSCKF

—3ns2

Input setup times: SD_CMD, SD_DATx tSHSIVKH 3—ns2

Input hold times: SD_CMD, SD_DATx tSHSIXKH 2—ns2

Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV 3—ns2

Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid tSHSKHOX –3 — ns 2

SD Card Input Setup tISU 6—ns3

SD Card Input Hold tIH 2—ns3

tCLK_DELAY

Output from the

SD CLK at

the Card Pin

SD Card Pins

tSFSIVKH

tSFSIXKH

Driving

Edge

Sampling

Edge

tOH

tDATA_DELAY

tODLY

tSFSCK (Clock Cycle)

(MPC8308 Input Hold)

SD CLK at the

MPC8308 Pin

Input at the

MPC8308 Pins

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 51

Enhanced Secure Digital Host Controller (eSDHC)

Figure 37 provides the eSDHC clock input timing diagram.

Figure 37. eSDHC Clock Input Timing Diagram

SD Card Output Valid tODLY —14ns3

SD Card Output Hold tOH 2.5 — ns 3

Notes:

1The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC

full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also

tSFSKHOV symbolizes eSDHC full-speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O)

going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five

letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2Measured at capacitive load of 40 pF.

3For reference only, according to the SD card specifications.

Table 40. eSDHC AC Timing Specifications for High-Speed Mode (continued)

At recommended operating conditions NVDD = 3.3 V ± 300 mV.

Parameter Symbol 1Min Max Unit Notes

eSDHC

tSHSCKR

External Clock VMVMVM

tSHSCK

tSHSCKF

VM = Midpoint Voltage (NVDD/2)

operational mode tSHSCKLtSHSCKH

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

52 Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

13.3.1 High-Speed Output Path (Write)

Figure 38 provides the data and command output timing diagram.

Figure 38. High-Speed Output Path

13.3.2 High-Speed Input Path (Read)

Figure 39 provides the data and command input timing diagram.

Figure 39. High-Speed Input Path

Output Valid Time: tSHSKHOV

Output Hold Time: tSHSKHOX

tIH (2 ns)

tCLK_DELAY

Input at the

SD CLK at

Driving

Edge

Sampling

Edge

the Card Pin

SD Card Pins

tISU (6 ns)

tDATA_DELAY

tSHSCKL

tSHSCK (Clock Cycle)

SD CLK at the

MPC8308 Pin

Output from the

MPC8308 Pins

tCLK_DELAY

Output from the

SD CLK at

the Card Pin

SD Card Pins

tSHSIVKH

Driving

Edge

Sampling

Edge

tOH tDATA_DELAY

tODLY

tSHSCK (Clock Cycle)

1/2 Cycle

tSHSIXKH

(MPC8308 Input

Input at the

MPC8308 Pins

SD CLK at the

MPC8308 Pin

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 53

JTAG

14 JTAG

This section describes the DC and AC electrical specif ications for the IEEE Std 1149. 1™ (JTAG)

interface.

14.1 JTAG DC Electrical Characteristics

Table 41 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface.

14.2 JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE 1 149.1 (JTAG) interface.

Table 42 provides the JTAG AC timing specifications as defined in Figure 41 through Figure 44.

Table 41. JTAG Interface DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage VIH —2.1NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN —±5μA

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1

At recommended operating conditions (see Ta b le 2 ).

Parameter Symbol2Min Max Unit Notes

JTAG external clock frequency of operation fJTG 033.3MHz—

JTAG external clock cycle time t JTG 30 — ns —

JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns —

JTAG external clock rise and fall times tJTGR & tJTGF 02ns—

TRST assert time tTRST 25 — ns 3

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

Valid times:

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

54 Freescale Semiconductor

JTAG

Figure 40 provides the AC test load for TDO and the boundary-scan outputs.

Figure 40. AC Test Load for the JTAG Interface

Figure 41 provides the JTAG clock input timing diagram.

Figure 41. JTAG Clock Input Timing Diagram

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

ns 5

JTAG external clock to output high impedance:

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

ns 5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 40).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device

timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)

going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals

(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design and characterization.

Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1 (continued)

At recommended operating conditions (see Ta b le 2 ).

Parameter Symbol2Min Max Unit Notes

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

JTAG

tJTKHKL tJTGR

External Clock VMVMVM

tJTG tJTGF

VM = Midpoint Voltage (NVDD/2)

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 55

JTAG

Figure 42 pr ovides the TRST timing diagram.

Figure 42. TRST Timing Diagram

Figure 43 provides the boundary-scan timing diagram.

Figure 43. Boundary-Scan Timing Diagram

Figure 44 provide s the test access port timing diagram.

Figure 44. Test Access Port Timing Diagram

TRST

VM = Midpoint Voltage (NVDD/2)

VM VM

tTRST

VM = Midpoint Voltage (NVDD/2)

VM VM

tJTDVKH

tJTDXKH

Boundary

Data Outputs

Boundary

Data Outputs

JTAG

External Clock

Boundary

Data Inputs

Output Data Valid

tJTKLDX

tJTKLDZ

tJTKLDV

Input

Data Valid

Output Data Valid

VM = Midpoint Voltage (NVDD/2)

VM VM

tJTIVKH

tJTIXKH

JTAG

External Clock

Output Data Valid

tJTKLOX

tJTKLOZ

tJTKLOV

Input

Data Valid

Output Data Valid

TDI, TMS

TDO

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

56 Freescale Semiconductor

I2C

15 I2C

This section describes the DC and AC electrical characteristics for the I2C interface.

15.1 I2C DC Electrical Characteristics

Table 43 provides the DC electrical characteristics for the I2C interface.

15.2 I2C AC Electrical Specifications

Table 44 provides the AC timing parameters for the I2C interf ace.

Table 43. I2C DC Electrical Characteristics

At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.

Parameter Symbol Min Max Unit Notes

Input high-voltage level VIH 0.7 × NVDD NVDD + 0.3 V —

Input low-voltage level VIL –0.3 0.3 × NVDD V—

Low-level output voltage VOL 00.2 × NVDD V1

High-level output voltage VOH 0.8 x NVDD NVDD + 0.3 V —

Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10

to 400 pF

tI2KLKV 20 + 0.1 × CB250 ns 2

Pulse width of spikes which must be suppressed by the input filter tI2KHKL 050ns3

Capacitance for each I/O pin CI—10pF—

Input current, (0 V ≤VIN ≤ NVDD)I

IN —± 5 μA—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. CB = capacitance of one bus line in pF.

3. For information on the digital filter used, see the

MPC8308 PowerQUICC II Pro Processor Reference Manual

Table 44. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Ta b le 43 ).

Parameter Symbol1Min Max Unit

SCL clock frequency fI2C 0 400 kHz

Low period of the SCL clock tI2CL 1.3 — μs

High period of the SCL clock tI2CH 0.6 — μs

Setup time for a repeated START condition tI2SVKH 0.6 — μs

Hold time (repeated) START condition (after this period, the first clock pulse is generated) tI2SXKL 0.6 — μs

Data setup time tI2DVKH 100 — ns

Data hold time:

I2C bus devices

tI2DXKL

—

0 2

—

0.9 3

μs

Fall time of both SDA and SCL signals5tI2CF — 300 ns

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 57

I2C

Figure 45 provides the AC test load for the I2C.

Figure 45. I2C AC Test Load

Figure 46 shows the AC timing diagram for the I2C bus.

Figure 46. I2C Bus AC Timing Diagram

Setup time for STOP condition tI2PVKH 0.6 — μs

Bus free time between a STOP and START condition tI2KHDX 1.3 — μs

Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 × NVDD —V

Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 × NVDD —V

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S)

went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing

(I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference

(K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R

(rise) or F (fall).

2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

3. The maximum tI2DXKL has only to be met if the device does not stretch the low period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

5. The device does not follow the

I2C-BUS Specifications, Version 2.1,

regarding the tI2CF AC parameter.

Table 44. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Ta b le 43 ).

Parameter Symbol1Min Max Unit

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

SrS

SDA

SCL

tI2CF

tI2SXKL

tI2CL

tI2CH

tI2DXKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2CR

tI2CF

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

58 Freescale Semiconductor

Timers

16 Timers

This section describes the DC and AC electrica l specific a tions for the timers.

16.1 Timers DC Electrical Characteristics

Table 45 provides the DC electrical characteristics for the MPC8308 timers pins, including TIN, T OUT,

and TGATE.

16.2 Timers AC Timing Specifications

Table 46 provides the Timers input and output AC timing specifications.

Figure 47 provides the AC test load for the T imers.

Figure 47. Timers AC Test Load

Table 45. Timers DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Input high voltage VIH —2.1NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN 0 V ≤ VIN ≤ NVDD — ± 5 μA

Table 46. Timers Input AC Timing Specifications

Characteristic Symbol1Min Unit

Timers inputs—minimum pulse width tTIWID 20 ns

Notes:

1. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any

external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 59

GPIO

17 GPIO

This section describes the DC and AC electrical specifications for the GPIO of MPC8308

17.1 GPIO DC Electrical Characteristics

Table 47 provides the DC electrical characteristics for the GPIO.

17.2 GPIO AC Timing Specifications

Table 48 provides the GPIO input and output AC timing specifications.

Figure 48 provides the AC test load for the GPIO.

Figure 48. GPIO AC Test Load

Table 47. GPIO DC Electrical Characteristic

Characteristic Symbol Condition Min Max Unit

Output high voltage VOH IOH =–8.0mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL =3.2mA — 0.4 V

Input high voltage VIH —2.1NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN 0V≤VIN ≤NVDD — ± 5 μA

Table 48. GPIO Input AC Timing Specifications

Characteristic Symbol1Min Unit

GPIO inputs—minimum pulse width tPIWID 20 ns

Notes:

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized

before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to

ensure proper operation.

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

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60 Freescale Semiconductor

IPIC

18 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

18.1 IPIC DC Electrical Characteristics

Table 49 provides the DC electrical characteristics for the external interrupt pins.

18.2 IPIC AC Timing Specifications

Table 50 provides the IPIC input and output AC timing specifications.

19 SPI

This section descr ibes t he DC and AC electrical speci f icat ions for the SP I of the device.

19.1 SPI DC Electrical Characteristics

Table 51 provides the DC electrical characteristics for the MPC8308 SPI.

Table 49. IPIC DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage VIH —2.1NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN ——±5μA

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Table 50. IPIC Input AC Timing Specifications

Characteristic Symbol1Min Unit

IPIC inputs—minimum pulse width tPIWID 20 ns

Notes:

1. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized

before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns

to ensure proper operation when working in edge triggered mode.

Table 51. SPI DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage VIH —2.1NV

DD +0.3 V

Input low voltage VIL — –0.3 0.8 V

Input current IIN 0 V ≤VIN ≤NVDD — ± 5 μA

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 61

SPI

19.2 SPI AC Timing Specifications

Table 52 provides the SPI input and output AC timing specifications.

Figure 49 provides the AC test load for the SPI.

Figure 49. SPI AC Test Load

Figure 50 and Figure 51 repre s ent the AC timing from Table 52. Note that although the spe cifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Table 52. SPI AC Timing Specifications 1

Characteristic Symbol

2Min Max Unit

SPI outputs valid—master mode (internal clock) delay tNIKHOV —6ns

SPI outputs hold—master mode (internal clock) delay tNIKHOX 0.5 — ns

SPI outputs valid—slave mode (external clock) delay tNEKHOV 8.5 ns

SPI outputs hold—slave mode (external clock) delay tNEKHOX 2—ns

SPI inputs—master mode (internal clock) input setup time tNIIVKH 6—ns

SPI inputs—master mode (internal clock) input hold time tNIIXKH 0—ns

SPI inputs—slave mode (external clock) input setup time tNEIVKH 4—ns

SPI inputs—slave mode (external clock) input hold time tNEIXKH 2—ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal

timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Table 51. SPI DC Electrical Characteristics (continued)

Characteristic Symbol Condition Min Max Unit

Output Z0 = 50 ΩNVDD/2

RL = 50 Ω

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

62 Freescale Semiconductor

Package and Pin Listings

Figure 50 shows the SPI timing in slave mode (external clock).

Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 51 shows the SPI timing in master mode (internal cl ock).

Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram

20 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in

a Moulded Array Process Ball Grid Array (MAP BGA). For informatio n on the MAPBGA, see

Section 20.1, “Package Parameters for the MPC8308 MAPBGA, ” and Section 20.2, “Mechanical

Dimensions of the MPC8308 MAPBGA.”

20.1 Package Parameters for the MPC8308 MAPBGA

The package parameters are a s provided in the following list. The package type is 19 mm × 19 mm, 473

MAPBGA.

Package outline 19 mm × 19 mm

Interconnects 473

Pitch 0.80 mm

Module height (typical) 1.39 mm

Solder Balls 96.5 Sn/ 3.5Ag

Ball diameter (typical) 0.40 mm

SPICLK (input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 63

Package and Pin Listings

20.2 Mechanical Dimensions of the MPC8308 MAPBGA

Figure 52 s hows the mechanical dimensions and bott om surface nomenclature of the MAPBGA package.

Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG

Notes:

1. All dimensions are in millimeters.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

64 Freescale Semiconductor

Package and Pin Listings

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

20.3 Pinout Listings

Table 53 provides the pin-out listing for the MPC8308, MAPBGA package.

Table 53. MPC8308 Pinout Listing

Signal Package Pin Number Pin Type Power

Supply Notes

DDR Memory Controller Interface

MEMC_MDQ[0] V6 I/O GVDDA —

MEMC_MDQ[1] Y4 I/O GVDDA —

MEMC_MDQ[2] AB3 I/O GVDDA —

MEMC_MDQ[3] AA3 I/O GVDDA —

MEMC_MDQ[4] AA2 I/O GVDDA —

MEMC_MDQ[5] AA1 I/O GVDDA —

MEMC_MDQ[6] W4 I/O GVDDA —

MEMC_MDQ[7] Y2 I/O GVDDA —

MEMC_MDQ[8] W3 I/O GVDDA —

MEMC_MDQ[9] W1 I/O GVDDA —

MEMC_MDQ[10] Y1 I/O GVDDA —

MEMC_MDQ[11] W2 I/O GVDDA —

MEMC_MDQ[12] U4 I/O GVDDA —

MEMC_MDQ[13] U3 I/O GVDDA —

MEMC_MDQ[14] V4 I/O GVDDA —

MEMC_MDQ[15] U6 I/O GVDDA —

MEMC_MDQ[16] T3 I/O GVDDB —

MEMC_MDQ[17] T2 I/O GVDDB —

MEMC_MDQ[18] R4 I/O GVDDB —

MEMC_MDQ[19] R3 I/O GVDDB —

MEMC_MDQ[20] P4 I/O GVDDB —

MEMC_MDQ[21] N6 I/O GVDDB —

MEMC_MDQ[22] P2 I/O GVDDB —

MEMC_MDQ[23] P1 I/O GVDDB —

MEMC_MDQ[24] N4 I/O GVDDB —

MEMC_MDQ[25] N3 I/O GVDDB —

MEMC_MDQ[26] N2 I/O GVDDB —

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 65

Package and Pin Listings

MEMC_MDQ[27] M6 I/O GVDDB —

MEMC_MDQ[28] M2 I/O GVDDB —

MEMC_MDQ[29] M3 I/O GVDDB —

MEMC_MDQ[30] L2 I/O GVDDB —

MEMC_MDQ[31] L3 I/O GVDDB —

MEMC_MDM[0] AB2 O GVDDA —

MEMC_MDM[1] V3 O GVDDA —

MEMC_MDM[2] P3 O GVDDB —

MEMC_MDM[3] M7 O GVDDB —

MEMC_MDM[8] K2 O GVDDB —

MEMC_MDQS[0] AC3 I/O GVDDA —

MEMC_MDQS[1] V1 I/O GVDDA —

MEMC_MDQS[2] R1 I/O GVDDB —

MEMC_MDQS[3] M1 I/O GVDDB —

MEMC_MDQS[8] K1 I/O GVDDB —

MEMC_MBA[0] C3 O GVDDB —

MEMC_MBA[1] B2 O GVDDB —

MEMC_MBA[2] H4 O GVDDB —

MEMC_MA0 C2 O GVDDB —

MEMC_MA1 D2 O GVDDB —

MEMC_MA2 D3 O GVDDB —

MEMC_MA3 D4 O GVDDB —

MEMC_MA4 E4 O GVDDB —

MEMC_MA5 F4 O GVDDB —

MEMC_MA6 E2 O GVDDB —

MEMC_MA7 E1 O GVDDB —

MEMC_MA8 F2 O GVDDB —

MEMC_MA9 F3 O GVDDB —

MEMC_MA10 C1 O GVDDB —

MEMC_MA11 F7 O GVDDB —

MEMC_MA12 G2 O GVDDB —

MEMC_MA13 G3 O GVDDB —

MEMC_MWE D5 O GVDDB —

MEMC_MRAS B4 O GVDDB —

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

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66 Freescale Semiconductor

Package and Pin Listings

MEMC_MCAS C5 O GVDDB —

MEMC_MCS[0] B6 O GVDDB —

MEMC_MCS[1] C6 O GVDDB —

MEMC_MCKE H3 O GVDDB 3

MEMC_MCK [0] A3 O GVDDB —

MEMC_MCK [1] U2 O GVDDB —

MEMC_MCK [2] G1 O GVDDB —

MEMC_MCK [0] A4 O GVDDB —

MEMC_MCK [1] U1 O GVDDB —

MEMC_MCK [2] H1 O GVDDB —

MEMC_MODT[0] A5 O GVDDB —

MEMC_MODT[1] B5 O GVDDB —

MEMC_MECC[0] L4 I/O GVDDB —

MEMC_MECC[1] L6 I/O GVDDB —

MEMC_MECC[2] K4 I/O GVDDB —

MEMC_MECC[3] K3 I/O GVDDB —

MEMC_MECC[4] J2 I/O GVDDB —

MEMC_MECC[5] K6 I/O GVDDB —

MEMC_MECC[6] J3 I/O GVDDB —

MEMC_MECC[7] J6 I/O GVDDB —

MVREF G6 IGVDDB —

Local Bus Controller Interface

LD0 U18 I/O NVDDP_K 8

LD1 V18 I/O NVDDP_K 8

LD2 U16 I/O NVDDP_K 8

LD3 Y20 I/O NVDDP_K 8

LD4 AA21 I/O NVDDP_K 8

LD5 AC22 I/O NVDDP_K 8

LD6 V17 I/O NVDDP_K 8

LD7 AB21 I/O NVDDP_K 8

LD8 Y19 I/O NVDDP_K 8

LD9 AA20 I/O NVDDP_K 8

LD10 Y17 I/O NVDDP_K 8

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

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Freescale Semiconductor 67

Package and Pin Listings

LD11 AC21 I/O NVDDP_K 8

LD12 AB20 I/O NVDDP_K 8

LD13 V16 I/O NVDDP_K 8

LD14 AA19 I/O NVDDP_K 8

LD15 AC17 I/O NVDDP_K 8

LA0 AC20 O NVDDP_K —

LA1 Y16 O NVDDP_K —

LA2 U15 O NVDDP_K —

LA3 V15 O NVDDP_K —

LA4 AA18 O NVDDP_K —

LA5 AA17 O NVDDP_K —

LA6 AC19 O NVDDP_K —

LA7 AA16 O NVDDP_K —

LA8 AB18 O NVDDP_K —

LA9 AC18 O NVDDP_K —

LA10 V14 O NVDDP_K —

LA11 AB17 O NVDDP_K —

LA12 AA15 O NVDDP_K —

LA13 AC16 O NVDDP_K —

LA14 Y14 O NVDDP_K —

LA15 AC15 O NVDDP_K —

LA16 U13 O NVDDP_K —

LA17 V13 O NVDDP_K —

LA18 Y13 O NVDDP_K —

LA19 AB15 O NVDDP_K —

LA20 AA14 O NVDDP_K —

LA21 AB14 O NVDDP_K —

LA22 U12 O NVDDP_K —

LA23 V12 O NVDDP_K —

LA24 Y12 O NVDDP_K —

LA25 AC14 O NVDDP_K —

LCS[0] AA13 O NVDDP_K 4

LCS[1] AB13 O NVDDP_K 4

LCS[2] AA12 O NVDDP_K 4

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

68 Freescale Semiconductor

Package and Pin Listings

LCS[3] Y11 O NVDDP_K 4

LWE[0] /LFWE0/LBS0 AB11 O NVDDP_K —

LWE[1]/LBS1AC11ONVDDP_K —

LBCTL U11 O NVDDP_K —

LGPL0/LFCLE Y10 O NVDDP_K —

LGPL1/LFALE AA10 O NVDDP_K —

LGPL2/LOE/LFRE AB10 O NVDDP_K 4

LGPL3/LFWP AC10 O NVDDP_K —

LGPL4/LGTA/LUPWAIT/LFRB AB9 I/O NVDDP_K 4

LGPL5 Y9 O NVDDP_K —

LCLK0 AC12 O NVDDP_K —

DUART

UART_SOUT1/MSRCID0/LSRCID0 C17 O NVDDB —

UART_SIN1/MSRCID1/LSRCID1 B18 I/O NVDDB —

UART_SOUT2/MSRCID2/LSRCID2 D17 O NVDDB —

UART_SIN2/MSRCID3/LSRCID3 D18 I/O NVDDB —

PEX PHY

TXA C14 O XPADVDD —

TXA C15 O XPADVDD —

RXA A13 I XCOREVDD —

RXA B13 I XCOREVDD —

SD_IMP_CAL_RX A15 I XCOREVDD —

SD_REF_CLK C12 I XCOREVDD —

SD_REF_CLK D12 I XCOREVDD —

SD_PLL_TPD F13 O ——

SD_IMP_CAL_TX A11 I XPADVDD —

SD_PLL_TPA_ANA F11 O ——

SDAVDD_0 G12 I——

SDAVSS_0 F12 I——

I2C interface

IIC_SDA1 C9 I/O NVDDA 2

IIC_SCL1 A9 I/O NVDDA 2

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 69

Package and Pin Listings

IIC_SDA2/CKSTOP_OUT D10 I/O NVDDA 2

IIC_SCL2/CKSTOP_IN C10 I/O NVDDA 2

Interrupts

IRQ[0]/MCP_IN A17 I NVDDB —

IRQ[1]/MCP_OUT F16 I/O NVDDB —

IRQ[2] /CKSTOP_OUT B17 I/O NVDDB —

IRQ[3] /CKSTOP_IN A18 I NVDDB —

JTAG

TCK Y7 I NVDDP_K —

TDI U9 I NVDDP_K 4

TDO AC5 O NVDDP_K 3

TMS AA6 I NVDDP_K 4

TRST V8 I NVDDP_K 4

TEST

TEST_MODE AC6 I NVDDP_K 5

System Control

HRESET AA9 I/O NVDDP_K 1

PORESET AA8 I NVDDP_K —

SRESET AB7 I/O NVDDP_K —

Clocks

SYS_CLK_IN AC8 I NVDDP_K —

RTC_PIT_CLOCK AA23 I NVDDJ —

MISC

QUIESCE AA7 O NVDDP_K —

THERM0 AC7 I NVDDP_K 6

ETSEC1

TSEC1_COL B20 I NVDDC —

TSEC1_CRS B21 I NVDDC —

TSEC1_GTX_CLK F18 O NVDDC 3

TSEC1_RX_CLK A22 I NVDDC —

TSEC1_RX_DV D21 I NVDDC —

TSEC1_RXD[3] C22 I NVDDC —

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

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70 Freescale Semiconductor

Package and Pin Listings

TSEC1_RXD[2] C21 I NVDDC —

TSEC1_RXD[1] C20 I NVDDC —

TSEC1_RXD[0] D20 I NVDDC —

TSEC1_RX_ER C23 I NVDDC —

TSEC1_TX_CLK/TSEC1_GTX_CLK125 E23 I NVDDC —

TSEC1_TXD[3]/CFG_RESET_SOURCE[0] F22 I/O NVDDC —

TSEC1_TXD[2]/CFG_RESET_SOURCE[1] F21 I/O NVDDC —

TSEC1_TXD[1]/CFG_RESET_SOURCE[2] E21 I/O NVDDC —

TSEC1_TXD[0]/CFG_RESET_SOURCE[3] D22 I/O NVDDC —

TSEC1_TX_EN/LBC_PM_REF_10 F20 O NVDDC —

TSEC1_TX_ER/LB_POR_CFG_BOOT_ECC E22 I/O NVDDC 7

Ethernet Mgmt

TSEC1_MDC A20 O NVDDB —

TSEC1_MDIO C19 I/O NVDDB 2

eSDHC/GTM

SD_CLK/GPIO_16 D7 O NVDDA —

SD_CMD/GPIO_17 G9 I/O NVDDA —

SD_CD/GTM1_TIN1/GPIO_18 A7 I NVDDA —

SD_WP/GTM1_TGATE1/GPIO_19 D8 I NVDDA —

SD_DAT[0]/GTM1_TOUT1/GPIO_20 C8 I/O NVDDA —

SD_DAT[1]/GTM1_TOUT2/GPIO_21 B8 I/O NVDDA —

SD_DAT[2]/GTM1_TIN2/GPIO_22 A8 I/O NVDDA —

SD_DAT[3]/GTM1_TGATE2/GPIO_23 B9 I/O NVDDA —

SPI

SPIMOSI/MSRCID4/LSRCID4 AB5 I/O NVDDP_K —

SPIMISO/MDVAL/LDVAL Y6 I/O NVDDP_K —

SPICLK AA5 I/O NVDDP_K —

SPISEL AB4 I NVDDP_K —

GPIO/ETSEC2

GPIO[0]/TSEC2_COL G21 I/O NVDDF —

GPIO[1]/TSEC2_TX_ER K23 I/O NVDDF —

GPIO[2]/TSEC2_GTX_CLK H18 I/O NVDDF —

GPIO[3]/TSEC2_RX_CLK G23 I/O NVDDF —

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 71

Package and Pin Listings

GPIO[4]/TSEC2_RX_DV J18 I/O NVDDF —

GPIO[5]/TSEC2_RXD3 J20 I/O NVDDF —

GPIO[6]/TSEC2_RXD2 H22 I/O NVDDF —

GPIO[7]/TSEC2_RXD1 H21 I/O NVDDF —

GPIO[8]/TSEC2_RXD0 H20 I/O NVDDF —

GPIO[9]/TSEC2_RX_ER J21 I/O NVDDF —

GPIO[10]/TSEC2_TX_CLK/TSEC2_GTX_CLK125 J23 I/O NVDDF —

GPIO[11]/TSEC2_TXD3 K22 I/O NVDDF —

GPIO[12]/TSEC2_TXD2 K20 I/O NVDDF —

GPIO[13]/TSEC2_TXD1 K18 I/O NVDDF —

GPIO[14]/TSEC2_TXD0 J17 I/O NVDDF —

GPIO[15]/TSEC2_TX_EN K21 I/O NVDDF —

USB/IEEE1588/GTM

USBDR_PWR_FAULT P20 I NVDDH —

USBDR_CLK R23 I NVDDH —

USBDR_DIR R21 I NVDDH —

USBDR_NXT P18 I NVDDH —

USBDR_TXDRXD0 T22 I/O NVDDH —

USBDR_TXDRXD1 T21 I/O NVDDH —

USBDR_TXDRXD2 U23 I/O NVDDH —

USBDR_TXDRXD3 U22 I/O NVDDH —

USBDR_TXDRXD4 T20 I/O NVDDH —

USBDR_TXDRXD5 R18 I/O NVDDH —

USBDR_TXDRXD6 V23 I/O NVDDH —

USBDR_TXDRXD7 V22 I/O NVDDH —

USBDR_PCTL0 R17 O NVDDH —

USBDR_PCTL1 U20 O NVDDH —

USBDR_STP V21 O NVDDH —

TSEC_TMR_CLK/ GPIO[8] W23 I NVDDH —

GTM1_TOUT3/ GPIO[9] T18 O NVDDH —

GTM1_TOUT4/ GPIO[10] V20 O NVDDH —

TSEC_TMR_TRIG1/ GPIO[11] W21 I NVDDH —

TSEC_TMR_TRIG2/ GPIO[12] Y21 I NVDDH —

TSEC_TMR_GCLK L17 O NVDDG —

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

72 Freescale Semiconductor

Package and Pin Listings

TSEC_TMR_PP1 L18 O NVDDG —

TSEC_TMR_PP2 L21 O NVDDG —

TSEC_TMR_PP3/ GPIO[13] L22 O NVDDG —

TSEC_TMR_ALARM1 L23 O NVDDG —

TSEC_TMR_ALARM2/ GPIO[14] M23 O NVDDG —

GPIO[7] M22 O — —

TSEC2_CRS M21 O NVDDG —

TSEC2_TMR_RX_ESFD/ GPIO[1] M18 O NVDDG —

TSEC2_TMR_TX_ESFD/GPIO[2] M20 O NVDDG —

TSEC1_TMR_RX_ESFD/GPIO[3] N23 O NVDDG —

TSEC1_TMR_TX_ESFD/ GPIO[4] N21 O NVDDG —

GTM1_TGATE3 N20 I NVDDG —

GTM1_TIN4 N18 I NVDDG —

GTM1_TGATE4/ GPIO[15] P23 I NVDDG —

GTM1_TIN3 P22 I NVDDG —

GPIO[5] N17 I NVDDH —

GPIO[6] P21 I NVDDH —

Power and Ground Supplies

AVDD1 R6 I — —

AVDD2 V10 I——

NC, No Connection Y23, B11, B16, D16 ———

VDD H8, H9, H10, H14,

H15, H16, J8, J16, K8,

K16, L8, L16, M8, M16,

N8, N16, P8, P16, R8,

R16, T8, T9, T10, T11,

T12, T13, T14, T15,

T16

I——

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 73

Package and Pin Listings

VSS A2, A21, B1, B19, B23,

C4, C16, D6, D19, E3,

F8, F15, F17, F23, G7,

G8, G10, G15, G16,

G17, G20, H2, H6, H7,

H17, H23, J7, J9, J10,

J11, J12, J13, J14,

J15, K9, K10, K11,

K12, K13, K14, K15,

L1, L7, L9, L10, L11,

L12, L13, L14, L15,

L20, M4, M9, M10,

M11, M12, M13, M14,

M15, N9, N10, N11,

N12, N13, N14, N15,

P6, P7, P9, P10, P11,

P12, P13, P14, P15,

R2, R7, R9, R10, R11,

R12, R13, R14, R15,

R22, T6, T7, U8, U17,

U21, V2, V7, V9, V11,

W20, Y8, Y15, AA4,

AB1, AB6, AB12,

AB19, AC2, AC9, AC23

I — —

NVDDA B7, B10, C7, D9, F9 I — —

NVDDB A16, A19, C18 I — —

NVDDC A23, B22, D23, E20,

G18

I — —

NVDDF G22, J22, K17 I — —

NVDDG M17, N22 I — —

NVDDH P17, R20, T17, T23,

W22, Y22

I — —

NVDDJ AB23, AA22 I — —

NVDDP_K U10, U14, Y5, Y18,

AA11, AB8, AB16,

AB22, AC4,

AC13

I — —

GVDD A1, A6, B3, D1, F1, F6,

G4, J1, J4, K7, N1, N7,

T1, T4, U7, Y3, AC1

I — —

XPADVDD D15, F10, F14 I — —

XPADVSS A10, B15, D14, G13,

G14, H12

I — —

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

74 Freescale Semiconductor

Package and Pin Listings

XCOREVDD A14, B12, C13 I — —

XCOREVSS A12, B14, C11, D11,

D13, G11, H11, H13

I — —

Notes:

1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to NVDD

2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to NVDD

3. This output is actively driven during reset rather than being three-stated during reset.

4. This pin has weak internal pull-up that is always enabled. 5. This pin must always be tied to VSS.

6. Internal thermally sensitive resistor, resistor value varies linearly with temperature. Useful for determining the junction

temperature.

7. The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor

enables the ECC by default. To disable the ECC an external strong pull up resistor or a buffer released to high impedance

is needed.

8. This pin has weak internal pull-down that is always enabled

Table 53. MPC8308 Pinout Listing (continued)

Signal Package Pin Number Pin Type Power

Supply Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 75

Clocking

21 Clocking

Figure 53 shows the internal distribution of clocks with in the devi ce.

1Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].

2Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].

Figure 53. MPC8308 Clock Subsystem

The following external clock sources are utilized on the MPC8308:

• System clock (SYS_CLK_IN)

• Ethernet Clock (TSEC1_RX_CLK/TSEC1_TX_CLK/TSEC1_GTX_CLK125 for eTSEC)

• SerDe s PHY clock

• eSHDC clock (SD_CLK)

For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Pr ocessor

Reference Manual.

All clock inputs can be supplied using an external canned oscillator , a clock generation chip, or som e other

source that provides a standard CMOS square wave input.

PCI Express

e300 Core

System

PLL

e300

PLL

Clk

Gen

125/100 MHz PLL

fbref

SYS_CLK_IN

PCVTR Mux

Protocol

Converter

SerDes PHY

24–66 MHz

SD_REF_CLK_B

SD_REF_CLK

MPC8308

eTSEC1

TSEC1_RX_CLK

TSEC1_TX_CLK/

TSEC1_GTX_CLK125

DDR

Clock

Divider

csb_clk

LBC

Clock

Divider

clk tree MCK[0:2]

MCK[0:2]

DDR

Memory

Device

Local

Bus

Memory

Device

ddr_clk

lbc_clk

x M1

x L2

eSHDC

SD_CLK

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

76 Freescale Semiconductor

Clocking

21.1 System Clock Domains

The primary clock input (SYS_CLK_IN) frequenc y is multiplied up by the system phase-locked loop

(PLL) and the clock unit to create three major clock domains:

• The coherent system bus clock (csb_clk)

• The internal clock for the DDR controller (ddr_clk)

• The internal clock for the local bus interface unit ( lbc_clk)

The csb_clk frequency is derived as follows:

csb_clk = [SYS_CLK_IN] × SPMF

The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the

csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multiplier s

are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is

loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset

Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual.

The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.

Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider

(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate

is the same frequency as ddr_clk.

The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that

lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the

external local bus clock outputs (LSYNC_OUT and LCLK0:2). The LBC clock divider ratio is controlled

by LCCR[CLKDIV]. For more information, see the Reset Clock Configuration chapter in the MPC8308

PowerQUICC II Pro Processor Reference Manual .

In addition, some of the inter nal units may be r equired to be shut off or operate at lower frequency than

the csb_clk frequency. These units have a default clock ratio that can be configured by a memory-mapped

frequency. For more information, see Reset Clock Configuration chapter in the MPC8308 PowerQUICC

II Pr o Processor Refer e nce Manual.

NOTE

The clock ratios of these units must be set before they are accessed.

Table 54. Configurable Clock Units

Unit Default Frequency Options

eTSEC1,eTSEC2

csb_clk/3

Off,

csb_clk, csb_clk/2, csb_clk/3

I2C

csb_clk

Off,

csb_clk,csb_clk

/2,

csb_clk

DMA complex

csb_clk

Off,

csb_clk,csb_clk/2,csb_clk/3

PCIEXP

csb_clk

Off,

csb_clk

/2,

csb_clk

eSDHC

csb_clk

Off

, csb_clk, csb_clk/2, csb_clk/3

USB

csb_clk

Off

, csb_clk, csb_clk/2, csb_clk/3

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 77

Clocking

Table 55 provides the operating frequencies for the device under recommended operating conditions

(Table 2).

21.2 System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 56 shows the multiplication factor

encodings for the system PLL.

As described in Section 21, “Clocking,” the LBCM, DDRCM, and SPMF paramet ers in the reset

configuration word low select the ratio between the pr imary clock input (SYS_CL K_IN) and the internal

Table 55. Operating Frequencies for MPC8308

Characteristic1Maximum Operating Frequency Unit

e300 core frequency (

core_clk

) 400 MHz

Coherent system bus frequency (

csb_clk

) 133 MHz

DDR2 memory bus frequency (MCK)2133 MHz

Local bus frequency (LCLK

)366 MHz

Notes:

1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting

csb_clk

MCK, LCLK0, and

core_clk

frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The DDR data rate is 2x the DDR memory bus frequency.

3. The local bus frequency is 1/2, 1/4, or 1/8 of the

lbc_clk

frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x

the

csb_clk

frequency (depending on RCWL[LBCM]).

Table 56. System PLL Ratio

RCWL[SPMF] csb_clk : SYS_CLK_IN

0000 Reserved

0001 Reserved

0010 2 : 1

0011 3 : 1

0100 4 : 1

0101 5 : 1

0110–1111 Reserved

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

78 Freescale Semiconductor

Clocking

coherent system bus clock (csb_clk). Table 57 shows the expected frequency values for the CSB frequency

for select csb_clk to SYS_CLK_IN ratios .

21.3 Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 58 shows the encodings for RCWL[ CORE P LL ]. COREPLL values that are

not listed in Table 58 should be considered as reserved.

NOTE

Core VCO frequency = core frequency × VCO divider. The VCO divider,

which is determined by RCWLR[COREPLL], must be set properly so that

the core VCO frequency is in the range of 400–800 MHz.

Table 57. CSB Frequency Options

SPMF

csb_clk

:Input Clock Ratio

Input Clock Frequency (MHz)

25 33.33 66.67

0010 2:1 133

0100 4:1 133

0101 5:1 125

Table 58. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk: csb_clk

Ratio1VCO Divider (VCOD)2

0–1 2–5 6

0000 0 PLL bypassed

(PLL off,

csb_clk

clocks core directly)

PLL bypassed

(PLL off,

csb_clk

clocks core directly)

nnnn

nn/a n/a

00 0001 01:1 2

01 0001 01:1 4

10 0001 01:1 8

00 0001 1 1.5:1 2

01 0001 1 1.5:1 4

10 0001 1 1.5:1 8

00 0010 02:1 2

01 0010 02:1 4

10 0010 02:1 8

00 0010 1 2.5:1 2

01 0010 1 2.5:1 4

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 79

Thermal

22 Thermal

This section describes the thermal specifications of the device.

22.1 Thermal Characteristics

Table 59 provides the package thermal characteristics for the 473, 19 × 19 mm MAPBGA.

10 0010 1 2.5:1 8

00 0011 03:1 2

01 0011 03:1 4

10 0011 03:1 8

Notes:

1For any

core_clk:csb_clk

ratios, the

core_clk

must not exceed its maximum operating frequency of 333 MHz.

2Core VCO frequency = core frequency × VCO divider. Note that VCO divider has to be set properly so that the

core VCO frequency is in the range of 400–800 MHz.

Table 59. Package Thermal Characteristics for MAPBGA

Characteristic Board Type Symbol Value Unit Notes

Junction to Ambient Natural Convection Single layer board (1s) RθJA 42 °C/W 1,2

Junction to Ambient Natural Convection Four layer board (2s2p) RθJA 27 °C/W 1,2,3

Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 35 °C/W 1,3

Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 24 °C/W 1,3

Junction to Board — RθJB 17 °C/W 4

Junction to Case — RθJC 9°C/W5

Junction to Package Top Natural Convection ΨJT 2°C/W6

Table 58. e300 Core PLL Configuration (continued)

RCWL[COREPLL]

core_clk: csb_clk

Ratio1VCO Divider (VCOD)2

0–1 2–5 6

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

80 Freescale Semiconductor

Thermal

22.2 Thermal Management Information

For the followin g sections, PD = (VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers.

22.2.1 Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction t emperature , TJ, can be obtained from the equation:

TJ = TA + (R

JA × PD)

where:

TJ = junction temperature (°C)

TA = ambient temp era ture for the package (°C)

JA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The junction-t o-ambient thermal resistance is an industry standard value that provides a quick and easy

estima tion of therma l performanc e . As a general sta teme nt, the value obtained on a single- laye r board is

appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low-power dissipation and the components are well

separated. T est cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.

22.2.2 Estimation of Junction Temperature with Junction-to-Board

Thermal Resistance

The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal

resistance. The thermal performance of any component is s trongly dependent on the power dissipation of

surrounding components. In addition, the ambient temperature varies widely within the application. For

many natural convection and especially closed box applications, the board temperature at the perimeter

(edge) of the package is approximately th e same as the local air temperatur e near the device. Specifying

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

Table 59. Package Thermal Characteristics for MAPBGA (continued)

Characteristic Board Type Symbol Value Unit Notes

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 81

System Design Information

the local ambient conditions e xplicitly a s the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

TJ = TB + (R

JB × PD)

where:

TJ = junction temperature (°C)

TB = board temperature at the package perimeter (°C)

JB = junction-to-board thermal resistance (°C/W) per JESD51–8

PD = power dissipation in the package (W)

When the heat loss from the package case to the air can be ignored, acceptable predicti ons of junction

temperature can be made. The application board should be similar to the thermal test condition: the

component is sol dered to a board with internal planes.

22.2.3 Experimental Determination of Junction Temperature

To determine the junction tem perature of the device in the application after prototypes are available, the

therma l character izat ion para met er (

JT) can be used to determine the junction temperature with a

measurement of the tempe rature at the top center of the package case using the f ollowing equation:

TJ = TT + (

JT × PD)

where:

TJ = junction temperature (°C)

TT = thermocouple temperature on top of package (°C)

JT = thermal character izat ion parame te r (°C/W)

PD = power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T

thermocouple epoxied to the top center of the package case . The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1 mm of wire extending from the juncti on. The thermocouple wire

is placed flat against the package case to avoid measurement errors caus ed by cooling effects of the

ther mocouple wire.

23 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

device

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

82 Freescale Semiconductor

System Design Information

23.1 System Clocking

The device includes two PL Ls.

1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input.

The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL

ratio configuration bi ts as described in Section 21. 2, “System PLL Configuration.”

2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e300 core clock and the platform clock is selected using the e300 PLL ratio

configuration bits as described in Section 21.3, “Core PLL Configuration.”

23.2 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 for

core PLL and AVDD2 fo r the p lat fo rm PLL) . Th e AVDD level should always be equivalent to VDD, and

preferably these voltages are derived directly from VDD through a low-pass filter scheme such as the

following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits as illustrated in Figure 54, one to each of the two AVDD pins. By

providing independent filters to each PLL the opportunity t o cause noise injection from one PLL to the

other is reduced.

This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).

Consistent with the recommendations of Dr . Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize

noise coupled from nearby circuits. It should be pos sible to r oute directly from the capacitors to the AVDD

pin, which is on the periphery of package, without the inductance of vias.

Figure 54 s hows the PLL power supply filter circuits.

Figure 54. PLL Power Supply Filter Circuit

23.3 Decoupling Recommendations

Due to large address and data buses and high-operating frequencies, the device can generate transient

power surges and high-frequency noise in its power supply , especially while driving large capacitive loads.

This noise m ust be prevented from reaching other components in the MPC8308 system, and the MPC8308

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each VDD, NV DD, GVDD, and LVDD pin of the device.

VDD AVDD1 and AVDD2

2.2 µF 2.2 µF

Low ESL Surface Mount Capacitors

10 Ω

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 83

System Design Information

These decoupling capacitors should receive their power from separate VDD, N VDD, G V DD, LV DD, and

VSS power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed

directly under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 s izes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, NVDD, GVDD, LVDD planes, to enable quick recharging of the smaller chip capacitors.

These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick

response time necessary . They should also be connected to the power and ground planes through two vias

to minimize inductance. Suggested bulk capacitors are in the range of 100–330 µF (AVX TPS tantalum or

Sanyo OSCON). However, customers should work directly with their power regulator vendor for best

values and types of bulk capacitors.

23.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active l ow inputs should be tied to NVDD, GVDD, and LVDD as required. Unused active high

inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, NVDD, AVDD1, AV DD2, GVDD, LVDD,

and VSS pins of the device.

23.5 Output Buffer DC Impedance

The device drivers are character ized over process , voltage, and temperature. For all buses, the driver is a

push–pull single-ended driver type (open drain for I2C, MDIO, and HRESET).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD

or VSS. Then, the value of each resistor is vari ed until the pad voltage is NVDD/2 (Figure 55). T he output

impedance is the average of two components: the resistances of the pull-up and pull-down devices. When

data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals

NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN)/2.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

84 Freescale Semiconductor

System Design Information

Figure 55. Driver Impedance Measurement

The value of this resistance and the strength of the dr iver’s current source can be found by making two

measurements. First, the output vol tage is measured while driving logic 1 without an external diff erential

termination resistor . The measured voltage is V1 = Rsource × Isource. Second, the output vol tage is measured

while driving logic 1 with an external precision differential termi nation resistor of value Rterm. The

measured voltage is V2=(1/(1/R

1+1/R

2)) × Isource. Solving for the output impedance gives Rsource =

Rterm × (V1/V2– 1). The drive current is then Isource =V

1/Rsource.

Table 60 summarizes the signal impedance t argets. The driver impedance are targeted at minimum VDD,

nominal NVDD, 105°C.

23.6 Configuration Pin Muxing

The device provides the user with power-on configuration options that can be set through the use of

external pull-up or pull-down resistors of 4.7 KΩ on certain output pins (see customer-v is ible

configuration pins). These pins are generally used as output-only pins in normal operation.

While PORESET is asserted, these pins are treated as inputs. The value presented on these pins while

PORESET is asserted is latched when PORESET deasserts, at which time the input receive r is disabled

and the I/O circuit takes on its normal function. Careful board layout with stubles s connections to these

pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize

the disruption of signal quality or speed for output pins thus configured.

Table 60. Impedance Characteristics

Impedance Local Bus, Ethernet, DUART, Control,

Configuration, Power Management DDR DRAM Symbol Unit

RN42 Target 20 Target Z0Ω

RP42 Target 20 Target Z0Ω

Note: Nominal supply voltages. See Ta bl e 2 , Tj = 105°C.

NVDD

VSS

Pad

Data

SW1

SW2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 85

Ordering Information

23.7 Pull-Up Resistor Requirements

The device requires high-resistance pull-up resistors (10 kΩ is recommended) on open drain type pins

including I2C, Ethernet management MDIO, HRESET and IPIC (integrated programmable interrupt

controller).

Correct operation of the JTAG int erface requir es configuration of a group of system control pin s as

demonstrated in Figure 56. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions, because most have asynchronous behavior and spurious assertion

that give unpredictable results.

24 Ordering Information

This section presents ordering information for the devices discussed in this document, and it shows an

example of how the parts are marked. Ordering information for the devices fully covered by this document

is provided in Section 24.1, “Part Numbers Fully Addressed by This Document. ”

24.1 Part Numbers Fully Addressed by This Document

Table 61 provides the Freescale part numbering nomenclature for the MPC8308 family. Note that the

individual part numbers correspond to a maximum processor core freq uency. For available frequencies,

contact your local Freescale sales office. In addition to the maximum processor core frequency, the part

numbering scheme also includes the maximum effective DDR memory speed. Each part number also

contains a revision code which refers to the die mask revision number.

Table 61. Part Numbering Nomenclature

MPC

nnnn CVM AD D A

Product

Code

Part

Identifier

Temperature

Range1Package2e300 Core

Frequency3

DDR

Frequency

Revision

Level

MPC 8308 Blank = 0 to

105°C

C = –40 to 105°C

VM = Pb-free 473

MAPBGA

AD = 266 MHz

AF = 333 MHz

AG = 400MHz

D = 266 MHz Contact local

Freescale

sales office

Notes:

1. Contact local Freescale office on availability of parts with C temperature range.

2. See Section 20, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support

other maximum core frequencies.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

86 Freescale Semiconductor

Document Revision History

24.2 Part Marking

Parts are marked as in the example shown in Figure 56.

Figure 56. Freescale Part Marking for PBGA Devices

Table 62 shows the SVR settings.

25 Document Revision History

Table 63 provides a revision history for this hardware specification.

Table 62. SVR Settings

Device Package SVR

MPC8308 MAPBGA 0x8101 _0110

Note: PVR = 8085_0020 for the device.

Table 63. Document Revision History

Revision Date Substantive Change(s)

Rev 1 07/2010 • In “Table 4,” TA = 105 replaced with TJ = 105

•In “Table 8,” fSYS_CLK_IN (Max) = 66 replaced with 66.67 and tSYS_CLK_IN (Min) = 15.15

replaced with 15

•In “Table 53,” TSEC1_TMR_RX_ESFD replaced with TSEC2_TMR_RX_ESFD

TSEC1_TMR_TX_ESFD replaced with TSEC2_TMR_TX_ESFD

TSEC0_TMR_RX_ESFD replaced with TSEC1_TMR_RX_ESFD

TSEC0_TMR_TX_ESFD replaced with TSEC1_TMR_TX_ESFD

•In “Table 56,” rows from 1000 to 1111 removed

Rev 0 05/2010 Initial release

MPCnnnnCVMADDA

core/platform MHZ

ATWLYYWW

CCCCC

PBGA

*MMMMM YWWLAZ

Notes:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor 87

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

Document Number: MPC8308EC

Rev. 1

07/2010

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