General Description
The MAX5841 is a quad, 10-bit voltage output, digital-
to-analog converter (DAC) with an I2C™-compatible,
2-wire interface that operates at clock rates up to
400kHz. The device operates from a single 2.7V to 5.5V
supply and draws only 230µA at VDD = 3.6V. A power-
down mode decreases current consumption to less
than 1µA. The MAX5841 features three software-selec-
table power-down output impedances: 100kΩ, 1kΩ,
and high impedance. Other features include internal
precision Rail-to-Rail®output buffers and a power-on
reset (POR) circuit that powers up the DAC in the
100kΩpower-down mode.
The MAX5841 features a double-buffered I2C-compati-
ble serial interface that allows multiple devices to share
a single bus. All logic inputs are CMOS-logic compati-
ble and buffered with Schmitt triggers, allowing direct
interfacing to optocoupled and transformer-isolated
interfaces. The MAX5841 minimizes digital noise
feedthrough by disconnecting the clock (SCL) signal
from the rest of the device when an address mismatch
is detected.
The MAX5841 is specified over the extended tempera-
ture range of -40°C to +85°C and is available in a
miniature 10-pin µMAX package. Refer to the MAX5842
data sheet for the 12-bit version.
Applications
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Programmable Attenuation
VCO/Varactor Diode Control
Low-Cost Instrumentation
Battery-Powered Equipment
ATE
Features
♦Ultra-Low Supply Current
230µA at VDD = 3.6V
280µA at VDD = 5.5V
♦300nA Low-Power Power-Down Mode
♦Single 2.7V to 5.5V Supply Voltage
♦Fast 400kHz I2C-Compatible 2-Wire Serial
Interface
♦Schmitt-Trigger Inputs for Direct Interfacing to
Optocouplers
♦Rail-to-Rail Output Buffer Amplifiers
♦Three Software-Selectable Power-Down Output
Impedances
100kΩ, 1kΩ, and High Impedance
♦Read-Back Mode for Bus and Data Checking
♦Power-On Reset to Zero
♦10-Pin µMAX Package
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
________________________________________________________________ Maxim Integrated Products 1
1
2
3
4
5
10
9
8
7
6
OUTD
OUTC
OUTB
OUTAGND
VDD
SCL
ADD
MAX5841
µMAX
TOP VIEW
REFSDA
Pin Configuration
Ordering Information
RP
RP
VDD
µC
SDA SCL
SDA
SDA
REF
REF
REF
SCL
SCL
VDD
VDD
RS
RS
VDD
OUTA
OUTB
MAX5841
MAX5841
RS
RS
OUTC
OUTD
OUTB
OUTC
OUTD
OUTA
Typical Operating Circuit
19-1777; Rev 0; 1/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP
RANGE
PIN-
PACKAGE ADDRESS
MAX5841LEUB -40oC to +85oC 10 µMAX 0111 10X
MAX5841MEUB -40oC to +85oC 10 µMAX 1011 10X
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
I2C is a trademark of Philips Corp.
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL= 5kΩ, CL= 200pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, SCL, SDA to GND............................................-0.3V to +6V
OUT_, REF, ADD to GND..............................-0.3V to VDD + 0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW above +70°C) ................444mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering 10s) ..................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY (NOTE 2)
Resolution N 10 Bits
Integral Nonlinearity INL (Note 3) ±0.5 ±4 LSB
Differential Nonlinearity DNL Guaranteed monotonic (Note 3) ±0.5 LSB
Zero-Code Error ZCE Code = 000 hex, VDD = 2.7V 6 40 mV
Zero-Code Error Tempco 2.3 ppm/oC
Gain Error GE Code = 3FF hex -0.8 -3 %FSR
Gain-Error Tempco 0.26 ppm/oC
Power-Supply Rejection Ratio PSRR Code = 3FF hex, VDD = 4.5V to 5.5V 58.8 dB
DC Crosstalk 30 µV
REFERENCE INPUT
Reference Input Voltage Range VREF 0V
DD V
Reference Input Impedance 32 45 kΩ
Reference Current Power-down mode ±0.3 ±1µA
DAC OUTPUT
Output Voltage Range No load (Note 4) 0 VDD V
DC Output Impedance Code = 200 hex 1.2 Ω
VDD = 5V, VOUT = full scale (short to GND) 42.2
Short-Circuit Current VDD = 3V, VOUT = full scale (short to GND) 15.1 mA
VDD = 5V 8
Wake-Up Time VDD = 3V 8 µs
DAC Output Leakage Current Power-down mode = high impedance,
VDD = 5.5V, VOUT_ = VDD or GND ±0.1 ±1 µA
DIGITAL INPUTS (SCL, SDA)
Input High Voltage VIH 0.7 ✕
VDD V
Input Low Voltage VIL 0.3 ✕
VDD V
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL= 5kΩ, CL= 200pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA= 25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis 0.05 ✕
VDD V
Input Leakage Current Digital inputs = 0 or VDD ±0.1 ±1µA
Input Capacitance 6pF
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage VOL ISINK = 3mA 0.4 V
Three-State Leakage Current ILDigital inputs = 0 or VDD ±0.1 ±1µA
Three-State Output Capacitance 6pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR 0.5 V/µs
Voltage Output Settling Time To 1/2LSB code 100 hex to 300 hex or 300
hex to 100 hex (Note 5) 412µs
Digital Feedthrough C od e = 000 hex, d i g i tal i np uts fr om 0 to V
DD 0.2 nV-s
Digital-to-Analog Glitch Impulse Major carry transition (code = 1FF hex to
200 hex and 200 hex to 1FF hex) 12 nV-s
DAC-to-DAC Crosstalk 2.4 nV-s
POWER SUPPLIES
Supply Voltage Range VDD 2.7 5.5 V
All digital inputs at 0 or VDD = 3.6V 230 395
Supply Current with No Load IDD All digital inputs at 0 or VDD = 5.5V 280 420 µA
Power-Down Supply Current IDDPD All digital inputs at 0 or VDD = 5.5V 0.3 1 µA
TIMING CHARACTERISTICS (FIGURE 1)
Serial Clock Frequency fSCL 0 400 kHz
Bus Free Time Between STOP
and START Conditions tBUF 1.3 µs
START Condition Hold Time tHD
,
STA 0.6 µs
SCL Pulse Width Low tLOW 1.3 µs
SCL Pulse Width High tHIGH 0.6 µs
Repeated START Setup Time tSU
,
STA 0.6 µs
Data Hold Time tHD
,
DAT 0 0.9 µs
Data Setup Time tSU
,
DAT 100 ns
SDA and SCL Receiving Rise
Time tr(Note 5) 0 300 ns
SDA and SCL Receiving Fall Time tf(Note 5) 0 300 ns
SDA Transmitting Fall Time tf(Note 5) 20 +
0.1Cb250 ns
STOP Condition Setup Time tSU
,
STO 0.6 µs
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
4 _______________________________________________________________________________________
INTEGRAL NONLINEARITY
vs. INPUT CODE
MAX5841 toc01
INPUT CODE
INL (LSB)
768512256
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 1024
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5841 toc02
SUPPLY VOLTAGE (V)
INL (LSB)
4.84.13.4
0.25
0.50
0.75
1.00
1.25
0
2.7 5.5
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5841 toc03
TEMPERATURE (°C)
INL (LSB)
603510-15
0.25
0.50
0.75
1.00
1.25
0
-40 85
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
MAX5841 toc04
INPUT CODE
DNL (LSB)
768512256
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 1024
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5841 toc05
SUPPLY VOLTAGE (V)
DNL (LSB)
4.84.13.4
-0.4
-0.3
-0.2
-0.1
0
-0.5
2.7 5.5
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5841 toc06
TEMPERATURE (°C)
DNL (LSB)
603510-15
-0.4
-0.3
-0.2
-0.1
0
-0.5
-40 85
Typical Operating Characteristics
(VDD = +5V, RL= 5kΩ, TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL= 5kΩ, CL= 200pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA= 25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus Capacitance Cb(Note 5) 400 pF
Maximum Duration of Suppressed
Pulse Widths tSP 050ns
Note 1: All devices are 100% production tested a at TA= +25°C and are guaranteed by design for TA= TMIN to TMAX.
Note 2: Static specifications are tested with the output unloaded.
Note 3: Linearity is guaranteed from codes 29 to 995.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design. Not production tested.
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 5
ZERO-CODE ERROR
vs. SUPPLY VOLTAGE
MAX5841 toc07
SUPPLY VOLTAGE (V)
ZERO-CODE ERROR (mV)
4.84.13.4
2
4
6
8
10
0
2.7 5.5
NO LOAD
ZERO-CODE ERROR
vs. TEMPERATURE
MAX5841 toc08
TEMPERATURE (°C)
ZERO-CODE ERROR (mV)
603510-15
2
4
6
8
10
0
-40 85
NO LOAD
GAIN ERROR vs. SUPPLY VOLTAGE
MAX5841 toc09
SUPPLY VOLTAGE (V)
GAIN ERROR (%FSR)
4.84.13.4
-0.4
-0.8
-1.2
-1.6
-2.0
0
2.7 5.5
NO LOAD
GAIN ERROR vs. TEMPERATURE
MAX5841 toc10
TEMPERATURE (°C)
GAIN ERROR (%FSR)
603510-15
-0.4
-0.8
-1.2
-1.6
-2.0
0
-40 85
NO LOAD
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
MAX5841 toc11
OUTPUT SOURCE CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
8642
1
2
3
4
5
6
0
010
CODE = 3FF hex
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
MAX5841 toc12
OUTPUT SINK CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
8642
0.5
1.0
1.5
2.0
2.5
0
010
CODE = 100 hex
SUPPLY CURRENT vs. INPUT CODE
MAX5841 toc13
INPUT CODE
SUPPLY CURRENT (µA)
820615410205
260
280
300
320
240
0 1024
SUPPLY CURRENT vs. TEMPERATURE
MAX5841 toc14
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
603510-15
260
280
300
320
240
-40 85
N0 LOAD
CODE = 3FF hex
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5841 toc15
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
4.84.13.4
260
280
300
320
240
2.7 5.5
CODE = 3FF hex
NO LOAD
Typical Operating Characteristics (continued)
(VDD = +5V, RL= 5kΩ, TA= +25°C.)
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
6 _______________________________________________________________________________________
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5841 toc16
SUPPLY VOLTAGE (V)
POWER-DOWN SUPPLY CURRENT (nA)
4.84.13.4
100
200
300
400
500
0
2.7 5.5
TA = +25°C
TA = -40°C
TA = +85°C
ZOUT = HIGH IMPEDANCE
NO LOAD
POWER-UP GLITCH
MAX5841 toc17
100µs/div
VDD
OUT_
0
5V
10mV/div
EXITING SHUTDOWN
MAX5841 toc18
2µs/div
OUT_ 500mV/div
CLOAD = 200pF
CODE = 200 hex
MAJOR CARRY TRANSITION
(POSITIVE)
MAX5841 toc19
2µs/div
OUT_ 5mV/div
CLOAD = 200pF
RL = 5kΩ
CODE = 1FF hex TO 200 hex
MAJOR CARRY TRANSITION
(NEGATIVE)
MAX5841 toc20
2µs/div
OUT_ 5mV/div
CLOAD = 200pF
RL = 5kΩ
CODE = 200 hex TO 1FF hex
Typical Operating Characteristics (continued)
(VDD = +5V, RL= 5kΩ, TA= +25°C.)
SETTLING TIME
(POSITIVE)
MAX5841 toc21
2µs/div
OUT_ 500mV/div
CLOAD = 200pF
CODE = 100 hex TO 300 hex
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 7
SETTLING TIME
(NEGATIVE)
MAX5841 toc22
2µs/div
OUT_ 500mV/div
CLOAD = 200pF
CODE = 300 hex TO 100 hex
DIGITAL FEEDTHROUGH
MAX5841 toc23
40µs/div
OUT_ 2mV/div
CLOAD = 200pF
fSCL = 12kHz
CODE = 000 hex
SCL 2mV/div
CROSSTALK
MAX5841 toc24
4µs/div
VOUTB 1mV/div
VOUTA 2V/div
Typical Operating Characteristics (continued)
(VDD = +5V, RL= 5kΩ, TA= +25°C.)
Note 6: The ability to drive loads less than 5kΩis not implied.
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
8 _______________________________________________________________________________________
Detailed Description
The MAX5841 is a quad, 10-bit, voltage-output DAC
with an I2C/SMBus-compatible 2-wire interface. The
device consists of a serial interface, power-down cir-
cuitry, four input and DAC registers, four 10-bit resistor
string DACs, four unity-gain output buffers, and output
resistor networks. The serial interface decodes the
address and control bits, routing the data to the proper
input or DAC register. Data can be directly written to
the DAC register, immediately updating the device out-
put, or can be written to the input register without
changing the DAC output. Both registers retain data as
long as the device is powered.
DAC Operation
The MAX5841 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5841’s
input coding is straight binary, with the output voltage
given by the following equation:
where N = 10 (bits), and D = the decimal value of the
input code (0 to 1023).
Output Buffer
The MAX5841 analog outputs are buffered by preci-
sion, unity-gain followers that slew 0.5V/µs. Each buffer
output swings rail-to-rail, and is capable of driving 5kΩ
in parallel with 200pF. The output settles to ±0.5LSB
within 4µs.
Power-On Reset
The MAX5841 features an internal POR circuit that ini-
tializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered down,
with the output buffers disabled and the outputs pulled
to GND through the 100kΩtermination resistor.
Following power-up, a wake-up command must be initi-
ated before any conversions are performed.
Power-Down Modes
The MAX5841 has three software-controlled low-power
power-down modes. All three modes disable the output
buffers and disconnect the DAC resistor strings from
REF, reducing supply current draw to 1µA and the ref-
erence current draw to less than 1µA. In power-down
mode 0, the device output is high impedance. In
power-down mode 1, the device output is internally
pulled to GND by a 1kΩtermination resistor. In power-
down mode 2, the device output is internally pulled to
GND by a 100kΩtermination resistor. Table 1 shows
the power-down mode command words.
Upon wake-up, the DAC output is restored to its previ-
ous value. Data is retained in the input and DAC regis-
ters during power-down mode.
Digital Interface
The MAX5841 features an I2C/SMBus-compatible
2-wire interface consisting of a serial data line (SDA)
and a serial clock line (SCL). The MAX5841 is SMBus
compatible within the range of VDD = 2.7V to 3.6V. SDA
and SCL facilitate bidirectional communication between
the MAX5841 and the master at rates up to 400kHz.
Figure 1 shows the 2-wire interface timing diagram. The
MAX5841 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5841 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed-
VVD
OUT REF
N
_()
=×
2
Pin Description
PIN NAME FUNCTION
1 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to zero.
2 SCL Serial Clock Input
3V
DD Power Supply
4 GND Ground
5 SDA Bidirectional Serial Data Interface
6 REF Reference Input
7 OUTA DAC A Output
8 OUTB DAC B Output
9 OUTC DAC C Output
10 OUTD DAC D Output
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 9
by a START (S) or REPEATED START (Sr) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5841 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor to generate, a logic
high voltage (see Typical Operating Circuit). Series
resistors RSare optional. These series resistors protect
the input stages of the MAX5841 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions). Both SDA and SCL idle high when
the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5841. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see
Acknowledge Bit (ACK)). The STOP condition frees the
bus. If a repeated START condition (Sr) is generated
instead of a STOP condition, the bus remains active.
When a STOP condition or incorrect address is detect-
ed, the MAX5841 internally disconnects SCL from the
serial interface until the next START condition, minimiz-
ing digital noise and feedthrough.
Early STOP Conditions
The MAX5841 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A REPEATED START (Sr) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Srmay also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5841 ser-
ial interface supports continuous write operations with
or without an Srcondition separating them. Continuous
POWER-DOWN
COMMAND BITS
PD1 PD0
MODE/FUNCTION
00
Power-up device. DAC output
restored to previous value.
01
Power-down mode 0. Power down
device with output floating.
10
Power-down mode 1. Power down
device with output terminated with
1kΩ to GND.
11
Power-down mode 2. Power down
device with output terminated with
100kΩ to GND.
Table 1. Power-Down Command Bits
SCL
SDA
STOP
CONDITION
START
CONDITION
REPEATED START CONDITIONSTART CONDITION
tLOW
tSU, DAT tSU, STA
tSP
tBUF
tHD, STA tSU, STO
tRtF
tHD, STA
tHIGH
tHD, DAT
Figure 1. 2-Wire Serial Interface Timing Diagram
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
10 ______________________________________________________________________________________
read operations require Srconditions because of the
change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5841 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5841 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Figure 4). When idle, the MAX5841
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/Windicates whether the master is writing to or read-
ing from the MAX5841 (R/W= 0 selects the write condi-
tion, R/W= 1 selects the read condition). After
receiving the proper address, the MAX5841 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5841 has four different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to VDD sets A0 = 1. This feature allows up to four
MAX5841s to share the same bus.
Write Data Format
In write mode (R/W= 0), data that follows the address
byte controls the MAX5841 (Figure 5). Bits C3–C0 con-
figure the MAX5841 (Table 3). Bits D9–D0 are DAC
data. Bits S0 and S1 are sub-bits and are always zero.
Input and DAC registers update on the falling edge of
SCL during the acknowledge bit. Should the write cycle
be prematurely aborted, data is not updated and the
write cycle must be repeated. Figure 6 shows two
example write data sequences.
Extended Command Mode
The MAX5841 features an extended command mode
that is accessed by setting C3–C0 = 1 and D9–D6 = 0.
The next data byte writes to the shutdown registers
(Figure 7). Setting bits A, B, C, or D to 1 sets that DAC
SCL
SDA
SS
rP
Figure 2. START and STOP Conditions
SCL
SDA
STOP START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 3. Early STOP Conditions
S A6A5A4A3A2A1A0R/W
Figure 4. Slave Address Byte Definition
C3 C2 C1 C0 D9 D8 D7 D6
Figure 5. Command Byte Definition
PART VADD DEVICE ADDRESS
(A6...A0)
MAX5841L GND 0111 100
MAX5841L VDD 0111 101
MAX5841M GND 1011 100
MAX5841M VDD 1011 101
Table 2. MAX5841 I2C Slave Addresses
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
______________________________________________________________________________________ 11
to the selected power-down mode based on the states
of PD0 and PD1 (Table 1). Any combination of the four
DACs can be controlled with a single write sequence.
Read Data Format
In read mode (R/W= 1), the MAX5841 writes the con-
tents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5841. The device transmits the first byte of
data, waits for the master to acknowledge, then trans-
mits the second byte. Figure 8 shows an example read
data sequence.
I2C Compatibility
The MAX5841 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typ-
ical I2C application. The communication protocol sup-
ports the standard I2C 8-bit communications. The
general call address is ignored. The MAX5841 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital Feedthrough Suppression
When the MAX5841 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5841 2-wire digital interface is I2C/SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and Ground
Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass VDD with a 0.1µF capacitor to
ground as close to the device as possible.
Chip Information
TRANSISTOR COUNT: 17,213
PROCESS: BiCMOS
S
MSB
MSB
A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D9 D8 D7 D6
D5 D4 D3 D2 D1 D0 S1 S0 P
R/W ACK
ACK
ACK
LSB MSB LSB
EXAMPLE WRITE DATA SEQUENCE
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
LSB
S
MSB
MSB
A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D9 D8 D7 D6
X X D C B A PD1 PD0 P
R/W ACK
ACK
ACK
LSB MSB LSB
LSB
Figure 6. Example Write Command Sequences
X X D C B A PD1 PD0
Figure 7. Extended Command Byte Definition
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
12 ______________________________________________________________________________________
SERIAL DATA INPUT
C3 C2 C1 C0 D9 D8 D7 D6 FUNCTION
0000
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC A input and DAC registers with new data.
Contents of DAC B, C, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
0001
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC B input and DAC registers with new data.
Contents of DAC A, C, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
0010
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC C input and DAC registers with new data.
Contents of DAC A, B, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
0011
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC D input and DAC registers with new data.
Contents of DAC A, B, and C input registers are transferred
to the respective DAC registers. All outputs are updated
simultaneously.
0100
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC A input register with new data. DAC outputs
remain unchanged.
0101
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC B input register with new data. DAC outputs
remain unchanged.
0110
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC C input register with new data. DAC outputs
remain unchanged.
0111
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC D input register with new data. DAC outputs
remain unchanged.
1000
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC A input register.
1001
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC B input register.
1010
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC C input register.
1011
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC D input register.
1100
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all DACs with new data and update all DAC outputs
simultaneously. Input and DAC registers are updated with
new data.
1101
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all input registers with new data. DAC outputs remain
unchanged.
Table 3. Command Byte Definitions
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
______________________________________________________________________________________ 13
SERIAL DATA INPUT
C3 C2 C1 C0 D9 D8 D7 D6 FUNCTION
1110 X X X XUpdate all DAC outputs simultaneously. Device ignores D9-
D6. Do not send the data byte.
1111 0 0 0 0E xtend ed com m and m od e. The next w or d w r i tes to the p ow er -
d ow n r eg i ster s ( E xtend ed C om m and M od e) .
1111 0 0 0 1Read DAC A data. The device expects an Sr condition
followed by an address word with R/W = 1.
1111 0 0 1 0Read DAC B data. The device expects an Sr condition
followed by an address word with R/W = 1.
1111 0 1 0 0Read DAC C data. The device expects an Sr condition
followed by an address word with R/W = 1.
1111 1 0 0 0Read DAC D data. The device expects an Sr condition
followed by an address word with R/W = 1.
Table 3. Command Byte Definitions (continued)
SA6A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D9 D8 D7 D6
Sr A6 A5 A4 A3 A2 A1 A0
MSB LSB MSB LSB
LSBMSB
ACK ACK
ACK
D5 D4 D3 D2 D1 D0 S1 S0
MSB LSB
ACK
ACK P
R/W
= 1 XX
PD1 PD0 D9 D8 D7 D6
MSB LSB
DATA BYTES GENERATED BY MASTER DEVICE
DATA BYTES GENERATED BY MAX5841 ACK GENERATED BY
MASTER DEVICE
R/W
= 0
Figure 8. Example Read Word Data Sequence
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
14 ______________________________________________________________________________________
10-BIT
DAC
A
INPUT
REGISTER
A
MUX AND DAC
REGISTER
RESISTOR
NETWORK
POWER-DOWN
CIRCUITRY
SERIAL
INTERFACE
10-BIT
DAC
B
RESISTOR
NETWORK
REF
SDA ADD SCL VDD GND
OUTA
OUTB
MAX5841
INPUT
REGISTER
B
MUX AND DAC
REGISTER
10-BIT
DAC
C
INPUT
REGISTER
C
MUX AND DAC
REGISTER
RESISTOR
NETWORK
10-BIT
DAC
D
RESISTOR
NETWORK
OUTC
OUTD
INPUT
REGISTER
D
MUX AND DAC
REGISTER
Functional Diagram
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
10LUMAX.EPS
