Dual Differential 16-Bit, 1 MSPS
PulSAR ADC 12.0 mW in QSOP
Data Sheet
AD7903
FEATURES
16-bit resolution with no missing codes
Throughput: 1 MSPS
Low power dissipation
7.0 mW at 1 MSPS (VDD1 and VDD2 only)
12.0 mW at 1 MSPS (total)
140 µW at 10 kSPS
INL: ±0.5 LSB typical, ±2.0 LSB maximum
SINAD: 93.5 dB at 1 kHz
THD: −112 dB at 1 kHz
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.4 V to 5.1 V
Allows use of any input range
Easy to drive with the ADA4941-1
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Serial port interface (SPI)/QSPI/MICROWIRE/DSP compatible
20-lead QSOP package
Wide operating temperature range: −40°C to +125°C
APPLICATIONS
Battery-powered equipment
Communications
Automated test equipment (ATE)
Data acquisition
Medical instrumentation
Redundant measurement
Simultaneous sampling
GENERAL DESCRIPTION
The AD7903 is a dual 16-bit, successive approximation, analog-
to-digital converter (ADC) that operates from a single power
supply, VDDx, per ADC. It contains two low power, high speed,
16-bit sampling ADCs and a versatile serial port interface (SPI).
On the CNVx rising edge, the AD7903 samples the voltage
difference between the INx+ and INx− pins. The voltages on
these pins usually swing in opposite phases between 0 V and
VREF. The externally applied reference voltage of the REFx pins
(VREF) can be set independently from the supply voltage pins,
VDDx. The power of the device scales linearly with throughput.
Using the SDIx inputs, the SPI-compatible serial interface can
also daisy-chain multiple ADCs on a single 3-wire bus and provide
an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V,
or 5 V logic, using the separate VIOx supplies.
The AD7903 is available in a 20-lead QSOP package with operation
specified from −40°C to +125°C.
Table 1. MSOP 14-/16-/18-Bit PulSAR® ADCs
Bits
100
kSPS
250
kSPS
400 kSPS
to 500 kSPS
1000
kSPS
ADC
Driver
18 AD76911 AD76901 AD79821 ADA4941-1
ADA4841-x
16 AD7680 AD76851 AD76861 AD79801 ADA4941-1
AD7683 AD76871 AD76881 AD7903 ADA4841-x
AD7684 AD7694 AD76931 AD7902
14
AD7940
AD7942
1
AD7946
1
1 Pin-for-pin compatible.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
AD7903 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Circuit Information .................................................................... 14
Converter Operation .................................................................. 14
Typical Connection Diagram.................................................... 15
Analog Inputs.............................................................................. 15
Driver Amplifier Choice ........................................................... 16
Single-to-Differential Driver .................................................... 16
Voltage Reference Input ............................................................ 17
Power Supply ............................................................................... 17
Digital Interface .......................................................................... 17
CS Mode ...................................................................................... 18
Chain Mode ................................................................................ 22
Applications Information .............................................................. 24
Simultaneous Sampling ............................................................. 24
Functional Safety Considerations ............................................ 25
Layout ............................................................................................... 26
Evaluating Performance of the AD7903.................................. 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
8/14—Rev. A to Rev. B
Changed Standby Current Unit from nA to µA ........................... 4
Changes to Power Supply Section ................................................ 17
1/14—Rev. 0 to Rev. A
Change to Gain Error Temperature Drift Parameter .................. 3
Changes to Figure 12 ........................................................................ 9
Changes to Figure 17 and Figure 20............................................. 10
Changes to Figure 28 ...................................................................... 11
12/13—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet AD7903
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.1
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range INx+ − INx− −VREF +VREF V
Absolute Input Voltage
INx+, INx−
−0.1
V
REF
+ 0.1
V
Common-Mode Input Range INx+, INx− VREF × 0.475 VREF × 0.5 VREF × 0.525 V
Analog Input CMRR fIN = 450 kHz 67 dB
Leakage Current at 25°C Acquisition phase 200 nA
Input Impedance See the Analog Inputs section
ACCURACY
No Missing Codes 16 Bits
Differential Nonlinearity Error VREF = 5 V −1.0 ±0.4 +1.0 LSB2
VREF = 2.5 V ±0.7 LSB2
Integral Nonlinearity Error
V
REF
= 5 V
−2.0
±0.5
+2.0
LSB
2
VREF = 2.5 V ±0.4 LSB2
Transition Noise VREF = 5 V 0.75 LSB2
VREF = 2.5 V 1.2 LSB2
Gain Error3 TMIN to TMAX −0.04 ±0.006 +0.04 % FS
Gain Error Temperature Drift
0.19
ppm/°C
Gain Error Match3 TMIN to TMAX 0.0 0.025 % FS
Offset Error3 TMIN to TMAX −0.5 ±0.015 +0.5 mV
Offset Temperature Drift 0.3 ppm/°C
Offset Error Match3 TMIN to TMAX 0.05 1.0 mV
Power Supply Sensitivity VDD = 2.5 V ± 5% ±0.1 LSB2
THROUGHPUT
Conversion Rate VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V
above 85°C, up to 125°C
0 1 MSPS
Transient Response Full-scale step 290 ns
AC ACCURACY
Dynamic Range
V
REF
= 5 V
95.5
dB
4
VREF = 2.5 V 92.5 dB4
Oversampled Dynamic Range fOUT = 10 kSPS 113.5 dB4
Signal-to-Noise Ratio (SNR) fIN = 1 kHz, VREF = 5 V 92 94 dB4
fIN = 1 kHz, VREF = 2.5 V 89 91 dB4
Spurious-Free Dynamic Range (SFDR) fIN = 1 kHz −115 dB4
Total Harmonic Distortion (THD) fIN = 1 kHz −112 dB4
Signal-to-(Noise + Distortion) (SINAD) fIN = 1 kHz, VREF = 5 V 91.5 93.5 dB4
fIN = 1 kHz, VREF = 2.5 V 88.5 90.5 dB4
Channel-to-Channel Isolation fIN = 10 kHz −120 dB4
1 In this data sheet, the voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively.
2 With the 5 V input range, 1 LSB = 152.6 µV. With the 2.5 V input range, 1 LSB = 76.3 µV.
3 See the Terminology section. These specifications include full temperature range variation, but they do not include the error contribution from the external reference.
4 All specifications in decibels (dB) are referred to a full-scale input FSR. Although these parameters are referred to full scale, they are tested with an input signal at 0.5 dB below
full scale, unless otherwise specified.
Rev. B | Page 3 of 28
AD7903 Data Sheet
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.1
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE
Voltage Range 2.4 5.1 V
Load Current 1 MSPS, VREF = 5 V, each ADC 330 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 10 MHz
Aperture Delay VDD = 2.5 V 2.0 ns
Aperture Delay Match VDD = 2.5 V 2.0 ns
DIGITAL INPUTS
Logic Levels
VIL VIO > 3 V −0.3 +0.3 × VIO V
VIO ≤ 3 V −0.3 +0.1 × VVIO V
VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V
IIL −1 +1 µA
I
IH
−1
+1
µA
DIGITAL OUTPUTS
Data Format Twos complement Bits
Pipeline Delay No delay; conversion results available
immediately after conversion is complete
0 Samples
VOL ISINK = +500 µA 0.4 V
VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
VDDx 2.375 2.5 2.625 V
VIOx Specified performance 2.3 5.5 V
VIOx Range Full Range 1.8 5.5 V
I
VDDx
Each ADC
1.4
1.6
mA
IVIOx Each ADC 0.2 0.45 mA
Standby Current2, 3 VDD and VIO = 2.5 V, 25°C 0.35 µA
Power Dissipation 10 kSPS throughput 140 µW
1 MSPS throughput 12.0 16 mW
VDD Only 7.0 mW
REF Only 3.3 mW
VIO Only 1.7 mW
Energy per Conversion 7.0 nJ/sample
TEMPERATURE RANGE4
Specified Performance TMIN to TMAX −40 +125 °C
1 In this data sheet, the voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively.
2 With all digital inputs forced to VIOx or to ground as required.
3 During the acquisition phase.
4 Contact Analog Devices, Inc., for the extended temperature range.
Rev. B | Page 4 of 28
Data Sheet AD7903
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time (CNVx Rising Edge to Data Available) tCONV 500 710 ns
Acquisition Time tACQ 290 ns
Time Between Conversions tCYC
VIOx Above 2.3 V 1000 ns
CNVx Pulse Width (CS Mode) tCNVH 10 ns
SCKx Period (CS Mode) tSCK
VIOx Above 4.5 V 10.5 ns
VIOx Above 3 V 12 ns
VIOx Above 2.7 V 13 ns
VIOx Above 2.3 V 15 ns
SCKx Period (Chain mode) tSCK
VIOx Above 4.5 V 11.5 ns
VIOx Above 3 V 13 ns
VIOx Above 2.7 V 14 ns
VIOx Above 2.3 V 16 ns
SCKx Low Time tSCKL 4.5 ns
SCKx High Time tSCKH 4.5 ns
SCKx Falling Edge to Data Remains Valid tHSDO 3 ns
SCKx Falling Edge to Data Valid Delay tDSDO
VIOx Above 4.5 V 9.5 ns
VIOx Above 3 V 11 ns
VIOx Above 2.7 V 12 ns
VIOx Above 2.3 V 14 ns
CNVx or SDIx Low to SDOx, D15 (MSB) Valid (CS Mode) tEN
VIOx Above 3 V 10 ns
VIOx Above 2.3 V 15 ns
CNVx or SDIx High or Last SCKx Falling Edge to SDOx High Impedance (CS Mode) tDIS 20 ns
SDIx Valid Setup Time from CNVx Rising Edge (CS Mode) tSSDICNV 5 ns
SDIx Valid Hold Time from CNVx Rising Edge (CS Mode) tHSDICNV 2 ns
SCKx Valid Setup Time from CNVx Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCKx Valid Hold Time from CNVx Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDIx Valid Setup Time from SCKx Falling Edge (Chain Mode) tSSDISCK 2 ns
SDIx Valid Hold Time from SCKx Falling Edge (Chain Mode) tHSDISCK 3 ns
SDIx High to SDOx High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns
Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing
500µA I
OL
500µA I
OH
1.4V
TO SDOx
C
L
20pF
11755-002
X% VIOx
1
Y% VIOx
1
V
IH2
V
IL2
V
IL2
V
IH2
t
DELAY
t
DELAY
1
FOR VIOx ≤ 3.0V, X = 90 AND Y = 10; FOR VIOx > 3.0V, X = 70 AND Y = 30.
2
MINIMUM V
IH
AND MAXIMUM V
IL
USED. SEE SPECIFICATIONS FOR DIGITAL
INPUTS PARAMETER IN TABLE 3.
11755-003
AD7903 Data Sheet
Rev. B | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
INx+, INx− to GND1 −0.3 V to VREF + 0.3 V or ±10 mA
Supply Voltage
REFx, VIOx to GND −0.3 V to +6.0 V
VDDx to GND −0.3 V to +3.0 V
VDDx to VIOx +3 V to −6 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperatures
Vapor Phase (60 sec) 255°C
Infrared (15 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 See the Analog Inputs section for an explanation of INx+ and INx−.
Data Sheet AD7903
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin
No. Mnemonic Type1 Description
1, 6 REF1, REF2 AI Reference Input Voltage. The REFx range is 2.4 V to 5.1 V. These pins are referred to the GND pin, and
decouple each pin closely to the GND pin with a 10 μF capacitor.
2, 7 VDD1, VDD2 P Power Supplies.
3, 8 IN1+, IN2+ AI Differential Positive Analog Inputs.
4, 9 IN1−, IN2− AI Differential Negative Analog Inputs.
5, 10 GND P Power Supply Ground.
11, 16 CNV2, CNV1 DI Conversion Inputs. These inputs have multiple functions. On the leading edge, they initiate conversions
and select the interface mode of the device: chain mode or active low chip select (CS) mode. In CS mode,
the SDOx pins are enabled when the CNVx pins are low. In chain mode, the data must be read when the CNVx
pins are high.
12, 17 SDO2, SDO1 DO Serial Data Outputs. The conversion result is output on these pins. The conversion result is synchronized
to SCKx.
13, 18 SCK2, SCK1 DI Serial Data Clock Inputs. When the device is selected, the conversion results are shifted out by these clocks.
14, 19 SDI2, SDI1 DI Serial Data Inputs. These inputs provide multiple functions. They select the interface mode of the ADC, as
follows: CS mode is selected if the SDIx pins are high during the CNVx rising edge. In this mode, either SDIx
or CNVx can enable the serial output signals when low. If SDIx or CNVx is low when the conversion is
complete, the busy indicator feature is enabled.
15, 20 VIO2, VIO1 P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (2.5 V or 3.3 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD1
IN1+
IN1–
VDD2
REF2
GND
REF1
SDI1
SCK1
SDO1
SDI2
VIO2
CNV1
GND
IN2–
IN2+
CNV2
SDO2
SCK2
VIO1
AD7903
TOP VI EW
(Not to Scale)
11755-004
AD7903 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, TA = 25°C, fSAMPLE = 1 MSPS, unless otherwise noted.
Figure 5. Integral Nonlinearity vs. Code, VREF = 5 V
Figure 6. Integral Nonlinearity vs. Code, VREF = 2.5 V
Figure 7. FFT Plot, VREF = 5 V
Figure 8. Differential Nonlinearity vs. Code, VREF = 5 V
Figure 9. Differential Nonlinearity vs. Code, VREF = 2.5 V
Figure 10. FFT Plot, VREF = 2.5 V
065536
163843276849152
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
INL (LSB)
CODE
11755-405
POSITIVE I NL: +0.35 LSB
NEGATIVE INL:–0.39 LSB
065536163843276849152
POSITIVE INL: +0.39 LSB
NEGATIVE INL: –0.44 LSB
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
INL (LSB)
CODE
11755-406
0500100 200 300 400
11755-407
0
–180
–160
–140
–120
–100
–80
–60
–40
–20
SNR (dB)
FRE Q UE NCY ( kHz )
f
SAMPLE
= 1MSPS
f
IN
= 10kHz
SNR = 95. 04dB
THD = –117.3d B
SF DR = 114.6d B
SINAD = 95.02d B
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
DNL(LSB)
CODE
11755-408
065536163843276849152
POSITIVE DNL: +0.31 LSB
NEGATIVE DNL: –0.38 LSB
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
DNL (LSB)
CODE
11755-409
065536163843276849152
POSITIVE DNL: +0.39 LSB
NEGATIVE DNL: –0.39 LSB
11755-410
0
–180
–160
–140
–120
–100
–80
–60
–40
–20
SNR (dB)
FRE Q UE NCY ( kHz )
f
SAMPLE
= 1MSPS
f
IN
= 10kHz
SNR = 91. 96dB
THD = –110.2d B
SF DR = 114.5d B
SINAD = 91.91d B
0500100 200 300 400
Rev. B | Page 8 of 28
Data Sheet AD7903
Figure 11. Histogram of a DC Input at the Code Center, VREF = 5 V
Figure 12. Histogram of a DC Input at the Code Transition, VREF = 5 V
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 14. Histogram of a DC Input at the Code Center, VREF = 2.5 V
Figure 15. SNR vs. Input Level
Figure 16. THD, SFDR vs. Reference Voltage
45000
40000
35000
30000
25000
20000
15000
10000
5000
0FFE1 FFE2 FFE3 FFE4 FFE5 FFE6 FFE7 FFE8 FFE9 FFEA
NUMBER OF OCCURRENCES
CODES IN HEX
11755-411
40000
35000
30000
25000
20000
15000
10000
5000
0FFD2 FFD3 FFD4 FFD5 FFD6 FFD7 FFD8 FFD9 FFDA FFDB
NUMBER O F O CCURRE NCE S
CODES IN HEX
11755-412
100
98
96
94
92
90
88
86
84
82
80
16.0
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
SNR, SINAD (dB)
ENO B ( Bits)
REFERENCE VOLTAGE (V)
SNR
SINAD
ENOB
11755-413
45000
40000
35000
30000
25000
20000
15000
10000
5000
0FFF1 FFF2 FFF3 FFF4 FFF5 FFF6 FFF7 FFF8 FFF9 FFFBFFFA
NUMBER OF OCCURRENCES
CODES IN HEX
11755-414
98
97
96
95
94
93
92 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
SNR (dB)
INPUT LEVEL (d B)
11755-415
–95
–125
–110
–115
–105
–100
–120
115
85
100
95
105
110
90
2.25 5.25
REFERENCE VOLTAGE (V)
THD ( dB)
SF DR ( dB)
2.75 3.25 3.75 4.25 4.75
THD
SFDR
11755-416
Rev. B | Page 9 of 28
AD7903 Data Sheet
Figure 17. SINAD vs. Input Frequency
Figure 18. SNR vs. Temperature
Figure 19. Operating Currents of Each ADC vs. VDD Supply Voltage
Figure 20. THD vs. Input Frequency
Figure 21. THD vs. Temperature
Figure 22. Operating Currents of Each ADC vs. Sample RateCr
96
85
86
87
88
89
90
91
92
93
94
95
10
INPUT F RE QUENCY ( kHz )
SINAD (dB)
100
11755-417
94.8
93.4
93.6
93.8
94.0
94.2
94.4
94.6
TEMPERATURE (°C)
SNR (dB)
–55 –35 –15 525 45 65 85 105 125
11755-418
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CURRENT ( mA)
2.425 2.475
VDD VOLTAGE (V)
2.375 2.525 2.575 2.625
IVDD
IREF
IVIO
11755-050
–80
–85
–90
–95
–100
–105
–110
–115
–12010
INPUT F RE QUENCY ( kHz )
THD ( dB)
100
11755-420
–100
–105
–110
–115
–120
–125
TEMPERATURE (°C)
THD ( dB)
–55 –35 –15 525 45 65 85 105 125
11755-421
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
10 100
SAMPLE RATE (kSPS)
CURRENT ( mA)
1000
IVDD
IVIO
TA = 25° C
11755-422
Rev. B | Page 10 of 28
Data Sheet AD7903
Figure 23. Operating Currents of Each ADC vs. Temperature
Figure 24. Offset Error vs. Temperature
Figure 25. Gain Error vs. Temperature
Figure 26. Power-Down Current of Each ADC vs. Temperature
Figure 27. Offset Error Match vs. Temperature
Figure 28. Gain Error Match vs. Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CURRENT ( mA)
–55 –35 –15 525
TEMPERATURE (°C)
45 65 85 105 125
IVDD
IREF
IVIO
11755-053
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TEMPERATURE (°C)
OFF SET ERROR (mV)
–55 –35 –15 525 45 65 85 105 125
11755-424
0.05
–0.05
–0.03
–0.01
0.01
0.03
TEMPERATURE (°C)
GAI N E RROR (% FS)
–55 –35 –15 525 45 65 85 105 125
11755-425
8
7
6
5
4
3
2
1
0
CURRENT ( µ A)
–55 –35 –15 525
TEMPERAT URE ( °C)
45 65 85 105 125
I
VDD
+ I
VIO
11755-054
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TEMPERATURE (°C)
OFFS E T ERRO R M ATCH (mV)
–55 –35 –15 525 45 65 85 105 125
11755-427
0.010
–0.010
–0.005
0
0.005
TEMPERATURE (°C)
GAI N E RROR MATCH (% F S )
–55 –35 –15 525 45 65 85 105 125
11755-428
Rev. B | Page 11 of 28
AD7903 Data Sheet
Figure 29. Channel-to-Channel Isolation vs. Temperature
Figure 30. Channel-to-Channel Isolation vs. Input Frequency
–112
–113
–114
–115
–116
–117
–118
–119
–120
–121
TEMPERATURE (°C)
–55–35–15 5 25 45 65 85 105125
f
IN
=10kHz
f
SAMPLE
= 1MSPS
11755-429
CHANNEL-TO-CHANNEL ISOLATION (dB)
–112
–124
–122
–120
–118
–116
–114
10
INPUT F RE QUENCY ( M Hz )
CHANNEL - TO- CHANNE L IS OLATION (d B)
100
11755-430
Rev. B | Page 12 of 28
Data Sheet AD7903
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
Offset error is the difference between the ideal midscale voltage
(that is, 0 V) and the actual voltage producing the midscale
output code (that is, 0 LSB).
Offset Error Match
It is the difference in offsets, expressed in millivolts between the
channels of a multichannel converter. It is computed with the
following equation:
Offset Matching = VOFFSETMAX − VOFFSETMIN
where:
VOFFSETMAX is the most positive offset error.
VOFFSETMIN is the most negative offset error.
Offset matching is usually expressed in millivolts with the full-
scale input range stated in the product data sheet.
Gain Error
The first transition (from 100 … 00 to 100 … 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) occurs for an analog voltage that is 1½ LSB below the
nominal full scale (4.999943 V for the ±5 V range). The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition from
the difference between the ideal levels.
Gain Error Match
It is the ratio of the maximum full scale to the minimum full
scale of a multichannel ADC. It is expressed as a percentage of
full scale using the following equation:
%100
2
×
+
−
=
MIN
MAX
MIN
MAX
FSRFSR
FSRFSR
MatchingGain
where:
FSRMAX is the most positive gain error of the ADC.
FSRMIN is the most negative gain error.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
ENOB is expressed in bits.
Noise Free Code Resolution
Noise free code resolution is the number of bits beyond which it
is impossible to distinctly resolve individual codes. It is calculated
as follows:
Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise)
Noise free code resolution is expressed in bits.
Effective Resolution
Effective resolution is calculated as follows:
Effective Resolution = log2(2N/RMS Input Noise)
Effective resolution is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels (dB).
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels (dB). It is
measured with a signal at −60 dBFS to include all noise sources
and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels (dB).
Signal-to-(Noise + Distortion) (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels (dB).
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNVx input and
when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Rev. B | Page 13 of 28
AD7903 Data Sheet
Rev. B | Page 14 of 28
THEORY OF OPERATION
Figure 31. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7903 is a fast, low power, precise, dual 16-bit ADC
using a successive approximation architecture.
The AD7903 is capable of simultaneously converting 1,000,000
samples per second (1 MSPS) and powers down between con-
versions. When operating at 10 kSPS, for example, it typically
consumes 70 μW per ADC, making it ideal for battery-powered
applications.
The AD7903 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multichannel multiplexed applications.
The AD7903 can be interfaced to any 1.8 V to 5 V digital logic
family. It is available in a 20-lead QSOP that allows flexible
configurations.
The device is pin-for-pin compatible with the pseudo differential,
16-bit AD7902.
CONVERTER OPERATION
The AD7903 is a dual successive approximation ADC based on
a charge redistribution DAC. Figure 31 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase of each ADC, terminals of the
array tied to the input of the comparator are connected to GND
via SWx+ and SWx−. All independent switches are connected
to the analog inputs. Therefore, the capacitor arrays are used as
sampling capacitors and acquire the analog signal on the INx+
and INx− inputs. When the acquisition phase is complete and
the CNVx input goes high, a conversion phase is initiated. When
the conversion phase begins, SWx+ and SWx− are opened first.
The two capacitor arrays are then disconnected from the inputs
and connected to the GND input. Therefore, the differential
voltage between the INx+ and INx− inputs, captured at the end
of the acquisition phase, is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and REFx,
the comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7903 has an on-board conversion clock, the
serial clock, SCKx, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7903 is shown in
Figure 32 and Table 7.
Figure 32. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input,
VREF = 5 V
Digital Output
Code (Hex)
FSR − 1 LSB +4.999962 V 0x7FFF1
Midscale + 1 LSB +38.15 μV 0x0001
Midscale 0 V 0x0000
Midscale − 1 LSB −38.15 μV 0xFFFF
−FSR + 1 LSB −4.999962 V 0x8001
−FSR −5 V 0x80002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
COMP
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNVx
CONTROL
LOGIC
SWx+LSB
SWx–LSB
INx+
REFx
GND
INx–
MSB
MSB
CC4C 2C16,384C32,768C
CC4C 2C16,384C32,768C
11755-011
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE ( TWO S CO M P L E M E NT)
ANALO G INP UT
+F S R – 1.5 L S B
+FSR – 1 L S B
–FSR + 1 LS B
–FSR
–FSR + 0.5 LSB
11755-112
Data Sheet AD7903
Rev. B | Page 15 of 28
TYPICAL CONNECTION DIAGRAM
Figure 35 shows an example of the recommended connection
diagram for the AD7903 when multiple supplies are available.
ANALOG INPUTS
Figure 33 shows an equivalent circuit of the input structure of
the AD7903.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, INx+ and INx−. The analog input signal must never
exceed the reference input voltage (VREF) by more than 0.3 V. If
the analog input signal exceeds this level, the diodes become
forward biased and start conducting current. These diodes can
handle a forward-biased current of 130 mA maximum.
However, if the supplies of the input buffer (for example, the
supplies of the ADA4841-1 in Figure 35) are different from
those of the VREF, the analog input signal may eventually exceed
the supply rails by more than 0.3 V. In such a case (for example,
an input buffer with a short circuit), the current limitation can
be used to protect the device.
Figure 33. Equivalent Analog Input Circuit
The analog input structure allows for the sampling of the
differential signal between INx+ and INx−. By using these
differential inputs, signals common to both inputs, and within
the allowable common-mode input range, are rejected.
Figure 34. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog inputs
(INx+ or INx−) can be modeled as a parallel combination of the
CPIN capacitor and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase, where the switches are closed, the
input impedance is limited to CPIN. RIN and CIN make a one-pole,
low-pass filter that reduces undesirable aliasing effects and limits
noise.
When the source impedance of the driving circuit is low, the
AD7903 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The
dc performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
Figure 35. Typical Application Diagram with Multiple Supplies
C
PIN
REFx
R
IN
C
IN
D1
D2
INx+ OR INx–
GND
11755-114
90
85
80
75
70
65
60
1k 10k 100k 1M 10M
FREQUENCY (Hz)
CMRR (dB)
11755-040
AD7903
ADCx
3-WIRE INTERFACE
2.5V
V+
1.8V TO 5V
100nF
10µF
2
100nF
REFx
INx+
INx–
VDDx VIOx SDIx
CNVx
SCKx
SDOx
GND
REF
1
20Ω
V+
V–
0V TO V
REF
2.7nF
4
20Ω
V+
V–
V
REF
TO 0V
ADA4841-1
3
2.7nF
4
1
SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2
C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE RECOMMENDED LAYOUT IN FIGURE 54.
3
SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4
OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.
11755-013
AD7903 Data Sheet
DRIVER AMPLIFIER CHOICE
Although the AD7903 is easy to drive, the driver amplifier must
meet the following requirements:
• The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7903. The noise from the driver is
filtered by the one-pole, low-pass filter of the AD7903
analog input circuit, made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7903 is 40 µV rms, the SNR degradation due to the
amplifier is
+
=
−2
2
)(
2
π
40
40
log20
N
3dB
LOSS
Nef
SNR
where:
f−3dB is the input bandwidth, in megahertz, of the AD7903
(10 MHz) or the cutoff frequency of the input filter, if one
is used.
N is the noise gain of the amplifier (for example, gain = 1
in buffer configuration; see Figure 35).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
• For ac applications, the driver must have a THD performance
that is commensurate with the AD7903.
• For multichannel, multiplexed applications, the driver
amplifier and the AD7903 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This may differ
significantly from the settling time at a 16-bit level. Be sure
to verify the settling time prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4941-1 Very low noise, low power, single to differential
ADA4841-x Very low noise, small, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8655 5 V single supply, low noise
AD8605, AD8615 5 V single supply, low power
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either bipolar
or unipolar, the ADA4941-1 single-ended-to-differential driver
allows a differential input to the device. The schematic is shown
in Figure 36.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R1 = 4 kΩ and R2 = 1 kΩ.
R3 and R4 set the common mode on the INx− input, and R5 and
R6 set the common mode on the INx+ input of the ADC. The
common mode must be close to VREF/2. For example, for the
±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ,
R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
Figure 36. Single-Ended-to-Differential Driver Circuit
20Ω
20Ω
10µF
R1
100nF
+2.5V
+5V REF
+5.2V
–0.2V
CF
R2
R4
R6
±10V,
±5V, ..
R3
R5
REFx VDDx
GND
INx+
INx–
AD7903
ADCx
2.7nF
2.7nF
ADA4941-1
IN
FB
OUTP
OUTN
REF
100nF
11755-115
Rev. B | Page 16 of 28
Data Sheet AD7903
VOLTAGE REFERENCE INPUT
The AD7903 voltage reference input, REF, has a dynamic input
impedance and must therefore be driven by a low impedance
source with efficient decoupling between the REFx and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference decoupling capacitor with values as small
as 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REFx
and GND pins.
POWER SUPPLY
The AD7903 uses two power supply pins per ADC: a core supply
(VDDx) and a digital input/output interface supply (VIOx).
VIOx allows direct interface with any logic between 1.8 V and
5.5 V. To reduce the number of supplies needed, VIOx and VDDx
can be tied together. The AD7903 is independent of power supply
sequencing between VIOx and VDDx. Additionally, it is very
insensitive to power supply variations over a wide frequency
range, as shown in Figure 37.
Figure 37. PSRR vs. Frequency
The AD7903 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the
sampling rate. This makes the part ideal for low sampling rates
(of even a few hertz) and low battery-powered applications.
Figure 38. Operating Currents per ADC vs. Sampling Rate
DIGITAL INTERFACE
Although the AD7903 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7903 is compatible with SPI, QSPI,
digital hosts, and DSPs. In this mode, the AD7903 can use either
a 3-wire or 4-wire interface. A 3-wire interface using the CNVx,
SCKx, and SDOx signals minimizes wiring connections useful,
for instance, in isolated applications. A 4-wire interface using
the SDIx, CNVx, SCKx, and SDOx signals allows CNVx, which
initiates the conversions, to be independent of the readback
timing (SDIx). This is useful in low jitter sampling or
simultaneous sampling applications.
When in chain mode, the AD7903 provides a daisy-chain feature
using the SDIx input for cascading multiple ADCs on a single
data line similar to a shift register. With the AD7903 housing
two ADCs in one package, chain mode can be utilized to
acquire data from both ADCs while using only one set of 4-wire
user interface signals.
The mode in which the device operates depends on the SDIx
level when the CNVx rising edge occurs. CS mode is selected if
SDIx is high, and chain mode is selected if SDIx is low. The
SDIx hold time is such that when SDIx and CNVx are connected
together, chain mode is always selected.
In either mode, the AD7903 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must time
out the maximum conversion time prior to readback.
The busy indicator feature is enabled as follows:
• In CS mode if CNVx or SDIx is low when the ADC
conversion ends (see Figure 42 and Figure 46).
• In chain mode if SCKx is high during the CNVx rising
edge (see Figure 50).
95
90
85
80
75
70
65
60
PSRR (dB)
1k 10k 100k 1M
FREQUENCY ( Hz )
11755-139
10
1
0.1
0.01
0.001
OPE RATING CURRENT S ( mA)
100000
SAMPLING RATE (SPS)
10000 1000000
I
REF
11755-137
I
VDD
I
VIO
Rev. B | Page 17 of 28
AD7903 Data Sheet
Rev. B | Page 18 of 28
CS MODE
CS Mode, 3-Wire Interface Without Busy Indicator
CS mode, using a 3-wire interface without a busy indicator, is
usually used when a single AD7903 is connected to a SPI-
compatible digital host.
The connection diagram is shown in Figure 39, and the
corresponding timing diagram is shown in Figure 40.
With SDIx tied to VIOx, a rising edge on CNVx initiates a
conversion, selects CS mode, and forces SDOx to high
impedance. When a conversion is initiated, it continues until
completion, irrespective of the state of CNVx. This can be
useful, for instance, to bring CNVx low to select other SPI
devices, such as analog multiplexers.
However, to avoid generation of the busy signal indicator, CNVx
must be returned high before the minimum conversion time
elapses and then held high for the maximum possible conversion
time. When the conversion is complete, the AD7903 enters the
acquisition phase and powers down. When CNVx goes low, the
MSB is automatically output onto SDOx. The remaining data bits
are clocked by subsequent SCKx falling edges. The data is valid on
both SCKx edges. Although the rising edge can be used to capture
the data, a digital host using the falling edge of SCKx allows a
faster reading rate, provided that it has an acceptable hold time.
After the 16th SCKx falling edge or when CNVx goes high
(whichever occurs first), SDOx returns to high impedance.
Figure 39. CS Mode, 3-Wire Interface Without Busy Indicator Connection Diagram (SDIx High)
Figure 40. CS Mode, 3-Wire Interface Without Busy Indicator Serial Interface Timing (SDI High)
AD7903
SDIx SDOx
CNVx
SCKx
CONVERT
DATA IN
CLK
DIGITAL HOST
VIOx
11755-116
SDIx = 1
t
CNVH
t
CONV
t
CYC
CNVx
ACQUISITION ACQUISITION
t
ACQ
t
SCK
t
SCKL
CONVERSION
SCKx
t
EN
t
HSDO
123 14 1516
t
DSDO
t
DIS
t
SCKH
SDOx D15 D14 D13 D1 D0
11755-216
Data Sheet AD7903
Rev. B | Page 19 of 28
CS Mode, 3-Wire Interface with Busy Indicator
CS mode, using a 3-wire interface with a busy indicator, is
usually used when a single AD7903 is connected to an SPI-
compatible digital host having an interrupt input.
The connection diagram is shown in Figure 41, and the
corresponding timing is shown in Figure 42.
With SDIx tied to VIOx, a rising edge on CNVx initiates
a conversion, selects CS mode, and forces SDOx to high
impedance. SDOx is maintained in high impedance until the
completion of the conversion, irrespective of the state of CNVx.
Prior to the minimum conversion time, CNVx can be used to
select other SPI devices, such as analog multiplexers, but CNVx
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high impedance
to low impedance. With a pull-up on the SDOx line, this transition
can be used as an interrupt signal to initiate the data reading
controlled by the digital host. The AD7903 then enters the
acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCKx falling edges. The
data is valid on both SCKx edges. Although the rising edge can
be used to capture the data, a digital host using the SCKx falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the optional 17th SCKx falling edge or when
CNVx goes high (whichever occurs first), SDOx returns to high
impedance.
If multiple ADCs are selected at the same time, the SDOx output
pin handles this contention without damage or induced latch-up.
Meanwhile, it is recommended that this contention be kept as
short as possible to limit extra power dissipation.
Figure 41. CS Mode, 3-Wire Interface with Busy Indicator Connection Diagram (SDIx High)
Figure 42. CS Mode, 3-Wire Interface with Busy Indicator Serial Interface Timing (SDIx High)
AD7903
SDIx SDOx
CNVx
SCKx
CONVERT
DATA IN
CLK
DIGITAL HOST
VIOx
IRQ
VIOx
47kΩ
11755-118
t
CONV
t
CNVH
t
CYC
ACQUISITION ACQUISITION
t
ACQ
t
SCK
t
SCKH
t
SCKL
CONVERSION
SCKx
CNVx
SDIx = 1
SDOx D15 D14 D1 D0
t
HSDO
123 15 1617
t
DSDO
t
DIS
11755-218
AD7903 Data Sheet
Rev. B | Page 20 of 28
CS Mode, 4-Wire Interface Without Busy Indicator
CS mode, using a 4-wire interface without a busy indicator, is
usually used when both ADCs within the AD7903 are
connected to a SPI-compatible digital host.
See Figure 43 for an AD7903 connection diagram example. The
corresponding timing diagram is shown in Figure 44.
With SDIx high, a rising edge on CNVx initiates a conversion,
selects CS mode, and forces SDOx to high impedance. In this
mode, CNVx must be held high during the conversion phase
and the subsequent data readback. (If SDIx and CNVx are low,
SDOx is driven low.) Prior to the minimum conversion time,
SDIx can be used to select other SPI devices, such as analog
multiplexers, but SDIx must be returned high before the
minimum conversion time elapses and then held high for the
maximum possible conversion time to avoid the generation of
the busy signal indicator. When the conversion is complete, the
AD7903 enters the acquisition phase and powers down. Each
ADC result can be read by bringing its respective SDIx input
low, which consequently outputs the MSB onto SDOx. The
remaining data bits are then clocked by subsequent SCKx falling
edges. The data is valid on both SCKx edges. Although the rising
edge can be used to capture the data, a digital host using the
SCKx falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16th SCKx falling edge or when
SDIx goes high (whichever occurs first), SDOx returns to high
impedance, and another ADC result can be read.
Figure 43. CS Mode, 4-Wire Interface Without Busy Indicator Connection Diagram
Figure 44. CS Mode, 4-Wire Interface Without Busy Indicator Serial Interface Timing
AD7903
ADC2
SDI2 SDO2
CNV2
SCK2
CONVERT
DATA IN
CLK
DIGITAL HOST
CS1
CS2
AD7903
ADC1
SDI1 SDO1
CNV1
SCK1
11755-120
tCONV
tCYC
ACQUISITION ACQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCKx
CNVx
tSSDICNV
tHSDICNV
SDOx D115 D113D114 D11D
10D
215 D214 D21D20
tHSDO
tEN
1 2 3 14 1516 1718 30 3132
tDSDO tDIS
SDI1 (CS1)
SDI2 (CS2)
11755-220
Data Sheet AD7903
Rev. B | Page 21 of 28
CS Mode, 4-Wire Interface with Busy Indicator
CS mode, using a 4-wire interface with a busy indicator, is
usually used when an AD7903 is connected to a SPI-compatible
digital host with an interrupt input. This CS mode is also used
when it is desirable to keep CNVx, which is used to sample the
analog input, independent of the signal that is used to select the
data reading. This independence is particularly important in
applications where low jitter on CNVx is desired.
The connection diagram is shown in Figure 45, and the
corresponding timing is given in Figure 46.
With SDIx high, a rising edge on CNVx initiates a conversion,
selects CS mode, and forces SDOx to high impedance. In this
mode, CNVx must be held high during the conversion phase
and the subsequent data readback. (If SDIx and CNVx are low,
SDOx is driven low.) Prior to the minimum conversion time,
SDIx can be used to select other SPI devices, such as analog
multiplexers, but SDIx must be returned low before the
minimum conversion time elapses and then held low for the
maximum possible conversion time to guarantee the generation
of the busy signal indicator. When the conversion is complete,
SDOx goes from high impedance to low impedance. With a
pull-up on the SDOx line, this transition can be used as an
interrupt signal to initiate the data readback controlled by the
digital host. The AD7903 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCKx falling edges. The data is valid on both SCKx
edges. Although the rising edge can be used to capture the data,
a digital host using the SCKx falling edge allows a faster reading
rate, provided that it has an acceptable hold time. After the
optional 17th SCKx falling edge or SDIx going high (whichever
occurs first), SDOx returns to high impedance.
Figure 45. CS Mode, 4-Wire Interface with Busy Indicator Connection Diagram
Figure 46. CS Mode, 4-Wire Interface with Busy Indicator Serial Interface Timing
AD7903
SDIx SDOx
CNVx
SCKx
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIOx
47kΩ
CS1
11755-122
t
CONV
t
CYC
A
CQUISITION
t
SSDICNV
ACQUISITION
t
ACQ
t
SCK
t
SCKH
t
SCKL
CONVERSION
SDIx
t
HSDICNV
SCKx
CNVx
SDOx
t
EN
D15 D14 D1 D0
t
HSDO
123 15 1617
t
DSDO
t
DIS
11755-222
AD7903 Data Sheet
Rev. B | Page 22 of 28
CHAIN MODE
Chain Mode Without Busy Indicator
Chain mode without a busy indicator can be used to daisy-
chain both ADCs within an AD7903 on a 3-wire serial interface.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
See Figure 47 for a connection diagram example using both
ADCs in an AD7903. The corresponding timing is shown in
Figure 48.
When SDIx and CNVx are low, SDOx is driven low. With SCKx
low, a rising edge on CNVx initiates a conversion, selects chain
mode, and disables the busy indicator. In this mode, CNVx is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDOx and the AD7903 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCKx falling edges. For
each ADC, SDIx feeds the input of the internal shift register and
is clocked by the SCKx falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCKx edges.
Although the rising edge can be used to capture the data, a
digital host using the SCKx falling edge allows a faster reading
rate and, consequently, more AD7903 devices in the chain,
provided that the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
Figure 47. Chain Mode Without Busy Indicator Connection Diagram
Figure 48. Chain Mode Without Busy Indicator Serial Interface Timing
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7903
ADC2
SDI2 SDO2
CNV2
SCK2
AD7903
ADC1
SDI1 SDO1
CNV1
SCK1
11755-124
t
CONV
t
CYC
t
SSDISCK
t
SCKL
t
SCK
t
HSDISCK
t
ACQ
ACQUISITION
t
SSCKCNV
ACQUISITION
t
SCKH
CONVERSION
SDO1 = SDI2
t
HSCKCNV
SCKx
CNVx
SDI1 = 0
SDO2
t
EN
D
1
15 D
1
14 D
1
13
D
2
15 D
2
14 D
2
13 D
2
1D
2
0D
1
15 D
1
14 D
1
0D
1
1
D
1
1D
1
0
t
HSDO
1 2 3 15161714 18 30 31 32
t
DSDO
11755-224
Data Sheet AD7903
Rev. B | Page 23 of 28
Chain Mode with Busy Indicator
Chain mode with a busy indicator can also be used to daisy-
chain both ADCs within an AD7903 on a 3-wire serial interface
while providing a busy indicator. This feature is useful for reducing
component count and wiring connections, for example, in isolated
multiconverter applications or for systems with limited interfacing
capacity. Data readback is analogous to clocking a shift register.
See Figure 49 for a connection diagram example using three
AD7903 ADCs. The corresponding timing is shown in Figure 50.
When SDIx and CNVx are low, SDOx is driven low. With SCKx
high, a rising edge on CNVx initiates a conversion, selects chain
mode, and enables the busy indicator feature. In this mode, CNVx
is held high during the conversion phase and the subsequent data
readback. When all ADCs in the chain have completed their
conversions, the SDOx pin of the ADC closest to the digital host
(see the ADC labeled ADCx in the AD7903 B box in Figure 49)
is driven high. This transition on SDOx can be used as a busy
indicator to trigger the data readback controlled by the digital host.
The AD7903 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCKx falling edges. For each ADC,
SDIx feeds the input of the internal shift register and is clocked
by the SCKx falling edge. Each ADC in the chain outputs its
data MSB first, and 16 × N + 1 clocks are required to read back
the N ADCs. Although the rising edge can be used to capture the
data, a digital host using the SCKx falling edge allows a faster
reading rate and, consequently, more ADCs in the chain,
provided that the digital host has an acceptable hold time.
Figure 49. Chain Mode with Busy Indicator Connection Diagram
Figure 50. Chain Mode with Busy Indicator Serial Interface Timing
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7903
SDIxB SDOxB
CNVx
SCKx
AD7903
AD7903 A AD7903 B
SDI1A SDO1A
CNVx
SCKx IRQ
AD7903
SDI2A SDO2A
CNVx
ADCx
ADC1 ADC2
SCKx
11755-126
NOTES
1. DASHED LINE DENOTED ADCs ARE WITHIN A GIVEN PACKAGE.
2. SDI1A AND SDO1A REFER TO THE SDI1 AND SDO1 PINS IN ADC1 IN THE FIRST AD7903 OF THE CHAIN (AD7903 A).
SDI2A AND SDO2A REFER TO THE SDI2 AND SDO2 PINS IN ADC2 OF AD7903 A. LIKEWISE, SDIxB AND SDOxB REFER
TO THE SDIx AND SDOx PINS IN BOTH ADC1 AND ADC2 OF THE SECOND AD7903 IN THE CHAIN (AD7903 B)
tCONV
tCYC
tSSDISCK
tSCKH
tSCK
t
HSDISCK
tACQ
tDSDOSDI
tDSDOSDI
tDSDODSI
ACQUISITION
tSSCKCNV
ACQUISITION
tSCKL
CONVERSION
tHSCKCNV
SCKx
CNVx = SDI1
A
S
DO1
A
=SDI2
A
S
DO2
A
=SDIx
B
SDOx
B
tEN
D
A1
15 D
A1
14 D
A1
13
D
A2
15 D
A2
14 D
A2
13
D
Bx
15 D
Bx
14 D
Bx
13
D
A2
1D
A2
0D
A1
15 D
A1
14 D
A1
1D
A1
0
D
Bx
1D
Bx
0D
A2
15 D
A2
14 D
A1
0D
A1
1D
A2
0D
A2
1D
A1
14D
A1
15
D
A1
1D
A1
0
tHSDO
123 1516174 1819 3132333435 474849
tDSDO
tDSDOSDI
tDSDOSDI
11755-226
AD7903 Data Sheet
APPLICATIONS INFORMATION
SIMULTANEOUS SAMPLING
By having two unique user interfaces, the AD7903 provides
maximum flexibility with respect to how conversion results are
accessed from the device. The AD7903 provides an option for
the two user interfaces to share the convert start (CNVx) signal
from the digital host, creating a 2-channel, simultaneous sampling
device. In applications such as control applications, where latency
between the sampling instant and the availability of results in
the digital host is critical, it is recommended that the AD7903
be configured as shown in Figure 51. This configuration allows
simultaneous data reads, in addition to simultaneous sampling.
However, this configuration also requires an additional data
input pin on the digital host. This scenario allows the fastest
throughput because it requires only 15 or 16 SCKx falling edges
(depending on the status of the busy indicator) to acquire data
from the ADC.
Alternatively, for applications where simultaneous sampling is
required but pins on the digital host are limited, the two user
interfaces on the AD7903 can be connected in one of the daisy-
chain configurations shown in Figure 47 and Figure 49. This daisy
chaining allows the user to implement simultaneous sampling
functionality while requiring only one digital host input pin.
This scenario requires 31 or 32 SCKx falling edges (depending
on the status of the busy indicator) to acquire data from the ADC.
Figure 51 shows an example of a simultaneous sampling system
using two data inputs for the digital host. The corresponding
timing diagram in Figure 52 shows a CS mode, 3-wire simul-
taneous sampling serial interface without a busy indicator.
However, any of the 3-wire or 4-wire serial interface timing
options can be used.
Figure 51. Potential Simultaneous Sampling Connection Diagram
Figure 52. Potential Simultaneous Sampling Serial Interface Timing
VIO1 VIO2
CONVERT
DATA IN 2
CLK
DIGITAL HOST
DATA IN 1
AD7903
ADC2
SDI2 SDO2
CNV2
SCK2
AD7903
ADC1
SDI1 SDO1
CNV1
SCK1
11755-324
SDIx = 1
tCNVH
tCONV
tCYC
CNVx
ACQUISITION ACQUISITION
tACQ
tSCK
tSCKL
CONVERSION
SCKx
tEN
tHSDO
123 14 15 16
tDSDO tDIS
tSCKH
SDO1 D15 D14 D13 D1 D0
SDO2 D15 D14 D13 D1 D0
11755-316
Rev. B | Page 24 of 28
Data Sheet AD7903
FUNCTIONAL SAFETY CONSIDERATIONS
The AD7903 contains two physically isolated ADCs, making it
ideally suited for functional safety applications. Because of this
isolation, each ADC features an independent user interface, an
independent reference input, an independent analog input, and
independent supplies. Physical isolation renders the device
suitable for taking verification/backup measurements while
separating the verification ADC from the system under control.
Although the Simultaneous Sampling section describes how to
operate the device in a simultaneous nature, the circuit is actually
composed of two individual signal chains. This separation makes
the AD7903 ideal for handling redundant measurement
applications. Implementing a signal chain with redundant ADC
measurement can contribute to a no single error system. Figure 53
shows a typical functional safety application circuit consisting of
a redundant measurement with the employment of monitoring the
inverted signal. The inversion is applied to detect common cause
failures where it is expected that the circuit output moves in the
same direction during a fault condition, instead of moving in the
opposite direction as expected.
In addition, the QSOP package that houses the device provides
access to the leads for inspection.
Figure 53. Typical Functional Safety Block Diagram
11755-146
GND
VDD1 VDD2
2.5V
REF1 REF2
REF = 2.5V T O 5V
ADC1
IN1+
IN1–
VIO1
SDI1
SCK1
CNV1
SDO1
SDI1
SCK1
CNV1
SDO1
SDI2
VIO1
VIO2
SCK2
CNV2
SDO2
ADC2
IN2+
IN2–
VIO2
SDI2
SCK2
CNV2
SDO2
AD7903
REF
±10V, ±5V, ...
ADA4941-1
ADA4941-1
PHYSICALLY
ISOLATED ADCs
Rev. B | Page 25 of 28
AD7903 Data Sheet
LAYOUT
Design the printed circuit board (PCB) of the AD7903 such that
the analog and digital sections are separated and confined to
certain areas of the board. The pinout of the AD7903, with its
analog signals on the left side and its digital signals on the right
side, eases this task.
Avoid running digital lines under the device because these couple
noise onto the die unless a ground plane under the AD7903 is used
as a shield. Do not run fast switching signals, such as CNVx or
clocks, near analog signal paths. Avoid crossover of digital and
analog signals. To avoid signal fidelity issues, take care to ensure
monotonicity of digital edges in the PCB layout.
Use at least one ground plane. It can be shared between or split
between the digital and analog sections. In the latter case, join
the planes underneath the AD7903.
The AD7903 voltage reference inputs, REF1 and REF2, have a
dynamic input impedance. Decouple these reference inputs with
minimal parasitic inductances by placing the reference decoupling
ceramic capacitor in close proximity to (ideally, right up
against) the REFx and GND pins and then connecting them
with wide, low impedance traces.
Finally, decouple the power supplies, VDDx and VIOx, with
ceramic capacitors, typically 100 nF. Place them in close proximity
to the AD7903 and connect them using short, wide traces to
provide low impedance paths and to reduce the effect of glitches
on the power supply lines.
See Figure 54 for an example of layout following these rules.
EVALUATING PERFORMANCE OF THE AD7903
Other recommended layouts for the AD7903 are outlined in
User Guide UG-609. The package for the evaluation board
(EVAL-AD7903SDZ) includes a fully assembled and tested
evaluation board, user guide, and software for controlling the
board from a PC via the EVAL-SDP-CB1Z.
Figure 54. Example Layout of the AD7903 (Top Layer)
11755-147
REF1
VDD1
IN1+
IN1–
GND
REF2
VDD2
IN2+
IN2–
GND
VIO1
SDI1
SCK1
SDO1
CNV1
VIO2
SDI2
SCK2
SDO2
CNV2
GND
REF
REF
REF
GND
GND
GNDVDD
VDD GND
VIO
VIO
GND
Rev. B | Page 26 of 28
Data Sheet AD7903
Rev. B | Page 27 of 28
OUTLINE DIMENSIONS
Figure 55. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
AD7903BRQZ −40°C to +125°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 Tube, 56
AD7903BRQZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 Reel, 1,000
EVAL-AD7903SDZ Evaluation Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS Compliant Part.
COMPLIANT TO JEDEC STANDARDS MO-137-AD
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
20 11
101
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0.64)
BSC
0.041 (1.04)
REF
0.010 (0.25)
0.006 (0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
8°
0°
COPLANARITY
0.004 (0.10)
0.065 (1.65)
0.049 (1.25) 0.069 (1.75)
0.053 (1.35)
0.345 (8.76)
0.341 (8.66)
0.337 (8.55)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
08-19-2008-A
AD7903 Data Sheet
Rev. B | Page 28 of 28
NOTES
©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11755-0-8/14(B)