AC175 ACT175 S4AC/74AC175 S54ACTI74ACT175 Quad D Flip-Flop Description Connection Diagrams The 'AC/ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are wal] ~ [16] vec common. The information on the D inputs is stored a during the LOW-to-HIGH clock transition. Both true oo [2 Hs} a and complemented outputs of each flip-flop are Go [3] [ia] Gs provided. A Master Reset input resets all flip-flops, Oo [4] ria} D3 independent of the Clock or D inputs, when LOW. of Fay 5 12| D2 * Edge-Triggered D-Type Inputs & [E] a] G2 Buffered Positive Edge-Triggered Clock * Asynchronous Common Reset of fig] a2 * True and Complement Output ono [8] gice Outputs Source/Sink 24 mA * *ACT175 has TTL-Compatible Inputs Pin Assignment for DIP, Flatpak and SOIC 5 Ordering Code: See Section 6 Logic Symbol | | | | Do Di D2 D3 -1 cP Oj MR Qo Go Gi Gi G2 Az Qs Q3 fia] 3) 6 fz] [eg] @ oO NC DO: G PIPER TT Pin Assignment for LCC Pin Names Do - Da Data Inputs CP Clock Pulse Input MR Master Reset Input Qo-Q3 True Outputs Q3-@3 Complement Outputs 5-89AC175 ACT175 Functional Description The 'AC/ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and @ outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and @ outputs HIGH independent of Clock or Data inputs. The *AC/ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Logic Diagram Truth Table Inputs Outputs @tn, MR=H @tn+1 Dn Qn Gn L L H H H L H=HIGH Voltage Level L= LOW Voltage Level tn= Bit Time before Clock Pulse tn+1=Blt Time after Ciock Pulse MA CP OD Dz D: Do Do Dp oa L D a D a L___9icp o Lol cp a L_olce a cP a cD cD co cD Q: Q. G: @ Q: Qa Gi Qc Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.DC Characteristics (unless otherwise specified) AC175 ACT175 Symbol Parameter S4ACIACT 74AC/ACT Units Conditions Vin = Voc or Maximum Quiescent Ground, Ice Supply Current 160 80 HA Vec = 5.5 V, Ta= Worst Case Vin = Vcc or Maximum Quiescent Ground, lec Supply Current 8.0 8.0 HA Vcc =5.5 V, TA = 25C . wg: Vin = Voc -2.1 V Maximum Additional locT : 1.6 1.5 mA Vcc =5.5 V, Icc/Input (ACT175) Ta = Worst Case AC Characteristics 74AC 54AC 74AC : 7 Tas 425C Ta= 55C | Ta= 40C Symbol _ Parameter Vec* CL= 50 pF to +125C | to +85C | Units | Fig. (V) =orP C.=50 pF | CL=50 pF No. a b Min Typ Max | Min Max | Min Max Maximum Glock - 8.3 148 frnax Frequency ~ /|:6.0 4140 MHz | 33 Propagation Delay 73:3 95 tHE CP to Qn or Gn 5.0 FQ ns | 36 Propagation Delay 3.3 8.5 tPLH CP to Qn or On 6.0 6.0 ns | 36 Propagation Delay 3.3 7.5 oe . tPHL MR to Qn 5.0 55 ns | 36 Propagation Delay 3.3 8.5 , tet MA to Gn 5.0 6.0 ns | 36 *Voltage Range 3.3 is 3.0 V+0.3 V Voitage Range 5.0 is .0 V+0.5 V Military parameters given herein are for general references only. For current military specifications and subgroup testing information please request Fairchilds Table | data sheet from your Fairchild sales engineer or account representative. 5-91AC175 ACT175 AC Operating Requirements ~ 74AC 54AC 74AC Ta= 55C Ta= 40C _- 9 Vec* Tan tae to + 125C to +85C | Units | Fig. (Vv) awe CL=50 pF CL=50 pF No. Typ Guaranteed Minimum f y ts HIGH or LOW: eel do | ns | 39 Dn to CP oo i. f I ? " no y | - tn Hold Time, HIGH or LOW] 3.$/[ /O ipo * 7[f f ns | 39 Dn to CP 5.0 om : io: ony tw CP Pulse Width 33 | 55 | Typ ns | 38 HIGH or LOW 5.0 4.0 ad - 5 , ; 3.3 | 55 ee ffs tw MR Puise Width, LOW 5.0 40 TS" a 36 Recovery Time 3.3 0 a : tree MR to CP 5.0 0 ns | 39 Voltage Range 3.3 is 3.3 V+03V Voltage Range 5.0 is 50 V+05V AC Characteristics 74ACT 54ACT 74ACT Ta= 55C | Ta= 40C _ oO Symbol Parameter Vec* on tare to +125C | to +85C | Units | Fig. (V) =oue C.=50 pF | C.=50 pF No. Min Typ Max | Min Max |] Min Max fmax Maximum Clock 5.0 | 175 160 95 145 MHz | 3-3 Frequency Propagation Delay tPLH CP to Qn or Gn 5.0 1.0 6.0 10.0 1.0 11.5 1.0 11.0 ns 3-6 Propagation Delay | tPHL CP to Qn or Gn 5.0 1.0 7.0 11.0 1.0 13.0 1.0 12.0 ns 3-6 Propagation Delay tPLH MR to Qn 5.0 1.0 6.0 9.5 1.0 11.5 1.0 10.5 ns 3-6 Propagation Delay tPHL MR to Qn 5.0 1.0 5.5 9.5 1.0 11.0 1.0 10.5 ns 3-6 Voltage Range 5.0 is 50V+05V Military parameters given herein are for generat references only. For current military specifications and subgroup testing information please request Fairchilds Table | data sheet from your Fairchild sales engineer or account representative. 5-92AC Operating Requirements AC175 ACT175 74ACT 54ACT 74ACT 2 | Ta=+25C Ta= 55C Ta= 40C Symbol Parameter Vcc CL =50 pF to + 125C to + 85C Units | Fig. (Vv) =ourP CL=50 pF CL=50 pF No. Typ Guaranteed Minimum (H) | Setup Time 3.0 2.0 2.5 2.0 ts 1) | Dn to cP 50 | 30 | 25 3.0 25 ns | 39 Hold Time, HIGH or LOW th Dn to CP 5.0 0 1.0 1.0 1.0 ns 3-9 CP Pulse Width tw HIGH or LOW 5.0 40 3.0 5.0 3.5 ns 3-6 tw MR Pulse Width, LOW 5.0 4.0 35 5.0 4.0 ns 3-6 trec Recovery Time, MR to CP] 5.0 0 0 0.5 0 ns 3-9 *Voltage Range 5.0 is 5.0 V+ 0.5 V Military parameters given herein are for general references only. For current military specifications and subgroup testing in- formation please request Fairchilds Table | data sheet from your Fairchild sales engineer or account representative. Capacitance 54/74AC/ACT Symbol Parameter Units Conditions Typ CIN Input Capacitance 4.5 pF Vec=5.5 V Power Dissipation _ Crp Capacitance 45.0 pF Vec=5.5 V 5-93