SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Bidirectional Transceiver
D
Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B and ITU
Recommendation V.11
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
3-State Driver and Receiver Outputs
D
Individual Driver and Receiver Enables
D
Wide Positive and Negative Input/Output
Bus Voltage Ranges
D
Driver Output Capability...±60 mA Max
D
Thermal-Shutdown Protection
D
Driver Positive- and Negative-Current
Limiting
D
Receiver Input Impedance...12 kΩ Min
D
Receiver Input Sensitivity...±200 mV
D
Receiver Input Hysteresis...50 mV Typ
D
Operates From Single 5-V Supply
D
Low Power Requirements
description
The SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data
communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets
ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11.
The SN75176A combines a 3-state differential line driver and a differential input line receiver, both of which
operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,
respectively, that can be externally connected together to function as a direction control. The driver differential
outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus
ports that are designed to offer minimum loading to the bus whenever the driver is disabled or V CC = 0. These
ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line
applications.
The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input
impedance of 12 kΩ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN75176A can be used in transmission-line applications employing the SN75172 and SN75174 quadruple
differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN75176A is characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D OR P PACKAGE
(TOP VIEW)
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z
RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
A – B RE R
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
X H Z
Open L ?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic symbol†
RE
DE
1
1
2
B
A
7
6
EN2
EN1
R
D
1
4
2
3
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
DE
RE
R
6
7
3
1
2
B
ABus
D4
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
Output
85 Ω
NOM
TYPICAL OF RECEIVER OUTPUT
Input/Output
Port
960 Ω
NOM
16.8 kΩ
NOM
TYPICAL OF A AND B I/O PORTS
Enable inputs: R(eq) = 8 kΩ NOM
Driver input: R(eq) = 3 kΩ NOM
R(eq)
VCC
EQUIVALENT OF EACH INPUT
VCC
Input
960 Ω
NOM
VCC
GND
R(eq) = equivalent resistor
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus terminal –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°CDERATING FACTOR T
A
= 70
_
C T
A
= 105
_
C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
D725 mW 5.8 mW/°C 464 mW 261 mW
P 1100 mW 8.8 mW/°C 704 mW 396 mW
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN TYP MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal (separately or common mode), VI or VIC –7 12 V
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 2) ±12 V
High level out
p
ut current IOH
Driver –60 mA
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OH Receiver –400 µA
Low level out
p
ut current IOL
Driver 60
mA
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OL Receiver 8
mA
Operating free-air temperature, TA0 70 °C
NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VOH
High level out
p
ut voltage
V
IH
= 2 V, V
IL
= 0.8 V,
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
IH ,
IOH = –33 mA
IL ,
.
V
VOL
Low level out
p
ut voltage
V
IH
= 2 V, V
IL
= 0.8 V,
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
IH ,
IOH = 33 mA
IL ,
.
V
|VOD1|Differential output voltage IO = 0 2VOD2 V
|VOD2|
Differential out
p
ut voltage
RL = 100 Ω, See Figure 1 2 2.7
V
|V
OD2
|
Differential
o
u
tp
u
t
v
oltage
RL = 54 Ω, See Figure 1 1.5 2.4
V
∆|VOD| Change in magnitude of differential output voltage‡±0.2 V
VOC Common-mode output voltage§RL = 54 Ω or 100 Ω,
See Figure 1 3 V
∆|VOC|
Chan
g
e in ma
g
nitude of common-mode output
±02
V
∆|V
OC
|
gg
voltage‡
±0
.
2
V
IO
Out
p
ut current
Output disabled, VO = 12 V 1
mA
I
O
O
u
tp
u
t
c
u
rrent
,
See Note 3 VO = – 7 V –0.8
mA
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V –400 µA
VO = –7 V –250
IOS Short-circuit output current VO = VCC 250 mA
VO = 12 V 500
ICC
Su
pp
ly current (total
p
ackage)
No load
Outputs enabled 35 50
mA
I
CC
S
u
ppl
y
c
u
rrent
(total
package)
No
load
Outputs disabled 26 40
mA
†All typical values are at VCC = 5 V and TA = 25°C.
‡∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC respectively , that occur when the input is changed from a high level to a low
level.
§In ANSI Standard EIA/TIA-422-B, VOC, which is the average of the two output voltages with respect to GND, is called output offset voltage, VOS.
NOTE 3: This applies for both power on and off; refer to ANSI Standard EIA/TIA-422-B for exact conditions.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time
RL=60Ω
See Figure 3
40 60 ns
tt(OD) Differential-output transition time
R
L =
60
Ω
,
See
Fig
u
re
3
65 95 ns
tPZH Output enable time to high level RL = 110 Ω, See Figure 4 55 90 ns
tPZL Output enable time to low level RL = 110 Ω, See Figure 5 30 50 ns
tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 85 130 ns
tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 20 40 ns
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2‡V
Vhys Input hysteresis voltage (VIT+ – VIT–)50 mV
VIK Enable clamp voltage II = –18 mA –1.5 V
VOH
High level out
p
ut voltage
V
ID
= 200 mV, I
OH
= –400
µ
A,
27
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
ID ,
See Figure 2
OH µ,
2
.
7
V
VOL
Low level out
p
ut voltage
V
ID
= –200 mV, I
OL
= 8 mA,
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
ID ,
See Figure 2
OL ,
.
V
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
II
Line in
p
ut current
Other input = 0 V, VI = 12 V 1
mA
I
I
Line
inp
u
t
c
u
rrent
,
See Note 3 VI = –7 V –0.8
mA
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V –100 µA
riInput resistance 12 kΩ
IOS Short-circuit output current –15 –85 mA
ICC
Su
pp
ly current (total
p
ackage)
No load
Outputs enabled 35 50
mA
I
CC
S
u
ppl
y
c
u
rrent
(total
package)
No
load
Outputs disabled 26 40
mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output
VID = 15Vto15V
See Figure 6
21 35 ns
tPHL Propagation delay time, high-to-low-level output
V
ID = –
1
.
5
V
to
1
.
5
V
,
See
Fig
u
re
6
23 35 ns
tPZH Output enable time to high level
See Figure 7
10 30 ns
tPZL Output enable time to low level
See
Fig
u
re
7
12 30 ns
tPHZ Output disable time from high level
See Figure 7
20 35 ns
tPLZ Output disable time from low level
See
Fig
u
re
7
17 25 ns
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
2
RL
VOD2
VOC
2
RL
Figure 1. Driver VOD and VOC
VOL
VOH
–IOH
+IOL
VID
0 V
Figure 2. Receiver VOH and VOL
3 V
VOLTAGE WAVEFORMS
tt(OD)
td(OD)
1.5 V
10%
tt(OD)
≈ 2.5 V
≈– 2.5 V
90%
50%
Output
td(OD)
0 V
3 V
1.5 V
Input
TEST CIRCUIT
Output
CL = 50 pF
(see Note B)
50 ΩRL = 60 Ω
Generator
(see Note A)
50%
10%
CL
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
tPHZ
1.5 V
2.3 V
0.5 V
0 V
3 V
tPZH
Output
Input 1.5 V
S1
0 or 3 V
Output
CL = 50 pF
(see Note B)
TEST CIRCUIT
50 Ω
VOH
Voff ≈ 0 V
RL = 110 Ω
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOLTAGE WAVEFORMS
5 V
VOL
0.5 V
tPZL
3 V
0 V
tPLZ
2.3 V
1.5 V
Output
Input
TEST CIRCUIT
Output
RL = 110 Ω
5 V
S1
CL = 50 pF
(see Note B)
50 Ω
3 V or 0
Generator
(see Note A)
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
1.3 V
0 V
3 V
VOL
VOH
tPHL
tPLH
1.5 V
Output
Input
TEST CIRCUIT
CL = 15 pF
(see Note B)
Output
0 V
1.5 V
51 Ω
Generator
(see Note A)
1.5 V
1.3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOH
0.5 V
≈1.3 V
tPHZ
Output
Input 1.5 V
0 V
3 V S1 to 1.5 V
S2 Closed
S3 Closed
tPLZ
≈1.3 V
VOL
0.5 V
Output
Input 1.5 V
0 V
3 V
≈4.5 V
VOL
1.5 V
S3 Open
S2 Closed
S1 to –1.5 V
0 V
1.5 V
3 V
tPZL
Output
Input
0 V
1.5 V
VOH
0 V
Output
Input
tPZH S3 Closed
S2 Open
S1 to 1.5 V
1.5 V
3 V
TEST CIRCUIT
50 Ω
1N916 or Equivalent
S3
5 V
S2
2 kΩ
5 kΩ
S1
–1.5 V
1.5 V
VOLTAGE WAVEFORMS
S1 to –1.5 V
S2 Closed
S3 Closed
Generator
(see Note A)
CL = 15 pF
(see Note B)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
VOH – High-Level Output Voltage – V
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 5 V
4.5
4
3.5
3
2.5
2
1.5
1
0.5
–100–80–60–40–20
0–120
5
IOH – High-Level Output Current – mA
0
VOH
TA = 25°C
Figure 9
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VCC = 5 V
TA = 25°C
IOL – Low-Level Output Current – mA
0 12020 40 60 80 100
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
– Low-Level Output Voltage – V
VOL
Figure 10
VOD – Differential Output Voltage – V
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.5
3
2.5
2
1.5
1
0.5
908070605040302010
0100
4
IO – Output Current – mA
0
VOD
VCC = 5 V
TA = 25°C
Figure 11
VCC = 5 V
TA = 25°C
0.3
0.2
0.1
00510
VOL – Low-Level Output Voltage – V
0.4
0.5
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
15 20 25 30
IOL – Low Level Output Current – mA
ÁÁ
ÁÁ
ÁÁ
VOL
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.3
0.2
0.1
00203050
VOL – Low-Levcel Output Voltage – V
0.4
0.5
70 80
10 40 60
VCC = 5 V
VID = –0.2 V
IOL = 8 mA
ÁÁ
ÁÁ
ÁÁ
VOL
TA – Free-Air Temperature – °C
Figure 13
2
1
00 0.5 1 1.5
VO – Output Voltage – V
3
4
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
2 2.5 3
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5 V VCC = 4.75 V
ÁÁ
ÁÁ
VO
VI – Enable Voltage – V
VCC = 5.25 V
3
2
1
00 0.5 1
VO – Output Voltage – V
4
5
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
1.5 2 2.5 3
VID = 0.2 V
Load = 1 kΩ to VCC
TA = 25°C
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
ÁÁ
ÁÁ
VO
VI – Enable Voltage – V
Figure 14
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Up to 32
Transceivers
SN65176A
SN65176A
RT
RT
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths of f the main line should be kept
as short as possible.
Figure 15. Typical Application Circuit
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75176AD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176ADE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176ADR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176ADRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176AP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75176APE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75176ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75176ADR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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