MO SEL VITELIC
1
V58C3643204SAT
HIGH PERFORMANCE
3.3 VOLT 2M X 32 DDR SDRAM
4 X 512K X 32
V58C3643204SAT Rev. 1.4 August 2001
PRELIMINARY
45 50 55 60
System Frequency (fCK) 225MHz 200 MHz 183 MHz 166 MHz
Clock Cycle Time (tCK3) 5 ns 5.5 ns 6 ns
Clock Cycle Time (tCK4)4.5ns
Features
■4 banks x 512K x 32 organization
■High speed data transfer rates with system
frequency up to 225 MHz
■Data Mask for Write Control (DM)
■Four Banks controlled by BA0 & BA1
■Programmable CAS Latency: 3, 4
■Programmable Wrap Sequence: Sequential
or Interleave
■Programmable Burst Length:
2, 4, 8 full page for Sequential Type
2, 4, 8 full page for Interleave Type
■Automatic and Controlled Precharge Command
■Suspend Mode and Power Down Mode
■Auto Refresh and Self Refresh
■Refresh Interval: 2048 cycles/16ms
■Available in 100-pin TQFP
■SSTL-2 Compatible I/Os
■Double Data Rate (DDR)
■Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
■On-Chip DLL alignsDQ and DQs transitions with
CLK transitions
■Differential clock inputs CLK and CLK
■Power Supply 3.3V ± 0.3V
Description
The V58C3643204SAT is a four bank DDR
DRAM organized as 4 banks x 512K x 32. The
V58C3643204SAT achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline CLK Cycle Time (ns) Power Temperature
Mark100-pin TQFP -45 -50 -55 -60 Std. L
0°Cto70°C • •••• • • Blank
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V58C3643204SAT
Block Diagram
Row decoder
Memory array
Bank 0
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
512K x 32
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 2
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 3
Column decoder
Sense amplifier & I(O) bus
Input buffer Output buffer
DQ0-DQ
Column address
counter Column address
buffer Row address
buffer Refresh Counter
A0 - A10, BA0, BA1A0 - A7, AP, BA0, BA1
Control logic & timing generator
CLK
CKE
CS
RAS
CAS
WE
DM0-DM3
Row Addresses
Column Addresses
DLL
Strobe
Gen. Data Strobe
CLK, CLK
CLK
DQS
512K x 32 512K x32512K x 32
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V58C3643204SAT
100 Pin TQFP
PIN CONFIGURATION Top View
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
N.C
N.C
N.C
N.C
N.C
VSSQ
RFU
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
WE
CAS
RAS
CS
BA0
BA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A10
VDD
A3
A2
A1
A0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
100 Pin TQFP
20 x 14 mm2
0.65mm pin Pitch
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
VREF
DM3
DM1
CLK
CLK
CKE
MCL
A8(AP)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Pin Names
CLK, CLK Differential Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
DQS Data Strobe (Bidirectional)
A0–A10 Address Inputs
BA0, BA1 Bank Select
DQ0–DQ7Data Input/Output
DM0-DM3 Data Mask
VDD Power (3.3V ± 0.3V)
VSS Ground
VDDQ Power for I/O’s(+2.5V)
VSSQ Ground for I/O’s
NC Not connected
VREF Reference Voltage for Inputs
RFU Reserved for future use.
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V58C3643204SAT
Signal Pin Description
Pin Type Signal Polarity Function
CLK
CLK Input Pulse Positive
Edge The system clock input. All inputs except DQs and DMsare sampled on the rising edge
of CLK.
CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS,CAS
WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS,RAS,andWEdefine the
command to be executed by the SDRAM.
DQS Input/
Output Pulse Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
A0 - A10 Input Level —During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge. CAn depends from the SDRAM organization:
2M x 32 SDRAM CAn = CA7 (Page)
In addition to the column address, A8 is used to invoke autoprecharge operation at the
end of the burst read orwrite cycle. If A8 is high,autoprecharge is selected and BA0, BA1
defines the bank to be precharged. If A8 is low, autoprecharge is disabled.
During a Precharge command cycle, A8(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
BA0,
BA1 Input Level —Selects which bank is to be active.
DQx Input/
Output Level —Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM0-DM3 Input Pulse Active High In Write mode, DM has a latency of zero and operates as a word maskby allowing input
data to be written if it is low but blocks the write operation if is high.
VDD, VSS Supply Power and ground for the input buffers and the core logic.
VDDQ
VSSQ Supply ——Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VREF Input Level —SSTL Reference Voltage for Inputs
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V58C3643204SAT
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A8high when a Read or Write com-
mandisissued.IfA
10 is low when a Read or Write command is issued, then normal Read or Write burst op-
eration is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once tRAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3
Begin Autoprecharge
NOPBA R w/AP NOPNOP NOP NOP NOP BA
CK, CK
Command
DQS
DQ
tRAS(min) tRP(min)
Earliest Bank A reactivate
T9
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V58C3643204SAT
DC Characteristics
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C
Notes: 1. Measured with outputs open.
2. Refresh period is 16ms.
Absolute Maximum Ratings
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter Symbol Test Condition
Version
Unit Note-45 -50 -55 -60
Operating Current
(One Bank Active) ICC1 Burst Lenth = 2 tRC ŠtRC(min)
IOL=0mA,t
CC =t
CC(min)
350 340 330 330 mA 1
Precharge Standby Current in
Power-down mode ICC2PCKEðVIL(max),t
CC =t
CC(min) 60 mA
Precharge Standby Current in Non
Power-down mode ICC2NCKEðVIH(min),CSŠVIH(min),
tCC =t
CC(min)
165 160 155 150 mA
ActiveStandbyCurrentpower-downmode ICC3PCKEðVIL(max),t
CC =t
CC(min) 95 mA
Active Standby Current in in Non
Power-down mode ICC3NCKEŠVIH(min),CSŠVIH(min),
tCC =t
CC(min)
205 200 195 190 mA
Operating Current
(Burst Mode) ICC4 IOL =0mA,t
CC =t
CC(min),
Page Burst, All Banks activated 470 450 430 410 mA 1
Refresh Current ICC5 tRC ŠtRFC(min) 470 450 430 410 mA 2
Self Refresh Current ICC6 CKE ð0.2V 4 mA
Parameter Symbol Value Unit
VoltageonanypinrelativetoV
SS VIN,V
OUT -1.0 ~ 4.6 V
VoltageonV
DD supply relative to VSS VDD,V
DDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1.6 W
Short circuit current IOS 50 mA
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V58C3643204SAT
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 65°C)
AC Input Operating Conditions
Recommended operating conditions
(Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%, TA=0 to 65°C)
SSTL_2 AC Test Conditions
Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device.
2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions.
3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input
signal swing.
Parameter Symbol Min Typ Max Unit
Device Supply voltage VDD 3.135 3.3 3.465 V
Output Supply voltage VDDQ 2.375 2.50 2.625 V
Reference voltage VREF 0.49*VDDQ -0.51*V
DDQ V
Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V
Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V
Input logic low voltage VIL -0.30 - VREF-0.15 V
Output logic high voltage IOH =-15.2mA V
OH Vtt+0.76 - - V
Output logic low voltage VOL - - Vtt-0.76 V
Input leakage current IIL -5 - 5 µA
Output leakage current IOL -5 - 5 µA
Parameter Symbol Min Typ Max Unit
Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V
Input Low (Logic 0) Voltage; DQ VIL --V
REF-0.35 V
Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V
Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V
Symbol Parameter Value Units Notes
VREF Input Reference Voltage 0.5*VDDQ V1
VSWING (max) Input Signal Maximum Peak to Peak Swing 1.5 V 1, 2
SLEW Input Signal Minimum Slew Rate 1.0 V/ns 3
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V58C3643204SAT
SSTL_2 Output Buffers
The input voltage provided to the receiver depends on three parameters:
■VDDQ and current drive capabilities of the output buffer
■Termination voltage
■Termination resistance
■VDDQ ðVDD
Class II SSTL_2 Output Buffer (Driver)
Capacitance (VDD =3.3V,T
A=25°C,f=1MHz)
Parameter Symbol Min Max Unit
Input capacitance (A0~A10,BA
0~BA1)C
IN1 2.5 4.5 pF
Input capacitance
(CK,CK
,CKE,CS,RAS,CAS,WE)CIN2 2.5 5.0 pF
Data & DQS input/output capacitance (DQ0~DQ31)C
OUT 2.5 5.5 pF
Input capacitance (DM0 ~ DM3) CIN3 2.5 5.5 pF
V
REF
V
IN
V
TT
= 0.5 *V
DDQ
C
LOAD
= 30pF
V
DDQ
V
SSQ
V
OUT
Receiver
RT=50Ω
Output
Buffer
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V58C3643204SAT
AC Characteristics
Parameter Symbol
-45 -50 -55 -60
UnitMin Max Min Max Min Max Min Max
CK cycle time CL=3 tCK •7 5 .0 7 5.5 7 6 .0 7 ns
CL=4 4.5 •••ns
CK high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS out access time from CK tDQSCK -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns
Output access time from CK tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns
Data strobe edge to output data edge tDQSQ - 0.5 - 0.5 - 0.5 ns
Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS-In setup time tWPRES 0-0-0-ns
DQS-in hold time tWPREH 0.25 - 0.25 - 0.25 - tCK
DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Address and Control input setup time tIS 1.2 - 1.2 - 1.2 - ns
Address and Control input hold time tIH 0.9 - 0.9 - 0.9 - ns
DQ and DM setup time to DQS tDS 0.5 - 0.5 - 0.5 - ns
DQ and DM hold time to DQS tDH 0.5 - 0.5 - 0.5 - ns
Clock half period tHP tCLmin or
tCHmin
-t
CLmin or
tCHmin
-t
CLmin or
tCHmin
-ns
Output DQS valid window tQH tHP-
0.75ns -t
HP-
0.75ns -t
HP-
0.75ns -ns
Row cycle time tRC 58 60 60.5 60 ns
Refresh row cycle time tRFC 69 70 71.5 72 ns
Row active time tRAS 40 100K 44 100K 48 100K ns
RAS to CAS delay tRCD 18 20 22 24 ns
Row precharge time tRP 12 20 16.5 18 ns
RowactivetoRowactivedelay t
RRD 9 141112ns
Last data in to Row precharge tWR 2222t
CK
Last data in to Read command delay tCDLR 2222t
CK
Col. address to Col. address delay tCCD 1111t
CK
Mode register set cycle time tMRD 2222t
CK
Power down exit time tPEDX 1tCK+tIS 1tCK+tIS 1tCK+tIS ns
Self refresh exit toactive command delay tXSA 69 70 71.5 72 ns
Selfrefreshexittoreadcommanddelay t
XSR 200 200 200 tCK
Auto precharge write recovery +
Precharge tDAL 6655t
CK
Refresh interval time tREF 7.8 7.8 7.8 µs
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V58C3643204SAT
AC Characteristics
V58C3643204SAT-45
V58C3643204SAT-50
V58C3643204SAT-55
V58C3643204SAT-60
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit
250MHz (4.5ns) 4 13 15 9 4 2 4 2 tCK
222MHz (5.0ns) 3 12 14 8 4 2 4 2 tCK
183MHz (5.5ns) 3 12 14 8 4 2 4 2 tCK
166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK
143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit
200MHz (5.0ns) 3 12 14 8 4 2 4 2 tCK
183MHz (5.5ns) 3 12 14 8 4 2 4 2 tCK
166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK
143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit
183MHz (5.5ns) 3 12 14 8 4 2 4 2 tCK
166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK
143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit
166MHz (6.0ns) 3 10 12 7 3 2 3 2 tCK
143MHz (7.0ns) 3 9 11 6 3 2 3 2 tCK
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V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
Package Diagram
100-Pin TQFP
0.825
0.575
0.65
0.13 MAX
Dimensions in Millimeters
0.10 MAX
0 ~ 7∞
17.20 ± 0.20
14.00 ± 0.10
23.20 ± 0.20
1.00 ± 0.10
1.20 MAX *
0.05 MIN
0.80 ± 0.20
#1
0.09~0.20
#100
0.30 ± 0.08
20.00 ± 0.10
MO SEL VITELIC
WORLDWIDE OFFICES V58C3643204SAT
© Copyright 2001, MOSEL VITELIC Inc. 8/01
Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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