PC8548E PowerQUICC III Integrated Processor Datasheet - Preliminary Specification Features * Embedded e500 Core, Initial Offerings up to 1.2 GHz * * * * * * * * * * * * * * * * * - Dual Dispatch Superscalar, 7-stage Pipeline Design with out-of-order Issue and Execution - 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1) 36-bit Physical Addressing Enhanced Hardware and Software Debug Support Double-precision Embedded Scalar and Vector Floating-point APUs Memory Management Unit (MMU) Integrated L1/L2 Cache - L1 Cache-32 KB Data and 32 KB Instruction Cache with Line-locking Support - L2 Cache-512 KB (8-Way Set Associative); 512 KB/256 KB/128 KB/64 KB Can Be Used As SRAM - L1 and L2 Hardware Coherency - L2 Configurable As SRAM, Cache and I/O Transactions Can Be Stashed Into L2 Cache Regions Integrated DDR Memory Controller With Full ECC Support, Supporting: - 200 MHz Clock Rate (400 MHz Data Rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption Algorithms Four On-chip Triple-speed Ethernet Controllers (GMACs) Supporting 10- and 100-Mbps, and 1-Gbps Ethernet/IEEE*802.3 Networks with MII, RMII, GMII, RGMII, RTBI and TBI Physical Interfaces - TCP/IP Checksum Acceleration - Advanced QoS Features General-purpose I/O (GPIO) Serial RapidIO and PCI Express High-speed Interconnect Interfaces, Supporting - Single x8 PCI Express, or Single x4 PCI Express and Single 4x Serial RapidIO On-chip Network (OCeaN) Switch Fabric Multiple PCI Interface Support - 64-bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O) - 64-bit PCI-X Bus Controller (Up to 133 MHz, 3.3V I/O), or Flexibility to Configure Two 32-bit PCI Controllers 166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller Integrated Four-channel DMA Controller Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUAR) Support Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG Test Access Port 1.1V Core Voltage with 3.3V and 2.5V I/O, 783-pin HITCE Package Visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors SAS 2007 0831B-HIREL-12/07 PC8548E [Preliminary] Description The PC8548E contains a PowerPC(R) processor core. The PC8548E integrates a processor that implements the PowerPC architecture with system logic required for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the PC8548E Integrated Processor Preliminary Reference Manual. Screening * Full Military Temperature Range (TC = -55C, TJ = +125C) * Industrial Temperature Range (TC = -40C, TJ = +110C) 1. PC8548E Architecture General Overview Figure 1-1. PC8548E Block Diagram DDR SDRAM DDR/DDR2/ Memory Controller Security Engine Flash SDRAM GPIO Local Bus Controller XOR Engine Programmable Interrupt Controller (PIC) IRQs Serial DUART I2C I2 C Controller I2C I2 C Controller MII, GMII, TBI, RTBI, RGMII, RMII eTSEC MII, GMII, TBI, RTBI, RGMII, RMII MII, GMII, TBI, RTBI, RGMII, RMII RTBI, RGMII, RMII 10/100/1Gb eTSEC 512-Kbyte L2 Cache/ SRAM e500 Core e500 Coherency Module Core Complex Bus 32-Kbyte L1 Instruction Cache Serial RapidIOTM or PCI Express OceaN Switch Fabric 32-Kbyte L1 Data Cache 4x RapidlO x8 PCI Express 32-bit PCI Bus Interface (If 64-bit not used) PCI 32-bit 66 MHz 32-bit PCI/ 64-bit PCI/PCI-X Bus Interface PCI/PCI-X 133 MHz 10/100/1Gb eTSEC 10/100/1Gb eTSEC 10/100/1Gb 4-Channel DMA Controller 2 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 2. Features Overview The following list provides an overview of the PC8548E feature set: * High-performance 32-bit Book E-enhanced core that implements the PowerPC(R) architecture - 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. - Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. - Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. - 36-bit real addressing - Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. - Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte-4-Gbyte page sizes. - Enhanced hardware and software debug support - Performance monitor facility that is similar to, but separate from, the PC8548E performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding of these differences can be critical to ensure proper operations. * 512-Kbyte L2 cache/SRAM - Flexible configuration. - Full ECC support on 64-bit boundary in both cache and SRAM modes - Cache mode supports instruction caching, data caching, or both. - External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). - 1, 2, or 4 ways can be configured for stashing only. - Eight-way set-associative cache organization (32-byte cache lines) - Supports locking entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions. - Global locking and flash clearing done through writes to L2 configuration registers - Instruction and data locks can be flash cleared separately. - SRAM features include the following: - I/O devices access SRAM regions by marking transactions as snoopable (global). - Regions can reside at any aligned location in the memory map. - Byte-accessible ECC is protected using read-modify-write transaction accesses for smallerthan-cache-line accesses. * Address translation and mapping unit (ATMU) - Eight local access windows define mapping within local 36-bit address space. - Inbound and outbound ATMUs map to larger external address spaces. - Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express 3 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] - Four inbound windows plus a default window on RapidIO - Four outbound windows plus default translation for PCI/PCI-X and PCI Express - Eight outbound windows plus default translation for RapidIO with segmentation and subsegmentation support * DDR/DDR2 memory controller - Programmable timing supporting DDR and DDR2 SDRAM - 64-bit data interface - Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes - DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports - Full ECC support - Page mode support - Up to 16 simultaneous open pages for DDR - Up to 32 simultaneous open pages for DDR2 - Contiguous or discontiguous memory mapping - Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions - Sleep mode support for self-refresh SDRAM - On-die termination support when using DDR2 - Supports auto refreshing - On-the-fly power management using CKE signal - Registered DIMM support - Fast memory access via JTAG port - 2.5V SSTL_2 compatible I/O (1.8V SSTL_1.8 for DDR2) - Support for battery-backed main memory * Programmable interrupt controller (PIC) - Programming model is compliant with the OpenPIC architecture. - Supports 16 programmable interrupt and processor task priority levels - Supports 12 discrete external interrupts - Supports 4 message interrupts with 32-bit messages - Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller - Four global high resolution timers/counters that can generate interrupts - Supports a variety of other internal interrupt sources - Supports fully nested interrupt delivery - Interrupts can be routed to external pin for external processing. - Interrupts can be routed to the e500 core's standard or critical interrupt inputs. - Interrupt summary registers allow fast identification of interrupt source. * Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP - Four crypto-channels, each supporting multi-command descriptor chains - Dynamic assignment of crypto-execution units via an integrated controller 4 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes - PKEU: public key execution unit - RSA and Diffie-Hellman; programmable field size up to 2048 bits - Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to 511 bits - DEU: Data Encryption Standard execution unit - DES, 3DES - Two key (K1, K2, K1) or three key (K1, K2, K3) - ECB and CBC modes for both DES and 3DES - AESU: Advanced Encryption Standard unit - Implements the Rijndael symmetric key cipher - ECB, CBC, CTR, and CCM modes - 128-, 192-, and 256-bit key lengths - AFEU: ARC four execution unit - Implements a stream cipher compatible with the RC4 algorithm - 40- to 128-bit programmable key - MDEU: message digest execution unit - SHA with 160- or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm - KEU: Kasumi execution unit - Implements F8 algorithm for encryption and F9 algorithm for integrity checking - Also supports A5/3 and GEA-3 algorithms - RNG: random number generator - XOR engine for parity checking in RAID storage applications * Dual I2C controllers - Two-wire interface - Multiple master support - Master or slave I2C mode support - On-chip digital filtering rejects spikes on the bus * Boot sequencer - Optionally loads configuration data from serial ROM at reset via the I2C interface - Can be used to initialize configuration registers and/or memory - Supports extended I2C addressing mode - Data integrity checked with preamble signature and CRC * DUART - Two 4-wire interfaces (SIN, SOUT, RTS, CTS) - Programming model compatible with the original 16450 UART and the PC16550D * Local bus controller (LBC) - Multiplexed 32-bit address and data bus operating at up to 133 MHz 5 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] - Eight chip selects support eight external slaves - Up to eight-beat burst transfers - The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. - Three protocol engines available on a per chip select basis: - General-purpose chip select machine (GPCM) - Three user programmable machines (UPMs) - Dedicated single data rate SDRAM controller - Parity support - Default boot ROM chip select with configurable bus width (8, 16, or 32 bits) * Four enhanced three-speed Ethernet controllers (eTSECs) - Three-speed support (10/100/1000 Mbps) - Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers - Support for various Ethernet physical interfaces: - 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII - 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMI - Flexible configuration for multiple PHY interface configurations. - TCP/IP acceleration and QoS features available - IP v4 and IP v6 header recognition on receive - IP v4 header checksum verification and generation - TCP and UDP checksum verification and generation - Per-packet configurable acceleration - Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers - Supported in all FIFO modes - Quality of service support: - Transmission from up to eight physical queues - Reception to up to eight physical queues - Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): - EEE 802.3 full-duplex flow control (automatic PAUSE frame generation or softwareprogrammed PAUSE frame generation and recognition) - Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE 802.1 virtual local area network (VLAN) tags and priority - VLAN insertion and deletion - Per-frame VLAN control word or default VLAN for each eTSEC - Extracted VLAN control word passed to software separately - Retransmission following a collision - CRC generation and verification of inbound/outbound frames - Programmable Ethernet preamble insertion and extraction of up to 7 bytes - MAC address recognition: - Exact match on primary and virtual 48-bit unicast addresses 6 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] - VRRP and HSRP support for seamless router fail-over - Up to 16 exact-match MAC addresses supported - Broadcast address (accept/reject) - Hash table match on up to 512 multicast addresses - Promiscuous mode - Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet programming models - RMON statistics support - 10-Kbyte internal transmit and 2-Kbyte receive FIFOs - MII management interface for control and status - Ability to force allocation of header information and buffer descriptors into L2 cache * OCeaN switch fabric - Full crossbar packet switch - Reorders packets from a source based on priorities - Reorders packets to bypass blocked packets - Implements starvation avoidance algorithms - Supports packets with payloads of up to 256 bytes * Integrated DMA controller - Four-channel controller - All channels accessible by both the local and remote masters - Extended DMA functions (advanced chaining and striding capability) - Support for scatter and gather transfers - Misaligned transfer capability - Interrupt on completed segment, link, list, and error - Supports transfers to or from any local memory or I/O port - Selectable hardware-enforced coherency (snoop/no snoop) - Ability to start and flow control each DMA channel from external 3-pin interface - Ability to launch DMA from single write transaction * Two PCI/PCI-X controllers - PCI 2.2 and PCI-X 1.0 compatible - One 32-/64-bit PCI/PCI-X port with support for speeds of up to 133 MHz (maximum PCI-X frequency in synchronous mode is 110 MHz) - One 32-bit PCI port with support for speeds from 16 to 66 MHz (available when the other port is in 32-bit mode) - Host and agent mode support - 64-bit dual address cycle (DAC) support - PCI-X supports multiple split transactions - Supports PCI-to-memory and memory-to-PCI streaming - Memory prefetching of PCI read accesses - Supports posting of processor-to-PCI and PCI-to-memory writes 7 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] - PCI 3.3V compatible - Selectable hardware-enforced coherency * Serial RapidIO interface unit - Supports RapidIO Interconnect Specification, Revision 1.2 - Both 1x and 4x LP-serial link interfaces - Long- and short-haul electricals with selectable pre-compensation - Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane - Auto detection of 1x- and 4x-mode operation during port initialization - Link initialization and synchronization - Large and small size transport information field support selectable at initialization time - 34-bit addressing - Up to 256 bytes data payload - All transaction flows and priorities - Atomic set/clr/inc/dec for read-modify-write operations - Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at a remote memory system - Receiver-controlled flow control - Error detection, recovery, and time-out for packets and control symbols as required by the RapidIO specification - Register and register bit extensions as described in part VIII (Error Management) of the RapidIO specification - Hardware recovery only - Register support is not required for software-mediated error recovery. - Accept-all mode of operation for fail-over support - Support for RapidIO error injection - Internal LP-serial and application interface-level loopback modes - Memory and PHY BIST for at-speed production test * RapidIO-compliant message unit - 4 Kbytes of payload per message - Up to sixteen 256-byte segments per message - Two inbound data message structures within the inbox - Capable of receiving three letters at any mailbox - Two outbound data message structures within the outbox - Capable of sending three letters simultaneously - Single segment multicast to up to 32 devIDs - Chaining and direct modes in the outbox - Single inbound doorbell message structure - Facility to accept port-write messages * PCI Express interface - PCI Express 1.0a compatible 8 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] - Supports x8, x4, x2, and x1 link widths - Auto-detection of number of connected lanes - Selectable operation as root complex or endpoint - Both 32- and 64-bit addressing - 256-byte maximum payload size - Virtual channel 0 only - Traffic class 0 only - Full 64-bit decode with 32-bit wide windows * Pin multiplexing for the high speed I/O interfaces supports one of the following configurations: - x8 PCI Express - x4 PCI Express and 4x serial RapidIO * Power management - Supports power saving modes: doze, nap, and sleep - Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle * System performance monitor - Supports eight 32-bit counters that count the occurrence of selected events - Ability to count up to 512 counter-specific events - Supports 64 reference events that can be counted on any of the eight counters - Supports duration and quantity threshold counting - Burstiness feature that permits counting of burst events with a programmable time between bursts - Triggering and chaining capability - Ability to generate an interrupt on overflow * System access port - Uses JTAG interface and a TAP controller to access entire system memory map - Supports 32-bit accesses to configuration registers - Supports cache-line burst accesses to main memory - Supports large block (4-Kbyte) uploads and downloads - Supports continuous bit streaming of entire block for fast upload and download * IEEE 1149.1 compliant, JTAG boundary scan * 783 HITCE package 3. Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the PC8548E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 3.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 9 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 3.2 Detailed Specification This specification describes the specific requirements for the microprocessor PC8548E in compliance with e2v standard screening. 3.3 Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein. 3.3.1 Absolute Maximum Ratings Table 3-1 provides the absolute maximum ratings. Table 3-1. Absolute Maximum Ratings(1) Characteristic Symbol Max Value Unit Core supply voltage VDD -0.3 to 1.21 V PLL supply voltage AVDD -0.3 to 1.21 V Core power supply for SerDes transceivers SVDD -0.3 to 1.21 V Pad power supply for SerDes transceivers XVDD -0.3 to 1.21 V DDR and DDR2 DRAM I/O voltage GVDD -0.3 to 2.75 -0.3 to 1.98 V LVDD (for eTSEC1 and eTSEC2) -0.3 to 3.63 -0.3 to 2.75 TVDD (for eTSEC3 and eTSEC4) -0.3 to 3.63 -0.3 to 2.75 PCI/PCI-X, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD -0.3 to 3.63 V (3) Local bus I/O voltage BVDD -0.3 to 3.63 -0.3 to 2.75 -0.3 to 1.98 V (3) MVIN -0.3 to (GVDD + 0.3) V (2)(5) DDR/DDR2 DRAM reference MVREF -0.3 to (GVDD/2 + 0.3) V (2)(5) Three-speed Ethernet signals LVIN TVIN -0.3 to (LVDD + 0.3) -0.3 to (TVDD + 0.3) V (4)(5) Local bus signals BVIN -0.3 to (BVDD + 0.3) DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN -0.3 to (OVDD + 0.3) V (5) PCI/PCI-X OVIN -0.3 to (OVDD + 0.3) V (6) TSTG -55 to 150 C Three-speed Ethernet I/O, MII management voltage DDR/DDR2 DRAM signals Input voltage Storage temperature range Notes: Notes V 1. Functional and tested operating conditions are given in Table 3-2 on page 11. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 10 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 2. Caution: MVIN must not exceed GVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during poweron reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during poweron reset and power-down sequences. 4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3-1 on page 12. 6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3V operation, as shown in Figure 7-1 on page 22. 3.3.2 Recommended Operating Conditions Table 3-2 provides the recommended operating conditions for this device. Note that the values in Table 3-2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 3-2. Recommended Operating Conditions Characteristic Symbol Recommended Value Unit Core supply voltage VDD 1.1V 55 mV V PLL supply voltage AVDD 1.1V 55 mV V Core power supply for SerDes transceivers SVDD 1.1V 55 mV V Pad power supply for SerDes transceivers XVDD 1.1V 55 mV V DDR and DDR2 DRAM I/O voltage GVDD 2.5V 125 mV 1.8V 90 mV V LVDD 3.3V 165 mV 2.5V 125 mV TVDD 3.3V 165 mV 2.5V 125 mV PCI/PCI-X, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD 3.3V 165 mV V Local bus I/O voltage BVDD 3.3V 165 mV 2.5V 125 mV V MVIN GND to GVDD V (2) MVREF GND to GVDD/2 V (2) Three-speed Ethernet signals LVIN TVIN GND to LVDD GND to TVDD V (4) Local bus signals BVIN GND to BVDD V PCI, Local bus, DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN GND to OVDD V TC,TJ TC = -55C to TJ = 125C C Three-speed Ethernet I/O voltage DDR and DDR2 DRAM reference Input voltage Notes: (1) (4) V DDR and DDR2 DRAM signals Operating Temperature range Notes (4) (3) (3) 1. This voltage is the input to the filter discussed in Section 22.2.1 "PLL Power Supply Filtering" on page 88 and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. 2. Caution: MVIN must not exceed GVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during poweron reset and power-down sequences. 11 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 3. Caution: OVIN must not exceed OVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during poweron reset and power-down sequences. 4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. Figure 3-1 shows the undershoot and overshoot voltages at the interfaces of the PC8548E. Figure 3-1. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD B/G/L/OVDD + 20% VIH B/G/L/OVDD + 5% B/G/L/OVDD VIL GND GND - 0.3V GND - 0.7V Note: Not to exceed 10% of tCLOCK (1) 1. tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For LBIU, tCLOCK references LCLK. For PCI, tCLOCK references PCIn_CLK or SYSCLK. For SerDes, tCLOCK references SD_REF_CLK. 2. Please note that with the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3). The core voltage must always be provided at nominal 1.1V. (See Table 3-2 on page 11 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3-2 on page 11. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard. 12 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 3.3.3 Output Driver Characteristics Table 3-3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3-3. Output Drive Capability Driver Type Programmable Output Impedance () Supply Voltage Notes 25 25 BVDD = 3.3V BVDD = 2.5V (1) 45 (default) 45 (default) BVDD = 3.3V BVDD = 2.5V Local bus interface utilities signals 25 PCI signals 45 (default) OVDD = 3.3V (2) DDR signal 18 36 (half strength mode) GVDD = 2.5V (3) DDR2 signal 18 36 (half strength mode) GVDD = 1.8V (3) TSEC/10/100 signals 45 L/TVDD = 2.5/3.3V DUART, system control, JTAG 45 OVDD = 3.3V I2C 150 OVDD = 3.3V Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset. 3. The drive strength of the DDR interface in half-strength mode is at TC = 105C and at GVDD (min). 3.4 Power Sequencing The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power-up: 1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD 2. GVDD All supplies must be at their stable values within 50 ms. Notes: 1. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. 2. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required. 13 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 4. Power Characteristics The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices is shown in Table 4-1. Table 4-1. PC8548E Power Dissipation(1) CCB Frequency(1) 400 533 Notes: Core Frequency SLEEP(2) Typical-65(3) Typical105(4) Maximum(5) 800 2.7 4.6 7.5 11 1000 2.7 5.0 7.9 11.6 1200 2.7 5.4 8.3 11.9 1333 6.2 7.9 10.8 12.8 Unit W W 1. CCB Frequency is the SoC platform frequency, which corresponds to the DDR data rate. 2. SLEEP is based on VDD = 1.1 V, TC = 65C. 3. Typical-65 is based on VDD = 1.1 V, TC = 65C, running Dhrystone. 4. Typical-105 is based on VDD = 1.1 V, TC = 105C, running Dhrystone. 5. Maximum is based on VDD = 1.1 V, TC = 125C, running a smoke test. At allowable voltage levels, the estimated power dissipation on the 1.1V AVDD supplies for the PC8548E PLLs is shown in Table 4-2. Because I/O usage varies from design to design, for power dissipation estimates on the G/L/OVDD power rails, refer to the PowerQUICC III I/O power calculator. Table 4-2. PC8548E Estimated I/O Power Dissipation Interface 1.8V (GVDD) 2.5V (B/G/L/TVDD) 266 MHz data 0.31 W 0.59 W 333 MHz data 0.38 W 0.73 W 400 MHz data 0.46 W 533 MHz data 0.60 W Parameters 1.1V (XVDD) 3.3V (B/L/O/TVDD) Comments DDR PCI-Express x8, 2.5 G-baud 0.71 W Serial RapidIO x4, 3.125 G-baud 0.49 W PCI-X 64-bit, 133 MHz 0.25 W 64-bit, 66 MHz 0.14 W 64-bit, 33 MHz 0.08 W 32-bit, 66 MHz 0.07 W 32-bit, 33 MHz 0.04 W PCI Local Bus 32-bit, 133 MHz 0.14 W 0.24 W 32-bit, 66MHz 0.07 W 0.13 W 32-bit, 33 MHz 0.04 W 0.07 W Power per PCI port 14 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 4-2. PC8548E Estimated I/O Power Dissipation (Continued) Interface Parameters eTSEC (10/100/1000 Ethernet) eTSEC (packet FIFO) 1.1V (XVDD) 2.5V (B/G/L/TVDD) 1.8V (GVDD) 3.3V (B/L/O/TVDD) MII 0.01 W GMII 0.07 W TBI 0.07 W RGMII 0.04 W RTBI 0.04 W 16-bit, 200 MHz 0.20 W 16-bit, 155 MHz 0.16 W 8-bit, 200 MHz 0.11 W 8-bit, 155 MHz 0.08 W Comments Power per eTSEC used Power per FIFO interface used 5. Input Clocks 5.1 System Clock Timing Table 5-1 provides the system clock (SYSCLK) AC timing specifications for the PC8548E. Table 5-1. SYSCLK AC Timing Specifications (At Recommended Operating Conditions with OVDD = 3.3V 165 mV (see Table 3-2 on page 11) Parameter/Condition Symbol Min Typical Max Unit Notes SYSCLK frequency fSYSCLK 16 - 133 MHz (1)(6) SYSCLK cycle time tSYSCLK 7.5 - 60 ns (6) SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns (2) tKHK/tSYSCLK 40 - 60 % (3) - - - 150 ps (4)(5) SYSCLK duty cycle SYSCLK jitter Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum operating frequencies. Refer to Section 20.2 "CCB/SYSCLK PLL Ratio" on page 85" and Section 20.3 "e500 Core PLL Ratio" on page 86, for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6V and 2.7V 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter - short term and long term - and is guaranteed by design. 5. The SYSCLK driver's closed loop jitter bandwidth should be < 500 kHz at -20 dB. The bandwidth must cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. 6. This parameter has been adjusted slower according to the workaround for device erratum GEN-13. 5.2 Real Time Clock Timing The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 x tCCB, and minimum clock low time is 2 x tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed. 15 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 5.3 eTSEC Gigabit Reference Clock Timing Table 5-2 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the PC8548E. Table 5-2. EC_GTX_CLK125 AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit EC_GTX_CLK125 frequency fG125 - 125 - MHz EC_GTX_CLK125 cycle time tG125 - 8 - ns - 0.75 1.0 ns (1) % (2)(3) EC_GTX_CLK125 rise and fall time - L/TVDD = 2.5V - L/TVDD = 3.3V tG125R/tG125F EC_GTX_CLK125 duty cycle - GMII, TBI - 1000Base-T for RGMII, RTBI tG125H/tG125 Note: 45 47 - 55 53 Notes 1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD = 2.5V, and from 0.6 and 2.7V for L/TVDD = 3.3V. 2. Timing is guaranteed by design and characterization. 3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the TSECn_ GTX_CLK. See Section 9.2.6 "RGMII and RTBI AC Timing Specifications" on page 33 for duty cycle for 10Base-T and 100Base-T reference clock. 5.4 PCI/PCI-X Reference Clock Timing When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. Table 5-3 provides the PCI/PCI-X reference clock AC timing specifications for the PC8548E. Table 5-3. PCIn_CLK AC Timing Specifications (At Recommended Operating Conditions with OVDD = 3.3V 165 mV (see Table 3-2 on page 11) Parameter/Condition Symbol Min Typical Max Unit PCIn_CLK frequency fPCICLK 16 - 133 MHz PCIn_CLK cycle time tPCICLK 7.5 - 60 ns tPCIKH, tPCIKL 0.6 1.0 2.1 ns (1)(2) tPCIKHKL/tPCICLK 40 - 60 % (2) PCIn_CLK rise and fall time PCIn_CLK duty cycle Notes: Notes 1. Rise and fall times for SYSCLK are measured at 0.6V and 2.7V. 2. Timing is guaranteed by design and characterization. 16 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 5.5 Platform to FIFO restrictions Please note the following FIFO maximum speed restrictions based on platform speed. For FIFO GMII mode: FIFO TX/RX clock frequency <= platform clock frequency / 4.2 For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 127 MHz For FIFO encoded mode: FIFO TX/RX clock frequency <= platform clock frequency / 3.2 For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz. 5.6 Platform Frequency Requirements for PCI-Express and Serial RapidIO The CCB clock frequency must be considered for proper operation of the high-speed PCI-Express and Serial RapidIO interfaces as described below. For proper PCI Express operation, the CCB clock frequency must be greater than: 500 MHz x (PCI-Express link width) 8 For proper serial RapidIO operation, the CCB clock frequency must be greater than: 2 x (0.80) x (Serial RapidIO interface frequency) x (Serial RapidIO link width) 64 5.7 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. 6. RESET Initialization This section describes the AC electrical specifications for the RESET initialization timing requirements of the PC8548E. Table 6-1 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s). Table 6-1. RESET Initialization Timing Specifications Parameter/Condition Min Max Unit Required assertion time of HRESET 100 - s Minimum assertion time for SRESET 3 - SYSCLKs 100 - s Input setup time for POR configs (other than PLL config) with respect to negation of HRESET 4 - SYSCLKs (1) Input hold time for all POR configs (including PLL config) with respect to negation of HRESET 2 - SYSCLKs (1) Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET - 5 SYSCLKs (1) PLL input setup time with stable SYSCLK before HRESET negation Note: Notes (1) 1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the PC8548E. 17 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 6-2 provides the PLL lock times. Table 6-2. PLL Lock Times Parameter/Condition Min Max Unit Core and platform PLL lock times - 100 s Local bus PLL lock time - 50 s PCI/PCI-X bus PLL lock time - 50 s 7. DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the PC8548E. Note that GVDD(typ) = 2.5V for DDR SDRAM, and GVDD(typ) = 1.8V for DDR2 SDRAM. 7.1 DDR SDRAM DC Electrical Characteristics Table 7-1 provides the recommended operating conditions for the DDR2 SDRAM controller of the PC8548E when GVDD(typ) = 1.8V. Table 7-1. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage GVDD 1.71 1.89 V (1) I/O reference voltage MVREF 0.49 x GVDD 0.51 x GVDD V (2) I/O termination voltage VTT MVREF - 0.04 MVREF + 0.04 V (3) Input high voltage VIH MVREF + 0.125 GVDD + 0.3 V Input low voltage VIL -0.3 MVREF - 0.125 V Output leakage current IOZ -50 50 A Output high current (VOUT = 1.420V) IOH -13.4 - mA Output low current (VOUT = 0.280V) IOL 13.4 - mA Notes: (4) 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0V VOUT GVDD. Table 7-2 provides the DDR capacitance when GVDD(typ) = 1.8V. Table 7-2. DDR2 SDRAM Capacitance for GVDD(typ)=1.8V Parameter/Condition Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS, DQS CIO 6 8 pF (1) Delta input/output capacitance: DQ, DQS, DQS CDIO - 0.5 pF (1) Note: 1. This parameter is sampled. GVDD = 1.8V 0.090V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2V. 18 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 7-3 provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5V. Table 7-3. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage GVDD 2.375 2.625 V (1) I/O reference voltage MVREF 0.49 x GVDD 0.51 x GVDD V (2) I/O termination voltage VTT MVREF - 0.04 MVREF + 0.04 V (3) Input high voltage VIH MVREF + 0.15 GVDD + 0.3 V Input low voltage VIL -0.3 MVREF - 0.15 V Output leakage current IOZ -50 50 A Output high current (VOUT = 1.95V) IOH -16.2 - mA Output low current (VOUT = 0.35V) IOL 16.2 - mA Notes: (4) 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0V VOUT GVDD. Table 7-4 provides the DDR capacitance when GVDD (typ) = 2.5V. Table 7-4. DDR SDRAM Capacitance for GVDD (typ) = 2.5V Parameter/Condition Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS CIO 6 8 pF (1) Delta input/output capacitance: DQ, DQS CDIO - 0.5 pF (1) Notes: 1. This parameter is sampled. GVDD = 2.5V 0.125V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2V. Table 7-5 provides the current draw characteristics for MVREF. Table 7-5. Current Draw Characteristics for MVREF Parameter/Condition Symbol Min Max Unit Note Current draw for MVREF IMVREF - 500 A (1) Notes: 1. The voltage regulator for MVREF must be able to supply up to 500 A current. 19 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 7.2 DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to 333 MHz. 7.2.1 DDR SDRAM Input AC Timing Specifications Table 7-6 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8V. Table 7-6. DDR2 SDRAM Input AC Timing Specifications for 1.8V Interface (At Recommended Operating Conditions) Parameter Symbol Min Max Unit AC input low voltage VIL - MVREF - 0.25 V AC input high voltage VIH MVREF + 0.25 V Table 7-7 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5V. Table 7-7. DDR SDRAM Input AC Timing Specifications for 2.5V Interface (At Recommended Operating Conditions) Parameter Symbol Min Max Unit AC input low voltage VIL - MVREF - 0.31 V AC input high voltage VIH MVREF + 0.31 V Table 7-8 provides the input AC timing specifications for the DDR SDRAM interface. Table 7-8. DDR SDRAM Input AC Timing Specifications (At Recommended Operating Conditions) Parameter Symbol Controller Skew for MDQS- MDQ/MECC/MDM tCISKEW Notes: Min Max 533 MHz -300 300 400 MHz -365 365 333 MHz -390 390 Unit Notes ps (1)(2) 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be determined by the following equation: tDISKEW = (T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 20 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 7.2.2 DDR SDRAM Output AC Timing Specifications Table 7-9. DDR SDRAM Output AC Timing Specifications (At Recommended Operating Conditions) Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing Symbol(1) Min Max Unit Notes tMCK 3.75 10 ns (2) 1.48 1.95 2.40 - - - ns (3) 1.48 1.95 2.40 - - - ns (3) 1.48 1.95 2.40 - - - ns (3) 1.48 1.95 2.40 - - - ns (3) ns (4) ps (5) ps (5) ADDR/CMD output setup with respect to MCK 533 MHz 400 MHz 333 MHz tDDKHAS ADDR/CMD output hold with respect to MCK 533 MHz 400 MHz 333 MHz tDDKHAX MCS[n] output setup with respect to MCK 533 MHz 400 MHz 333 MHz tDDKHCS MCS[n] output hold with respect to MCK 533 MHz 400 MHz 333 MHz tDDKHCX MCK to MDQS Skew tDDKHMH -0.6 0.6 MDQ/MECC/MDM output setup with respect to MDQS 533 MHz 400 MHz 333 MHz tDDKHDS, tDDKLDS 538 700 900 - - - MDQ/MECC/MDM output hold with respect to MDQS 533 MHz 400 MHz 333 MHz tDDKHDX, tDDKLDX 538 700 900 - - - MDQS preamble start tDDKHMP -0.5 x tMCK - 0.6 -0.5 x tMCK +0.6 ns (6) MDQS epilogue end tDDKHME -0.6 0.6 ns (6) Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note (1). For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the PC8548E PowerQUICC III Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 21 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note (1). Note: For the ADDR/CMD setup and hold specifications in Table 7-9 on page 21, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. Figure 7-1 on page 22 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 7-1. Timing Diagram for tDDKHMH MCK[n] MCK[n] tMCK tDDKHMH(max) = 0.6 ns MDQS tDDKHMH(min) = -0.6 ns MDQS Figure 7-2 shows the DDR SDRAM output timing diagram. Figure 7-2. DDR SDRAM Output Timing Diagram MCK[n] MCK[n] tMCK tDDKHAS, tDDKHCS tDDKHAX, tDDKHCX ADDR/CMD Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHME tDDKHDS tDDKLDS MDQ[x] D0 tDDKHDX D1 tDDKLDX 22 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 7-3 provides the AC test load for the DDR bus. Figure 7-3. DDR AC Test Load Z0 = 50 Output GVDD /2 RL = 50 8. DUART This section describes the DC and AC electrical specifications for the DUART interface of the PC8548E. 8.1 DUART DC Electrical Characteristics Table 8-1 provides the DC electrical characteristics for the DUART interface. Table 8-1. DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current (VIN(1) = 0V or VIN = VDD) IIN - 5 A High-level output voltage (OVDD = mn, IOH = -100 A) VOH OVDD- 0.2 - V Low-level output voltage (OVDD = min, IOL = 100 A) VOL - 0.2 V Note: 8.2 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 10 and Table 3-2 on page 11. DUART AC Electrical Specifications Table 8-2 provides the AC timing parameters for the DUART interface. Table 8-2. DUART AC Timing specifications Parameter Value Unit Notes Minimum baud rate fCCB/1,048,576 baud (1)(2) Maximum baud rate fCCB clock/16 baud (1)(2)(3) 16 - (1)(4) Oversample rate Notes: 1. Guaranteed by design 2. fCCB refers to the internal platform clock. 3. Actual attainable baud rate will be limited by the latency of interrupt processing 4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 23 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9. Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management. 9.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1Gb Mbps) - GMII/MII/TBI/ RGMII/RTBI/RMII Electrical Characteristics The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI interfaces are defined for 2.5V, while the GMII and TBI interfaces can be operated at 3.3V. The GMII, MII, or TBI interface timing is compliant with the IEEE Std. 802.3. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 10. "Ethernet Management Interface Electrical Characteristics" on page 36. 9.1.1 eTSEC DC Electrical Characteristics All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 9-1 and Table 9-2. The RGMII and RTBI signals are based on a 2.5V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 9-1. GMII, MII, RMII, and TBI DC Electrical Characteristics Parameter Symbol Min Max Unit Notes LVDD TVDD 3.13 3.47 V (1)(2) Output high voltage (LVDD/TVDD = Min, IOH = -4.0 mA) VOH 2.40 LVDD/TVDD + 0.3 V Output low voltage (LVDD/TVDD = Min, IOL = 4.0 mA) VOL GND 0.50 V Input high voltage VIH 2.0 LVDD/TVDD + 0.3 V Input low voltage VIL -0.3 0.90 V Input high current (VIN = LVDD, VIN = TVDD) IIH - 40 A (1)(2)(3) Input low current (VIN = GND) IIL -600 - A (3) Supply voltage 3.3V Notes: 1. LVDD supports eTSECs 1 and 2. 2. TVDD supports eTSECs 3 and 4. 3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 3-1 on page 10 and Table 3-2 on page 11 24 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] . Table 9-2. RGMII, RTBI and FIFO DC Electrical Characteristics Parameter Symbol Min Max Unit Notes LVDD TVDD 2.37 2.63 V (1)(2) Output high voltage (LVDD/TVDD = Min, IOH = -1.0 mA) VOH 2 LVDD/TVDD + 0.3 V Output low voltage (LVDD/TVDD = Min, IOL = 1.0 mA) VOL GND - 0.3 0.40 V Input high voltage VIH 1.70 LVDD/TVDD + 0.3 V Input low voltage VIL -0.3 0.90 V Input high current (VIN = LVDD, VIN = TVDD) IIH - 10 A (1)(2)(3) Input low current (VIN = GND) IIL -15 - A (3) Supply voltage 2.5V Notes: 1. LVDD supports eTSECs 1 and 2. 2. TVDD supports eTSECs 3 and 4. 3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 3-1 on page 10 and Table 3-2 on page 11. 9.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this section. 9.2.1 FIFO AC Specifications The basis for the AC specifications for the eTSEC's FIFO modes is the double data rate RGMII and RTBI specifications, since they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and source clock in GMII fashion. When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn's TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and the platform speed. For more information see Section 5.5 "Platform to FIFO restrictions" on page 17. 25 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] A summary of the FIFO AC specifications appears in Table 3-2 and Table 9-4 on page 26. Table 9-3. FIFO Mode Transmit AC Timing Specification Parameter/Condition Symbol Min Typ Max Unit tFIT 5.0 8.0 100 ns tFITH/tFIT 45 50 55 % TX_CLK, GTX_CLK peak-to-peak jitter tFITJ - - 250 ps Rise time TX_CLK (20%-80%) tFITR - - 0.75 ns Fall time TX_CLK (80%-20%) tFITF - - 0.75 ns FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK tFITDV 2.0 - - ns GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time tFITDX 0.5 () - 3.0 ns Parameter/Condition Symbol Min Typ Max Unit RX_CLK clock period tFIR 5.0 8.0 100 ns tFIRH/tFIR 45 50 55 % RX_CLK peak-to-peak jitter tFIRJ - - 250 ps Rise time RX_CLK (20%-80%) tFIRR - - 0.75 ns Fall time RX_CLK (80%-20%) tFIRF - - 0.75 ns RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tFIRDV 1.5 - - ns RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tFIRDX 0.5 - - ns TX_CLK, GTX_CLK clock period TX_CLK, GTX_CLK duty cycle Table 9-4. FIFO Mode Receive AC Timing Specification RX_CLK duty cycle Timing diagrams for FIFO appear in Figure 9-1 and Figure 9-2 on page 27. Figure 9-1. FIFO Transmit AC Timing Diagram tFITF tFITR tFIT GTX_CLK tFITH tFITDV tFITDX TXD[7:0] TX_EN TX_ER 26 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 9-2. FIFO Receive AC Timing Diagram tFIRR tFIR RX_CLK tFIRH tFIRF RXD[7:0] RX_DV RX_ER valid data tFIRDV 9.2.2 tFIRDX GMII AC Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 9.2.2.1 GMII Transmit AC Timing Specifications Table 9-5 provides the GMII transmit AC timing specifications. Table 9-5. GMII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Symbol(1) Min Typ Max Unit GMII data TXD[7:0], TX_ER, TX_EN setup time tGTKHDV 2.5 - - ns GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay tGTKHDX 0.5 - 5.0 ns GTX_CLK data clock rise time (20%-80%) tGTXR(2) - - 1.0 ns GTX_CLK data clock fall time (80%-20%) tGTXF(2) - - 1.0 ns Parameter/Condition Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. Figure 9-3 shows the GMII transmit AC timing diagram. Figure 9-3. GMII Transmit AC Timing Diagram tGTX tGTXR GTX_CLK tGTXH tGTXF TXD[7:0] TX_EN TX_ER tGTKHDX tGTKHDV 27 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9.2.2.2 GMII Receive AC Timing Specifications Table 9-6 provides the GMII receive AC timing specifications.. Table 9-6. GMII Receive AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Parameter/Condition Symbol(1) Min Typ Max Unit RX_CLK clock period tGRX - 8.0 - ns tGRXH/tGRX 40 - 60 ns RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tGRDVKH 2.0 - - ns RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0 - - ns RX_CLK clock rise (20%-80%) tGRXR(2) - - 1.0 ns RX_CLK clock fall time (80%-20%) tGRXF(2) 1.0 ns RX_CLK duty cycle Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. Figure 9-4 provides the AC test load for eTSEC. Figure 9-4. eTSEC AC Test Load Z0 = 50 Output LVDD/2 RL = 50 Figure 9-5 shows the GMII receive AC timing diagram. Figure 9-5. GMII Receive AC Timing Diagram tGRX tGRXR RX_CLK tGRXH tGRXF RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKV 28 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 9.2.3.1 MII Receive AC Timing Specifications Table 9-7 provides the MII transmit AC timing specifications. Table 9-7. MII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Symbol(1) Min Typ Max Unit TX_CLK clock period 10 Mbps tMTX(2) - 400 - ns TX_CLK clock period 100 Mbps tMTX - 40 - ns tMTXH/tMTX 35 - 65 % TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1.0 5 15 ns TX_CLK data clock rise (20%-80%) tMTXR(2) 1.0 - 4 ns (2) 1.0 - 4 ns Parameter/Condition TX_CLK duty cycle TX_CLK data clock fall (80%-20%) Notes: tMTXF 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. Figure 9-6 shows the MII transmit AC timing diagram. Figure 9-6. MII Transmit AC Timing Diagram tMTX tMTXR TX_CLK tMTXH tMTXF TXD[3:0] TX_EN TX_ER tMTKHDX 29 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9.2.3.2 MII Receive AC Timing Specifications Table 9-8 provides the MII receive AC timing specifications. Table 9-8. MII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Symbol(1) Min Typ Max Unit RX_CLK clock period 10 Mbps tMRX(2) - 400 - ns RX_CLK clock period 100 Mbps tMRX - 40 - ns tMRXH/tMRX 35 - 65 % RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10 - - ns RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10 - - ns RX_CLK clock rise (20%-80%) tMRXR (2) 1.0 - 4 ns RX_CLK clock fall time (80%-20%) tMRXF(2) 1.0 - 4 ns Parameter/Condition RX_CLK duty cycle Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with 2. Guaranteed by design. Figure 9-7 provides the AC test load for eTSEC. Figure 9-7. eTSEC AC Test Load Z0 = 50 Output LVDD/2 RL = 50 Figure 9-8 shows the MII receive AC timing diagram. Figure 9-8. MII Receive AC Timing Diagram tMRX tMRXR RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRXF Valid Data tMRDVKH tMRDXKL 30 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 9.2.4.1 TBI Transmit AC Timing Specifications Table 9-9 provides the TBI transmit AC timing specifications. Table 9-9. TBI Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Symbol(1) Min Typ Max Unit TCG[9:0] setup time GTX_CLK going high tTTKHDV 2.0 - - ns TCG[9:0] hold time from GTX_CLK going high tTTKHDX Parameter/Condition 1.0 - - ns GTX_CLK rise (20%-80%) tTTXR (2) - - 1.0 ns GTX_CLK fall time (80%-20%) tTTXF(2) - - 1.0 ns Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. Figure 9-9 shows the TBI transmit AC timing diagram. Figure 9-9. TBI Transmit AC Timing Diagram tTTX tTTXR GTX_CLK tTTXH tTTXF tTTXF TCG[9:0] tTTXR tTTKHDV tTTKHDX 31 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9.2.4.2 TBI Receive AC Timing Specifications Table 9-10 provides the TBI receive AC timing specifications. Table 9-10. TBI Receive AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Symbol(1) Min Typ Max Unit tTRX - 16.0 - ns tSKTRX 7.5 - 8.5 ns tTRXH/tTRX 40 - 60 % RCG[9:0] setup time to rising PMA_RX_CLK tTRDVKH 2.5 - - ns RCG[9:0] hold time to rising PMA_RX_CLK tTRDXKH 1.5 - - ns PMA_RX_CLK[0:1] clock rise time (20%-80%) tTRXR (2) 0.7 - 2.4 ns PMA_RX_CLK[0:1] clock fall time (80%-20%) tTRXF(2) 0.7 - 2.4 ns Parameter/Condition PMA_RX_CLK[0:1] clock period PMA_RX_CLK[0:1] skew PMA_RX_CLK[0:1] duty cycle Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. Figure 9-10 shows the TBI receive AC timing diagram. Figure 9-10. TBI Receive AC Timing Diagram tTRXR tTRX PMA_RX_CLK1 tTRXF tTRXH Valid Data RCG[9:0] Valid Data tTRDVKH tSKTRX tTRDXKH PMA_RX_CLK0 tTRXH tTRDXKH tTRDVKH 9.2.5 TBI Single-Clock Mode AC Specifications When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface. In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the in all TBI modes. 32 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] A summary of the single-clock TBI mode AC specifications for receive appears in Table 9-11. Table 9-11. TBI single-clock Mode Receive AC Timing Specification Parameter/Condition Symbol Min Typ Max Unit RX_CLK clock period tTRRX 7.5 8.0 8.5 ns tTRRH/TRRX 40 50 60 % RX_CLK peak-to-peak jitter tTRRJ - - 250 ps Rise time RX_CLK (20%-80%) tTRRR - - 1.0 ns Fall time RX_CLK (80%-20%) tTRRF - - 1.0 ns RCG[9:0] setup time to RX_CLK rising edge tTRRDVKH 2.0 - - ns RCG[9:0] hold time to RX_CLK rising edge tTRRDXKH 1.0 - - ns RX_CLK duty cycle A timing diagram for TBI receive appears in Figure 9-11 on page 33. Figure 9-11. TBI Single-Clock Mode Receive AC Timing Diagram tTRRR tTRRX RX_CLK tTRRH tTRRF RCG[9:0] valid data tTRRDVKH tTRRDXKH 9.2.6 RGMII and RTBI AC Timing Specifications Table 9-12 presents the RGMII and RTBI AC timing specifications. Table 9-12. RGMII and RTBI AC Timing Specifications (At Recommended Operating Conditions with LVDD of 2.5V 5%) Symbol(1) Min Typ Max Unit tSKRGT(5) -500(6) 0 500(6) ps tSKRGT 1.0 - 2.8 ns tRGT(5) 7.2 8 8.8 ns tRGTH/tRGT(5) 40 50 60 % Rise time (20%-80%) tRGTR(5) - - 0.75 ns Fall time (20%-80%) tRGTF(5) - - 0.75 ns Parameter/Condition Data to clock output skew (at transmitter) (2) Data to clock input skew (at receiver) Clock period (3) Duty cycle for 10BASE-T and 100BASE-TX(3)(4) Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 33 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t RGT of the lowest speed transitioned between. 5. Guaranteed by characterization. 6. In rev 1.0 silicon, due to errata, tSKRGT is -650 ps (Min) and 650 ps (Max). Please refer to "eTSEC 10" in the device errata document. Figure 9-12 on page 34 shows the RGMII and RTBI AC timing and multiplexing diagrams. Figure 9-12. RGMII and RTBI AC Timing and Multiplexing Diagrams tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RX_CTL RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CLK (At PHY) 9.2.7 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 9.2.7.1 RMII Transmit AC Timing Specifications The RMII transmit AC timing specifications are in Table 9-13. Table 9-13. RMII Transmit AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Parameter/Condition Symbol(1) Min Typ Max Unit REF_CLK clock period tRMT 15.0 20.0 25.0 ns REF_CLK duty cycle tRMTH 35 50 65 % REF_CLK peak-to-peak jitter tRMTJ - - 250 ps Rise time REF_CLK (20%-80%) tRMTR 1.0 - 2.0 ns Fall time REF_CLK (80%-20%) tRMTF 1.0 - 2.0 ns REF_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX 1.0 - 10 ns 34 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 9-13 shows the RMII transmit AC timing diagram. Figure 9-13. RMII Transmit AC Timing Diagram tRMT tRMTR REF_CLK tRMTF tRMTH TXD[1:0] TX_EN TX_ER tRMTDX 9.2.7.2 RMII Receive AC Timing Specifications Table 9-14. RMII Receive AC Timing Specifications (At Recommended Operating Conditions with LVDD of 3.3V 5%) Parameter/Condition Symbol(1) Min Typ Max Unit REF_CLK clock period tRMR 15.0 20.0 25.0 ns REF_CLK duty cycle tRMRH 35 50 65 % REF_CLK peak-to-peak jitter tRMRJ - - 250 ps Rise time REF_CLK (20%-80%) tRMRR 1.0 - 2.0 ns Fall time REF_CLK (80%-20%) tRMRF 1.0 - 2.0 ns RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge tRMRDV 4.0 - - ns RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge tRMRDX 2.0 - - ns Note: 1. The symbols used for timing specificationsherein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 9-14 provides the AC test load for eTSEC. Figure 9-14. eTSEC AC Test Load Output Z0 = 50 LVDD/2 RL = 50 35 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 9-15 shows the RMII receive AC timing diagram. Figure 9-15. RMII Receive AC Timing Diagram tRMRR tRMR REF_CLK tRMRF tRMRH RXD[1:0] CRS_DV RX_ER Valid Data tRMRDV tRMRDX 10. Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI and RTBI are specified in Section 9. "Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management" on page 24. 10.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3.3V. The DC electrical characteristics for MDIO and MDC are provided in Table 10-1. Table 10-1. MII Management DC Electrical Characteristics Parameter Symbol Min Max Unit OVDD 3.13 3.47 V Output high voltage (OVDD = Min, IOH = -1 mA) VOH 2.10 OVDD + 0.3 V Output low voltage (OVDD = Min, IOL = 1 mA) VOL GND 0.50 V Input high voltage VIH 2.0 - V Input low voltage VIL - 0.90 V Input high current (OVDD = Max, VIN(1) = 2.1V) IIH - 40 A Input low current (OVDD = Max, VIN = 0.5V) IIL -600 - A Supply voltage (3.3V) Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 10 and Table 3-2 on page 11. 36 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 10.2 MII Management AC Electrical Specifications Table 10-2 provides the MII management AC timing specifications. Table 10-2. MII Management AC Timing Specifications (At Recommended Operating Conditions with OVDD is 3.3V 5%) Symbol(1) Min Max Unit Notes MDC frequency fMDC 5.2 8.3 MHz (2)(4) MDC period tMDC 120 192 ns MDC clock pulse width high tMDCH 32 - ns MDC to MDIO valid tMDKHDV 16*tCCB MDC to MDIO delay tMDKHDX 10 MDIO to MDC setup time tMDDVKH MDIO to MDC hold time Parameter/Condition ns (5) 16*tCCB ns (3)(5) 5 - ns tMDDXKH 0 - ns MDC rise time tMDCR - 10 ns (4) MDC fall time tMDHF - 10 ns (4) Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency divided by 64.) 3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.) 4. Guaranteed by design. 5. tplb_clk is the platform (CCB) clock. Figure 10-1 shows the MII management AC timing diagram. Figure 10-1. MII Management Interface Timing Diagram tMDCR tMDC MDC tMDCF tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX 37 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 11. Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the PC8548. 11.1 Local Bus DC Electrical Characteristics Table 11-1 provides the DC electrical characteristics for the local bus interface operating at BVDD = 3.3V DC Table 11-1. Local Bus DC Electrical Characteristics (3.3V DC) Parameter Symbol Min Max Unit High-level input voltage VIH 2 BVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current (VIN(1) = 0V or VIN = BVDD) IIN - 5 A High-level output voltage (BVDD = min, IOH = -2 mA) VOH BVDD - 0.2 - V Low-level output voltage (BVDD = min, IOL = 2 mA) VOL - 0.2 V Note: 1. Note that the symbol VIN, in this case, represents the BVIN symbol referenced in Table 3-1 on page 10 and Table 3-2 on page 11. Table 11-2 provides the DC electrical characteristics for the local bus interface operating at BVDD = 2.5V DC. Table 11-2. Local Bus DC Electrical Characteristics (2.5V DC) Parameter Symbol Min Max Unit High-level input voltage VIH 1.70 BVDD+ 0.3 V Low-level input voltage VIL -0.3 0.7 V IIH - 10 A Input current (VIN(1) = 0V or VIN = BVDD) IIL -15 High-level output voltage (BVDD = min, IOH = -1 mA) VOH 2.0 BVDD+ 0.3 V Low-level output voltage (BVDD = min, IOL = 1 mA) VOL GND - 0.3 0.4 V Note: 1. Note that the symbol VIN, in this case, represents the BVIN symbol referenced in Table 3-1 on page 10 and Table 3-2 on page 11. 38 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 11.2 Local Bus AC Electrical Specifications Table 11-3 describes the general timing parameters of the local bus interface at BVDD = 3.3V DC. For information about the frequency range of local bus see Section 20.1 "Clock Ranges" on page 84. Table 11-3. Local Bus General Timing Parameters (BVDD = 3.3V DC) - PLL Enabled Symbol(1) Min Max Unit Notes Local bus cycle time tLBK 7.5 12 ns (2) Local bus duty cycle tLBKH/tLBK 43 57 % LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW 150 ps (7)(8) Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 1.8 - ns (3)(4) LGTA/LUPWAIT input setup to local bus clock tLBIVKH2 1.7 - ns (3)(4) Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.0 - ns (3)(4) LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1.0 - ns (3)(4) LALE output transition to LAD/LDP output transition (LATCH setup and hold time) tLBOTOT 1.5 - ns (6) Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 - 2.0 ns Local bus clock to data valid for LAD/LDP tLBKHOV2 - 2.2 ns (3) Local bus clock to address valid for LAD tLBKHOV3 - 2.3 ns (3) Local bus clock to LALE assertion tLBKHOV4 2.3 ns (3) Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.7 - ns (3) Output hold from local bus clock for LAD/LDP tLBKHOX2 0.7 - ns (3) Local bus clock to output high Impedance (except LAD/LDP and LALE) tLBKHOZ1 - 2.5 ns (5) Local bus clock to output high impedance for LAD/LDP tLBKHOZ2 - 2.5 ns (5) Parameter Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 BVDD of the signal in question for 3.3V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 8. Guaranteed by design. 39 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 11-4 describes the general timing parameters of the local bus interface at BVDD = 2.5V DC. Table 11-4. Local Bus Timing Parameters (BVDD = 2.5V): PLL Enabled Symbol(1) Min Max Unit Notes Local bus cycle time tLBK 7.5 12 ns (2) Local bus duty cycle tLBKH/tLBK 43 57 % LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW - 150 ps (7)(8) Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 1.9 - ns (3)(4) LGTA/LUPWAIT input setup to local bus clock tLBIVKH2 1.8 - ns (3)(4) Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.1 - ns (3)(4) LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1.1 - ns (3)(4) LALE output transition to LAD/LDP output transition (LATCH hold time) tLBOTOT 1.5 - ns (6) Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 - 2.1 ns Local bus clock to data valid for LAD/LDP tLBKHOV2 - 2.3 ns (3) Local bus clock to address valid for LAD tLBKHOV3 - 2.4 ns (3) Local bus clock to LALE assertion tLBKHOV4 - 2.4 ns (3) Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.8 - ns (3) Output hold from local bus clock for LAD/LDP tLBKHOX2 0.8 - ns (3) Local bus clock to output high Impedance (except LAD/LDP and LALE) - 2.6 ns (5) tLBKHOZ1 Local bus clock to output high impedance for LAD/LDP tLBKHOZ2 - 2.6 ns (5) Parameter Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 BVDD of the signal in question for 3.3V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. Figure 9-1 on page 26 provides the AC test load for the local bus. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 8. Guaranteed by design. 40 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 11-1 provides the AC test load for the local bus. Figure 11-1. Local Bus AC Test Load Output Z0 = 50 BVDD/2 RL = 50 Note: PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz. When LBIU operates above 83 Mhz, LBIU PLL is recommended to be enabled. Figure 11-2 to Figure 11-7 on page 47 show the local bus signals. Figure 11-2. Local Bus Signals, (PLL Enabled) LSYNC_IN tLBIXKH1 tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH2 tLBIVKH2 Input Signal: LGTA LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] tLBKHOV1 tLBKHOZ1 tLBKHOX1 tLBKHOV2 tLBKHOZ2 tLBKHOX2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV3 tLBKHOZ2 tLBKHOX2 Output (Address) Signal: LAD[0:31] tLBOTOT tLBKHOV4 LALE 41 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 11-5 describes the timing parameters of the local bus interface at BVDD = 3.3V with PLL disabled. Table 11-5. Local Bus Timing Parameters: PLL Bypassed Symbol(1) Min Max Unit Notes Local bus cycle time tLBK 12 - ns (2) Local bus duty cycle tLBKH/tLBK 43 57 % Internal launch/capture clock to LCLK delay tLBKHKT 2.3 4.4 ns (8) Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 6.2 - ns (4)(5) LGTA/LUPWAIT input setup to local bus clock tLBIVKL2 6.1 - ns (4)(5) Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 -1.8 - ns (4)(5) LGTA/LUPWAIT input hold from local bus clock tLBIXKL2 -1.3 - ns (4)(5) LALE output transition to LAD/LDP output transition (LATCH hold time) tLBOTOT 1.5 - ns (6) Local bus clock to output valid (except LAD/LDP and LALE) tLBKLOV1 - -0.3 ns Local bus clock to data valid for LAD/LDP tLBKLOV2 - -0.1 ns (4) Local bus clock to address valid for LAD tLBKLOV3 - 0 ns (4) Output hold from local bus clock (except LAD/LDP and LALE) tLBKLOX1 -3.7 - ns (4) Output hold from local bus clock for LAD/LDP tLBKLOX2 -3.7 - ns (4) Local bus clock to output high Impedance (except LAD/LDP and LALE) tLBKLOZ1 - 0.2 ns (7) Local bus clock to output high impedance for LAD/LDP tLBKLOZ2 - 0.2 ns (7) Parameter Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which preceeds LCLK by tLBKHKT. 3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3V signaling levels. 5. Input timings are measured at the pin. 6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD. 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Guaranteed by characterization. 9. Guaranteed by design. 42 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 11-3. Local Bus Signals (PLL Bypass Mode) Internal launch/capture clock tLBKHKT LCLK[n] tLBIVKH1 tLBIXKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKL2 Input Signal: LGTA tLBIXKL2 LUPWAIT tLBKLOV1 tLBKLOX1 Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] tLBKLOZ1 tLBKLOZ2 tLBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 tLBKLOX2 Output (Address) Signal: LAD[0:31] tLBKLOV4 tLBOTOT LALE Note: In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of tLBKHKT. In this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock withe the exception of LGTA/LUPWAIT (which is captured on on the rising edge of the internal clock). 43 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 11-4. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled) LSYNC_IN T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKHOV1 tLBKHOZ1 GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 tLBKHOV1 tLBKHOZ1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] 44 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 11-5. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode) Internal launch/capture clock T1 T3 LCLK tLBKLOX1 tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] 45 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 11-6. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabled) LSYNC_IN T1 T2 T3 T4 tLBKHOV1 tLBKHOZ1 GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 tLBKHOV1 tLBKHOZ1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] 46 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 11-7. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode) Internal launch/capture clock T1 T2 T3 T4 LCLK tLBKLOX1 tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] 12. Programmable Interrupt Controller In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at lest 3 system clocks (SYSCLK periods). 47 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 13. JTAG This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the PC8548E. 13.1 JTAG DC Electrical Characteristics Table 13-1 provides the DC electrical characteristics for the JTAG interface. Table 13-1. JTAG DC Electrical Characteristics Symbol(2) Min Max Unit High-level input voltage VIH 2.0 OVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current (VIN(1) = 0 V or VIN = VDD) IIN - 5 A High-level output voltage (OVDD = min, IOH = -2 mA) VOH 2.4 - V Low-level output voltage (OVDD = min, IOL = 2 mA) VOL - 0.4 V Parameter Note: 13.2 1. Note that the symbol VIN, in this case, represents the OVIN. JTAG AC Electrical Specifications Table 13-2 provides the JTAG AC timing specifications as defined in Figure 13-2 through Figure 13-4 on page 50. Table 13-2. JTAG AC Timing Specifications (Independent of SYSCLK)(1) Symbol(2) Min Max Unit JTAG external clock frequency of operation fJTG 0 33.3 MHz JTAG external clock cycle time tJTG 30 - ns tJTKHKL 15 - ns tJTGR & tJTGF 0 2.0 ns (6) tTRST 25 - ns (3) Input setup times: - Boundary-scan data - TMS, TDI tJTDVKH tJTIVKH 4 0 - - ns (4) Input hold times: - Boundary-scan data - TMS, TDI tJTDXKH tJTIXKH 20 25 - - ns (4) Parameter JTAG external clock pulse width measured at 1.4V JTAG external clock rise and fall times TRST assert time Notes 48 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 13-2. JTAG AC Timing Specifications (Independent of SYSCLK)(1) (Continued) Parameter Valid times: - Boundary-scan data - TDO Symbol(2) Min Max Unit Notes tJTKLDV tJTKLOV 4 4 20 25 ns (5) ns (5) ns (5)(6) Output hold times: - Boundary-scan data - TDO tJTKLDX tJTKLOX JTAG external clock to output high impedance: - Boundary-scan data - TDO tJTKLDZ tJTKLOZ Notes: 30 30 3 3 19 9 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 13-1 on page 49). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design. Figure 13-1 provides the AC test load for TDO and the boundary-scan outputs. Figure 13-1. AC Test Load for the JTAG Interface Z0 = 50 Output OVDD/2 RL = 50 Figure 13-2 provides the JTAG clock input timing diagram. Figure 13-2. JTAG Clock Input Timing Diagram JTAG External Clock VM VM tJTKHKL tJTGR tJTG Note: VM tJTGF VM = Midpoint Voltage (OVDD/2). 49 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 13-3 provides the TRST timing diagram. Figure 13-3. TRST Timing Diagram VM TRST Note: VM tTRST VM = Midpoint Voltage (OVDD/2). Figure 13-4 provides the boundary-scan timing diagram. Figure 13-4. Boundary-scan Timing Diagram JTAG External Clock VM VM tJTDVKH tJTDXKH Boundary Data Inputs Input Data Valid tJTKLDV tJTKLDX Boundary Data Outputs Output Data Valid tJTKLDZ Boundary Data Outputs Note: Output Data Valid VM = Midpoint Voltage (OVDD/2). 14. I2C This section describes the DC and AC electrical characteristics for the I2C interface of the PC8548E. 14.1 I2C DC Electrical Characteristics Table 14-1 provides the DC electrical characteristics for the I2C interface. Table 14-1. I2C DC Electrical Characteristics (At Recommended Operating Conditions with OVDD of 3.3V 5%) Parameter Symbol Min Max Unit Input high voltage level VIH 0.7 x OVDD OVDD + 0.3 V Input low voltage level VIL -0.3 0.3 x OVDD V Low level output voltage VOL 0 0.2 x OVDD V (1) Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns (2) Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD (max) II -10 10 A (3) Capacitance for each I/O pin CI - 10 pF Notes: Notes 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the PC8548E PowerQUICC III Integrated Host Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off. 50 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 14.2 I2C AC Electrical Specifications Table 14-2 provides the AC timing parameters for the I2C interfaces. Table 14-2. I2C AC Electrical Specifications (All Values Refer to VIH (min) and VIL (max) Levels (see Table 14-1) Parameter SCL clock frequency Low period of the SCL clock Symbol(1) Min Max Unit fI2C 0 400 kHz tI2CL(5) 1.3 - s (5) 0.6 - s Setup time for a repeated START condition tI2SVKH (5) 0.6 - s Hold time (repeated) START condition (after this period, the first clock pulse is generated) tI2SXKL(5) 0.6 - s Data setup time tI2DVKH(5) 100 - ns Data hold time: - CBUS(4) compatible masters - I2C bus devices tI2DXKL - 0(2) - 0.9(3) s Set-up time for STOP condition tI2PVKH 0.6 - s Bus free time between a STOP and START condition tI2KHDX 1.3 s Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 x OVDD V Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 x OVDD V High period of the SCL clock Notes: tI2CH 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. PC8548E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. As a transmitter, the PC8548E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When PC8548Eacts as the I2C bus master while transmitting, PC8548E drives both SCL and SDA. As long as the load on SCL and SDA are balanced, PC8548E would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for PC8548E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16): I2C Source Clock Frequency FDR Bit Setting Actual FDR Divider Selected 2 Actual I C SCL Frequency Generated 333 MHz 266 MHz 200 MHz 133 MHz 0x2A 0x05 0x26 0x00 896 704 512 384 371 KHz 378 KHz 390 KHz 346 KHz 51 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] For the detail of I2C frequency calculation, refer to the application note AN2919 "Determining the I2C Frequency Divider Ratio for SCL". Note that the I2C Source Clock Frequency is half of the CCB clock frequency for MPC8548E. 3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. 5. Guaranteed by design. Figure 14-1 provides the AC test load for the I2C. Figure 14-1. I2C AC Test Load Z0 = 50 Output OVDD/2 RL = 50 Figure 14-2 shows the AC timing diagram for the I2C bus. Figure 14-2. I2C Bus AC Timing Diagram SDA tI2CF tI2CF tI2KHKL tI2DVKH tI2SXKL tI2CL tI2CR SCL tI2SXKL S tI2CH tI2DXKL, tI2OVKL tI2PVKH tI2SVKH Sr P S 15. PCI/PCI-X Table 15-1 on page 52 describes the DC and AC electrical specifications for the PCI/PCI-X bus of the PC8548E. Note that the maximum PCI-X frequency in synchronous mode is 110 MHz. 15.1 PCI/PCI-X DC Electrical Characteristics Table 15-1 provides the DC electrical characteristics for the PCI/PCI-X interface. Table 15-1. PCI/PCI-X DC Electrical Characteristics(1) Parameter Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current (VIN(2) = 0V or VIN = VDD) IIN - 5 A High-level output voltage (OVDD = min, IOH = -100 A) VOH OVDD - 0.2 - V Low-level output voltage (OVDD = min, IOL = 100 A) VOL - 0.2 V Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications. 2. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 10 and Table 3-2 on page 11. 52 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 15.2 PCI/PCI-X AC Electrical Specifications This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock reference CLK is represented by SYSCLK when the PCI controller is configured for asynchronous mode and by PCIn_CLK when it is configured for asynchronous mode. Table 15-2 provides the PCI AC timing specifications at 66 MHz. Table 15-2. PCI AC Timing Specifications at 66 MHz Symbol(1) Min Max Unit Notes SYSCLK to output valid tPCKHOV - 6 ns (2)(3) Output hold from SYSCLK tPCKHOX 2 - ns (2)(10) SYSCLK to output high impedance tPCKHOZ - 14 ns (2)(4)(11) Input setup to SYSCLK tPCIVKH 3 - ns (2)(5)(10) Input hold from SYSCLK tPCIXKH 0 - ns (2)(5)(10) REQ64 to HRESET(9) setup time tPCRVRH 10 x tSYS - clocks (6)(7)(11) HRESET to REQ64 hold time tPCRHRX 0 50 ns (7)(11) HRESET high to first FRAME assertion tPCRHFV 10 - clocks (8)(11) Parameter Notes: 1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI/PCI-X timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 OVDD of the signal in question for 3.3V PCI signaling levels. 4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Input timings are measured at the pin. 6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values see Section 20. "Clocking" on page 84. 7. The setup and hold time is with respect to the rising edge of HRESET. 8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus Specifications. 9. The reset assertion timing requirement for HRESET is 100 s. 10. Guaranteed by characterization. 11. Guaranteed by design. Figure 15-1 provides the AC test load for PCI and PCI-X. Figure 15-1. PCI/PCI-X AC Test Load Output Z0 = 50 OVDD/2 RL = 50 53 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 15-2 shows the PCI/PCI-X input AC timing conditions. Figure 15-2. PCI/PCI-X Input AC Timing Measurement Conditions CLK tPCIVKH tPCIXKH Input Figure 15-3 shows the PCI/PCI-X output AC timing conditions. Figure 15-3. PCI/PCI-X Output AC Timing Measurement Condition CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output Table 15-3 provides the PCI-X AC timing specifications at 66 MHz. Table 15-3. PCI-X AC Timing Specifications at 66 MHz Parameter Symbol Min Max Unit Notes SYSCLK to signal valid delay tPCKHOV - 3.8 ns (1)(2)(3)(7)(8) Output hold from SYSCLK tPCKHOX 0.7 - ns (1)(10) SYSCLK to output high impedance tPCKHOZ - 7 ns (1)(4)(8)(11) Input setup time to SYSCLK tPCIVKH 1.7 - ns (3)(5) Input hold time from SYSCLK tPCIXKH 0.5 - ns (10) REQ64 to HRESETsetup time tPCRVRH 10 - clocks (11) HRESET to REQ64 hold time tPCRHRX 0 50 ns (11) HRESET high to first FRAME assertion tPCRHFV 10 - clocks (9)(11) PCI-X initialization pattern to HRESET setup time tPCIVRH 10 - clocks (11) HRESET to PCI-X initialization pattern hold time tPCRHIX 0 50 ns (6)(11) Notes: 1. See the timing measurement conditions in the PCI-X 1.0a Specification. 2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and load circuit. 3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused. 54 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is asserted. 7. A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency. 8. Device must meet this specification independent of how many outputs switch simultaneously. 9. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification. 10. Guaranteed by characterization. 11. Guaranteed by design. Table 15-4 provides the PCI-X AC timing specifications at 133 MHz. Note that the maximum PCI-X frequency in synchronous mode is 110 MHz. Table 15-4. PCI-X AC Timing Specifications at 133 MHz Parameter Symbol Min Max Unit Notes SYSCLK to signal valid delay tPCKHOV - 3.8 ns (1)(2)(3)(7)(8) Output hold from SYSCLK tPCKHOX 0.7 - ns (1)(11) SYSCLK to output high impedance tPCKHOZ - 7 ns (1)(4)(8)(12) Input setup time to SYSCLK tPCIVKH 1.2 - ns (3)(5)(9)(11) Input hold time from SYSCLK tPCIXKH 0.5 - ns (11) REQ64 to HRESET setup time tPCRVRH 10 - clocks (12) HRESET to REQ64 hold time tPCRHRX 0 50 ns (12) HRESET high to first FRAME assertion tPCRHFV 10 - clocks (10)(12) PCI-X initialization pattern to HRESET setup time tPCIVRH 10 - clocks (12) HRESET to PCI-X initialization pattern hold time tPCRHIX 0 50 ns (6)(12) Notes: 1. See the timing measurement conditions in the PCI-X 1.0a Specification. 2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and load circuit. 3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused. 4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is asserted. 7. A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency. 8. Device must meet this specification independent of how many outputs switch simultaneously. 9. The timing parameter tPCIVKH is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the PCI-X 1.0a Specification. 10. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification. 11. Guaranteed by characterization. 55 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 12. Guaranteed by design. 16. High-Speed Interfaces This section describes the common DC electrical specifications for the high-speed interconnect interfaces (Serial RapidIO and PCI Express) of the PC8548E. 16.1 DC Requirements for SerDes Reference Clocks The SerDes reference clocks are SD_REF_CLK and SD_REF_CLK. * Recommended minimum operating voltage is -0.4V; recommended maximum operating voltage is 1.32V; Maximum absolute voltage is 1.72V. * Each differential clock input has an internal 50 termination to GND. The reference clock must be able to drive this termination. The input is AC-coupled on chip following the termination. * The amplitude of the clock must be at least a 400 mV differential peak-peak for single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. * The differential reference clock (SD_REF_CLK/SD_REF_CLK) input is HCSL compatible DC coupled or LVDS compatible with AC coupling. Figure 16-1. Driver and Receiver of SerDes (PCI Express, Serial RapidIO, and SD_REF_CLK/SD_REF_CLK 50 50 SD_REF_CLK/ SD_RXn SD_TXn Output Driver SD_TXn 50 Input Amp SD_REF_CLK/ SD_RXn 50 16.2 Spread Spectrum Clock SD_REF_CLK/SD_REF_CLK_B was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended modulation. 17. PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the PC8548E. 17.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 16.1 "DC Requirements for SerDes Reference Clocks" on page 56. 56 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 17.2 AC Requirements for PCI Express SerDes Clocks Table 17-1 lists AC requirements. Table 17-1. SD_REF_CLK and SD_REF_CLK AC Requirements Symbol Min Typical Max Units Notes REFCLK cycle time - 10 - ns (1) tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles - - 100 ps - tREFPJ Phase jitter. Deviation edge location in edge location with respect to mean -50 - 50 ps - tREF Parameter Description Note: 1. Typical based on PCI Express Specification 2.0. 17.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all times. This is specified to allow bit rate clock sources with a 300 ppm tolerance. 17.4 Physical Layer Specifications The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the Transport and Data Link layer please use the PCI EXPRESS Base Specification. REV. 1.0a document. 17.4.1 Differential Transmitter (TX) Output Table 17-2 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 17-2. Differential Transmitter (TX) Output Specifications Symbol Parameter Min Nom Max Units UI Unit Interval 399.88 400 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note (1). VTX-DIFFp-p Differential Peak-toPeak Output Voltage 0.8 1.2 V VTX-DIFFp-p = 2*|VTX-D+- VTX-D-| See Note (2). VTX-DE-RATIO De- Emphasized Differential Output Voltage (Ratio) -3.0 -4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note (2). TTX-EYE Minimum TX Eye Width 0.70 UI The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE = 0.3 UI. See Notes (2) and (3). UI Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes (2) and (3). TTX-EYE-MEDIANto-MAX-JITTER Maximum time between the jitter median and maximum deviation from the median. -3.5 0.15 Comments 57 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 17-2. Differential Transmitter (TX) Output Specifications (Continued) Symbol Parameter TTX-RISE, TTX- D+/D- TX Output Rise/Fall Time FALL VTX-CM-ACp VTX-CM-DCACTIVE-IDLEDELTA Min Nom 0.125 RMS AC Peak Common Mode Output Voltage Absolute Delta of DC Common Mode Voltage During LO and Electrical Idle Max 20 0 100 Units Comments UI See Notes (2) and (4) mV VTX-CM-ACp = RMS(|VTXD+- VTXD-|/2 -VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+- VTX-D-|/2 See Note (2) mV |VTX-CM-DC (during LO) - VTX-CM-Idle-DC (During Electrical Idle)|<=100 mV VTX-CM-DC = DC(avg) of |VTX-D+- VTX-D-|/2 [LO] VTX-CM-Idle-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 [Electrical Idle] See Note (2). Absolute Delta of DC Common Mode between D+ and D- 0 25 mV |VTX-CM-DC-D+ - VTX-CM-DC-D-| <= 25 mV VTX-CM-DC-D+ = DC(avg) of |VTX-D+| VTX-CM-DC-D- = DC(avg) of |VTX-D-| See Note (2). VTX-IDLE-DIFFp Electrical Idle differential Peak Output Voltage 0 20 mV VTX-IDLE-DIFFp = |VTX-IDLE-D+ -VTX-IDLE-D-| <= 20 mV See Note (2). VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detection 600 mV The total amount of voltage change that a transmitter can apply to sense whether a low impedance Receiver is present. See Note (5). VTX-DC-CM The TX DC Common Mode Voltage 3.6 V The allowed DC Common Mode voltage under any conditions. See Note (5). ITX-SHORT TX Short Circuit Current Limit 90 mA The total current the Transmitter can provide when shorted to its ground TTX-IDLE-MIN Minimum time spent in Electrical Idle UI Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set UI After sending an Electrical Idle ordered set, the Transmitter must meet all Electrical Idle Specifications within this time. This is considered a debounce time for the Transmitter to meet Electrical Idle after transitioning from LO. UI Maximum time to meet all TX specifications when transitioning from Electrical Idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving Electrical Idle VTX-CM-DC-LINEDELTA TTX-IDLE-SET-TOIDLE TTX-IDLE-TODIFF-DATA 0 50 Maximum time to transition to a valid Electrical idle after sending an Electrical Idle ordered set 20 Maximum time to transition to valid TX specifications after leaving an Electrical idle condition 20 RLTX-DIFF Differential Return Loss 12 dB Measured over 50 MHz to 1.25 GHz. See Note (3) RLTX-CM Common Mode Return Loss 6 dB Measured over 50 MHz to 1.25 GHz. See Note (3) ZTX-DIFF-DC DC Differential TX Impedance 80 TX DC Differential mode Low Impedance 100 120 58 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 17-2. Differential Transmitter (TX) Output Specifications (Continued) Symbol Parameter ZTX-DC Transmitter DC Impedance LTX-SKEW Lane-to-Lane Output Skew CTX AC Coupling Capacitor Tcrosslink Crosslink Random Timeout Notes: Min Nom Max Units Comments Required TX D+ as wellall states 500 + 2 UI ps Static skew between any two Transmitter Lanes within a single Link 200 nF All Transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. ms This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one Downstream and one Upstream Port. See Note (6). 40 75 0 1 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 17-3 on page 63 and measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 17-1 on page 60.) 3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 probes; see Figure 17-3 on page 63). Note that the series capacitors CTX is optional for the return loss measurement. 5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 17-3 on page 63 for both VTX-D+ and VTX-D-. 6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a. 7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a. 17.4.2 Transmitter Compliance Eye Diagrams The TX eye diagram in Figure 17-1 on page 60 is specified using the passive compliance/test measurement load (see Figure 17-3 on page 63) in place of any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. Note: It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits). 59 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 17-1. Minimum Transmitter Timing and Voltage Output Compliance Specifications VTX-DIFF = 0 mV (D+ D- Crossing Point) VTX-DIFF = 0 mV (D+ D- Crossing Point) (Transition Bit) VTX-DIFFp-p-MIN = 800 mV (De-emphasized Bit) 566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB) .07 UI = UI - 0.3 UI(JTX-TOTAL-MAX) (Transition Bit) VTX-DIFFp-p-MIN = 800 mV 17.4.3 Differential Receiver (RX) Input Specifications Table 17-3 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins. Table 17-3. Differential Receiver (RX) Input Specifications Symbol Parameter Min Nom Max Units UI Unit Interval 399.8 8 400 400.1 2 ps Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note (1). VRX-DIFFp-p Differential Peak-toPeak Output Voltage 0.175 1.200 V VRX-DIFFp-p= 2*|VRX-D+ - VRX-D-| See Note (2). UI The maximum interconnect media and Transmitter jitter that can be tolerated by the Receiver can be derived as TRX-MAXJITTER = 1 - TRX-EYE = 0.6 UI. See Notes (2) and (3). UI Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes (2)(3)(7). Minimum Receiver Eye Width TRX-EYE TRX-EYE-MEDIAN-to-MAX JITTER Maximum time between the jitter median and maximum deviation from the median 0.4 0.3 Comments 60 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 17-3. Differential Receiver (RX) Input Specifications (Continued) Symbol Parameter VRX-CM-ACp AC Peak Common Mode Input Voltage Min Nom Max Units Comments 150 mV VRX-CM-ACp = |VRXD+ - VRXD-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg)of |VRX-D+- VRX-D-|/2 See Note (2) Measured over 50 MHz to 1.25 GHz with the D+ and D-lines biased at +300 mV and -300 mV, respectively. See Note (4) RLRX-DIFF Differential Return Loss 15 dB RLRX-CM Common Mode Return Loss 6 dB ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 RX DC Differential (5) ZRX-DC DC Input Impedance 40 50 60 Required RX D+ as well as D-DC Impedance (50 20% tolerance). See Notes (2) and (5) ZRX-HIGH-IMP-DC Powered Down DC Input Impedance Measured over 50 MHz to 1.25 GHz with the D+ and D-lines biased at 0V. See Note (4) 200 k Required RX D+ as well as D-DC Impedance when the Receiver terminations do not have power. See Note (6) VRX-IDLE-DET-DIFFp-p TRX-IDLE-DET-DIFFENTERTIME LTX-SKEW Notes: Electrical Idle Detect Threshold 65 Unexpected Electrical Idle Enter Detect Threshold Integration Time Total 175 10 Skew 20 mV VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ -VRX-D-| Measured at the package pins of the Receiver ms An unexpected Electrical Idle (VRX-DIFFp-p < VRX-IDLE-DET-DIFFp-p) must be recognized no longer than TRX-IDLE-DET-DIFF-ENTERING to signal an unexpected idle condition. ns Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (e.g. COM and one to five Symbols) at the RX as well as any delay differences arising from the interconnect itself. 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 17-3 on page 63 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 17-2 on page 62). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 61 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 probes - see Figure 17-3 on page 63). Note: that the series capacitors CTX is optional for the return loss measurement. 5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port. 6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground. 7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. 17.5 Receiver Compliance Eye Diagrams The RX eye diagram in Figure 17-2 on page 62 is specified using the passive compliance/test measurement load (see Figure 17-3 on page 63) in place of any real PCI Express RX component. Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see Figure 17-3 on page 63) will be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in Figure 17-2) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. Note: The reference impedance for return loss measurements is 50. to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer with 50. probes; see Figure 17-3 on page 63). Note that the series capacitors, CTX, are optional for the return loss measurement. Figure 17-2. Minimum Receiver Eye Timing and Voltage Compliance Specification VRX-DIFF = 0 mV (D+ D- Crossing Point) VRX-DIFF = 0 mV (D+ D- Crossing Point) VRX-DIFFp-p-MIN > 175 mV 0.4 UI = TRX-EYE-MIN 62 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 17.5.1 Compliance Test and Measurement Load The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 17-3 on page 63. Note: The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary. Figure 17-3. Compliance Test/Measurement Load D+ Package Pin C = CTX TX Silicon + Package D- Package Pin C = CTX R = 50 R = 50 18. Serial RapidIO This section describes the DC and AC electrical specifications for the RapidIO interface of the PC8548E, for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud. Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors across a backplane. A single receiver specification is given that will accept signals from both the short run and long run transmitter specifications. The short run transmitter should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall power used by the transceivers. The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications allow a distance of at least 50 cm at all baud rates. All unit intervals are specified with a tolerance of 100 ppm. The worst case frequency difference between any transmit and receive clock will be 200 ppm. To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver input must be used. 18.1 DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK For more information, see Section 16.1 "DC Requirements for SerDes Reference Clocks" on page 56. 63 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 18.2 AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK Table 18-1 lists AC requirements. Table 18-1. SD n_REF_CLK and SDn_REF_CLK AC Requirements Symbol Parameter Description Min Typical Max Units tREF REFCLK cycle time - 10(8) - ns 8 ns applies only to serial RapidIO with 125-MHz reference clock tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles - - 80 ps - tREFPJ Phase jitter. Deviation in edge location with respect to mean edge location -40 - 40 ps 18.3 Comments Signal Definitions LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential signals. Figure 18-1 shows how the signals are defined. The figures show waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows: 1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak swing of A - B Volts 2. The differential output signal of the transmitter, VOD, is defined as VTD-VTD 3. The differential input signal of the receiver, VID, is defined as VRD-VRD 4. The differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts 5. The peak value of the differential transmitter output signal and the differential receiver input signal is A - B Volts 6. The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (A - B) Volts Figure 18-1. Differential Peak-Peak Voltage of Transmitter or Receiver A Volts B Volts TD or RD TD or RD Differential Peak-Peak = 2 x (A-B) To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV and -500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p. 64 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 18.4 Equalization With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The most common equalization techniques that can be used are: * A passive high pass filter network placed at the receiver. This is often referred to as passive equalization. * The use of active circuits in the receiver. This is often referred to as adaptive equalization. 18.5 Explanatory Note on Transmitter and Receiver Specifications AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002. XAUI has similar application goals to serial RapidIO, as described in Section 9.1 "Enhanced ThreeSpeed Ethernet Controller (eTSEC) (10/100/1Gb Mbps) - GMII/MII/TBI/ RGMII/RTBI/RMII Electrical Characteristics" on page 24. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein. 18.6 Transmitter Specifications LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of the transmitter in each case shall be better than * -10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and * -10 dB + 10log(f/625 MHz) dB for 625 MHz Freq(f) Baud Frequency The reference impedance for the differential return loss measurements is 100 resistive. Differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance requirement applies to all valid output levels. It is recommended that the 20% - 80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB. 65 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 18-2. Short Run Transmitter AC Timing Specifications: 1.25 GBaud Range Characteristic Symbol Min Max Unit Output Voltage, VO -0.40 2.30 V VDIFFPP 500 1000 mV p-p Differential Output Voltage Notes Voltage relative to COMMON of either signal comprising a differential pair Deterministic Jitter JD 0.17 UI p-p Total Jitter JT 0.35 UI p-p SMO 1000 ps Skew at the transmitter output between lanes of a multilane link 800 ps 100 ppm Multiple output skew Unit Interval Table 18-3. UI 800 Short Run Transmitter AC Timing Specifications: 2.5 GBaud Range Characteristic Symbol Min Max Unit Output Voltage, VO -0.40 2.30 V VDIFFPP 500 1000 mV p-p Differential Output Voltage Notes Voltage relative to COMMON of either signal comprising a differential pair Deterministic Jitter JD 0.17 UI p-p Total Jitter JT 0.35 UI p-p SMO 1000 ps Skew at the transmitter output between lanes of a multilane link 400 ps 100 ppm Multiple output skew Unit Interval Table 18-4. UI 400 Short Run Transmitter AC Timing Specifications: 3.125 GBaud Range Characteristic Symbol Min Max Unit Output Voltage, VO -0.40 2.30 V VDIFFPP 500 1000 mV p-p Differential Output Voltage Notes Voltage relative to COMMON of either signal comprising a differential pair Deterministic Jitter JD 0.17 UI p-p Total Jitter JT 0.35 UI p-p SMO 1000 ps Skew at the transmitter output between lanes of a multilane link 320 ps 100 ppm Multiple output skew Unit Interval UI 320 66 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 18-5. Long Run Transmitter AC Timing Specifications: 1.25 GBaud Range Characteristic Symbol Min Max Unit Output Voltage, VO -0.40 2.30 V VDIFFPP 800 1600 mV p-p Differential Output Voltage Notes Voltage relative to COMMON of either signal comprising a differential pair Deterministic Jitter JD 0.17 UI p-p Total Jitter JT 0.35 UI p-p SMO 1000 ps Skew at the transmitter output between lanes of a multilane link 800 ps 100 ppm Multiple output skew Unit Interval Table 18-6. UI 800 Long Run Transmitter AC Timing Specifications: 2.5 GBaud Range Characteristic Symbol Min Max Unit Output Voltage, VO -0.40 2.30 V VDIFFPP 800 1600 mV p-p Differential Output Voltage Notes Voltage relative to COMMON of either signal comprising a differential pair Deterministic Jitter JD 0.17 UI p-p Total Jitter JT 0.35 UI p-p SMO 1000 ps Skew at the transmitter output between lanes of a multilane link 400 ps 100 ppm Multiple output skew Unit Interval Table 18-7. UI 400 Long Run Transmitter AC Timing Specifications: 3.125 GBaud Range Characteristic Symbol Min Max Unit Output Voltage, VO -0.40 2.30 V VDIFFPP 800 1600 mV p-p Differential Output Voltage Notes Voltage relative to COMMON of either signal comprising a differential pair Deterministic Jitter JD 0.17 UI p-p Total Jitter JT 0.35 UI p-p SMO 1000 ps Skew at the transmitter output between lanes of a multilane link 320 ps 100 ppm Multiple output skew Unit Interval UI 320 67 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask shown in Figure 18-2 with the parameters specified in Table 18-8 when measured at the output pins of the device and the device is driving a 100 5% differential resistive load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized. Transmitter Differential Output Voltage Figure 18-2. Transmitter Output Compliance Mask VDIFF max VDIFF min 0 -VDIFF min -VDIFF max 0 A B 1-B 1-A 1 Time in UI Table 18-8. Transmitter Differential Output Eye Diagram Parameters Transmitter Type VDIFFmin (mV) VDIFFmax (mV) A (UI) B (UI) 1.25 GBaud short range 250 500 0.175 0.39 1.25 GBaud long range 400 800 0.175 0.39 2.5 GBaud short range 250 500 0.175 0.39 2.5 GBaud long range 400 800 0.175 0.39 3.125 GBaud short range 250 500 0.175 0.39 3.125 GBaud long range 400 800 0.175 0.39 68 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 18.7 Receiver Specifications LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100 resistive for differential return loss and 25 resistive for common mode. Table 18-9. Receiver AC Timing Specifications - 1.25 GBaud Range Characteristic Symbol Min Max Unit Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver Deterministic Jitter Tolerance JD 0.37 UI p-p Measured at receiver Combined Deterministic and Random Jitter Tolerance JDR 0.55 UI p-p Measured at receiver Total Jitter Tolerance(1) JT 0.65 UI p-p Measured at receiver Multiple Input Skew SMI 24 BER 10-12 Bit Error Rate Unit Interval Note: UI 800 800 Notes ns Skew at the receiver input between lanes of a multilane link ps 100 ppm 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 18-3 on page 70. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Table 18-10. Receiver AC Timing Specifications: 2.5 GBaud Range Characteristic Symbol Min Max Unit Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver Deterministic Jitter Tolerance JD 0.37 UI p-p Measured at receiver Combined Deterministic and Random Jitter Tolerance JDR 0.55 UI p-p Measured at receiver Total Jitter Tolerance(1) JT 0.65 UI p-p Measured at receiver Multiple Input Skew SMI 24 Bit Error Rate BER 10-12 Unit Interval Note: UI 400 400 Notes ns Skew at the receiver input between lanes of a multilane link ps 100 ppm Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 18-3 on page 70. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. 69 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 18-11. Receiver AC Timing Specifications: 3.125 GBaud Range Characteristic Symbol Min Max Unit Differential Input Voltage VIN 200 1600 mV p-p Measured at receiver Deterministic Jitter Tolerance JD 0.37 UI p-p Measured at receiver Combined Deterministic and Random Jitter Tolerance JDR 0.55 UI p-p Measured at receiver Total Jitter Tolerance(1) JT 0.65 UI p-p Measured at receiver Multiple Input Skew SMI 22 Bit Error Rate BER 10-12 Unit Interval Note: UI 320 320 Notes ns Skew at the receiver input between lanes of a multilane link ps 100 ppm 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 18-3. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects Figure 18-3. Single Frequency Sinusoidal Jitter Limits 8.5 UIp-p Sinusoidal Jitter Amplitude 0.10 UIp-p 22.1 kHz Frequency 1.875 MHz 20 MHz 70 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 18.8 Receiver Eye Diagrams For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding Bit Error Rate specification (Table 18-9 on page 69, Table 18-10 on page 69, Table 18-11 on page 70) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver Input Compliance Mask shown in Figure 18-4 with the parameters specified in Table 18-12 on page 71. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ohm 5% differential resistive load. Figure 18-4. Receiver Input Compliance Mask Receiver Differential Input Voltage VDIFF max VDIFF min 0 -VDIFF min -VDIFF max 0 A B 1-B 1 1-A Time in UI Table 18-12. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter Receiver Type VDIFF min (mV) VDIFF max (mV) A (UI) B (UI) 1.25 GBaud 100 800 0.275 0.400 2.5 GBaud 100 800 0.275 0.400 3.125 GBaud 100 800 0.275 0.400 71 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 18.9 Measurement and Test Requirements Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE802.3ae-2002 is recommended as a reference for additional information on jitter test methods. 18.9.1 Eye Template Measurements For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE802.3ae. All lanes of the LPSerial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12. The eye pattern shall be measured with AC coupling and the compliance template centered at 0V differential. The left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ohms resistive 5% differential to 2.5 GHz. 18.9.2 Jitter Test Measurements For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured with AC coupling and at 0V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE802.3ae. 18.9.3 Transmit Jitter Transmit jitter is measured at the driver output when terminated into a load of 100 Ohms resistive 5% differential to 2.5 GHz. 18.9.4 Jitter Tolerance Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum of deterministic and random jitter defined in Section 8.6 and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in Figure 8-4 and Table 8-11. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested. 72 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 19. Package Description This section details package parameters, pin assignments, and dimensions. 19.1 Package Parameters The package parameters are as provided in the following list. The package type is 29 mm x 29 mm, 783 flip chip HITCE ball grid array (HITCE). Table 19-1. Package Parameters CBGA(1) PBGA(2) 29 mm x 29 mm 29 mm x 29 mm 783 783 1 mm 1 mm Ball diameter (typical) 0.6 mm 0.6 mm Solder ball (eutectic) 62% Sn 36% Pb 2% Ag 62% Sn 36% Pb 2% Ag Solder ball high lead 90% Sn 10pb N.A. Solder ball (lead-free) 96,5% Sn 3% Ag 0.5% Cu 96.5% Sn 3.5% Ag Parameter Package outline Interconnects Ball pitch (3) Notes: 1. The HiCTE FC-CBGA package is available on Version 2.0 and 2.1 of the device. 2. The FC-PBGA package is available on only Version 2.1 of the device. 3. High lead solder spheres are upon request. 73 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 19.1.1 Mechanical Dimensions of the HITCE Figure 19-1 shows the mechanical dimensions and bottom surface nomenclature of the 783 HITCE package. Figure 19-1. Mechanical Dimensions of the HITCE FC-CBGA with Full Lid 29 A1 Corner LID Chamfer 783X B 0.2 A A 0.25 C A Seating plane 4 0.35 A 5 28.7 Max LID ZONE 29 4X 0.2 28.7 Max LID ZONE Top view 0.5 2 1 3 4 5 6 7 8 27X 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AH AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AG AF AE AD AC AB AA Y W V U T R 27X 1 3.38 Max P N M L K J H G F E D C B 0.6 0.35 1.32 1.08 1.63 1.37 0.5 Side view A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (783X) Bottom view 0.3 0.65 3 0.5 M A B C 0.15 M A Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Capacitors may not be present on all devices. 6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. All dimensions are symetric across the package center lines, unless dimensioned otherwise. 74 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 19.2 Pinout Listings Note: The DMA_DACK[0:1] and TEST_SEL/ TEST_SEL pins must be set to a proper state during POR configuration. Please refer to the pinlist table of the individual device for more details. For PC8548/47/45, GPIOs are still available on PCI1_AD[63:32]/PC2_AD[31:0] pins if they are not used for PCI funcationality. For MPC8545/43, eTSEC does not support 16 bit FIFO mode. Table 19-2 provides the pin-out listing for the PC8548E 783 HITCE package. Table 19-2. PC8548E Pinout Listing Pin Type Power Supply PCI1_AD[63:32]/PCI2_AD[31:0] AB14, AC15, AA15, Y16, W16, AB16, AC16, AA16, AE17, AA18, W18, AC17, AD16, AE16, Y17, AC18, AB18, AA19, AB19, AB21, AA20, AC20, AB20, AB22, AC22, AD21, AB23, AF23, AD23, AE23, AC23, AC24 I/O OVDD (16) PCI1_AD[31:0] AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9, AH9, AC10, AB10, AD10, AG10, AA10, AH10, AA11, AB12, AE12, AG12, AH12, AB13, AA12, AC13, AE13, Y14, W13, AG13, V14, AH13, AC14, Y15, AB15 I/O OVDD (16) PCI1_C_BE[7:4]/PCI2_C_BE[3:0] AF15, AD14, AE15, AD15 I/O OVDD (16) PCI1_C_BE[3:0] AF9, AD11, Y12, Y13 I/O OVDD (16) PCI1_PAR64/PCI2_PAR W15 I/O OVDD PCI1_GNT[4:1] AG6, AE6, AF5, AH5 O OVDD PCI1_GNT0 AG5 I/O OVDD PCI1_IRDY AF11 I/O OVDD PCI1_PAR AD12 I/O OVDD PCI1_PERR AC12 I/O OVDD (2) PCI1_SERR V13 I/O OVDD (2)(3) PCI1_STOP W12 I/O OVDD (2) PCI1_TRDY AG11 I/O OVDD (2) PCI1_REQ[4:1] AH2, AG4, AG3, AH4 I OVDD PCI1_REQ0 AH3 I/O OVDD PCI1_CLK AH26 I OVDD (32) PCI1_DEVSEL AH11 I/O OVDD (2) PCI1_FRAME AE11 I/O OVDD (2) PCI1_IDSEL AG9 I OVDD PCI1_REQ64/PCI2_FRAME AF14 I/O OVDD (2)(4)(9) PCI1_ACK64/PCI2_DEVSEL V15 I/O OVDD (2) Signal Package Pin Number Notes PCI1 and PCI2 (one 64-bit or two 32-bit) (4)(8)(29) (2) 75 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply AE28 I OVDD (2) PCI2_IRDY AD26 I/O OVDD (2) PCI2_PERR AD25 I/O OVDD (2) PCI2_GNT[4:1] AE26, AG24, AF25, AE25 O OVDD (4)(8)(29) PCI2_GNT0 AG25 I/O OVDD PCI2_SERR AD24 I/O OVDD (2)(3) PCI2_STOP AF24 I/O OVDD (2) PCI2_TRDY AD27 I/O OVDD (2) PCI2_REQ[4:1] AD28, AE27, W17, AF26 I OVDD PCI2_REQ0 AH25 I/O OVDD MDQ[0:63] L18, J18, K14, L13, L19, M18, L15, L14, A17, B17, A13, B12, C18, B18, B13, A12, H18, F18, J14, F15, K19, J19, H16, K15, D17, G16, K13, D14, D18, F17, F14, E14, A7, A6, D5, A4, C8, D7, B5, B4, A2, B1, D1, E4, A3, B2, D2, E3, F3, G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3, J2, L1, M6 I/O GVDD MECC[0:7] H13, F13, F11, C11, J13, G13, D12, M12 I/O GVDD MDM[0:8] M17, C16, K17, E16, B6, C4, H4, K1, E13 O GVDD MDQS[0:8] M15, A16, G17, G14, A5, D3, H1, L2, C13 I/O GVDD MDQS[0:8] L17, B16, J16, H14, C6, C2, H3, L4, D13 I/O GVDD MA[0:15] A8, F9, D9, B9, A9, L10, M10, H10, K10, G10, B8, E10, B10, G6, A10, L11 O GVDD MBA[0:2] F7, J7, M11 O GVDD MWE E7 O GVDD MCAS H7 O GVDD MRAS L8 O GVDD MCKE[0:3] F10, C10, J11, H11 O GVDD MCS[0:3] K8, J8, G8, F8 O GVDD MCK[0:5] H9, B15, G2, M9, A14, F1 O GVDD MCK[0:5] J9, A15, G1, L9, B14, F2 O GVDD MODT[0:3] E6, K6, L7, M7 O GVDD MDIC[0:1] A19, B19 I/O GVDD Signal Package Pin Number PCI2_CLK Notes DDR SDRAM Memory Interface (10) (30) Local Bus Controller Interface 76 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply LAD[0:31] E27, B20, H19, F25, A20, C19, E28, J23, A25, K22, B28, D27, D19, J22, K20, D28, D25, B25, E22, F22, F21, C25, C22, B23, F20, A23, A22, E19, A21, D21, F19, B21 I/O BVDD LDP[0:3] K21, C28, B26, B22 I/O BVDD LA[27] H21 O BVDD (4)(8) LA[28:31] H20, A27, D26, A28 O BVDD (4)(6)(8) LCS[0:4] J25, C20, J24, G26, A26 O BVDD LCS5/DMA_DREQ2 D23 I/O BVDD (1) LCS6/DMA_DACK2 G20 O BVDD (1) LCS7/DMA_DDONE2 E21 O BVDD (1) LWE0/LBS0/LSDDQM[0] G25 O BVDD (4)(8) LWE1/LBS1/LSDDQM[1] C23 O BVDD (4)(8) LWE2/LBS2/LSDDQM[2] J21 O BVDD (4)(8) LWE3/LBS3/LSDDQM[3] A24 O BVDD (4)(8) LALE H24 O BVDD (4)(7)(8) LBCTL G27 O BVDD (4)(7)(8) LGPL0/LSDA10 F23 O BVDD (4)(8) LGPL1/LSDWE G22 O BVDD (4)(8) LGPL2/LOE/LSDRAS B27 O BVDD (4)(7)(8) LGPL3/LSDCAS F24 O BVDD (4)(8) LGPL4/LGTA/LUPWAIT/LPBSE H23 I/O BVDD LGPL5 E26 O BVDD LCKE E24 O BVDD LCLK[0:2] E23, D24, H22 O BVDD LSYNC_IN F27 I BVDD LSYNC_OUT F28 O BVDD Signal Package Pin Number Notes (4)(8) DMA DMA_DACK[0:1] AD3, AE1 O OVDD DMA_DREQ[0:1] AD4, AE2 I OVDD DMA_DDONE[0:1] AD2, AD1 O OVDD (4)(8)(35) Programmable Interrupt Controller UDE AH16 I OVDD MCP AG19 I OVDD IRQ[0:7] AG23, AF18, AE18, AF20, AG18, AF17, AH24, AE20 I OVDD 77 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply AF19 I OVDD IRQ[9]/DMA_DREQ3 AF21 I OVDD (1) IRQ[10]/DMA_DACK3 AE19 I/O OVDD (1) IRQ[11]/DMA_DDONE3 AD20 I/O OVDD (1) IRQ_OUT AD18 O OVDD (2)(3) (4)(8) Signal Package Pin Number IRQ[8] Notes Ethernet Management Interface EC_MDC AB9 O OVDD EC_MDIO AC8 I/O OVDD I LVDD Gigabit Reference Clock EC_GTX_CLK125 V11 Three-SpeeDEthernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] R5, U1, R3, U2, V3, V1, T3, T2 I LVDD TSEC1_TXD[7:0] T10, V7, U10, U5, U4, V6, T5, T8 O LVDD TSEC1_COL R4 I LVDD TSEC1_CRS V5 I/O LVDD TSEC1_GTX_CLK U7 O LVDD TSEC1_RX_CLK U3 I LVDD TSEC1_RX_DV V2 I LVDD TSEC1_RX_ER T1 I LVDD TSEC1_TX_CLK T6 I LVDD TSEC1_TX_EN U9 O LVDD TSEC1_TX_ER T7 O LVDD (4)(8) (18) (24) Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_RXD[7:0] P2, R2, N1, N2, P3, M2, M1, N3 I TSEC2_TXD[7:0] N9, N10, P8, N7, R9, N5, R8, N6 O TSEC2_COL P1 I TSEC2_CRS R6 I/O TSEC2_GTX_CLK P6 O TSEC2_RX_CLK N4 I TSEC2_RX_DV P5 I TSEC2_RX_ER R1 I LVDD TSEC2_TX_CLK P10 I LVDD TSEC2_TX_EN P7 O LVDD (24) TSEC2_TX_ER R10 O LVDD (4)(8)(27) Three-Speed Ethernet Controller (Gigabit Ethernet 3) 78 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply V8, W10, Y10, W7 O TVDD TSEC3_RXD[3:0] Y1, W3, W5, W4 I TVDD TSEC3_GTX_CLK W8 O TVDD TSEC3_RX_CLK W2 I TVDD TSEC3_RX_DV W1 I TVDD TSEC3_RX_ER Y2 I TVDD TSEC3_TX_CLK V10 I TVDD TSEC3_TX_EN V9 O TVDD (24) Signal Package Pin Number TSEC3_TXD[3:0] Notes (4)(8)(23) Three-Speed Ethernet Controller (Gigabit Ethernet 4) TSEC4_TXD[3:0]/TSEC3_TXD[7:4] AB8, Y7, AA7, Y8 O TVDD (1)(4)(8)(23) TSEC4_RXD[3:0]/TSEC3_RXD[7:4] AA1, Y3, AA2, AA4 I TVDD (1) TSEC4_GTX_CLK AA5 O TVDD TSEC4_RX_CLK/TSEC3_COL Y5 I TVDD (1) TSEC4_RX_DV/TSEC3_CRS AA3 I/O TVDD (1)(25) TSEC4_TX_EN/TSEC3_TX_ER AB6 O TVDD (1)(24) DUART UART_CTS[0:1] AB3, AC5 I OVDD UART_RTS[0:1] AC6, AD7 O OVDD UART_SIN[0:1] AB5, AC7 I OVDD UART_SOUT[0:1] AB7, AD8 O OVDD I2C interface IIC1_SCL AG22 I/O OVDD (3)(22) IIC1_SDA AG21 I/O OVDD (3)(22) IIC2_SCL AG15 I/O OVDD (3)(22) IIC2_SDA AG14 I/O OVDD (3)(22) SerDes SD_RX[0:7] M28, N26, P28, R26, W26, Y28, AA26, AB28 I XVDD SD_RX[0:7] M27, N25, P27, R25, W25, Y27, AA25, AB27 I XVDD SD_TX[0:7] M22, N20, P22, R20, U20, V22, W20, Y22 O XVDD SD_TX[0:7] M23, N21, P23, R21, U21, V23, W21, Y23 O XVDD SD_PLL_TPD U28 O XVDD SD_REF_CLK T28 I XVDD SD_REF_CLK T27 I XVDD Reserved AC1, AC3 - - (2) Reserved M26, V28 - - (33) (19) 79 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply M25, V27 - - (28) M20, M21, T22, T23 - - (31) O BVDD Signal Package Pin Number Reserved Reserved Notes General-Purpose Output GPOUT[24:31] K26, K25, H27, G28, H25, J26, K24, K23 System Control HRESET AG17 I OVDD HRESET_REQ AG16 O OVDD SRESET AG20 I OVDD CKSTP_IN AA9 I OVDD CKSTP_OUT AA8 O OVDD (23) (2)(3) Debug TRIG_IN AB2 I OVDD TRIG_OUT/READY/QUIESCE AB1 O OVDD MSRCID[0:1] AE4, AG2 O OVDD (4)(5)(8) MSRCID[2:4] AF3, AF1, AF2 O OVDD (5)(17)(23) MDVAL AE5 O OVDD (5) CLK_OUT AE21 O OVDD (10) (5)(8)(17) (23) Clock RTC AF16 I OVDD SYSCLK AH17 I OVDD JTAG TCK AG28 I OVDD TDI AH28 I OVDD (11) TDO AF28 O OVDD (10) TMS AH27 I OVDD (11) TRST AH23 I OVDD (11) DFT L1_TSTCLK AC25 I OVDD (20) L2_TSTCLK AE22 I OVDD (20) LSSD_MODE AH20 I OVDD (20) TEST_SEL AH14 I OVDD (20) Thermal Management THERM0 AG1 - (13) THERM1 AH1 - (13) 80 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply O OVDD GND A11, B7, B24, C1, C3, C5, C12, C15, C26, D8, D11, D16, D20, D22, E1, E5, E9, E12, E15, E17, F4, F26, G12, G15, G18, G21, G24, H2, H6, H8, H28, J4, J12, J15, J17, J27, K7, K9, K11, K27, L3, L5, L12, L16, N11, N13, N15, N17, N19, P4, P9, P12, P14, P16, P18, R11, R13, R15, R17, R19, T4, T12, T14, T16, T18, U8, U11, U13, U15, U17, U19, V4, V12, V18, W6, W19, Y4, Y9, Y11, Y19, AA6, AA14, AA17, AA22, AA23, AB4, AC2, AC11, AC19, AC26, AD5, AD9, AD22, AE3, AE14, AF6, AF10, AF13, AG8, AG27 K28, L24, L26, N24, N27, P25, R28, T24, T26, U24, V25, W28, Y24, Y26, AA24, AA27, AB25, AC28 L21, L23, N22, P20, R23, T21, U22, V20, W23, Y21 U27 - - OVDD V16, W11, W14, Y18, AA13, AA21, AB11, AB17, AB24, AC4, AC9, AC21, AD6, AD13, AD17, AD19, AE10, AE8, AE24, AF4, AF12, AF22, AF27, AG26 Power for PCI and other standards (3.3V) OVDD N8, R7, T9, U6 Power for TSEC1 and TSEC2 (2.5V ,3.3V) LVDD TVDD W9, Y6 Power for TSEC3 and TSEC4 (2,5V, 3.3V) TVDD GVDD B3, B11, C7, C9, C14, C17, D4, D6, D10, D15, E2, E8, E11, E18, F5, F12, F16, G3, G7, G9, G11, H5, H12, H15, H17, J10, K3, K12, K16, K18, L6, M4, M8, M13 Power for DDR1 and DDR2 DRAM I/Ovoltage (1.8V,2.5V) GVDD BVDD C21, C24, C27, E20, E25, G19, G23, H26, J20 Power for Local Bus (1.8V, 2.5V, 3.3V) BVDD VDD M19, N12, N14, N16, N18, P11, P13, P15, P17, P19, R12, R14, R16, R18, T11, T13, T15, T17, T19, U12, U14, U16, U18, V17, V19 Power for Core (1.1V) VDD Signal Package Pin Number Notes Power Management ASLEEP AH18 (8)(17)(23) Power and Ground Signals LVDD 81 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 19-2. PC8548E Pinout Listing (Continued) Pin Type Power Supply Signal Package Pin Number SVDD L25, L27, M24, N28, P24, P26, R24, R27, T25, V24, V26, W24, W27, Y25, AA28, AC27 Core Power for SerDes transceivers (1.1V) SVDD XVDD L20, L22, N23, P21, R22, T20, U23, V21, W22, Y20 Pad Power for SerDes transceivers (1.1V) XVDD AVDD_LBIU J28 Power for local bus PLL (1.1V) (21) AVDD_PCI1 AH21 Power for PCI1 PLL (1.1V) (21) AVDD_PCI2 AH22 Power for PCI2 PLL (1.1V) (21) AVDD_CORE AH15 Power for e500 PLL (1.1V) (21) AVDD_PLAT AH19 Power for CCB PLL (1.1V) (21) AVDD_SRDS U25 Power for SRDSPLL (1.1V) (21) SENSEVDD M14 O SENSEVSS M16 VDD Notes (12) (12) Analog Signals MVREF A18 I Reference voltage signal for DDR SD_IMP_CAL_RX L28 I 200 to GND SD_IMP_CAL_TX AB26 I 100 to GND SD_PLL_TPA U26 O Notes: MVREF (19) 1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2. 2. Recommend a weak pull-up resistor (2-10 k) be placed on this pin to OVDD. 3. This pin is an open drain signal. 82 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 4. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7 k pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 5. Treat these pins as no connects (NC) unless using debug address functionality. 6. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7 k pull-up or pull-down resistors. See Section 20.2 "CCB/SYSCLK PLL Ratio" on page 85. 7. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7 k pull-up or pull-down resistors. See the Section 20.3 "e500 Core PLL Ratio" on page 86. 8. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan. 9. This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit PCI device. Refer to the PCI Specification. 10. This output is actively driven during reset rather than being three-stated during reset. 11. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 12. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking and regulation. 13. Internal thermally sensitive resistor. 14. No connections should be made to these pins if they are not used. 15. These pins are not connected for any use. 16. PCI specifications recommend that a weak pull-up resistor (2-10 k) be placed on the higher order pins to OVDD when using 64-bit buffer mode (pins PCI_AD[63:32] and PCI1_C_BE[7:4]). 17. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 18. This pin is only an output in FIFO mode when used as Rx Flow Control. 19. Do not connect. 20. These are test signals for factory use only and must be pulled up (100 . - 1 k.) to OVDD for normal machine operation. 21. Independent supplies derived from board VDD. 22. Recommend a pull-up resistor (~1 K.) b placed on this pin to OVDD. 23. The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], TSEC4_TXD3/TSEC3_TXD7, HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. For rev 2.0 silicon, cfg_srds_en added to TSEC4_TXD[2]/TSEC3_TXD[6] -This POR config powers down the SERDES block entirely if pulled down. If the SERDES is going to be used in any way, then this pin should be pulled up or it can be left without a pullup or pulldown. For Rev. 1.x/Rev 1.1.x silicon, TSEC4_TXD[2:3] pin values during POR configuration are don't care. 24. This pin requires an external 4.7 k pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 25. This pin is only an output in eTSEC3 FIFO mode when used as Rx flow control. 26. These pins should be connected to XVDD. 27. TSEC2_TXD1, TSEC2_TX_ER are multiplexedas cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET ASSERTION. 28. These pins should be pulled to ground through a 300 (10%) resistor. 29. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCI n_AD pins as "No Connect" or terminated through 2-10 k pull-up resistors with the default of internal arbiter if the PCI n_AD pins are not connected to any other PCI device. The PCI block will drive the PCI n_AD pins if it is configured to be the PCI arbiter, through POR config pins, irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI device connected on the bus. 30. MDIC0 is grounded through an 18.2 precision 1% resistor and MDIC1 is connected to GVDD through an 18.2 precision 1% resistor. These pins are used for automatic calibration of the DDR IOs. 83 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 31. These pins should be left floating. 32. If PCI1 or PCI2 is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI1_CLK or PCI2_CLK. Otherwise the processor will not boot up. 33. These pins should be connected to GND. 34. This pin requires an external 4.7 k resistor to GND. 35. For Rev. 2.0 silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for Rev. 1.x silicon, the pin values during POR configuration are don't care. 36. If these pins are not used as GPINn (general-purpose input), they should be pulled low (to GND) or high (to LVDD) through 2-10 k resistors. 37. These should be pulled low to GND through 2-10 k resistors if they are not used. 38. These should be pulled low or high to LVDD through 2-10 k resistors if they are not used. 39. For Rev. 2.0 silicon, DMA_DACK[0:1] must be 0b10 during POR configuration; for Rev. 1.x silicon, the pin values during POR configuration are don't care. 40. For Rev. 2.0 silicon, DMA_DACK[0:1] must be 0b01 during POR configuration; for Rev. 1.x silicon, the pin values during POR configuration are don't care. 41. For Rev. 2.0 silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for Rev. 1.x silicon, the pin values during POR -+configuration are don't care. 42. This is a test signal for factory use only and must be pulled down (100 - 1 k) to GND for normal machine operation. 43. These pins should be pulled high to OVDD through 2-10 k resistors. 44. If these pins are not used as GPINn (general-purpose input), they should be pulled low (to GND) or high (to OVDD) through 2-10 k resistors. 45. This pin must not be pulled down during POR configuration. 46. These should be pulled low or high to OVDD through 2-10 k resistors. 20. Clocking This section describes the PLL configuration of the PC8548E. Note that the platform clock is identical to the core complex bus (CCB) clock. 20.1 Clock Ranges Table 20-1 provides the clocking specifications for the processor cores and Table 20-2 provides the clocking specifications for the memory bus. Table 20-1. Processor Core Clocking Specifications Maximum Processor Core Frequency 1000 MHz 1200 MHz 1333 MHz Characteristic Min Max Min Max Min Max Unit Notes e500 core processor frequency 533 1000 533 1200 533 1333 MHz (1)(2) Notes: 1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 20.2 "CCB/SYSCLK PLL Ratio" on page 85, and Section 20.3 "e500 Core PLL Ratio" on page 86, for ratio settings. 2. The minimum e500 core frequency is based on the minimum platform frequency of 266 MHz. 84 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 20-2. Memory Bus Clocking Specifications Maximum Processor Core Frequency 1000, 1200, 1333 MHz Characteristic Min Max Unit Notes Memory bus clock speed 133 266 MHz (1)(2) Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 20.2 "CCB/SYSCLK PLL Ratio" on page 85, and Section 20.3 "e500 Core PLL Ratio" on page 86, for ratio settings. 2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency. 20.2 CCB/SYSCLK PLL Ratio The clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency of the CCB is set using the following reset signals, as shown in Table 20-3: * SYSCLK input signal * Binary value on LA[28:31] at power up Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note that the DDR data rate is the determining factor in selecting the bus frequency, since the frequency must equal the DDR data rate. For specifications on the PCI_CLK, refer to the PCI 2.2 Specification. Table 20-3. CCB Clock Ratio Binary Value of LA[28:31] Signals :SYSCLK Ratio 0000 16:1 0001 Reserved 0010 2:1 0011 3:1 0100 4:1 0101 5:1 0110 6:1 0111 Reserved 1000 8:1 1001 9:1 1010 10:1 1011 Reserved 1100 12:1 1101 20:1 1110 Reserved 1111 Reserved 85 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 20.3 e500 Core PLL Ratio Table 20-4 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in Table 20-4. Table 20-4. 20.4 20.4.1 e500 Core to CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 Signals e500 core:CCB Clock Ratio 000 4:1 001 9:2 010 1:1 011 3:2 100 2:1 101 5:2 110 3:1 111 7:2 Frequency Options Sysclk to Platform Frequency Options Table 20-5 shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in comparison to the memory bus clock speed. Table 20-5. Frequency Options of SYSCLK with Respect to Memory Bus Speeds SYSCLK (MHz) CCB to SYSCLK Ratio 16.66 25 33.33 41.66 66.66 83 100 111 133.33 166 267 332 498 Platform/CCB Frequency (MHz) 2 3 300 333 400 445 533 4 267 333 400 5 333 415 500 6 400 500 8 267 333 9 300 375 10 333 417 300 400 500 533 12 16 267 400 20 333 500 533 86 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 21. Thermal This section describes the thermal specifications of the PC8548. 21.1 Thermal for Revision 2.0 Silicon HiCTE FC-CBGA with Full Lid This section describes the thermal specifications for the HiCTE FC-CBGA package for revision 2.0 silicon. Table 21-1 shows the package thermal characteristics. Table 21-1. Package Thermal Characteristics for HiCTE FC-CBGA Characteristic JEDEC Board Symbol Value Unit Notes Die Junction-to-Ambient (Natural Convection) Single-layer board (1s) RJA 17 C/W (1)(2) Die Junction-to-Ambient (Natural Convection) Four-layer board (2s2p) RJA 12 C/W (1)(2) Die Junction-to-Ambient (200 ft/min) Single-layer board (1s) RJA 11 C/W (1)(2) Die Junction-to-Ambient (200 ft/min) Four-layer board (2s2p) RJA 8 C/W (1)(2) Die Junction-to-Board N/A RJB 3 C/W (3) Die Junction-to-Case N/A RJC 0.8 C/W (4) Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). The cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the interface layer. 21.2 Thermal for Version 2.1 Silicon FC-PBGA with Full Lid This section describes the thermal specifications for the FC-PBGA package for revision 2.1 silicon. Table 21-2 shows the package thermal characteristics. Table 21-2. Package Thermal Characteristics for HiCTE FC-PBGA Characteristic JEDEC Board Symbol Value Unit Notes Die Junction-to-Ambient (Natural Convection) Single-layer board (1s) RJA 18 C/W (1)(2) Die Junction-to-Ambient (Natural Convection) Four-layer board (2s2p) RJA 13 C/W (1)(2) Die Junction-to-Ambient (200 ft/min) Single-layer board (1s) RJA 13 C/W (1)(2) Die Junction-to-Ambient (200 ft/min) Four-layer board (2s2p) RJA 9 C/W (1)(2) Die Junction-to-Board N/A RJB 5 C/W (3) Die Junction-to-Case N/A RJC 0.8 C/W (4) 87 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). The cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the interface layer. 21.3 Heat Sink Solution Every system application has different conditions that the thermal management solution must solve. As such, providing a recommended heat sink has not been found to be very useful. When a heat sink is chosen, give special consideration to the mounting technique. Mounting the heat sink to the printed circuit board is the recommended procedure using a maximum of 10 lbs. force (45 Newtons) perpendicular to the package and board. Clipping the heat sink to the package is not recommended. 22. System Design Information This section provides electrical and thermal design recommendations for successful application of the PC8548E. 22.1 System Clocking This device includes five PLLs, as follows: 1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 20.2 "CCB/SYSCLK PLL Ratio" on page 85. 2. The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 20.3 "e500 Core PLL Ratio" on page 86. 3. The PCI PLL generates the clocking for the PCI bus 4. The local bus PLL generates the clock for the local bus. 5. There is a PLL for the SerDes block. 22.2 22.2.1 Power Supply Design PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 22-1, one to each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). 88 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783 HITCE the footprint, without the inductance of vias. Figure 22-1 shows the PLL power supply filter circuits. Figure 22-1. PC8548E PLL Power Supply Filter Circuit 10 VDD AVDD 2.2 F 2.2 F Low ESL Surface Mount Capacitors GND The AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDS ball. The 0.003 F capacitor is closest to the ball, followed by the 1 F capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from AVDD_SRDS to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct. Figure 22-2. SerDes PLL Power Supply Filter 1.0 SVDD 2.2 F 1 2.2 F 1 AVDD_SRDS 0.003 F GND Note: 1. An 0805 sized capacitor is recommended for system initial bring-up. Note the following: * AVDD_SRDS should be a filtered version of SVDD. * Signals on the SerDes interface are fed from the XVDD power plane. * Power: XVDD consumes less than 300 mW; SVDD + AVDD_SRDS consumes less than 750 mW. 89 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 22.3 Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC8548E system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD,pin of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD, OVDD, GVDD, and LVDD,and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD,planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors: 100-330 F (AVX TPS tantalum or Sanyo OSCON). 22.4 SerDes Block Power Supply Decoupling Recommendations The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. * First, the board should have at least 10 x 10 nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. * Second, there should be a 1 F ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies. * Third, between the device and any SerDes voltage regulator there should be a 10 F, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100 F, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies. 22.5 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to V DD , TV DD , BV DD , OV DD , GV DD , and LV DD , as required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD,TVDD, BVDD, OVDD, GVDD, and LVDD, and GND pins of the device. 90 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 22.6 Pull-Up and Pull-Down Resistor Requirements The PC8548E requires weak pull-up resistors (2-10 k is recommended) on open drain type pins including I2C pins and MPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 22-5 on page 94. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL/ TEST_SEL pins must be set to a proper state during POR configuration. Please refer to the pinlist table of the individual device for more details. Refer to the PCI 2.2 specification for all pull-ups required for PCI. 22.7 Output Buffer DC Impedance The PC8548E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 22-3). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 22-3. Driver Impedance Measurement OVDD RN SW2 Pad Data SW1 RP OGND 91 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table 22-1 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD, 105C. Table 22-1. Impedance Local Bus, Ethernet, DUART, Control, Configuration, Power Management PCI DDR DRAM Symbol Unit RN 43 Target 25 Target 20 Target Z0 W RP 43 Target 25 Target 20 Target Z0 W Note: 22.8 Impedance Characteristics Nominal supply voltages. See Table 3-1 on page 10, TC = 105C. Configuration Pin Muxing The PC8548E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k. This value should permit the 4.7 k resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices. 22.9 JTAG Configuration Signals Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, generally systems will assert TRST during the poweron reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function. The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. 92 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] The arrangement shown in Figure 22-5 on page 94 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 22-5 on page 94, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 22-5 is common to all known emulators. 22.9.1 Termination of Unused Signals If the JTAG interface and COP header will not be used, Freescale recommends the following connections: * TRST should be tied to HRESET through a 0 k isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 22-4. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. * No pull-up/pull-down is required for TDI, TMS, TDO, or TCK. Figure 22-4. COP Connector Physical Pinout COP_TDO 1 2 NC COP_TDI 3 4 COP_TRST COP_RUN/STOP 5 6 COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS 9 10 NC COP_SRESET 11 12 NC COP_HRESET 13 KEY No pin COP_CHKSTP_OUT 15 16 GND 93 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Figure 22-5. JTAG Interface Connection OVDD SRESET From Target Board Sources (if any) HRESET 10 k SRESET 10 k HRESET 6 1 COP_HRESET 13 10 k COP_SRESET 11 10 k B A 5 10 k 10 k TRST COP_TRST 2 3 4 5 6 7 8 9 10 11 12 13 KEY No pin 15 4 6 5 COP Header 1 15 COP_VDD_SENSE 2 10 NC COP_CHKSTP_OUT CKSTP_OUT 10 k 14 3 10 k COP_CHKSTP_IN CKSTP_IN 8 COP_TMS 16 9 COP Connector Pysical Pinout 1 1 TMS COP_TDO TDO COP_TDI 3 TDI COP_TCK 7 TCK 2 NC 10 NC 12 4 16 Note: 1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core. 94 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 22.10 Guidelines for High-Speed Interface Termination 22.10.1 SerDes Interface Entirely Unused If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. The following pins must be left unconnected (float): * SD_TX[7:0] * SD_TX[7:0] * Reserved pins T22, T23, M20, M21 The following pins must be connected to GND: * SD_RX[7:0] * SD_RX[7:0] * SD_REF_CLK * SD_REF_CLK Note: It is recommended to power down the unused lane through SERDESCR1[0:7] register (offset = 0xE_0F08) (This prevents the oscillations and holds the receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly. Pins V28 and M26 must be tied to XV DD. Pins V27 and M25 must be tied to GND through a 300 resistor. In Rev 2.0 silicon, POR configuration pin cfg_srds_en on TSEC4_TXD[2] /TSEC3_TXD[6] can be used to power down SerDes block. 22.10.2 SerDes Interface Partly Unused If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: * SD_TX[7:0] * SD_TX[7:0] * reserved pins: T22, T23, M20, M21 The following pins must be connected to GND if not used: * SD_RX[7:0] * SD_RX[7:0] * SD_REF_CLK * SD_REF_CLK Note: It is recommended to power down the unused lane through SERDESCR1[0:7] register (offset = 0xE_0F08) (This prevents the oscillations and holds the receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly. Pins V28 and M26 must be tied to XV DD. Pins V27 and M25 must be tied to GND through a 300 resistor. 95 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 22.11 Guideline for PCI Interface Temination PCI termination if PCI 1 or PCI 2 is not used at all. Option 1 If PCI arbiter is enabled during POR, * All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating. * All PCI control pins can be grouped together and tied to OVDD through a single 10 k resistor. * It is optional to disable PCI block through DEVDISR register after POR reset. Option 2 If PCI arbiter is disabled during POR, * All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied to OVDD through a single (or multiple) 10 k resistor(s) * All PCI control pins can be grouped together and tied to OVDD through a single 10K resistor * It is optional to disable PCI block through DEVDISR register after POR reset. 22.12 Guideline for LBIU Parity Temination In LBIU parity pins are not used. Here is the termination recommendation: For LDP[0:3]: tie them to ground or the power supply rail via a 4.7K resistor. For LPBSE: tie it to the power supply rail via a 4.7K resistor (pull-up resistor). 23. Definitions 23.1 Life Support Applications These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. 24. Ordering Information Figure 24-1. Ordering Information xx 8548 Product Part (1) Identifier Code (2) PC(X) Notes: 8548E y xx U Temperature Range (1) Package (1) Screening Level GH = HiTCE CBGA V: TC = -40C ; TJ = 110C LH = HiTCE LGA M: TC = -55C ; TJ = 125C GHY = ROHS BGA ZFU = PBGA upscreening xx Processor Frequency x x Platform Frequency Revision (1) Level AV = 1500 MHz (TBC) J = 533 MHz (TBC) Blank = 2.0 AU = 1333 MHz (TBC) G = 400 MHz A = version 2.1 AT = 1200 MHz AQ = 1000 MHz AN = 800 MHz 1. For availability of the different versions, contact your local e2v sales office. 2. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX partnumber is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes. 96 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 25. Document Revision History Table 25-1 provides a revision history for this hardware specification. Table 25-1. Revision Number Document Revision History Date Substantive Change(s) B 11/2007 * Adjusted maximum SYSCLK frequency down in Table 6, "SYSCLK AC Timing Specifications" per device eratum GEN-13 * Clarified notes to Table 5-2 on page 16 * Added Section 5.4 "PCI/PCI-X Reference Clock Timing" on page 16 * Clarified descriptions and added PCI/PCI-X to Table 6-2 * Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in Section 7. "DDR and DDR2 SDRAM" on page 18 * Clarified Note 4 of Table 7-9 on page 21 * Clarified the reference clock used in Section 8.2 "DUART AC Electrical Specifications" on page 23 * Corrected VIH(min) in Table 9-1 on page 24 * Corrected VIL(max) in Table 9-2 on page 25 * Removed DC parameters from Table 9-3 on page 26, Table 9-5 on page 27, Table 9-5 on page 27, Table 9-6 on page 28, Table 9-7 on page 29, Table 9-14 on page 35, Table 9-11 on page 33, Table 9-13 on page 34 and Table 9-14 on page 35 * Corrected VIH(min) in Table 10-1, "MII Management DC Electrical Characteristics," on page 36 * Corrected tMDC(min) in Table 10-2, "MII Management AC Timing Specifications (At Recommended Operating Conditions with OVDD is 3.3V 5%)," on page 37 * Updated parameter descriptions for tLBIVKH1, tLBIVKH2, tLBIXKH1, and tLBIXKH2 in Table 11-4, "Local Bus Timing Parameters (BVDD = 2.5V): PLL Enabled," on page 40 and Table 11-5, "Local Bus Timing Parameters: PLL Bypassed," on page 42 * Updated parameter descriptions for tLBIVKH1, tLBIVKL2, tLBIXKH1, and tLBIXKL2 in Table 11-5, "Local Bus Timing Parameters: PLL Bypassed," on page 42 Note that tLBIVKL2 and tLBIXKL2 were previously labeled tLBIVKH2 and tLBIXKH2 * Added LUPWAIT signal to Figure 11-2 on page 41 and Figure 11-4 on page 44. * Added LGTA signal to Figure 11-4, Figure 11-6, Figure 11-5 and Figure 11-7 * Corrected LUPWAIT assertion in Figure 11-5 and Figure 11-7 * Clarified the PCI reference clock in Section 15.2 "PCI/PCI-X AC Electrical Specifications" on page 53 * Updated Figure 16-1 on page 56 * Added Section 19.1 "Package Parameters" on page 73 * Added PBGA thermal information in Section 21.2 "Thermal for Version 2.1 Silicon FC-PBGA with Full Lid" on page 87 * Updated Section 21.3 "Heat Sink Solution" on page 88 A 08/2007 Initial revision 97 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] Table of Contents Features .................................................................................................... 1 Description ............................................................................................... 2 Screening ................................................................................................. 2 1 PC8548E Architecture General Overview .............................................. 2 2 Features Overview ................................................................................... 3 3 Electrical Characteristics ........................................................................ 9 3.1 Overall DC Electrical Characteristics ...................................................................... 9 3.2 Detailed Specification ........................................................................................... 10 3.3 Applicable Documents .......................................................................................... 10 3.3.1 Absolute Maximum Ratings ................................................................... 10 3.3.2 Recommended Operating Conditions ................................................... 11 3.3.3 Output Driver Characteristics ................................................................ 13 3.4 Power Sequencing ............................................................................................... 13 4 Power Characteristics ........................................................................... 14 5 Input Clocks ........................................................................................... 15 5.1 System Clock Timing ............................................................................................ 15 5.2 Real Time Clock Timing ....................................................................................... 15 5.3 eTSEC Gigabit Reference Clock Timing .............................................................. 16 5.4 PCI/PCI-X Reference Clock Timing ..................................................................... 16 5.5 Platform to FIFO restrictions ................................................................................ 17 5.6 Platform Frequency Requirements for PCI-Express and Serial RapidIO ............. 17 5.7 Other Input Clocks ................................................................................................ 17 6 RESET Initialization ............................................................................... 17 7 DDR and DDR2 SDRAM ......................................................................... 18 7.1 DDR SDRAM DC Electrical Characteristics ......................................................... 18 7.2 DDR SDRAM AC Electrical Characteristics ......................................................... 20 7.2.1 DDR SDRAM Input AC Timing Specifications ....................................... 20 7.2.2 DDR SDRAM Output AC Timing Specifications .................................... 21 8 DUART .................................................................................................... 23 8.1 DUART DC Electrical Characteristics .................................................................. 23 8.2 DUART AC Electrical Specifications .................................................................... 23 i 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management 24 9.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1Gb Mbps) - GMII/MII/TBI/ RGMII/RTBI/RMII Electrical Characteristics 24 9.1.1 eTSEC DC Electrical Characteristics ....................................................24 9.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications ............. 25 9.2.1 FIFO AC Specifications ......................................................................... 25 9.2.2 GMII AC Timing Specifications .............................................................. 27 9.2.2.1 GMII Transmit AC Timing Specifications ............................... 27 9.2.2.2 GMII Receive AC Timing Specifications ................................ 28 9.2.3 MII AC Timing Specifications ................................................................ 29 9.2.3.1 MII Receive AC Timing Specifications ................................... 29 9.2.3.2 MII Receive AC Timing Specifications ................................... 30 9.2.4 TBI AC Timing Specifications ............................................................... 31 9.2.4.1 TBI Transmit AC Timing Specifications ................................. 31 9.2.4.2 TBI Receive AC Timing Specifications .................................. 32 9.2.5 TBI Single-Clock Mode AC Specifications ............................................. 32 9.2.6 RGMII and RTBI AC Timing Specifications ........................................... 33 9.2.7 RMII AC Timing Specifications .............................................................. 34 9.2.7.1 RMII Transmit AC Timing Specifications ............................... 34 9.2.7.2 RMII Receive AC Timing Specifications ................................ 35 10 Ethernet Management Interface Electrical Characteristics ............... 36 10.1 MII Management DC Electrical Characteristics .................................................. 36 10.2 MII Management AC Electrical Specifications ....................................................37 11 Local Bus ................................................................................................ 38 11.1 Local Bus DC Electrical Characteristics ............................................................. 38 11.2 Local Bus AC Electrical Specifications ............................................................... 39 12 Programmable Interrupt Controller ...................................................... 47 13 JTAG ....................................................................................................... 48 13.1 JTAG DC Electrical Characteristics ..................................................................... 48 13.2 JTAG AC Electrical Specifications ...................................................................... 48 14 I2C ............................................................................................................ 50 14.1 I2C DC Electrical Characteristics ......................................................................... 50 14.2 I2C AC Electrical Specifications ........................................................................... 51 15 PCI/PCI-X ................................................................................................ 52 ii 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 15.1 PCI/PCI-X DC Electrical Characteristics ............................................................ 52 15.2 PCI/PCI-X AC Electrical Specifications .............................................................. 53 16 High-Speed Interfaces ........................................................................... 56 16.1 DC Requirements for SerDes Reference Clocks ............................................... 56 16.2 Spread Spectrum Clock ..................................................................................... 56 17 PCI Express ............................................................................................ 56 17.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK ............. 56 17.2 AC Requirements for PCI Express SerDes Clocks ............................................ 57 17.3 Clocking Dependencies ...................................................................................... 57 17.4 Physical Layer Specifications ............................................................................. 57 17.4.1 Differential Transmitter (TX) Output ....................................................57 17.4.2 Transmitter Compliance Eye Diagrams ............................................... 59 17.4.3 Differential Receiver (RX) Input Specifications .................................... 60 17.5 Receiver Compliance Eye Diagrams .................................................................. 62 17.5.1 Compliance Test and Measurement Load .......................................... 63 18 Serial RapidIO ........................................................................................ 63 18.1 DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK .......... 63 18.2 AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK .......... 64 18.3 Signal Definitions ................................................................................................ 64 18.4 Equalization ........................................................................................................ 65 18.5 Explanatory Note on Transmitter and Receiver Specifications .......................... 65 18.6 Transmitter Specifications .................................................................................. 65 18.7 Receiver Specifications ...................................................................................... 69 18.8 Receiver Eye Diagrams ...................................................................................... 71 18.9 Measurement and Test Requirements ............................................................... 72 18.9.1 Eye Template Measurements ............................................................. 72 18.9.2 Jitter Test Measurements .................................................................... 72 18.9.3 Transmit Jitter ...................................................................................... 72 18.9.4 Jitter Tolerance .................................................................................... 72 19 Package Description ............................................................................. 73 19.1 Package Parameters .......................................................................................... 73 19.1.1 Mechanical Dimensions of the HITCE ................................................. 74 19.2 Pinout Listings .................................................................................................... 75 20 Clocking .................................................................................................. 84 iii 0831B-HIREL-12/07 e2v semiconductors SAS 2007 PC8548E [Preliminary] 20.1 Clock Ranges ..................................................................................................... 84 20.2 CCB/SYSCLK PLL Ratio .................................................................................... 85 20.3 e500 Core PLL Ratio .......................................................................................... 86 20.4 Frequency Options ............................................................................................. 86 20.4.1 Sysclk to Platform Frequency Options ................................................ 86 21 Thermal ................................................................................................... 87 21.1 Thermal for Revision 2.0 Silicon HiCTE FC-CBGA with Full Lid ........................ 87 21.2 Thermal for Version 2.1 Silicon FC-PBGA with Full Lid ..................................... 87 21.3 Heat Sink Solution ..............................................................................................88 22 System Design Information .................................................................. 88 22.1 System Clocking ................................................................................................. 88 22.2 Power Supply Design ......................................................................................... 88 22.2.1 PLL Power Supply Filtering .................................................................88 22.3 Decoupling Recommendations .......................................................................... 90 22.4 SerDes Block Power Supply Decoupling Recommendations ............................ 90 22.5 Connection Recommendations .......................................................................... 90 22.6 Pull-Up and Pull-Down Resistor Requirements .................................................. 91 22.7 Output Buffer DC Impedance ............................................................................. 91 22.8 Configuration Pin Muxing ................................................................................... 92 22.9 JTAG Configuration Signals ............................................................................... 92 22.9.1 Termination of Unused Signals ........................................................... 93 22.10 Guidelines for High-Speed Interface Termination ............................................. 95 22.10.1 SerDes Interface Entirely Unused ..................................................... 95 22.10.2 SerDes Interface Partly Unused ........................................................ 95 22.11 Guideline for PCI Interface Temination ............................................................. 96 22.12 Guideline for LBIU Parity Temination ................................................................ 96 23 Definitions .............................................................................................. 96 23.1 Life Support Applications .................................................................................... 96 24 Ordering Information ............................................................................. 96 25 Document Revision History .................................................................. 97 Table of Contents ..................................................................................... i iv 0831B-HIREL-12/07 e2v semiconductors SAS 2007 How to reach us Home page: www.e2v.com Sales Office: Americas Northern Europe e2v inc. e2v ltd 4 Westchester Plaza 106 Waterhouse Lane Elmsford Chelmsford NY 10523-1482 Essex CM1 2QU USA England Tel: +1 (914) 592 6050 Tel: +44 (0)1245 493493 Fax:: +1 (914) 592-5148 Fax: +44 (0)1245 492492 E-Mail: enquiries-na@e2v.com E-Mail: enquiries@e2v.com Asia Pacific Southern Europe e2v ltd e2v sas 11/F, 16 Burospace Onfem Tower, F-91572 Bievres 29 Wyndham Street,Central, Cedex Hong Kong France Tel: +33 (0) 1 60 19 55 00 Fax:+33 (0) 1 60 19 55 29 Tel: +852 3679 364 8/9 Fax: +852 3583 1084 E-Mail: enquiries-ap@e2v.com E-Mail: enquiries-fr@e2v.com Product Contact: Germany and Austria e2v gmbh Industriestrae 29 82194 Grobenzell Germany Tel: +49 (0) 842 410 570 Fax:: +49 (0) 842 284 547 e2v Avenue de Rochepleine BP 123 - 38521 Saint-Egreve Cedex France Tel: +33 (0)4 76 58 30 00 Hotline: hotline-xxx@e2v.com E-Mail: enquiries-de@e2v.com Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa- e2v semiconductors SAS 2007 0831B-HIREL-12/07