IDT72235LB25PFB - Integrated Device Technology, Inc.

FEATURES:

• 256 x 18-bit organization array (72205LB)

• 512 x 18-bit organization array (72215LB)

• 1024 x 18-bit organization array (72225LB)

• 2048 x 18-bit organization array (72235LB)

• 4096 x 18-bit organization array (72245LB)

• 15 ns read/write cycle time

• Easily expandable in depth and width

• Read and write clocks can be asynchronous or coincident

• Dual-Port zero fall-through time architecture

• Programmable almost-empty and almost-full flags

• Empty and Full flags signal FIFO status

• Half-Full flag capability in a single device configuration

• Output enable puts output data bus in high-impedance

state

• High-performance submicron CMOS technology

• Available in a 64-lead thin quad flatpack (TQFP/STQFP),

pin grid array (PGA), and plastic leaded chip carrier

(PLCC)

• Military product compliant to MIL-STD-883, Class B

• Industrial temperature range (-40OC to +85OC) is avail-

able, tested to military electrical specifications

Integrated Device Technology, Inc.

IDT72205LB

IDT72215LB

IDT72225LB

IDT72235LB

IDT72245LB

CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x

18 and 4096 x 18

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc

MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996

1996 Integrated Device Technology, Inc. DSC-2766/7

DESCRIPTION:

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

are very high-speed, low-power First-In, First-Out (FIFO)

memories with clocked read and write controls. These FIFOs

are applicable for a wide variety of data buffering needs, such

as optical disk controllers, Local Area Networks (LANs), and

interprocessor communication.

Both FIFOs have 18-bit input and output ports. The input

port is controlled by a free-running clock (WCLK), and a data

input enable pin (

WEN

). Data is read into the synchronous

FIFO on every clock when

WEN

is asserted. The output port

is controlled by another clock pin (RCLK) and another enable

pin (

REN

). The read clock can be tied to the write clock for

single clock operation or the two clocks can run asynchronous

of one another for dual-clock operation. An Output Enable pin

(

) is provided on the read port for three-state control of the

output.

The synchronous FIFOs have two fixed flags, Empty (

)

and Full (

), and two programmable flags, Almost-Empty

(

PAE

) and Almost-Full (

PAF

). The offset loading of the pro-

grammable flags is controlled by a simple state machine, and

is initiated by asserting the Load pin (

). A Half-Full flag (

)

is available when the FIFO is used in a single device configu-

ration.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

are depth expandable using a daisy-chain technique. The XI

and

pins are used to expand the FIFOs. In depth expan-

sion configuration, FL is grounded on the first device and set

to HIGH for all other devices in the daisy chain.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB is

fabricated using IDT’s high-speed submicron CMOS technol-

ogy. Military grade product is manufactured in compliance

with the latest revision of MIL-STD-883, Class B.

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

256 x 18, 512 x 18

1024 x 18, 2048 x 18

4096 x 18

•

OFFSET REGISTER

FLAG

LOGIC

PAF

PAE

WXO

)

READ POINTER

READ CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

EXPANSION LOGIC

RESET LOGIC

WEN

WCLK D0-D17

(

WXO

WXI

REN

RCLK

Q0-Q17

RXO

RXI

2766 drw 01

FUNCTIONAL BLOCK DIAGRAM

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.16 1

5.16 2

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

Pin 1 Designator

ABCDEFGHJKL

FF WXI

VCC

VCCQ17

Q16Q15

REN

RCLK

D16

D17 D14

D15

D12

D13

D10

D11

VCC

D3D4

PAE

GND

WCLK

WEN

VCC

PAF

WXO

VCC

Q1Q2

RXO

Q6Q5

VCC

Q14 Q13

Q12

Q11

Q10 Q9

VCC

01 GND GND

GND

FLRXI

GND

G68-1

2766 drw 02

PGA

TOP VIEW

60 VCC

Q14

Q13

GND

Q12

Q11

VCC

Q10

GND

VCC

GND

D14

D13

D12

D11

D10

VCC

GND

98765432 6867666564636261

27 28 29 30 31 32 33 34 35 36 37 38 3940414243

2766 drw 03

J68-1

D15

D16

VCC

D17

GND

RCLK

REN

GND

VCC

Q17

Q16

GND

Q15

PAE

WCLK

WEN

WXI

VCC

PAF

RXI

WXO

RXO

GND

VCC

PLCC

TOP VIEW

5.16 3

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

PIN 1

GND

RCLK

REN

GND

Q14

Q13

GND

Q12

Q11

VCC

Q10

GND

VCC

D15

D14

D13

D12

D11

D10

PAE

WCLK

WEN

WXI

PAF

RXI

WXO

RXO

GND

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

2766 drw 04

PN 64-1

NOTE:

1. For information on the flatpack (F68-1), contact factory.

TQFP/STQFP

TOP VIEW

PP64-1

5.16 4

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O Description

D0–D17 Data Inputs I Data inputs for a 18-bit bus.

Reset I When

is set LOW, internal read and write pointers are set to the first location of the

RAM array,

and

PAF

go HIGH, and

PAE

and

go LOW. A reset is required before an

initial WRITE after power-up.

WCLK Write Clock I When

WEN

is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,

if the FIFO is not full.

WEN

Write Enable I When

WEN

is LOW, data is written into the FIFO on every LOW-to-HIGH transition of

WCLK. When

WEN

is HIGH, the FIFO holds the previous data. Data will not be written

into the FIFO if the

is LOW.

RCLK Read Clock I When

REN

is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if

the FIFO is not empty.

REN

Read Enable I When

REN

is LOW, data is read from the FIFO on every LOW-to-HIGH transition of

RCLK. When

REN

is HIGH, the output register holds the previous data. Data will not be

read from the FIFO if the

is LOW.

Output Enable I When

is LOW, the data output bus is active. If

is HIGH, the output data bus will

be in a high-impedance state.

Load I When

is LOW, data on the inputs D0–D11 is written to the offset and depth registers

on the LOW-to-HIGH transition of the WCLK, when

WEN

is LOW. When

is LOW,

data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-

HIGH transition of the RCLK, when

REN

is LOW.

First Load I In the single device or width expansion configuration,

is grounded. In the depth

expansion configuration,

is grounded on the first device (first load device) and set to

HIGH for all other devices in the daisy chain.

WXI

Write Expansion I In the single device or width expansion configuration,

WXI

is grounded. In the depth

Input expansion configuration,

WXI

is connected to

WXO

(Write Expansion Out) of the

previous device.

RXI

Read Expansion I In the single device or width expansion configuration, RXI is grounded. In the depth

Input expansion configuration,

RXI

is connected to

RXO

(Read Expansion Out) of the previous

device.

Empty Flag O When

is LOW, the FIFO is empty and further data reads from the output are inhibited.

When

is HIGH, the FIFO is not empty.

is synchronized to RCLK.

PAE

Programmable O When

PAE

is LOW, the FIFO is almost empty based on the offset programmed into the

Almost-Empty Flag FIFO. The default offset at reset is 31 from empty for 72205LB, 63 from empty for

72215LB, and 127 from empty for 72225LB/72235LB/72245LB.

PAF

Programmable O When

PAF

is LOW, the FIFO is almost full based on the offset programmed into the FIFO.

The default offset at reset is 31 from full for 72205LB, 63 from full for 72215LB, and

127 from full for 72225LB/72235LB/72245LB.

Full Flag O When

is LOW, the FIFO is full and further data writes into the input are inhibited.

When

is HIGH, the FIFO is not full.

is synchronized to WCLK.

WXO

Write Expansion O In the single device or width expansion configuration, the device is more than half full

Out/Half-Full Flag when

is LOW. In the depth expansion configuration, a pulse is sent from

WXO

WXI

of the next device when the last location in the FIFO is written.

RXO

Read Expansion O In the depth expansion configuration, a pulse is sent from

RXO

RXI

of the next device

Out when the last location in the FIFO is read.

Q0–Q17 Data Outputs O Data outputs for a 18-bit bus.

VCC Power Eight +5V power supply pins for the PLCC and PGA, five pins for the TQFP.

GND Ground Eight ground pins for the PLCC and PGA, seven pins for the TQFP. 2766 tbl 01

5.16 5

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Rating Commercial MIilitary Unit

VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with respect to GND

TAOperating 0 to +70 –55 to +125 °C

Temperature

TBIAS Temperature Under –55 to +125 –65 to +135 °C

Bias

TSTG Storage –55 to +125 –65 to +155 °C

Temperature

IOUT DC Output Current 50 50 mA

NOTE: 2766 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maimum rating conditions for extended

RECOMMENDED DC

OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCCM Military Supply 4.5 5.0 5.5 V

Voltage

VCCC Commercial Supply 4.5 5.0 5.5 V

Voltage

GND Supply Voltage 0 0 0 V

VIH Input High Voltage 2.0 — — V

Commercial

VIH Input High Voltage 2.2 — — V

Military

VIL(1) Input Low Voltage — — 0.8 V

Commercial & Military

NOTE: 2766 tbl 03

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

IDT72205LB IDT72205LB

IDT72215LB IDT72215LB

IDT72225LB IDT72225LB

Commercial Military

tCLK = 15, 20, 25, 35, 50ns tCLK = 25, 35, 50ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

ILI(1) Input Leakage Current (any input) –1 — 1 –10 — 10 µA

ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA

VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V

VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

ICC1(3) Active Power Supply Current — — 200 — — 250 mA

ICC2(3) Average Standby Current (All Input = VCC – 0.2V, — — 70 — — 85 mA

except RCLK and WCLK which are free-running)

IDT72235LB IDT72235LB

IDT72245LB IDT72245LB

Commercial Military

tCLK = 15, 20, 25, 35, 50ns tCLK = 25, 35, 50ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

ILI(1) Input Leakage Current (any input) –1 — 1 –10 — 10 µA

ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA

VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V

VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

ICC1(4) Active Power Supply Current — — 200 — — 250 mA

ICC2(4) Average Standby Current (All Input = VCC – 0.2V, — — 70 — — 85 mA

except RCLK and WCLK which are free-running)

NOTES: 2766 tbl 04

1. Measurements with 0.4 ≤ VIN ≤ VCC.

≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3 & 4. Tested at f = 20MHz with outputs unloaded.

(3) Typical Icc1 = 60 + (fCLK*0.57/MHz) + (fCLK*CL*0.02/MHz-pF) mA

(4 ) Typical Icc1 = 80 + (fCLK + 0.73/MHz) + (fCLK*CL*0.02/MHz-pF) mA

fCLK = 1/tCLK, CL = external capacitive load (30 pF typical)

5.16 6

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Commercial Commercial and Military

72205LB15 72205LB20 72205LB25 72205LB35 72205LB50

72215LB15 72215LB20 72215LB25 72215LB35 72215LB50

72225LB15 72225LB20 72225LB25 72225LB35 72225LB50

72235LB15 72235LB20 72235LB25 72235LB35 72235LB50

72245LB15 72245LB20 72245LB25 72245LB35 72245LB50

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

fSClock Cycle Frequency — 66.7 — 50 — 40 — 28.6 — 20 MHz

tAData Access Time 2 10 2 12 3 15 3 20 3 25 ns

tCLK Clock Cycle Time 15 — 20 — 25 — 35 — 50 — ns

tCLKH Clock HIGH Time 6.5 — 8 — 10 — 14 — 20 — ns

tCLKL Clock LOW Time 6.5 — 8 — 10 — 14 — 20 — ns

tDS Data Set-up Time 4 — 5 — 6 — 7 — 10 — ns

tDH Data Hold Time 1 — 1 — 1 — 2 — 2 — ns

tENS Enable Set-up Time 4 — 5 — 6 — 7 — 10 — ns

tENH Enable Hold Time 1 — 1 — 1 — 2 — 2 — ns

tRS Reset Pulse Width(1) 15 — 20 — 25 — 35 — 50 — ns

tRSS Reset Set-up Time 10 — 12 — 15 — 20 — 30 — ns

tRSR Reset Recovery Time 10 — 12 — 15 — 20 — 30 — ns

tRSF Reset to Flag and Output Time — 35 — 35 — 40 — 45 — 50 ns

tOLZ Output Enable to Output in Low-Z(2) 0—0—0— 0—0—ns

OE Output Enable to Output Valid — 8 — 9 — 12 — 15 — 20 ns

tOHZ Output Enable to Output in High-Z(2) 1 8 1 9 1 12 1 15 1 20 ns

tWFF Write Clock to Full Flag — 10 — 12 — 15 — 20 — 30 ns

tREF Read Clock to Empty Flag — 10 — 12 — 15 — 20 — 30 ns

tPAF Clock to Programmable — 28 — 30 — 35 — 40 — 40 ns

Almost-Full Flag

tPAE Clock to Programmable — 28 — 30 — 35 — 40 — 40 ns

Almost-Empty Flag

tHF Clock to Half-Full Flag — 28 — 30 — 35 — 40 — 40 ns

tXO Clock to Expansion Out — 10 — 12 — 15 — 20 — 30 ns

tXI Expansion In Pulse Width 6.5 — 8 — 10 — 14 — 20 — ns

tXIS Expansion In Set-Up Time 5 — 8 — 10 — 15 — 20 — ns

tSKEW1 Skew time between Read Clock & 10 — 14 — 16 — 18 — 20 — ns

Write Clock for Full Flag

tSKEW2 Skew time between Read Clock & 10 — 14 — 16 — 18 — 20 — ns

Write Clock for Empty Flag

NOTES: 2766 tbl 06

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

Symbol Parameter(1) Conditions Max. Unit

CIN(2) Input VIN = 0V 10 pF

Capacitance

COUT(1,2) Output VOUT = 0V 10 pF

Capacitance

CAPACITANCE (TA = +25°C, f = 1.0MHz)

NOTES: 2766 tbl 05

1. With output deselected, (

= HIGH).

2. Characterized values, not currently tested.

5.16 7

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 1

2766 tbl 07

Figure 1. Output Load

* Includes jig and scope capacitances.

30pF*

1.1K

680Ω

D.U.T.

2766 drw 05

The write and read clocks can be asynchronous or

coincident.

READ ENABLE (

REN

)

When Read Enable (

REN

) is LOW, data is loaded from the

RAM array to the output register on the LOW-to-HIGH transi-

tion of the read clock (RCLK).

When

REN

is HIGH, the output register holds the previous

data and no new data is loaded into the register.

When all the data has been read from the FIFO, the Empty

Flag (

) will go LOW, inhibiting further read operations. Once

a write is performed, the

will go HIGH after tREF and a read

can begin.

REN

is ignored when the FIFO is empty.

OUTPUT ENABLE (

)

When Output Enable (

) is enabled (LOW), the parallel

output buffers receive data from the output register. When

is disabled (HIGH), the Q output data bus is in a high-

impedance state.

LOAD (

)

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

devices contain two 12-bit offset registers with data on the

inputs, or read on the outputs. When the Load (

) pin is set

LOW and

WEN

is set LOW, data on the inputs D0-D11 is

written into the Empty offset register on the first LOW-to-HIGH

transition of the write clock (WCLK). When the

pin and

SIGNAL DESCRIPTIONS:

INPUTS:

DATA IN (D0 - D17)

Data inputs for 18-bit wide data.

CONTROLS:

RESET (

)

Reset is accomplished whenever the Reset (

) input is

taken to a LOW state. During reset, both internal read and

write pointers are set to the first location. A reset is required

after power-up before a write operation can take place. The

Full Flag (

), Half-Full Flag (

), and Programmable Almost-

Full Flag (

PAF

) will be reset to HIGH after tRSF. The Empty

Flag (

) and Programmable Almost-Empty Flag (

PAE

) will be

reset to LOW after tRSF. During reset, the output register is

initialized to all zeros and the offset registers are initialized to

their default values.

WRITE CLOCK (WCLK)

A write cycle is initiated on the LOW-to-HIGH transition of

the write clock (WCLK). Data set-up and hold times must be

met with respect to the LOW-to-HIGH transition of the write

clock (WCLK).

The write and read clocks can be asynchronous or

coincident.

WRITE ENABLE (

WEN

)

When Write Enable (

WEN

) is LOW, data can be loaded into

the input register and RAM array on the LOW-to-HIGH transi-

tion of every write clock (WCLK). Data is stored in the RAM

array sequentially and independently of any on-going read

operation.

When

WEN

is HIGH, the input register holds the previous

data and no new data is loaded into the FIFO.

To prevent data overflow, the Full Flag (

) will go LOW,

inhibiting further write operations. Upon the completion of a

valid read cycle, the

will go HIGH after tWFF allowing a write

to begin.

WEN

is ignored when the FIFO is full.

READ CLOCK (RCLK)

Data can be read on the outputs on the LOW-to-HIGH

transition of the read clock (RCLK), when Output Enable (

)

is set LOW.

LD WEN WCLK(1) Selection

0 0 Writing to offset registers:

Empty Offset

Full Offset

0 1 No Operation

1 0 Write Into FIFO

1 1 No Operation

NOTE: 2766 tbl 08

1. The same selection sequence applies to reading from the registers.

REN

is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Figure 2. Write Offset Register

5.16 8

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

(

WEN

) are held LOW then data is written into the Full offset

clock (WCLK). The third transition of the write clock (WCLK)

again writes to the Empty offset register.

However, writing all offset registers does not have to occur

at one time. One or two offset registers can be written and then

by bringing the

pin HIGH, the FIFO is returned to normal

read/write operation. When the LD pin is set LOW, and

WEN

is LOW, the next offset register in sequence is written.

When the

pin is LOW and

WEN

is HIGH, the WCLK input

is disabled; then a signal at this input can neither increment the

write offset register pointer, nor execute a write.

The contents of the offset registers can be read on the

output lines when the

pin is set LOW and

REN

is set LOW;

then, data can be read on the LOW-to-HIGH transition of the

read clock (RCLK). The act of reading the control registers

employs a dedicated read offset register pointer. (The read

and write pointers operate independently).

A read and a write should not be performed simultaneously

to the offset registers.First Load (FL)

First Load (

) is grounded to indicate operation in the

Single Device or Width Expansion mode. In the Depth Expan-

sion configuration,

is grounded to indicate it is the first

device loaded and is set to HIGH for all other devices in the

daisy chain. (See Operating Configurations for further de-

tails.)

WRITE EXPANSION INPUT (

WXI

)

This is a dual purpose pin. Write Expansion In (

WXI

) is

grounded to indicate operation in the Single Device or Width

Expansion mode.

WXI

is connected to Write Expansion Out

(

WXO

) of the previous device in the Depth Expansion or Daisy

Chain mode.

READ EXPANSION INPUT (RXI)

This is a dual purpose pin. Read Expansion In (

RXI

) is

grounded to indicate operation in the Single Device or Width

Expansion mode.

RXI

is connected to Read Expansion Out

(

RXO

) of the previous device in the Depth Expansion or Daisy

Chain mode.

NOTE: 2766 drw 06

1. Any bits of the offset register not being programmed should be set to zero.

EMPTY OFFSET REGISTER

17 11 0

001FH (72205) 003FH (72215):

007FH (72225/72235/72245)

FULL OFFSET REGISTER

17 11 0

001FH (72205) 003FH (72215):

007FH (72225/72235/72245)

DEFAULT VALUE

TABLE I — STATUS FLAGS

Number of Words in FIFO

72205 72215 72225 72235 72245

FF PAF

PAF HF

HF PAE

PAE EF

00 0 0 0HHHLL

1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HH H LH

(n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1024 (n + 1) to 2048 H H H H H

129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1024-(m+1)) 1025 to (2048-(m+1)) 2049 to (4096-(m+1)) H H L H H

(256-m)(2) to 255 (512-m)(2) to 511 (1024-m)(2) to 1023 (2048-m)(2) to 2047 (4096-m)(2) to 4095 H L L H H

256 512 1024 2048 4096 L L L H H

NOTES: 2766 tbl 09

1. n = Empty Offset (Default Values : 72205 n=31, 72215 n = 63, 72225/72235/72245 n = 127)

2. m = Full Offset (Default Values : 72205 n=31, 72215 n = 63, 72225/72235/72245 n = 127)

Figure 3. Offset Register Location and Default Values

EMPTY FLAG (EF)

The Empty Flag (

) will go LOW, inhibiting further read

operations, when the read pointer is equal to the write pointer,

indicating the device is empty.

The

is updated on the LOW-to-HIGH transition the read

clock (RCLK).

PROGRAMMABLE ALMOST-FULL FLAG (

PAF

)

The Programmable Almost-Full Flag (

PAF

) will go LOW

when FIFO reaches the Almost-Full condition. If no reads are

performed after Reset (

), the

PAF

will go LOW after (256-

OUTPUTS:

FULL FLAG (

)

The Full Flag (

) will go LOW, inhibiting further write

operation, indicating that the device is full. If no reads are

performed after Reset (

), the Full Flag (

) will go LOW

after 256 writes for the IDT72205LB, 512 writes for the

IDT72215LB, 1024 writes for the IDT72225LB, 2048 writes for

the IDT72235LB and 4096 writes for the IDT72245LB.

The Full Flag (

) is updated on the LOW-to-HIGH transi-

tion of the write clock (WCLK).

5.16 9

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

m) writes for the IDT72205LB, (512-m) writes for the

IDT72215LB, (1024-m) writes for the IDT72225LB, (2048–m)

writes for the IDT72235LB and (4096–m) writes for the

IDT72245LB. The offset “m” is defined in the FULL offset

If there is no Full offset specified, the

PAF

will be LOW when

the device is 31 away from completely full for 72205LB, 63

away from completely full for 72215LB, and 127 away from

completely full for 72225LB/72235LB/72245LB.

The

PAF

is asserted LOW on the LOW-to-HIGH transition

of the write clock (WCLK).

PAF

is reset to HIGH on the LOW-

to-HIGH transition of the read clock (RCLK). Thus

PAF

asychronous.

PROGRAMMABLE ALMOST-EMPTY FLAG (

PAE

)

The Programmable Almost-Empty Flag (

PAE

) will go LOW

when the read pointer is “n+1” locations less than the write

pointer. The offset “n” is defined in the EMPTY offset register.

If there is no Empty offset specified, the Programmable

Almost Empty Flag (

PAE

) will be LOW when the device is 31

away from completely empty for 72205LB, 63 away from

completely empty for 72215LB, and 127 away from com-

pletely empty for 72225LB/72235LB/72245LB.

The

PAE

is asserted LOW on the LOW-to-HIGH transition

of the read clock (RCLK).

PAE

is reset to HIGH on the LOW-

to-HIGH transition of the write clock (WCLK). Thus

PAF

asychronous.

WRITE EXPANSION OUT/HALF-FULL FLAG (

WXO

)

This is a dual-purpose output. In the Single Device and

Width Expansion mode, when Write Expansion In (

WXI

) is

grounded, this output acts as an indication of a half-full

memory.

After half of the memory is filled, and at the LOW-to-HIGH

transition of the next write cycle, the Half-Full Flag goes LOW

and will remain set until the difference between the write

pointer and read pointer is less than or equal to one half of the

total memory of the device. The Half-Full Flag (

) is then reset

to HIGH by the LOW-to-HIGH transition of the read clock

(RCLK). The

is asychronous.

In the Depth Expansion or Daisy Chain mode,

WXI

connected to

WXO

of the previous device. This output acts as

a signal to the next device in the Daisy Chain by providing a

pulse when the previous device writes to the last location of

memory.

READ EXPANSION OUT (

RXO

)

In the Depth Expansion or Daisy Chain configuration, Read

Expansion In (

RXI

) is connected to Read Expansion Out

(

RXO

) of the previous device. This output acts as a signal to

the next device in the Daisy Chain by providing a pulse when

the previous device reads from the last location of memory.

DATA OUTPUTS (Q0-Q17)

Q0-Q17 are data outputs for 18-bit wide data.

REN

WEN

PAE

PAF

RSF

RSR

Q0 - Q17

tRSF

= 0

= 1(1)

Figure 5. Reset Timing(2)

NOTES:

1. After reset, the outputs will be LOW if

= 0 and tri-state if

= 1.

2. The clocks (RCLK, WCLK) can be free-running during reset.

5.16 10

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

2766 drw 08

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

will go HIGH during the current clock cycle. If

the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then

may not change state until the next WCLK edge.

Figure 6. Write Cycle Timing

WCLK

D0 - D17

WEN

CLKH CLKL

CLK

DS DH

ENS ENH

WFF WFF

DATA IN VALID

NO OPERATION

RCLK

SKEW1(1)

REN

5.16 11

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

2766 drw 09

NO OPERATION

RCLK

REN

CLKH CLKL

CLK

ENS ENH

REF REF

VALID DATA

OLZ

OHZ

Q0 - Q17

WCLK

WEN

SKEW2(1)

Figure 7. Read Cycle Timing

NOTE:

1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that

will go HIGH during the current clock cycle. If the

time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then

may not change state until the next RCLK edge.

5.16 12

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

D0 - D17

WEN

RCLK

Q0 - Q17

REN

SKEW2

ENS

REF

012 3

DDD

(first valid write)

tOE

tOLZ

tFRL

(1)

2766 drw 10

Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write

NOTES:

1. When tSKEW2 ≥ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK +

tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (

= LOW).

2. The first word is available the cycle after

goes HIGH, always.

5.16 13

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA READ

WCLK

- D

WEN

RCLK

- Q

SKEW1

WFF

DATA WRITE

REN

WFF

ENH

ENS

WFF

ENH

ENS

DATA WRITE

NEXT DATA READ

SKEW1

NO WRITE NO WRITE

DATA IN OUTPUT REGISTER

LOW

(1)

2766 drw 11

Figure 9. Full Flag Timing

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

will go HIGH during the current clock cycle. If the

time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then

may not change state until the next WCLK edge.

5.16 14

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 10. Empty Flag Timing

NOTE:

1. When tSKEW2 ≥ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2.

or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (

= LOW).

WCLK

D0 - D17

WEN

RCLK

Q0 - Q17

tDS

tFRL

tENS

tSKEW2

DATA WRITE 1

DATA READ

tENH

tREF

tDS

tENS

DATA WRITE 2

tENH

tREF

REN

tFRL

DATA IN OUTPUT REGISTER

(1) (1)

LOW

tSKEW2

2766 drw 12

5.16 15

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

tCLKH tCLKL

tCLK

tENS tENH

tENS

WEN

D0–D15

tDS tDH

PAE OFFSET PAF OFFSET D0–D11

PAE OFFSET

RCLK

tCLKH tCLKL

tCLK

tENS tENH

tENS

REN

Q0–Q15 PAE OFFSET PAF OFFSET

PAE OFFSET

UNKNOWN

Figure 12. Read Programmable Registers

Figure 11. Write Programmable Registers

2766 drw 14

2766 drw 13

5.16 16

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

CLKH

CLKL

ENS

ENH

WEN

PAE

ENS

PAE

n + 1 words

in FIFO n words in FIFO

RCLK

PAE

REN

WCLK

tCLKH tCLKL

tENS tENH

WEN

PAF

tENS

tPAF Full – m words

in FIFO(2) Full – m + 1 words

in FIFO(3)

RCLK

tPAF

REN

(1)

2766 drw 15

2766 drw 16

NOTE:

1. PAE is offset = n. Number of data words written into FIFO already = n.

Figure 13. Programmable Almost Empty Flag Timing

Figure 14. Programmable Almost-Full Flag Timing

NOTES:

1. PAF offset = m. Number of data words written into FIFO already = 256 - m + 1 for the IDT72205B, 512 - m + 1 for the IDT72215B, 1024 - m + 1 for the

IDT72225B, 2048 – m + 1 for the IDT72235B and 4096 – m +1 for the IDT72245B.

2. 256 - m words in IDT72205B, 512 - m words in IDT72215B, 1024 - m words in IDT72225B, 2048 – m words in IDT72235B and 4096 – m words in IDT72245B.

3. 256 - m + 1 words in IDT72205B, 512 - m + 1 words in IDT72215B, 1024 - m + 1 words in IDT72225B, 2048 – m + 1 words in IDT72235B and 4096 – m

+ 1 words in IDT72245B.

5.16 17

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 15. Half-Full Flag Timing

WCLK

tCLKH tCLKL

tENS tENH

WEN

tENS

tHF Half Full + 1

or More Half Full or Less

RCLK

tHF

REN

Half Full or Less

WCLK

WEN

tENS

WXO

tCLKH

tXO

Note 1 tXO

RCLK

REN

tENS

RXO

tCLKH

tXO

Note 1 tXO

2766 drw 17

2766 drw 18

2766 drw 19

NOTE:

1. Read from Last Physical Location. Figure 17. Read Expansion Out Timing

Figure 16. Write Expansion Out Timing

NOTE:

1. Write to Last Physical Location.

5.16 18

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONFIGURATIONS

SINGLE DEVICE CONFIGURATION

A single IDT72205LB/72215LB/72225LB/72235LB/

72245LB may be used when the application requirements are

for 256/512/1024/2048/4096 words or less. The IDT72205LB/

Figure 20. Block Diagram of Single 256 x 18/512 x 18/1024 x 18/2048 x 18/4096 x 18 Synchronous FIFO

Figure 19. Read Expansion In Timing

WXI

WCLK

XIS

2766 drw 20

Figure 18. Write Expansion In Timing

RXI

RCLK

XIS

2766 drw 21

72215LB/72225LB/72235LB/72245LB are in a single Device

Configuration when the Write Exansion In (

WXI

), Read Ex-

pansion In (

RXI

), and First Load (

) control inputs are

grounded (Figure 20).

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN

)READ CLOCK (RCLK)

READ ENABLE (

REN

)

LOAD (

)OUTPUT ENABLE (

)

DATA IN (D0 - D17)DATA OUT (Q0 - Q17)

FULL FLAG (

)

PROGRAMMABLE (

PAE

)

HALF-FULL FLAG (

)

EMPTY FLAG (

)

PROGRAMMABLE (

PAF

)

READ EXPANSION IN (

RXI

)

RESET (

)

IDT

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

WRITE EXPANSION IN (

WXI

)

FIRST LOAD (

)

2766 drw 22

5.16 19

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting to-

gether the control signals of multiple devices. Status flags can

be detected from any one device. The exceptions are the

Empty Flag and Full Flag. Because of variations in skew

between RCLK and WCLK, it is possible for flag assertion and

deassertion to vary by one cycle between FIFOs. To avoid

DEPTH EXPANSION CONFIGURATION

(WITH PROGRAMMABLE FLAGS)

The IDT72205LB/72215LB/72225LB/72235LB/72245LB can

easily be adapted to applications requiring more than 256/

512/1024/2048/4096 words of buffering. Figure 22 shows

Depth Expansion using three IDT72205LB/72215LB/72225LB/

72235LB/72245LBs. Maximum depth is limited only by signal

loading. Follow these steps:

1. The first device must be designated by grounding the

First Load (

) control input.

2. All other devices must have

in the HIGH state.

3. The Write Expansion Out (

WXO

) pin of each device

must be tied to the Write Expansion In (

WXI

) pin of

the next device. See Figure 24.

4. The Read Expansion Out (

RXO

) pin of each device

must be tied to the Read Expansion In (

RXI

) pin of

the next device. See Figure 24.

5. All Load (

) pins are tied together.

6. The Half-Full Flag (

) is not available in the Depth

Expansion Configuration.

PAE

, and

PAF

are created with composite

flags by ORing together every respective flags for

monitoring. The composite

PAE

and

PAF

flags are not

precise.

NOTE:

1. Do not connect any output control signals directly together.

Figure 21. Block Diagram of 256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a

Width Expansion Configuration

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN

)

READ CLOCK (RCLK)

READ ENABLE (

REN

)

LOAD (

)OUTPUT ENABLE (

)

DATA IN (D)

DATA OUT (Q)

FULL FLAG (

)

PROGRAMMABLE (

PAE

)

HALF FULL FLAG (

)

EMPTY FLAG (

)

PROGRAMMABLE (

PAF

)

RESET (

)

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

RESET (

)

18 18

READ EXPANSION IN (

RXI

)

WRITE EXPANSION IN (

WXI

)

FIRST LOAD (

)

FF FF EFEF

2766 drw 23

problems the user must create composite flags by ANDing the

Empty Flags of every FIFO, and separately ANDing all Full

Flags. Figure 21 demonstrates a 36-word width by using two

IDT72205B/72215B/72225B/72235B/72245Bs. Any word

width can be attained by adding additional IDT72205B/72215B/

72225B/72235B/72245Bs. Please see the Application Note

AN-83.

5.16 20

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOAD

WRITE CLOCK

WRITE ENABLE

READ CLOCK

READ ENABLE

OUTPUT ENABLE

DATA IN DATA OUT

RESET

IDT

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

WXO

WXI

RXO

RXI

FIRST LOAD (

)

Vcc

WXO

WXI

RXO

RXI

WXO

WXI

RXO

RXI

IDT

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

IDT

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

PAF EF

PAE

PAF

PAE

PAF

PAE

PAF

2766 drw 24

•

••••

•

RCLK

REN

WCLK

WEN

•

RCLK

REN

WCLK

WEN

RCLK

REN

WCLK

WEN

Dn Qn

•

Figure 22. Block Diagram of 768 x 18/1536 x 18/3072 x 18/6144 x 18/12288 x 18 Synchronous FIFO Memory

With Programmable Flags used in Depth Expansion Configuration

5.16 21

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XXXXX

Device Type X

Power XX

Speed X

Package X

BLANK

15 Com'l Only

20 Com'l Only

72205

72215

72225

72235

72245

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

Plastic Leaded Chip Carrier

Pin Grid Array

Thin Plastic Quad Flatpack

Slim Thin Plastic Quad Flatpack

Low Power

256 x 18 Synchronous FIFO

512 x 18 Synchronous FIFO

1024 x 18 Synchronous FIFO

2048 x 18 Synchronous FIFO

4096 x 18 Synchronous FIFO

Clock Cycle Time (tCLK)

Speed in Nanoseconds

Process /

Temperature

Range

2766 drw 25