MPC9456FA - INTEGRATED DEVICE TECHNOLOGY

DATA SHEET

Clock Generator for PowerQUICC and PowerPC

Microprocessors and Microcontrollers

MPC9817

The MPC9817 is a PLL-based clock generator specifically designed for Freescale

Semiconductor Microprocessor and Microcontroller applications including the PowerPC and

PowerQUICC. This device generates the microprocessor input clock and other microprocessor

system and bus clocks at any one of four output frequencies. These frequencies include the

popular

33- and 66-MHz PCI bus frequencies. The device offers five low-skew clock outputs plus three

reference outputs. The clock input reference is 25 MHz and may be derived from an external

source or by the addition of a 25-MHz crystal to the on-chip crystal oscillator. The extended

temperature range of the MPC9817 supports telecommunication and networking requirements.

Features

• 5 LVCMOS Outputs for Processor and Other System Circuitry

• 3 Buffered 25-MHz Reference Clock Outputs

• Crystal Oscillator or External Reference Input

• 25-MHz Input Reference Frequency

• Selectable Output Frequencies Include: 25, 33, 50, or 66 MHz

• Low Cycle-to-Cycle and Period Jitter

• Package: 20-Lead SSOP

• 3.3-V Supply

• Supports Computing, Networking, and Telecommunications Applications

• Ambient Temperature Range: –40°C to +85°C

Functional Description

The MPC9817 uses a PLL with a 25-MHz input reference frequency to generate a single

bank of five configurable LVCMOS output clocks. The output frequency of this bank is

configurable to either 25, 33, 50, or 66 MHz by two FSEL pins. The 25-MHz reference may be either an external frequency source or a 25-MHz

crystal. The 25-MHz crystal is directly connected to the XTAL_IN and XTAL_OUT pins with no additional components required. An external

reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an

external input, is also directly buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for

processor I/O applications such as an Ethernet PHY. When FSEL0 and FSEL1 are both configured low, the QA outputs are directly fed from

the input reference providing a total of eight low-skew 25-MHz outputs. For all other combinations of FSEL0 and FSEL1 the single-ended

LVCMOS outputs provide five low-skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system

components.

The MPC9817 is packaged in a 20-lead SSOP package.

MICROPROCESSOR

CLOCK GENERATOR

EN SUFFIX

20 SSOP PACKAGE

Pb-FREE PACKAGE

CASE 1461-01

SD SUFFIX

20 SSOP PACKAGE

CASE 1461-01

MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

Figure 1. MPC9817 Logic Diagram

Table 1. Pin Configurations

Pin I/O Type Function

QA0, QA1, QA2, QA3, QA4 Output LVCMOS Clock Outputs

QREF0, QREF1, QREF2 Output LVCMOS Reference Output (25 MHz)

XTAL_IN Input LVCMOS Crystal Oscillator Input Pin

XTAL_OUT Output LVCMOS Crystal Oscillator Output Pin

FSEL0, FSEL1 Input LVCMOS Configures Bank A Clock Output Frequency (pull-up)

MR/OE Input LVCMOS Enables All Outputs (pull-down)

VDD — — 3.3-V Supply

GND — — Ground

Table 2. Function Table

Control Default 00 01 10 11

FSEL0,FSEL1 11 25 MHz fed directly

from reference input,

PLL disabled

33 MHz 50 MHz 66 MHz

Ref

PLL

400 MHz

QA0

QA1

QA2

QA4

XTAL_IN

OSC

XTAL_OUT

FSEL0

QREF0

FSEL1

QA3

QREF1

QREF2

Data

Generator

MR/OE

33,50,66 MHz

25 MHz

MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

Figure 2. MPC9817 20-Lead SSOP Package Pinout (Top View)

MPC9817 OPERATION

Crystal Oscillator

The MPC9817 features a fully integrated Pierce oscillator

to minimize system implementation costs. Other than the

addition of a 25-MHz crystal, no external components are

required.The crystal selection should be: 25 MHz, parallel

resonant type with a load specification of CL = 10 pF. Crystals

with a load specification of CL = 20 pF may be used, however,

the reference frequency may be higher than the specified

25 MHz. Externally supplied capacitors on both the XTAL_IN

and XTAL_OUT pins may be used to trim the frequency as

desired.

The crystal should be located as close to the MPC9817

XTAL_IN and XTAL_OUT pins as possible to avoid any board

level parasitic.

Power Supply Bypassing

The MPC9817 should have all VDD pins bypassed with

0.01 capacitors and a minimum of one 1.0 capacitor for the

overall package. All capacitors should be located as close to

the SSOP pins as possible.

External Clock Source

An external reference source of 25 MHz may be applied to

the XTAL_IN pin. In this mode of operation, the XTAL_OUT

pin should be left floating.

XTAL_IN

XTAL_OUT

FSEL0

VDD

FSEL1

QREF2

GND

QREF1

QREF0

VDD

QA4

QA3

GND

QA2

QA1

VDD

QA0

MR/OE

GND

Table 3. Crystal Specifications

Parameter Value

Crystal Cut Fundamental AT Cut

Resonance Parallel Resonance

Shunt Capacitance (CL) 5–7 pF

Load Capacitance (CO) 10 pF

Equivalent Series Resistance (ESR) 20–60 Ω

MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

Table 4. Absolute Maximum Ratings(1)

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

Symbol Characteristics Min Max Unit

VDD Supply Voltage –0.3 3.8 V

IIN DC Input Current —±20 mA

IOUT DC Output Current —±75 mA

TSStorage Temperature –65 125 °C

Table 5. General Specifications

Symbol Characteristics Min Typ Max Unit Condition

VTT Output Termination Voltage — VDD ÷ 2 — V —

MM ESD Protection (machine model) 200 — — V —

HBM ESD Protection (human body model) 2000 — — V —

LU Latch-Up Immunity 200 — — mA —

CIN Input Capacitance — 4 — pF Inputs

θJA Thermal Resistance (junction-to-ambient) —80.8 —°C/W —

TCAmbient Temperature –40 85 °C —

Table 6. DC Characteristics (VDD = 3.3 V ± 5%, TA = –40° to +85°C)

Symbol Characteristics Min Typ Max Unit Condition

VIH Input High Voltage (XTAL_IN) 2.4 — VDD + 0.3 VInput threshold = VDD/2

VIH Input High Voltage 2.0 — VDD + 0.3 V —

VIL Input Low Voltage — — 0.8 VLVCMOS

IIN Input Current(1)

1. Inputs have pull-down resistors affecting the input current.

— — 150 µA VIN = VDDL or GND

VOH Output High Voltage 2.4 — — V IOH = –12 mA

VOL Output Low Voltage — — 0.4 V IOL = 12 mA

ZOUT Output Impedance —14 —Ω—

IDD Maximum Quiescent Supply Current —8.0 15.0 mA VDD pins

MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs)

Table 7. AC Characteristics(1) (2) (VDD = 3.3 V ± 5%, TA = –40° to +85°C)

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50 Ω to VTT.

Symbol Characteristics Min Typ Max Unit Condition

Input and Output Timing Specification

fref Input Reference Frequency 25 MHz Input

X TA L I np ut

—25

—MHz

MHz

—

fVCO VCO Frequency Range —400 —MHz —

fMCX Output Frequency (QAx)FSEL0, FSEL1 = 00

FSEL0, FSEL1 = 01

FSEL0, FSEL1 = 10

FSEL0, FSEL1 = 11

Output Frequency (QREFx)

—25

—MHz

MHz

PLL locked

frefPW Reference Input Pulse Width 10 — — ns @ 25 MHz

DC Output Duty Cycle 47.5 50 52.5 % —

fout Output Frequency Accuracy Crystal(3)

External Reference

3. Based upon recommended crystal specifications as outlined in MPC9817 Operation.

— — 100

ppm

With recommended

crystal

see Table 3

PLL Specifications

BW PLL Closed Loop Bandwidth(4)

4. –3 dB point of PLL transfer characteristics.

—500 —kHz —

tLOCK Maximum PLL Lock Time — — 10 ms —

Skew and Jitter Specifications

tsk(O) Output-to-Output Skew (within a bank) — — 100 ps —

tsk(O) Output-to-Output Skew (between bank A and bank

Ref)

— — 200 —FSEL0, FSEL1 = 00

tJIT(CC) Cycle-to-Cycle Jitter — — 150 ps @ 25 MHz Input

Reference QA output

tJIT(PER) Period Jitter — — 100 ps @ 25 MHz Input

Reference QA output

tr, tfOutput Rise/Fall Time — — 1 ns 20% to 80%

Z = 50 Ω

RT = 50 Ω

VTT

Z = 50 Ω

VTT

DUT MPC9817

Pulse

Generator

Z = 50 Ω

RT = 50 Ω

MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

Table 8. MPC9817 Pin List

Pin Description Pin Description

1XTAL_IN 11 GND

2XTAL_OUT 12 MR/OE

3FSEL0 13 QA0

4 VDD 14 VDD

5FSEL1 15 QA1

6QREF2 16 QA2

7GND 17 GND

8QREF1 18 QA3

9QREF0 19 QA4

10 VDD 20 VDD

PACKAGE DIMENSIONS

.337

.150

10 11

PIN 1 ID

.157

.344

.236

.118

.010 C A-B D

2X 10 TIPS

.003 H A-B D

.035

SECTION B-B

R.003 MIN

.0098

.0040

.016

0˚

8˚

0˚

.010

GAUGE PLANE

MIN

.004 C

.055

SEATING

PLANE

.025

20X

18X

.061

.0125

(.010)

.012

.010 (.008)

PLATING

BASE METAL

SECTION A-A

.007

.008

.007 C A-B D

NOTES:

DIMENSIONS ARE IN INCHES.

DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

DATUM PLANE H LOCATED AT MOLD PARTING

LINE AND COINCIDENT WITH LEAD, WHERE

LEAD EXITS PLASTIC BODY AT BOTTOM OF

PARTING LINE.

DATUM A, B AND D TO BE DETRMINED WHERE

CENTERLINE BETWEEN LEADS EXITS PLASTIC

BODY AT DATUM PLANE H.

THIS DIMENSION DOES NOT INCLUDE MOLD

FLASH OR PROTRUSIONS, BUT DO INCLUDE

MOLD MISMATCH AND ARE MEASURED AT THE

MOLD PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED .006

INCHES FOR ENDS AND .008 INCHES FOR

SIDES.

THIS DIMENSION IS LENGTH OF TERMINAL FOR

SOLDERING A SUBSTRATE.

FORMED LEADS SHALL BE PLANAR WITH

RESPECT TO ONE ANOTHER WITHIN .004

INCHES AT SEATING PLANE.

THIS DIMENSION IS DEFINED AS THE DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT OF THE PACKAGE BODY.

CASE 1461-02

ISSUE O

20 SSOP PACKAGE

MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

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