PCF8562TT/S400/2,5 - NXP Semiconductors / Philips Semiconductors

1. General description

The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD) with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562

is compatible with most microprocessors or microcontrollers and communicates via a

two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM

with auto-incremented addressing, by hardware subaddressing and by display memory

switching (static and duplex drive modes).

AEC-Q100 compliant (PCF8562TT/S400) for automotive applications.

2. Features

nSingle chip LCD controller and driver

nSelectable backplane drive conﬁguration: static or 2, 3, 4 backplane multiplexing

nSelectable display bias conﬁguration: static, 1⁄2 or 1⁄3

nInternal LCD bias generation with voltage-follower buffers

n32 segment drives:

uUp to sixteen 7-segment numeric characters

uUp to eight 14-segment alphanumeric characters

uAny graphics of up to 128 elements

n32 × 4-bit RAM for display data storage

nAuto-incremented display data loading across device subaddress boundaries

nDisplay memory bank switching in static and duplex drive modes

nVersatile blinking modes

nIndependent supplies possible for LCD and logic voltages

nWide power supply range: from 1.8 V to 5.5 V

nWide logic LCD supply range:

uFrom 2.5 V for low-threshold LCDs

uUp to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs

nLow power consumption

n400 kHz I2C-bus interface

nNo external components

nManufactured in silicon gate CMOS process

PCF8562

Universal LCD driver for low multiplex rates

Rev. 04 — 18 March 2009 Product data sheet

Product data sheet Rev. 04 — 18 March 2009 2 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

3. Ordering information

4. Marking

Table 1. Ordering information

Type number Package

Name Description Version

PCF8562TT/2 TSSOP48 plastic thin shrink small outline package; 48 leads;

body width 6.1 mm SOT362-1

PCF8562TT/S400/2 TSSOP48 plastic thin shrink small outline package; 48 leads;

body width 6.1 mm SOT362-1

Table 2. Marking codes

Type number Marking code

PCF8562TT/2 PCF8562TT

PCF8562TT/S400/2 PCF8562TT

Product data sheet Rev. 04 — 18 March 2009 3 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

5. Block diagram

Fig 1. Block diagram of PCF8562

001aac262

LCD

VOLTAGE

SELECTOR

CLOCK SELECT

AND TIMING BLINKER

TIMEBASE

OSCILLATOR

INPUT

FILTERS I2C-BUS

CONTROLLER

POWER-ON

RESET

CLK

SYNC

OSC

SCL

SDA

SA0

BACKPLANE

OUTPUTS

DISPLAY

CONTROLLER

BP0

VDD 14

19 16 17 18

23 24 25

BP2 BP1 BP3

DISPLAY SEGMENT OUTPUTS

DISPLAY REGISTER

OUTPUT BANK SELECT

AND BLINK CONTROL

26 to 48,

1 to 9

S0 to S31

A0 A1 A2

PCF8562

LCD BIAS

GENERATOR

VSS

VLCD

COMMAND

DECODER WRITE DATA

CONTROL

DISPLAY

RAM

40 × 4-BIT

DATA POINTER AND

AUTO INCREMENT

SUBADDRESS

COUNTER

Product data sheet Rev. 04 — 18 March 2009 4 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

Top view. For mechanical details, see Figure 20.

Fig 2. Pinning diagram for PCF8562

PCF8562TT

S23 S22

S24 S21

S25 S20

S26 S19

S27 S18

S28 S17

S29 S16

S30 S15

S31 S14

SDA S13

SCL S12

SYNC S11

CLK S10

VDD S9

OSC S8

A0 S7

A1 S6

A2 S5

SA0 S4

VSS S3

VLCD S2

BP0 S1

BP2 S0

BP1 BP3

001aac263

Product data sheet Rev. 04 — 18 March 2009 5 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

6.2 Pin description

7. Functional description

The PCF8562 is a versatile peripheral device designed to interface any

microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any

static or multiplexed LCD containing up to four backplanes and up to 32 segments.

The possible display conﬁgurations of the PCF8562 depend on the number of active

backplane outputs required. A selection of display conﬁgurations is shown in Table 4. All

of these conﬁgurations can be implemented in the typical system shown in Figure 3.

Table 3. Pin description

Symbol Pin Description

SDA 10 I2C-bus serial data input and output

SCL 11 I2C-bus serial clock input

SYNC 12 cascade synchronization input or output

CLK 13 external clock input or output

VDD 14 supply voltage

OSC 15 internal oscillator enable input

A0 to A2 16 to 18 subaddress inputs

SA0 19 I2C-bus address input; bit 0

VSS 20 ground supply voltage

VLCD 21 LCD supply voltage

BP0 to BP3 22 to 25 LCD backplane outputs

S0 to S22,

S23 to S31 26 to 48,

1 to 9 LCD segment outputs

Table 4. Display conﬁgurations

Number of: 7-segment numeric 14-segment numeric Dot matrix

Backplanes Segments Digits Indicator

symbols Characters Indicator

symbols

4 128 16 16 8 16 128 dots (4 × 32)

3 96 12 12 6 12 96 dots (3 × 32)

2 64 8 8 4 8 64 dots (2 × 32)

1 32 4 4 2 4 32 dots (1 × 32)

Product data sheet Rev. 04 — 18 March 2009 6 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

The host microprocessor or microcontroller maintains the 2-line I2C-bus communication

channel with the PCF8562. The internal oscillator is enabled by connecting

pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms

are generated internally. The only other connections required to complete the system are

to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.

7.1 Power-on reset

At power-on the PCF8562 resets to the following starting conditions:

•All backplane outputs are set to VLCD

•All segment outputs are set to VLCD

•The selected drive mode is: 1:4 multiplex with 1⁄3bias

•Blinking is switched off

•Input and output bank selectors are reset

•The I2C-bus interface is initialized

•The data pointer and the subaddress counter are cleared (set to logic 0)

•Display is disabled

Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the

reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between VLCD and VSS. The middle resistor can be

bypassed to provide a 1⁄2bias voltage level for the 1:2 multiplex conﬁguration. The LCD

voltage can be temperature compensated externally using the supply to pin VLCD.

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive conﬁguration. The operation of the voltage selector is controlled by the

mode-set command (see Section 7.17) from the command decoder. The biasing

The resistance of the power lines must be kept to a minimum.

Fig 3. Typical system conﬁguration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

2Cb

SDA

SCL

OSC

32 segment drives

4 backplanes

LCD PANEL

(up to 128

elements)

PCF8562

10 14 21

17 18 19 20

A1 A2 SA0

VDD

VSS

VDD VLCD

001aac264

R ≤

Product data sheet Rev. 04 — 18 March 2009 7 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

conﬁgurations that apply to the preferred modes of operation, together with the biasing

characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in

Table 5.

A practical value for VLCD is determined by equating Voff(RMS) with a deﬁned LCD

threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is VLCD >3V

th.

Multiplex drive modes of 1:3 and 1:4 with 1⁄2bias are possible but the discrimination and

hence the contrast ratios are smaller.

Bias is calculated by , where the values for a are

a = 1 for 1⁄2 bias

a = 2 for 1⁄3 bias

The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation

(1)

where VLCD is the resultant voltage at the LCD segment and where the values for n are

n = 1 for static mode

n = 2 for 1:2 multiplex

n = 3 for 1:3 multiplex

n = 4 for 1:4 multiplex

The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation:

(2)

Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:

(3)

Table 5. Discrimination ratios

LCD drive

mode Number of: LCD bias

conﬁguration

Backplanes Levels

static 1 2 static 0 1 ∞

1:2 multiplex 2 3 1⁄20.354 0.791 2.236

1:2 multiplex 2 4 1⁄30.333 0.745 2.236

1:3 multiplex 3 4 1⁄30.333 0.638 1.915

1:4 multiplex 4 4 1⁄30.333 0.577 1.732

off

RMS

()

LCD

--------------------------

RMS

()

LCD

-------------------------

RMS

()

off

RMS

()

--------------------------=

-------------

Von RMS()

---n

–()

-------------





------------------------------------------------------------

LCD

Voff RMS()

n+()–

+()

---------------------------------

LCD

on RMS()

off RMS()

------------------------

+()

–()+

–()

–()+

--------------------------------------------=

Product data sheet Rev. 04 — 18 March 2009 8 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

1⁄2bias is and the discrimination for an LCD drive mode of 1:4 multiplex with

1⁄2bias is .

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD

as follows:

•1:3 multiplex (1⁄2 bias):

•1:4 multiplex (1⁄2 bias):

These compare with when 1⁄3 bias is used.

It should be noted that VLCD is sometimes referred as the LCD operating voltage.

3 1.732

----------

1.528

LCD

off

RMS

()

2.449V

off

RMS

(

)

LCD

×()

----------------------

2.309V

off

RMS

()

LCD

off

RMS

()

Product data sheet Rev. 04 — 18 March 2009 9 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 4.

(1) Vstate1(t) = VSn(t) − VBP0(t).

(2) Von(RMS) = VLCD.

(3) Vstate2(t) = VSn+1(t) − VBP0(t).

(4) Voff(RMS) = 0 V.

Fig 4. Static drive mode waveforms

mgl745

VSS

VLCD

VSS

VLCD

VSS

VLCD

−VLCD

VLCD

state 1 0 V

BP0

Sn+1

state 2 0 V

(a) Waveforms at driver.

(b) Resultant waveforms

at LCD segment.

LCD segments

state 1

(on) state 2

(off)

Tfr

Product data sheet Rev. 04 — 18 March 2009 10 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This

mode allows fractional LCD bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figure 5 and

Figure 6.

(1) Vstate1(t) = VSn(t) − VBP0(t).

(2) Von(RMS) = 0.791VLCD.

(3) Vstate2(t) = VSn+1(t) − VBP1(t).

(4) Voff(RMS) = 0.354VLCD.

Fig 5. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias

mgl746

state 1

BP0

(a) Waveforms at driver.

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 2

state 1

VSS

VLCD

VLCD / 2

VSS

VLCD

VSS

VLCD

0 V

VLCD / 2

−VLCD

−VLCD / 2

Sn+1

Tfr

Product data sheet Rev. 04 — 18 March 2009 11 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

(1) Vstate1(t) = VSn(t) − VBP0(t).

(2) Von(RMS) = 0.745VLCD.

(3) Vstate2(t) = VSn+1(t) − VBP1(t).

(4) Voff(RMS) = 0.333VLCD.

Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias

mgl747

state 1

BP0

(a) Waveforms at driver.

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 1

state 2

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

Sn+1

Tfr

VSS

VLCD

2VLCD / 3

VLCD / 3

Product data sheet Rev. 04 — 18 March 2009 12 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies

(see Figure 7).

(1) Vstate1(t) = VSn(t) − VBP0(t).

(2) Von(RMS) = 0.638VLCD.

(3) Vstate2(t) = VSn+1(t) − VBP1(t).

(4) Voff(RMS) = 0.333VLCD.

Fig 7. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias

mgl748

state 1

BP0

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 1

state 2

(a) Waveforms at driver.

BP2

Sn+1

Sn+2

Tfr

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

VSS

VLCD

2VLCD / 3

VLCD / 3

Product data sheet Rev. 04 — 18 March 2009 13 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.4.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see

Figure 8).

(1) Vstate1(t) = VSn(t) − VBP0(t).

(2) Von(RMS) = 0.577VLCD.

(3) Vstate2(t) = VSn+1(t) − VBP1(t).

(4) Voff(RMS) = 0.333VLCD.

Fig 8. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias

mgl749

state 1

BP0

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 1

state 2

BP2

(a) Waveforms at driver.

BP3

Sn+1

Sn+2

Sn+3

Tfr

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

VSS

VLCD

2VLCD / 3

VLCD / 3

Product data sheet Rev. 04 — 18 March 2009 14 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.5 Oscillator

7.5.1 Internal clock

The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal

oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC

to pin VSS. After power-on, pin SDA must be HIGH to guarantee that the clock starts.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.

The LCD frame signal frequency is determined by the clock frequency (fclk).

A clock signal must always be supplied to the device; removing the clock freezes the LCD

in a DC state.

7.6 Timing

The PCF8562 timing controls the internal data ﬂow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. The timing

also generates the LCD frame signal whose frequency is derived from the clock

frequency. The frame signal frequency is a ﬁxed division of the clock frequency from either

the internal or an external clock: .

7.7 Display register

The display latch holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs and each column of the display RAM.

7.8 Segment outputs

The LCD drive section includes 32 segment outputs S0 to S31 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display latch. When

less than 32 segment outputs are required, the unused segment outputs should be left

open-circuit.

7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals

and may also be paired to increase the drive capabilities.

In the static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

ffr

clk

--------

Product data sheet Rev. 04 — 18 March 2009 15 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.10 Display RAM

The display RAM is a static 32 × 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the individual bits of a RAM word and

the backplane outputs. The display RAM bit map Figure 9 shows the rows 0 to 3 which

correspond with the backplane outputs BP0 to BP3, and the columns 0 to 31 which

correspond with the segment outputs S0 to S31. In multiplexed LCD applications the

segment data of the ﬁrst, second, third and fourth row of the display RAM are

time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8562, the display bytes received are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for an acknowledge cycle as with the commands. Depending on

the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets.

To illustrate the ﬁlling order, an example of a 7-segment numeric display showing all drive

modes is given in Figure 10; the RAM ﬁlling organization depicted applies equally to other

LCD types.

The following applies to Figure 10:

•In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

•In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

•In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to

three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difﬁcult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

•In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2 and 3 of two successive 4-bit RAM words.

Display RAM bit map showing direct relationship between RAM addresses and segment outputs;

also between bits in a RAM word and the backplane outputs.

Fig 9. Display RAM bit map

1234 2728293031

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

001aac265

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 04 — 18 March 2009 16 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

x = data bit unchanged.

Fig 10. Relationship between LCD layout, drive mode, display RAM ﬁlling order and display data transmitted over the I2C-bus

001aaj646

acbDPfegd

MSB LSB

bDPcadgfe

MSB LSB

abfgecdDP

MSB LSB

cbafgedDP

MSB LSB

drive mode

static

1:2

multiplex

1:3

multiplex

1:4

multiplex

LCD segments LCD backplanes display RAM filling order transmitted display byte

BP0

BP1

BP0

BP1 BP2

BP1

BP2

BP3

BP0

n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7

display RAM

bits (rows)/

backplane

outputs (BP)

byte1

display RAM addresses (columns)/segment outputs (S)

n + 1 n + 2 n + 3

byte1 byte2

display RAM

bits (rows)/

backplane

outputs (BP)

display RAM addresses (columns)/segment outputs (S)

n + 1 n + 2

byte1 byte2 byte3

display RAM

bits (rows)/

backplane

outputs (BP)

display RAM addresses (columns)/segment outputs (S)

n + 1

byte1 byte2 byte3 byte4 byte5

display RAM

bits (rows)/

backplane

outputs (BP)

display RAM addresses (columns)/segment outputs (S)

Sn+2

Sn+3

Sn+1

Sn+2

Sn+1

Sn+7

Sn+3

Sn+5

Sn+6

Sn+4

Sn+1

Sn+2

Sn+1

Product data sheet Rev. 04 — 18 March 2009 17 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer.

This allows the loading of an individual display data byte, or a series of display data bytes,

into any location of the display RAM. The sequence commences with the initialization of

the data pointer by the load-data-pointer command (see Section 7.17).

Following this command, an arriving data byte is stored at the display RAM address

indicated by the data pointer. The ﬁlling order shown in Figure 10.

After each byte is stored, the contents of the data pointer is automatically incremented by

a value dependent on the selected LCD drive mode:

•In static drive mode by eight

•In 1:2 multiplex drive mode by four

•In 1:3 multiplex drive mode by three

•In 1:4 multiplex drive mode by two

If an I2C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer should be re-written prior to further RAM accesses.

7.12 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter agree

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device-select command (see Section 7.17). If the contents of the

subaddress counter and the hardware subaddress do not agree then data storage is

inhibited but the data pointer is incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overﬂows.

The hardware subaddress must not be changed while the device is being accessed on the

I2C-bus interface.

7.13 Output bank selector

The output bank selector selects one of the four rows per display RAM address for

transfer to the display register. The actual row selected depends on the particular LCD

drive mode in operation and on the instant in the multiplex sequence.

•In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, row 2 and then row 3.

•In 1:3 multiplex mode, row 0, 1 and 2 are selected sequentially

•In 1:2 multiplex mode, row 0 and 1 are selected

•In static mode, row 0 is selected

The PCF8562 includes a RAM bank switching feature in the static and 1:2 drive modes. In

the static drive mode, the bank-select command (see Section 7.17) may request the

contents of row 2 to be selected for display instead of the contents of row 0. In 1:2 mode,

the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

Product data sheet Rev. 04 — 18 March 2009 18 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.14 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive conﬁguration.

The bank-select command (see Section 7.17) can be used to load display data in row 2 in

static drive mode or in rows 2 and 3 in 1:2 mode. The input bank selector functions are

independent of the output bank selector.

7.15 Blinker

The PCF8562 has a very versatile display blinking capability. The whole display can blink

at a frequency selected by the blink-select command (see Table 13). Each blink frequency

is a fraction of the clock frequency; the ratio between the clock frequency and blink

frequency depends on the blink mode selected (see Table 6).

An additional feature allows an arbitrary selection of LCD segments to blink in the static

and 1:2 drive modes. This is implemented without any communication overheads by the

output bank selector which alternates the displayed data between the data in the display

RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can

also be implemented by the blink-select command (see Section 7.17).

In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of

LCD segments can blink selectively by changing the display RAM data at ﬁxed time

intervals.

The entire display can blink at a frequency other than the nominal blink frequency by

sequentially resetting and setting the display enable bit E at the required rate using the

mode-set command (see Section 7.17).

[1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator

frequency (fclk) of 1536 Hz (see Section 11).

Table 6. Blinking frequencies[1]

Blink mode Normal operating mode ratio Nominal blink frequency

off - blinking off

1 2 Hz

2 1 Hz

3 0.5 Hz

clk

768

----------

clk

1536

-------------

clk

3072

-------------

Product data sheet Rev. 04 — 18 March 2009 19 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 11).

7.16.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is deﬁned as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition - P (see Figure 12).

7.16.3 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves (see Figure 13).

Fig 11. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 12. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL P

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 04 — 18 March 2009 20 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.16.4 Acknowledge

The number of data bytes that can be transferred from transmitter to receiver between the

START and STOP conditions is unlimited. Each byte of eight bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted

by the transmitter during which time the master generates an extra acknowledge related

clock pulse. An addressed slave receiver must generate an acknowledge after receiving

each byte. Also a master receiver must generate an acknowledge after receiving each

byte that has been clocked out of the slave transmitter. The acknowledging device must

pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold

times must be taken into consideration). A master receiver must signal an end of data to

the transmitter by not generating an acknowledge on the last byte that has been clocked

out of the slave. In this event the transmitter must leave the data line HIGH to enable the

master to generate a STOP condition (see Figure 14).

7.16.5 I2C-bus controller

The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

Fig 13. System conﬁguration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig 14. Acknowledgement of the I2C-bus

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Product data sheet Rev. 04 — 18 March 2009 21 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

7.16.6 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.16.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562.

The least signiﬁcant bit of the slave address that a PCF8562 will respond to is deﬁned by

the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to

a read access.

The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of two possible PCF8562

slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the

slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is

ignored by all PCF8562s whose SA0 inputs are set to the alternative level.

After an acknowledgement, one or more command bytes follow, that deﬁne the status of

each addressed PCF8562.

The last command byte sent is identiﬁed by resetting its most signiﬁcant bit, continuation

bit C, (see Figure 16). The command bytes are also acknowledged by all addressed

PCF8562s on the bus.

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address speciﬁed by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically

updated.

Fig 15. I2C-bus protocol

Fig 16. Format of command byte

mdb078

S011100 0AC COMMAND A P

ADISPLAY DATA

slave address R/W

acknowledge by

all addressed

PCF8576Ds

acknowledge

by A0, A1 and A2

selected

PCF8576D only

1 byte

update data pointers

and if necessary,

subaddress counter

n ≥ 1 byte(s) n ≥ 0 byte(s)

msa833

REST OF OPCODE

MSB LSB

Product data sheet Rev. 04 — 18 March 2009 22 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

An acknowledgement after each byte is asserted only by the PCF8562s that are

addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master

asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus

access.

7.17 Command decoder

The command decoder identiﬁes command bytes that arrive on the I2C-bus.

The commands available to the PCF8562 are deﬁned in Table 7.

[1] Not used.

All available commands carry a continuation bit C in their most signiﬁcant bit position as

shown in Figure 16. When this bit is set, it indicates that the next byte of the transfer to

arrive will also represent a command. If this bit is reset, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data (see Table 8).

Table 7. Deﬁnition of PCF8562 commands

Command Operation Code Reference

Bit 7 6 5 4 3 2 1 0

mode-set C 1 0 [1] E B M1 M0 Table 9

load-data-pointer C 0 0 P4 P3 P2 P1 P0 Table 10

device-select C 1100A2A1A0

Table 11

bank-select C 11110I O

Table 12

blink-select C 1110ABF1BF0

Table 13

Table 8. C bit description

Bit Symbol Value Description

7C continue bit

0 last control byte in the transfer; next byte will be regarded

as display data

1 control bytes continue; next byte will be a command too

Product data sheet Rev. 04 — 18 March 2009 23 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

[1] The possibility to disable the display allows implementation of blinking under external control.

Table 9. Mode-set command bits description

Bit Symbol Value Description

7 C 0, 1 see Table 8

6, 5 - 10 ﬁxed value

4 - - unused

3E display status

0 disabled (blank)[1]

1 enabled

2B LCD bias conﬁguration

01⁄3 bias

11⁄2 bias

1 to 0 M[1:0] LCD drive mode selection

01 static; BP0

10 1:2 multiplex; BP0, BP1

11 1:3 multiplex; BP0, BP1, BP2

00 1:4 multiplex; BP0, BP1, BP2, BP3

Table 10. Load-data-pointer command bits description

Bit Symbol Value Description

7 C 0, 1 see Table 8

6, 5 - 00 ﬁxed value

4 to 0 P[4:0] 00000 to

11111 5 bit binary value, 0 to 31; transferred to the data pointer to

deﬁne one of 32 display RAM addresses

Table 11. Device-select command bits description

Bit Symbol Value Description

7 C 0, 1 see Table 8

6 to 3 - 1100 ﬁxed value

2 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress

counter to deﬁne one of eight hardware subaddresses

Product data sheet Rev. 04 — 18 March 2009 24 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternating RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.18 Display controller

The display controller executes the commands identiﬁed by the command decoder. It

contains the device’s status registers and coordinates their effects. The display controller

is also responsible for loading display data into the display RAM in the correct ﬁlling order.

7.19 Multiple chip operation

For large display conﬁgurations or for more segments (> 128 elements) to drive please

refer to the PCF8576D device.

The contact resistance between the SYNC input/output on each cascaded device must be

controlled. If the resistance is too high, the device will not be able to synchronize properly;

this is particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 14.

Table 12. Bank-select command bits description

Bit Symbol Value Description

Static 1:2 multiplex[1]

7 C 0, 1 see Table 8

6 to 2 - 11110 ﬁxed value

1I input bank selection; storage of arriving display data

0 RAM bit 0 RAM bits 0 and 1

1 RAM bit 2 RAM bits 2 and 3

0O output bank selection; retrieval of LCD display data

0 RAM bit 0 RAM bits 0 and 1

1 RAM bit 2 RAM bits 2 and 3

Table 13. Blink-select command bits description

Bit Symbol Value Description

7 C 0, 1 see Table 8

6 to 3 - 1110 ﬁxed value

2A blink mode selection

0 normal blinking[1]

1 alternate RAM bank blinking[2]

1 to 0 BF[1:0] blink frequency selection

00 off

01 1

10 2

11 3

Product data sheet Rev. 04 — 18 March 2009 25 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

8. Internal circuitry

Table 14. SYNC contact resistance

Number of devices Maximum contact resistance

2 6000 Ω

3 to 5 2200 Ω

6 to 10 1200 Ω

10 to 16 700 Ω

Fig 17. Device protection circuits

SA0

VDD VDD

VSS VSS

VLCD

VSS

SDA

001aac269

VSS

SCL

VSS

CLK

VDD

VSS

OSC

VDD

VSS

SYNC

VDD

VSS

A0, A1, A2

VDD

VSS

BP0, BP1,

BP2, BP3

VLCD

VSS

S0 to S31

VLCD

VSS

Product data sheet Rev. 04 — 18 March 2009 26 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

9. Limiting values

[1] Pass level; Human Body Model (HBM) according to JESD22-A114.

[2] Pass level; Machine Model (MM), according to JESD22-A115.

[3] Pass level; Charged-Device Model (CDM), according to JESD22-C101.

[4] Pass level; latch-up testing, according to JESD78.

[5] According to the NXP store and transport conditions (document

SNW-SQ-623

) the devices have to be

stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.

Table 15. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 6.5 V

VLCD LCD supply voltage −0.5 +7.5 V

VIinput voltage on each of the pins CLK,

SDA, SCL, SYNC, SA0,

OSC, A0 to A2

−0.5 +6.5 V

VOoutput voltage on each of the pins S0 to

S31, BP0 to BP3 −0.5 +7.5 V

IIinput current −10 +10 mA

IOoutput current −10 +10 mA

IDD supply current −50 +50 mA

IDD(LCD) LCD supply current −50 +50 mA

ISS ground supply current −50 +50 mA

Ptot total power dissipation - 400 mW

Pooutput power - 100 mW

Vesd electrostatic discharge

voltage HBM [1] -±2000 V

MM [2] -±200 V

CDM [3] -±2000 V

Ilu latch-up current [4] - 100 mA

Tstg storage temperature [5] −65 +150 °C

Product data sheet Rev. 04 — 18 March 2009 27 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

10. Static characteristics

[1] VLCD > 3 V for 1⁄3 bias.

[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[3] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 15 (see Figure 17

too).

[4] Propagation delay of driver between clock (CLK) and LCD driving signals.

[5] Periodically sampled, not 100 % tested.

[6] Outputs measured one at a time.

Table 16. Static characteristics

= 1.8 V to 5.5 V; V

= 0 V; V

LCD

= 2.5 V to 6.5 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 1.8 - 5.5 V

VLCD LCD supply voltage [1] 2.5 - 6.5 V

IDD supply current fclk = 1536 Hz [2] -820µA

IDD(LCD) LCD supply current fclk = 1536 Hz [2] -2460µA

Logic

VP(POR) power-on reset supply voltage 1.0 1.3 1.6 V

VIL LOW-level input voltage on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

VSS - 0.3VDD V

VIH HIGH-level input voltage on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

[3][4] 0.7VDD -V

DD V

IOL LOW-level output current VOL = 0.4 V; VDD =5V

on pins CLK and SYNC 1 - - mA

on pin SDA 3 - - mA

IOH(CLK) HIGH-level output current on pin CLK VOH = 4.6 V; VDD =5V −1- - mA

ILleakage current VI=V

DD or VSS;

on pins CLK, SCL, SDA,

A0 to A2 and SA0

−1- +1µA

IL(OSC) leakage current on pin OSC VI=V

DD −1- +1µA

CIinput capacitance [5] --7pF

LCD outputs

∆VOoutput voltage variation on pins BP0 to BP3 and

S0 to S31 −100 - +100 mV

ROoutput resistance VLCD = 5 V [6]

on pins BP0 to BP3 - 1.5 - kΩ

on pins S0 to S31 - 6.0 - kΩ

Product data sheet Rev. 04 — 18 March 2009 28 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

11. Dynamic characteristics

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] Not tested in production.

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 17. Dynamic characteristics

= 1.8 V to 5.5 V; V

= 0 V; V

LCD

= 2.5 V to 6.5 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Clock

fclk(int) internal clock frequency [1] 1440 1850 2640 Hz

fclk(ext) external clock frequency 960 - 2640 Hz

tclk(H) HIGH-level clock time 60 - - µs

tclk(L) LOW-level clock time 60 - - µs

Synchronization

tPD(SYNC_N) SYNC propagation delay - 30 - ns

tSYNC_NL SYNC LOW time 1 - - µs

tPD(drv) driver propagation delay VLCD = 5 V [2] --30µs

I2C-bus[3]

Pin SCL

fSCL SCL clock frequency - - 400 kHz

tLOW LOW period of the SCL clock 1.3 - - µs

tHIGH HIGH period of the SCL clock 0.6 - - µs

Pin SDA

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - ns

Pins SCL and SDA

tBUF bus free time between a STOP and

START condition 1.3 - - µs

tSU;STO set-up time for STOP condition 0.6 - - µs

tHD;STA hold time (repeated) START condition 0.6 - - µs

tSU;STA set-up time for a repeated START

condition 0.6 - - µs

trrise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 µs

fSCL < 125 kHz - - 1.0 µs

tffall time of both SDA and SCL signals - - 0.3 µs

Cbcapacitive load for each bus line - - 400 pF

tw(spike) spike pulse width on the I2C-bus - - 50 ns

Product data sheet Rev. 04 — 18 March 2009 29 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

Fig 18. Driver timing waveforms

Fig 19. I2C-bus timing waveforms

001aac268

0.7VDD

0.3VDD

0.7VDD

0.3VDD

SYNC

CLK

0.5 V

tPD(LCD)

tPD(SYNC)

BP0 to BP3,

and S0 to S31

tPD(SYNC)

tSYNCL

(VDD = 5 V)

1/fCLK tCLKL

tCLKH

SDA

mga728

SDA

SCL

tSU;STA tSU;STO

tHD;STA

tBUF tLOW

tHD;DAT tHIGH

tSU;DAT

Product data sheet Rev. 04 — 18 March 2009 30 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

12. Package outline

Fig 20. Package outline SOT362-1 (TSSOP48)

UNIT A1A2A3bpcD

(1) E(2) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.2

0.1 8

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT362-1 99-12-27

03-02-19

detail X

(A )

0.25

124

48 25

pin 1 index

1.05

0.85 0.28

0.17 0.2

0.1 12.6

12.4 6.2

6.0 0.5 1 0.25

8.3

7.9 0.50

0.35 0.8

0.4

0.08

0.8

0.4

EvMA

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1

max.

1.2

2.5

5 mm

scale

MO-153

Product data sheet Rev. 04 — 18 March 2009 31 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

13. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in

JESD625-A

IEC 61340-5

or equivalent

standards.

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

Product data sheet Rev. 04 — 18 March 2009 32 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

14.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 18 and 19

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 21.

Table 18. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 19. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 04 — 18 March 2009 33 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 21. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 20. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

CDM Charged-Device Model

HBM Human Body Model

ITO Indium Tin Oxide

LCD Liquid Crystal Display

LSB Least Signiﬁcant Bit

MM Machine Model

MSB Most Signiﬁcant Bit

MSL Moisture Sensitivity Level

PCB Printed Circuit Board

RAM Random Access Memory

RMS Root Mean Square

SCL Serial Clock Line

SDA Serial Data Line

SMD Surface Mount Device

Product data sheet Rev. 04 — 18 March 2009 34 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

16. Revision history

Table 21. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8562_4 20090318 Product data sheet - PCF8562_3

Modiﬁcations: •The typical value of the frame frequency has been corrected (see Table 17)

PCF8562_3 20081202 Product data sheet - PCF8562_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Added AEC-Q100 qualiﬁcation

PCF8562_2 20070122 Product data sheet - PCF8562_1

PCF8562_1 20050801 Product data sheet - -

Product data sheet Rev. 04 — 18 March 2009 35 of 36

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCF8562

Universal LCD driver for low multiplex rates

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 March 2009

Document identifier: PCF8562_4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 6

7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6

7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 9

7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9

7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10

7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12

7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13

7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.5.1 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.6 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.7 Display register. . . . . . . . . . . . . . . . . . . . . . . . 14

7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14

7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14

7.10 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17

7.13 Output bank selector. . . . . . . . . . . . . . . . . . . . 17

7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 18

7.15 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.16 Characteristics of the I2C-bus. . . . . . . . . . . . . 19

7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.16.2 START and STOP conditions . . . . . . . . . . . . . 19

7.16.3 System conﬁguration . . . . . . . . . . . . . . . . . . . 19

7.16.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.16.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 20

7.16.6 Input ﬁlters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.16.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21

7.17 Command decoder. . . . . . . . . . . . . . . . . . . . . 22

7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 24

7.19 Multiple chip operation . . . . . . . . . . . . . . . . . . 24

8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 27

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 28

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30

13 Handling information . . . . . . . . . . . . . . . . . . . 31

14 Soldering of SMD packages. . . . . . . . . . . . . . 31

14.1 Introduction to soldering. . . . . . . . . . . . . . . . . 31

14.2 Wave and reﬂow soldering. . . . . . . . . . . . . . . 31

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 32

14.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 32

15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 34

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 35

17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 35

17.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35

18 Contact information . . . . . . . . . . . . . . . . . . . . 35

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36