392 PS8137A 03/15/99
Pin Configuration
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PI6C671F
Clock Generator for Pentium Modules
Block Diagram
Description
Supports Pentium or Pentium II CPU modules
Spread Spectrum capability reduces EMI
Low power consumption
Four CPU Clocks with VDDQ2 of 3.3V or 2.5V
Enhanced drive on CPUCLK0
Seven PCI synchronous clocks (3.3V)
One IOAPIC Clock @14.31818 MHz
(Power from pin 46), with VDDQ1 of 3.3V or 2.5V
Two 48/24 MHz clocks (3.3V)
Six/eight SDRAM clocks (3.3V)
Three Ref. Clocks @14.31818 MHz (3.3V)
Internal crystal loading capacitor
Ref. 14.31818 MHz crystal oscillator input
Separate 66/60# MHz select pin
Separate power management MODE control pin
I2C 2-Wire Serial Interface
48-pin SSOP Package (V) and TSSOP (A)
The PI6C671F is a mixed-voltage clock generator designed to
provide all timing signals for Intel Pentium/Pentium II module-based
motherboards. It provides four CPU, seven PCI, and up to eight
SDRAM clocks. Additionally, three reference clocks (same fre-
quency as the crystal) and two selectable 24/48 MHz clocks are
available.
Pericom design improvements resulted in a low-power device
optimized for 2.5V CPU operation. A special spread-spectrum
feature may be enabled to minimize EMI.
The two-wire I2C serial interface can be used to reduce circuit
noise and power consumption. I2C control lets you enable/disable
each clock output driver, change CPU frequencies, and select 24 or
48 MHz outputs.
A power-down function (pin 44) puts the whole system in a low-
power mode by stopping the crystal oscillator and both PLLs. CPU
and PCI clocks may also be stopped by the CPU_STOP# (pin 27), and
PCI _STOP# (pin 26) functions.
Note: Purchase of I2C components from Pericom conveys a license
to use them in an I2C system as defined by Philips.
Features
All trademarks are of their respective companies.
REF1 1
REF0 2
V
SS
3
XIN 4
XOUT 5
MODE 6
V
DDQ
37
PCICLK_F 8
PCICLK0 9
V
SS
10
PCICLK1 11
PCICLK2 12
PCICLK3 13
PCICLK4 14
V
DDQ
315
PCICLK5 16
V
SS
17
SEL66/60# 18
SDATA 19
SDCLK 20
V
DDQ
321
48/24MHz 22
48/24MHz 23
V
SS
24
V
DD
REF2
V
DDQ
1
IOAPIC0
PWR_DWN#
V
SS
CPUCLK0
CPUCLK1
V
DDQ
2
48
CPUCLK2
47
CPUCLK3
46
V
SS
45
SDRAM0
44
SDRAM1
43
V
DDQ
3
42
SDRAM2
41
SDRAM3
40
V
SS
39
SDRAM4
38
SDRAM5
37
V
DDQ
3
36
SDRAM6/CPU_STOP#
35
SDRAM7/PCI_STOP#
34
V
DD
33
32
31
30
29
28
27
26
25
48-Pin
A, V
V
DDQ
1
V
DDQ
3
V
DDQ
2
÷
2
SEL
REF
OSC
PLL1
PLL2
XOUT
XIN
4
Up to 8
6
REF0,1,2
IOAPIC0
CPUCLK0-3
SDRAM0-7
PCICLK0-5
PCICLK_F
48/24 MHz
48/24 MHz
3
Buffers
393
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PS8137A 03/15/99
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C671F
Clock Generator for Pentium Modules
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2QDD
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V
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V
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V
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Pin Descriptions
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2D 0FER.tuptuokcolczHM813.41
74,1C 2FER,1FER.tuptuokcolczHM813.41
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32,22C zHM42/84.elbatcelesV3.3tuptuokcolczHM42/84
,03,92,72,62 63,53,33,23 DMARDS.zHM66/06skcolcMARDS
24,14,93,83AKLCUPCV3.3roV5.2:stuptuokcolctsohdnaUPC
54B ,0CIPAOI 1CIPAOI .V3.3roV5.2:tuptuokcolcCIPAOI
Driver Types
394 PS8137A 03/15/99
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PI6C671F
Clock Generator for Pentium Modules
Power Management Functions
Any or all clocks can be enabled or shut down via the I2C control
interface. All clocks stop in the LOW state. CPU, SDRAM, and PCI
clocks wait for one rising edge of PCICLK_F followed by a falling
#POTS_UPC#POTS_ICP#NWD_RWP ,KLCUPC MARDS KLCICP rehtO skcolC &latsyrC sOCV
XX 0 WOLWOLWOLffO
00 1 WOLWOLgninnuRgninnuR
01 1 WOLzHM03/33gninnuRgninnuR
10 1 zHM06/66WOLgninnuRgninnuR
11 1 zHM06/66zHM03/33gninnuRgninnuR
The I2C interface permits individual enable/disable of each
clock output and test mode enable.
The PI6C671F is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving
device.
During normal data transfers SDATA changes only when SDCLK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SDCLK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SDCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C671F generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts the
following data bytes until another start or stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
The I2C interface is disabled when the PWR_DWN# pin is LOW.
Preset control register contents are retained.
I2C Serial Configuration
Byte 0: Functional and Frequency Select
Clock Register (1 = enable, 0 = disable)
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70)devreseR(
60 )egnahct'nod,devreseR(
50 )egnahct'nod,devreseR(
40 )egnahct'nod,devreseR(
3321 )tceleSqerF(zHM42/84 zHM42=0,zHM84=1
2221 )tceleSqerF(zHM42/84 zHM42=0,zHM84=1
1
00
00tiB1tiB etatS-irT:11 murtcepSdaerpS:01 edoMtseT:10 noitarepOlamroN:00
2-Wire I2C Control
edge of the clock of interest before settling in the LOW state. To
reduce power consumption the PI6C671F clocks may be disabled in
accordance with the following table.
395
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PS8137A 03/15/99
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PI6C671F
Clock Generator for Pentium Modules
Byte 1: CPU 24/48 MHz Active/Inactive Register
(1 = enable, 0 = disable)
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7321 )evitcanI/evitcA(zHM42/84
6221 )evitcanI/evitcA(zHM42/84
5X)devreseR(
4A/NX )evitcanI/evitcA(4KLCUPC
3831 )evitcanI/evitcA(3KLCUPC
2931 )evitcanI/evitcA(2KLCUPC
1141 )evitcanI/evitcA(1KLCUPC
0241 )evitcanI/evitcA(0KLCUPC
Byte3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
tiB.oNniPpurewoP@noitpircseD
7621 )evitcanI/evitcA(7MARDS
6721 )evitcanI/evitcA(6MARDS
5921 )evitcanI/evitcA(5MARDS
4031 )evitcanI/evitcA(4MARDS
3231 )evitcanI/evitcA(3MARDS
2331 )evitcanI/evitcA(2MARDS
1531 )evitcanI/evitcA(1MARDS
0631 )evitcanI/evitcA(0MARDS
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
tiB.oNniPpurewoP@noitpircseD
7X)devreseR(
68 1 )evitcanI/evitcA(F_KLCICP
5611 )evitcanI/evitcA(5KLCICP
4411 )evitcanI/evitcA(4KLCICP
3311 )evitcanI/evitcA(3KLCICP
2211 )evitcanI/evitcA(2KLCICP
1111 )evitcanI/evitcA(1KLCICP
09 1 )evitcanI/evitcA(0KLCICP
Byte 4: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
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7A/N)evitcanI/evitcA(51MARDS
6A/N)evitcanI/evitcA(41MARDS
5A/N)evitcanI/evitcA(31MARDS
4A/N)evitcanI/evitcA(21MARDS
3A/N)evitcanI/evitcA(11MARDS
2A/N)evitcanI/evitcA(01MARDS
1A/N)evitcanI/evitcA(9MARDS
0A/N)evitcanI/evitcA(8MARDS
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
tiB.oNniPpurewoP@noitpircseD
7X)devreseR(
6X)devreseR(
51)devreseR(
4541 )evitcanI/evitcA(CIPAOI
3X)devreseR(
2741 )evitcanI/evitcA(2FER
11 1 )evitcanI/evitcA(1FER
02 1 )evitcanI/evitcA(0FER
Byte 6: Optional Register
for Possible Future Requirements
tiBrebmuNniPnoitpircseD
7X )devreseR(
6X )devreseR(
5X )devreseR(
4X )devreseR(
3X )devreseR(
2X )devreseR(
1X )devreseR(
0X )devreseR(
396 PS8137A 03/15/99
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PI6C671F
Clock Generator for Pentium Modules
Byte 7: Frequency Control
2LESF1LESF0LESFycneuqerF
000 )devreseR(
001 )devreseR(
010 )devreseR(
011 zHM33
100 zHM05
10 1 zHM55
110 zHM06
111 nip#06/66LESmorF
tiBpurewoP@noitpircseD
7X )devreseR(
6X )devreseR(
5X )devreseR(
4X )devreseR(
3X )devreseR(
21 2LESF
11 1LESF
01 0LESF
DC Specifications
Absolute Maximum DC Power Supply
lobmySegatloVylppuS.niM.xaMstinU
V
3QDD
O/I&eroCV3.35.0-6.4
V
V
DD
eroCV3.35.0-6.4
V
2QDD
O/IV3.3/5.25.0-6.4
V
1QDD
O/IV3.3/5.25.0-6.4
DC Operating Requirements
(VDD, VDDQ3=3.3V ±5%, VDDQ2=2.5V ±5%, TA=0 to 70°C)
Note: Typical values are at room temperature
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V
2HO
tuptuOV5.2 egatloVhgiH I
HO
Am1-=1.2
V
V
3HO
tuptuOV3.3 egatloVhgiH I
HO
Am1-=4.2
V
2LO
tuptuOV5.2 egatloVwoL I
LO
Am1=4.0
V
3LO
tuptuOV3.3 egatloVwoL I
LO
Am1=4.0
I
DD
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zHM66 dedaolnU stuptuO 5507Am
I
DP
nwoDrewoP ylppuS tnerruC
0=#NWD_RWP taolF=EDOM )hgih( 4102µA
397
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PS8137A 03/15/99
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PI6C671F
Clock Generator for Pentium Modules
Driver Specifications
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reffuBV5.23-1KLCUPC:AepyT
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nimloItnerruCnwod-lluPV2.1=tuoV84
reffuBV3.33-1KLCUPC:AepyT
nimhoItnerruCpu-lluPV0.1=tuoV96- Am
nimloItnerruCnwod-lluPV6.1=tuoV36
reffuBV5.2CIPAOI:BepyT
nimhoItnerruCpu-lluPV4.1=tuoV63- Am
nimloItnerruCnwod-lluPV0.1=tuoV63
reffuBV3.3CIPAOI:BepyT
nimhoItnerruCpu-lluPV0.1=tuoV85- Am
nimloItnerruCnwod-lluPV9.1=tuoV75
reffuB)V3.3(zHM42/84,2FER,1FER:CepyT
nimhoItnerruCpu-lluPV0.1=tuoV92- Am
nimloItnerruCnwod-lluPV59.1=tuoV92
reffuB)V3.3(MARDS,0FER:DepyT
nimhoItnerruCpu-lluPV0.2=tuoV45- Am
nimloItnerruCnwod-lluPV0.1=tuoV45
reffuBkcolCICP:EepyT
nimhoItnerruCpu-lluPV0.1=tuoV33- Am
nimloItnerruCnwod-lluPV59.1=tuoV03
reffuBV5.20KLCUPC:FepyT
nimhoI xamhoI tnerruCpu-lluP V0.1=tuoV26-
Am
V5.2=tuoV91-
nimhoItnerruCnwod-lluP V2.1=tuoV06
V3.0=tuoV14
398 PS8137A 03/15/99
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PI6C671F
Clock Generator for Pentium Modules
AC Timing
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tFRV0.2-V4.0,emitllaf/esirKLCtsoH4.06.1sn
tRETTIJrettiJKLCtsoH052sp
elcyCytuD ehtrofV52.1tasKLCegdegnisirehtderusaeM skcolcV3.3ehtrofV5.1tadnaskcolcV5.2 5455%
tWKSHweksKLCsuBtsoH052
sp
tDSKSHMARDSottsoH005
tSPKPytilibatsdoirepKLCICP005
tWKSPweksKLCsuBICP005
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tBTSpu-rewoptanoitazilibatSKLC3sm
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
N/PnoitpircseD
VF176C6IPegakcaPPOSSnip-84
AF176C6IPegakcaPPOSSTnip-84
Ordering Information
48-Pin SSOP Package Data
48-Pin TSSOP Package Data
.236
.244
.488
.496
.002
.006
SEATING PLANE
.007
.010
.0197
BSC
.004
.008
.319
1
48
12.4
12.6
6.0
6.2
0.50 0.17
0.27
8.1
0.05
0.15
0.09
0.20
X.XX
X.XX DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
1.20 Max
BSC
0.20
0.51
1.01
0.25
0.381
0.635
.008
.008
.016
0-8˚ 0.20
0.40
.110 2.79
.010
Gauge Plane
.02
.04
.015
.025 x 45˚
.025 BSC
0.635
.291
.299
X.XX
X.XX DENOTES DIMENSIONS
IN MILLIMETERS
7.39
7.59
.395
.420
10.03
10.67
.620
.630
15.75
16.00
.008
.0135 0.20
0.34
1
48
Nom.
Max
