MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-B ASE TYPE
INSULATED TYPE
May 2001
Some parametric limits are subject to change.
LABEL
Terminals Assignment:
115
± 1
96
1
5
13
8.5
55
1010
50
32
15.5 15.5
2.5
105
± 0.5
63.5
± 0.8
17.5
(102)
(22) 0.5
0.5
3
3
12.7
± 0.3
76
± 1
41
± 0.5
2
± 0.3
56
±
0.8 20.4
± 1
17
± 0.8
60
± 0.5
63
± 0.8
1
± 0.3
15.5
6
± 0.3
4-φ5
4-R2
4-R5
4-φ4.5
4-φ3.2
MOUNTING
HOLE
17
23
31 36
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br
31 P
32 Br
33 N
34 U
35 V
36 W
PS11017 INTEGRATED FUNCTIONS AND FEATURES
• 3-phase IGBT inver ter bridge configured by the latest 3rd.
generation IGBT and diode technologies.
• Circuit for dynamic braking of motor regenerative energy.
• Inverter output current capability IO (Note 1):
PACKAGE OUTLINES
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Po wer Module>
PS11017
FLAT -B ASE TYPE
INSULATED TYPE
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2
(Fig. 1)
Type Name
PS11017 100% load
17.0A (rms) 150% over load
25.5A (rms), 1min
APPLICATION
Acoustic noise-less 3.7kW/AC200V class 3 phase inverter and other motor control applica-
tions.
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For P-Side IGBTs :Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protection (SC),
Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protection (UV).
• For N-Side IGBTs :Drive circuit, Short circuit protection (SC), Control-supply Under voltage and Over voltage protection (OV/UV), Sys-
tem Over-temperature protection (OT), Fault output (FO) signaling circuit, and Current-Limit warning signal output
(CL)
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV)
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter phase current (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-B ASE TYPE
INSULATED TYPE
May 2001
Each output IGBT collector current
Brake IGBT collector current
Brake diode anode current
INTERNAL FUNCTIONS BLOCK DIAGRAM
(Fig. 2)
V
V
450
500
Applied between P-N
Applied between P-N, Surge-value
Applied between P-U, V, W, Br or U, V, W,
Br-N
Applied between P-U, V, W, Br or U, V, W,
Br-N
TC = 25°C
Note: “( )” means IC peak value
Supply voltage
Supply voltage (surge)
VCC
VCC(surge)
ConditionSymbol Item Ratings Unit
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)
VP or VN
V
P(S)
or V
N(S)
±IC(±ICP)
IC(ICP)
IF(IFP)
Each output IGBT collector-emitter static voltage
Each output IGBT collector-emitter
switching surge voltage
600
600
±50 (±100)
15 (30)
15 (30)
V
V
A
A
A
VDHGND
B
P
R
S
T
CZ
N
M
CBU–
CBU+
CBV–
CBV+
CBW–
CBW+
Application Specific Intelligent
Power Module
CUCV CW CL, FO
1
, FO
2
, FO
3
U
P
V
P
W
P
V
N
W
N
B
r
U
N
Protection
circuit
Control supply
fault sense
Fo Logic
Drive Circuit
Input signal conditioning
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit may become necessary
depending on the application environment].
W
AC 200V line
output
V
U
AC 200V line input
Brake resistor connection,
Inrush prevention circuit,
etc.
Protection
Circuit Level shifter
Drive Circuit
Current sensing
circuit
Note 1) To prevent chances of signal oscillation, a series resistor (1kΩ) coupling at each output is recommended.
Note 2) By virtue of integrating an photo-coupler inside the module, direct coupling to CPU, without any external opto or transformer isolation is possible.
Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance.
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage.
For extra precaution, a small film snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins.
Analogue signal output corresponding to
each phase current (5V line) Note 1) PWM input
(5V line) Note 2) Fault output
(5V line) Note 3)
T
S
V
20
Applied between VDH-GND, CBU+-CBU–,
CBV+-CBV–, CBW+-CBW–
Applied between UP · VP · WP · UN · VN ·
WN · Br-GND
Applied between FO1 · FO2 · FO3-GND
Sink current of FO1 · FO2 · FO3
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW
VDH, VDB Supply voltage
Symbol Item Ratings Unit
CONTROL PART
Condition
–0.5 ~ 7
15
–0.5 ~ 7
15
±1
V
V
mA
V
mA
mA
VCIN
VFO
IFO
VCL
ICL
ICO
Input signal voltage
Fault output supply voltage
Fault output current
Current-limit warning (CL) output voltage
CL output current
Analogue current signal output current
–0.5 ~ 7.5
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-B ASE TYPE
INSULATED TYPE
May 2001
Tc
LABEL
1.75
2.4
2.9
4.5
0.031
°C/W
°C/W
°C/W
°C/W
°C/W
—
—
—
—
—
Junction to case Thermal
Resistance
Condition
Symbol Item Ratings Unit
(Note 2)
—(Fig. 3)
60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.
Mounting screw: M4.0
Tj
Tstg
TC
Viso
Junction temperature
Storage temperature
Module case operating temperature
Isolation voltage
Mounting torque
–20 ~ +125
–40 ~ +125
–20 ~ +100
2500
0.98 ~ 1.47
°C
°C
°C
Vrms
N·m
TOTAL SYSTEM
Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How-
ever, these power elements can endure instantaneous junction temperature as high as 150°C instantaneously . To make use of this ad-
ditional temperature allo wance, a detailed study of the exact application conditions is required and, accordingly, necessary information
is requested to be provided before use.
Condition
Symbol Item Ratings
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
Brake FWDi
Case to fin, thermal grease applied
Rth(j-c)Q
Rth(j-c)F
Rth(j-c)Q
Rth(j-c)F
Rth(c-f)
Min.
THERMAL RESISTANCE
Typ. Max.
—
—
—
—
—
Unit
(Fig. 3)
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
Contact Thermal Resistance
Circuit current
Input on threshold voltage
Input off threshold voltage
Input pull-up resister
Min.
VFBr
ton
tc(on)
toff
tc(off)
trr
Collector-emitter saturation voltage
FWDi forward voltage
VCE(sat)
VEC
Ratings
VDH = VDB = 15V, Input = ON, Tj = 25°C, Ic = 50A
Condition
Symbol Item Typ. Max. Unit
• No destruction
• FO output by protection operation
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)
Tj = 25°C, Ic = –50A, Input = OFF
IDH
Vth(on)
Vth(off)
Ri
• No destruction
• No protecting operation
• No FO output
VCE(sat)Br
Brake IGBT
Collector-emitter saturation voltage
Brake diode forward voltage
VDH = 15V, Input = ON, Tj = 25°C, Ic = 15A
Tj = 25°C, IF = 15A, Input = OFF
Switching times
1/2 Bridge inductive, Input = ON
VCC = 300V, Ic = 50A, Tj = 125°C
VDH = 15V, VDB = 15V
Note : ton, toff include delay time of the internal control
circuit
FWD reverse recovery time
Short circuit endurance
(Output, Arm, and Load,
Short Circuit Modes)
VCC ≤ 400V, Input = ON (one-shot)
Tj = 125°C start
13.5V ≤ VDH = VDB ≤ 16.5V
VCC ≤ 400V, Tj ≤ 125°C,
Ic < IOL(CL) operation level, Input = ON,
13.5V ≤ VDH = VDB ≤ 16.5V
Switching SOA
VDH = 15V, VCIN = 5V
—
—
—
—
—
—
0.8
2.5
Integrated between input terminal-VDH —
—
0.40
—
—
—
—
—
0.40
1.5
—
1.4
3.0
150
—
0.8
0.15
0.6
2.9
2.9
3.5
1.0
2.4
150
2.0
4.0
—
2.9
2.0
—
1.3
V
V
V
V
µs
µs
µs
µs
µs
mA
V
V
kΩ
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-B ASE TYPE
INSULATED TYPE
May 2001
—
—
10.0
16.50
18.00
11.55
—
td(read)
ICL(H)
ICL(L)
±IOL
SC
OT
OTr
UVDH
UVDHr
OVDH
OVDHr
UVDB
UVDBr
tdV
IFO(H)
IFO(L)
0.77
txx —
ELECTRICAL CHARACTERISTICS (Tj = 25 °C, VDH = 15V, VDB = 15V unless otherwise noted)
—
3.37
Idle
Active
Tr ip level
Reset level
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Filter time
Idle
Active
Ic = 0A
Ic = IOP(200%)
Ic = –IOP(200%)
tint
VCO
V
C+
(200%)
V
C–
(200%)
|∆VCO|
VC+
VC–
∆VC(200%)
TC = –20 ~ +100°C,
Tj ≤ 125°C
VDH = 15V
TC = –20°C ~ 100°C
(Fig. 4)
TC ≤ 100°C, Tj ≤ 125°C
VDH = 15V, TC = –20°C ~ +100°C (Note 3)
PWM input frequency
Condition
Symbol Ratings
fPWM Min. Typ. Max. Unit
VDH = 15V, TC = –20°C ~ 100°C
Ic > IOP(200%), VDH = 15V (Fig. 4)
|VCO-VC±(200%)|
After input signal trigger point (Fig. 8)
Fault output current
Open collector output
VD = 15V, TC = –20°C ~ 100°C (Note 4)
Tj = 25°C (Fig. 7) (Note 5)
Analogue signal over all linear variation
Item
tdead
Allowable input on-pulse width
Allowable input signal dead time for
blocking arm shoot-through
Relates to corresponding input (Except break part)
Analogue signal linearity with output current
Offset change area vs temperature
Analogue signal output voltage limit
rCH Analogue signal data hold accuracy
Analogue signal reading time
Correspond to max. 500µs data hold period
only, Ic = IOP(200%) (Fig. 5)
CL warning operation level
Short circuit over current trip level
1
2.5
—
1.87
—
—
—
4.0
–5
48.2
79.2
100
11.05
Open collector output —
—
—
—
65
2.27
1.17
—
15
—
1.1
1
—
60.0
102
110
90
11.0
12.00
12.50
19.20
10
—
1
15
500
—
100
2.57
1.47
3.67
0.7
—
1
—
—
5
72.0
—
120
—
12.0
12.5
12.75
13.25
20.15
18.65
—
1
—
—3
——
—
kHz
µs
µs
ns
V
V
V
mV
V
V
V
%
µs
µA
mA
A
A
°C
°C
V
V
V
V
µs
µA
mA
17.50
Relates to corresponding inputs,
(Except brake part), TC = –20°C ~ +100°C
Input inter-lock sensing
2.97
Signal output current of
CL operation —
Over temperature
protection
Supply circuit under &
over voltage protection
11.510.5 V
V
VDH = 15V
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-
tarily. The protection function is, thus meant primarily to protect the ASIPM against shor t circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its FO1 pin of the ASIPM indicating a short circuit situation.
Supply voltage ripple
Input on voltage
Input off voltage
PWM Input frequency
Arm shoot-through blocking time
Supply voltage
∆V
DH
, ∆V
DB
VCIN(on)
VCIN(off)
fPWM
tdead
RECOMMENDED CONDITIONS
V
400 (max.)
Applied across P-N terminals
Condition
Symbol Item Ratings
VCC
Unit
VDH, VDB Control Supply voltage Applied between VDH-GND, CBU+-CBU–, CBV+-CBV–,
CBW+-CBW–
Using application circuit
Using application circuit
15±1.5
±1 (max.)
0 ~ 0.3
4.8 ~ 5.0
2 ~ 15
2.5 (min.)
V
V/µs
V
V
kHz
µs
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-B ASE TYPE
INSULATED TYPE
May 2001
S
C
delay time
Short circuit sensing signal V
S
Error output F
O1
Gate signal Vo of each phase
upper arm(ASIPM internal)
Input signal V
CIN
of each phase
upper arm 0V
0V
0V
0V
0V
0V
0V
0V
0V
Input signal V
CIN(p)
of each phase upper arm
Input signal V
CIN(n)
of each phase lower arm
Gate signal V
o(p)
of each phase upper arm
(ASIPM internal)
Gate signal V
o(n)
of each phase upper arm
(ASIPM internal)
Error output F
O1
200–200
Analogue output signal
data hold range
1
2
3
4
5
4003001000–100–300–400
0
V
C
+(200%)
V
C0
V
C
–
(200%)
V
C
(V)
VC+
V
C
–
min max
Real load current peak value.(%)(Ic=Io✕ 2)
V
DH
=15V
T
C
=
–
20
~
100˚C
(Fig. 4)
Fig. 4 OUTPUT CURRENT ANALOGUE SIG-
NALING LINEARITY Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-ar m pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F
O
” signal is outputted. After an “input
interlock” operation the circuit is latched. The “F
O
” is reset by the high-to-lo w going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Note : Short circuit protection oper ation. The protection operates with “F
O
” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
V
CH
(5
µ
s) V
CH
(505
µ
s)
0V
V
C
500µs
r
CH
=V
CH
(505
µ
s)-V
CH
(5
µ
s)
V
CH
(5
µ
s)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-B ASE TYPE
INSULATED TYPE
May 2001
R
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
,Br
F
01
,F
02
,F
03
,CL
CU,CV,CW
GND(Logic)
ASIPM
5V
CPU
R
5.1kΩ
10kΩ
0.1nF0.1nF
on
on
on
on
0
0
0
V
PN
DC-Bus voltage
Control voltage supply
Boot-strap voltage
N-Side input signal
P-Side input signal
Brake input signal
F
O
1 output signal
V
DB
V
CIN(N)
V
CIN(P)
V
CIN(Br)
F
OI
V
DH
b)
a)
PWM starts
N-side IGBT Current N-side FWDi Current
t(hold)
td(read)
Delay time
+I
CL
–I
CL
on
off
on
off
0
0
on
off
0
Ref
V
CIN
V(hold)
I
C
(V
S
)
V
C
V
CL
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to Supply voltage (OFF level); however, FO1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. FO1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for ad-
equate charging (pulse width = approx. 20 µs number of pulses =10
~ 500 depending on the boot-strap capacitor size)
b) FO1 resetting sequence:
Apply ON signals to the following input pins : Br → Un/Vn/Wn →
Up/Vp/Wp in that order.